| 51st week of 2012 patent applcation highlights part 15 |
| Patent application number | Title | Published |
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| 20120319095 | ORGANIC ELECTROLUMINESCENT DEVICE - Disclosed is an organic electroluminescent device (organic EL device) that is improved in luminous efficiency, sufficiently secures driving stability, and has a simple configuration. This organic EL device comprises organic layers between an anode and a cathode piled one upon another on a substrate and at least one organic layer selected from a light-emitting layer, a hole-transporting layer, an electron-transporting layer, and a hole-blocking layer contains a carbazole compound represented by the following formula (1). In the case where the light-emitting layer of the organic electroluminescent device contains a phosphorescent dopant and a host material, it is the carbazole compound that is contained as the host material. In formula (1), X is C—Y or a nitrogen atom; Y is a hydrogen atom, an alkyl group, a cycloalkyl group, or an aromatic group; n is an integer of 2 to 4: A is an n-valent aromatic group; L is a direct bond or a divalent aromatic group; and R is a hydrogen atom, an alkyl group, or a cycloalkyl group. | 2012-12-20 |
| 20120319096 | SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY PERCOLATING SOURCE LAYER AND METHODS OF FABRICATING THE SAME - Various embodiments are provided for semiconductor devices including an electrically percolating source layer and methods of fabricating the same. In one embodiment, a semiconductor device includes a gate layer, a dielectric layer, a memory layer, a source layer, a semiconducting channel layer, and a drain layer. The source layer is electrically percolating and perforated. The semiconducting channel layer is in contact with the source layer and the memory layer. The source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier. | 2012-12-20 |
| 20120319097 | ELECTRODE TREATMENT PROCESS FOR ORGANIC ELECTRONIC DEVICES - The present invention relates to a process for the treatment of electrodes in organic electronic (OE) devices, in particular organic field effect transistors (OFETs), to devices prepared by such a process, and to materials and formulations used in such a process. | 2012-12-20 |
| 20120319098 | SUBSTITUTED PYRIDYL COMPOUND AND ORGANIC ELECTROLUMINESCENT ELEMENT - The present invention relates to a substituted pyridyl compound represented by the following general formula (1), (2), or (3) and an organic electroluminescent element containing a pair of electrodes and at least one organic layer interposed therebetween, in which the at least one organic layer contains the substituted pyridyl compound represented by the following general formula (1), (2), or (3). | 2012-12-20 |
| 20120319099 | MATERIAL FOR ORGANIC ELECTROLUMINESCENCE DEVICES AND ORGANIC ELECTROLUMINESCENCE DEVICE USING THE MATERIAL - A material for organic electroluminescence devices comprising a compound in which a heterocyclic group having nitrogen is bonded to an arylcarbazolyl group or a carbazolylalkylene group and an organic electroluminescence device comprising an anode, a cathode and an organic thin film layer comprising at least one layer and disposed between the anode and the cathode, wherein at least one layer in the organic thin film layer comprises the material for organic electroluminescence devices described above. The material can provide an organic electro-luminescence device emitting bluish light with a high purity of color. The organic electroluminescence device uses the material. | 2012-12-20 |
| 20120319100 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A miniaturized semiconductor device in which an increase in power consumption is suppressed and a method for manufacturing the semiconductor device are provided. A highly reliable semiconductor device having stable electric characteristics and a method for manufacturing the semiconductor device are provided. An oxide semiconductor film is irradiated with ions accelerated by an electric field in order to reduce the average surface roughness of a surface of the oxide semiconductor film. Consequently, an increase in the leakage current and power consumption of a transistor can be suppressed. Moreover, by performing heat treatment so that the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to the surface of the oxide semiconductor film, a change in electric characteristics of the oxide semiconductor film due to irradiation with visible light or ultraviolet light can be suppressed. | 2012-12-20 |
| 20120319101 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film. | 2012-12-20 |
| 20120319102 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided. | 2012-12-20 |
| 20120319103 | THIN FILM TRANSISTOR AND METHOD FOR PREPARING THE SAME - The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide material including Si as a channel material of a semiconductor layer, and a method of manufacturing the same. | 2012-12-20 |
| 20120319104 | METHOD FOR PRODUCING CIRCUIT BOARD, CIRCUIT BOARD AND DISPLAY DEVICE - Provided is a method of producing a circuit board of which the aperture ratio is increased. The method of producing a circuit board of the present invention is a method of producing a circuit board that includes a thin film transistor, the thin film transistor including an oxide semiconductor layer, the method including steps of: forming the oxide semiconductor layer; and converting the oxide semiconductor layer into a conductive form. | 2012-12-20 |
| 20120319105 | ZINC-TIN OXIDE THIN-FILM TRANSISTORS - Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate. | 2012-12-20 |
| 20120319106 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THE SAME - An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced. | 2012-12-20 |
| 20120319107 | LIQUID CRYSTAL DISPLAY DEVICE - An object of the present invention is to provide a liquid crystal display device which allows a desirable storage capacitor to be ensured in a pixel without decreasing the aperture ratio in response to changes in frame frequency. In a liquid crystal display device including a pixel transistor and two capacitive elements using an oxide semiconductor material in each pixel, one of the capacitive elements comprises a light-transmitting material to improve the aperture ratio of the pixel. Furthermore, through the use of characteristics of the light-transmitting capacitive element, the size of the storage capacitor in the pixel is varied by adjusting the voltage value of a capacitance value in response to the frame frequency varied depending on images displayed. | 2012-12-20 |
| 20120319108 | TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND MANUFACTURING METHOD OF THE TRANSISTOR AND THE SEMICONDUCTOR DEVICE - To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided. | 2012-12-20 |
| 20120319109 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads. | 2012-12-20 |
| 20120319110 | SEMICONDUCTOR STRUCTURE HAVING TEST AND TRANSISTOR STRUCTURES - A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading. | 2012-12-20 |
| 20120319111 | THIN-FILM PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCTION THEREOF - A thin-film photoelectric conversion device includes a crystalline germanium photoelectric conversion layer having improved open circuit voltage, fill factor, and photoelectric conversion efficiency for light having a longer wavelength. The photoelectric conversion device comprises a first electrode layer, one or more photoelectric conversion units, and a second electrode layer sequentially stacked on a substrate, wherein each of the photoelectric conversion units comprises a photoelectric conversion layer arranged between a p-type semiconductor layer and an n-type semiconductor layer. At least one of the photoelectric conversion units includes a crystalline germanium photoelectric conversion layer comprising a crystalline germanium semiconductor that is substantially intrinsic or weak n-type and is essentially free of silicon. A first interface layer which is a substantially intrinsic amorphous silicon semiconductor layer is arranged between the p-type semiconductor layer and the crystalline germanium photoelectric conversion layer. | 2012-12-20 |
| 20120319112 | THIN FILM TRANSISTOR, THIN FILM TRANSISTOR PANEL AND METHODS FOR MANUFACTURING THE SAME - A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and a drain electrode and a source electrode on the oxide semiconductor layer and spaced apart from each other. The drain electrode includes a first drain sub-electrode on the oxide semiconductor layer, and a second drain sub-electrode on the first drain sub-electrode. The source electrode includes a first source sub-electrode on the oxide semiconductor layer, and a second source sub-electrode on the first source sub-electrode. The first drain sub-electrode and the first source sub-electrode include gallium zinc oxide (GaZnO), and the second source sub-electrode and the second drain sub-electrode include a metal atom. | 2012-12-20 |
| 20120319113 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - At least part of the oxide semiconductor layer which serves as the channel formation region is thinned by etching and the thickness of the channel formation region is adjusted by the etching. Further, a dopant containing phosphorus (P) or boron (B) is introduced into a thick region of the oxide semiconductor layer to form a source region and a drain region in the oxide semiconductor layer, so that the contact resistance between the source and drain regions and the channel formation region which are connected to each other is reduced. | 2012-12-20 |
| 20120319114 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use, and a semiconductor device including the transistor are provided. In a transistor in which a semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order over an oxide insulating film, an oxide semiconductor stack composed of at least two oxide semiconductor layers having different energy gaps is used as the semiconductor layer. Oxygen and/or a dopant may be introduced into the oxide semiconductor stack. | 2012-12-20 |
| 20120319115 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device including a substrate; a thin film transistor on the substrate, the thin film transistor including an active layer, a gate electrode, and source and drain electrodes that are electrically connected to the active layer; a first resonance layer at the same layer level as the gate electrode; a second resonance layer on the first resonance layer, the second resonance layer being at the same layer level as the source and drain electrodes, and electrically connected to the source and drain electrodes; an insulating layer between the second resonance layer and the first resonance layer; an intermediate layer on the second resonance layer, the intermediate layer including a light-emitting layer; and an opposite electrode on the intermediate layer. | 2012-12-20 |
| 20120319116 | SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SAME, DISPLAY DEVICE, AND ELECTRONIC DEVICE - A semiconductor element includes: an organic semiconductor layer; an electrode disposed on the organic semiconductor layer so as to be in contact with the organic semiconductor layer; and a wiring layer formed separately from the electrode and electrically connected to the electrode. | 2012-12-20 |
| 20120319117 | EL DISPLAY PANEL, EL DISPLAY APPARATUS, AND METHOD OF MANUFACTURING EL DISPLAY PANEL - A light-emitting panel includes a thin film semiconductor that includes a thin film transistor. The thin film transistor includes a gate electrode, a semiconductor layer above the gate electrode, a gate insulating film between the gate electrode and the semiconductor layer, a first electrode electrically connected to the semiconductor layer, and a second electrode. A first interlayer insulating film is above the thin film semiconductor. A gate line and an auxiliary line are above the first interlayer insulating film and between the first interlayer insulating film and a second interlayer insulating film. The gate line is electrically connected to the gate electrode. An electroluminescence emitter includes two electrodes and a light-emitting layer between the two electrodes. One of the two electrodes is connected to the auxiliary line. | 2012-12-20 |
| 20120319118 | DISPLAY DEVICE - One object is to provide a transistor including an oxide semiconductor film which is used for the pixel portion of a display device and has high reliability. A display device has a first gate electrode; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode over the oxide semiconductor film; a second gate insulating film over the source electrode, the drain electrode and the oxide semiconductor film; a second gate electrode over the second gate insulating film; an organic resin film having flatness over the second gate insulating film; a pixel electrode over the organic resin film having flatness, wherein the concentration of hydrogen atoms contained in the oxide semiconductor film and measured by secondary ion mass spectrometry is less than 1×10 | 2012-12-20 |
| 20120319119 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate in accordance with one or more embodiments includes a first line pattern, a first insulation layer, a second line pattern, a color filter layer and a pixel electrode, which are formed on a substrate. The first line pattern includes a gate line and a light-blocking layer. The light-blocking layer has a first opening portion formed in a storage capacitor region. The first insulation layer is formed on the substrate having the first line pattern. The second line pattern is formed on the first insulation layer. The color filter layer is formed on the substrate having the second line pattern, and has a second opening portion overlapping with the storage electrode. The pixel electrode is formed on the substrate having the color filter layer. Thus, short circuits between the storage electrode and the pixel electrode may be prevented. | 2012-12-20 |
| 20120319120 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The disclosure involves a semiconductor device and a manufacturing method thereof. First, a dielectric layer and a stack comprising a Si layer and at least one SiGe layer located on the Si layer are formed in sequence on a substrate. Then the stack and the dielectric layer are patterned to form a dummy gate and a gate dielectric layer, respectively. Next, sidewall spacers are formed on opposite sides of the dummy gate, and source and drain regions with embedded SiGe are formed. Then, the dummy gate is removed to form an opening, in which a gate material such as metal is filled. In RMG techniques, by adopting the stack consisting of Si and SiGe layers as a dummy gate, the method can further increase the compressive stress in the channel of a MOS device and thus improve carrier mobility as compared to traditional polysilicon dummy gate process. | 2012-12-20 |
| 20120319121 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES, AND CORRESPONDING STRUCTURE - A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes. | 2012-12-20 |
| 20120319122 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE INCLUDING BLACK MATRIX-CONTAINING NEUTRAL DENSITY FILM - An organic light-emitting display device including: a substrate; a plurality of pixels each including a first electrode, a second electrode, and an organic emission layer interposed between the first electrode and the second electrode; and a black matrix-containing neutral density (ND) film formed in a direction in which light is emitted from the plurality of pixels. | 2012-12-20 |
| 20120319123 | Display Device and Method of Manufacturing the Same - A display device may include a first substrate comprising a display region and a non-display region surrounding the display region, a first metal wiring formed in the display region of the first substrate, a second metal wiring formed in the non-display region of the first substrate, a sealing member formed on the second metal wiring, and a second substrate disposed on the sealing member so as to face the first substrate. The first metal wiring and the second wiring are made of the same material. | 2012-12-20 |
| 20120319124 | THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME - A display device with a display region and a non-display region surrounding the display region, the display device comprising: a first substrate and a second substrate. The first substrate comprises: a first insulating substrate; a gate line formed on the first insulating substrate; a pixel thin film transistor formed on the display region and electrically connected to the gate line; a pixel electrode electrically connected to the pixel thin film transistor; a gate driver formed on the non-display region and connected to the gate line; and a direct current (DC)/DC converter formed on the non-display region and having a capacitance part. The capacitance part includes: a first capacitance part with a first electrode, a first dielectric layer, and a second electrode; and a second capacitance part with the second electrode, a second dielectric layer, and a third electrode. | 2012-12-20 |
| 20120319125 | SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A first single crystal substrate has a first side surface and it is composed of silicon carbide. A second single crystal substrate has a second side surface opposed to the first side surface and it is composed of silicon carbide. A bonding portion connects the first and second side surfaces to each other between the first and second side surfaces. At least a part of the bonding portion is made of particles composed of silicon carbide and having a maximum length not greater than 1 μm. | 2012-12-20 |
| 20120319126 | Optoelectronic Semiconductor Chip and Method for Fabrication Thereof - An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region the first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region. | 2012-12-20 |
| 20120319127 | CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER - A current aperture vertical electron transistor (CAVET) with ammonia (NH | 2012-12-20 |
| 20120319128 | SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 2012-12-20 |
| 20120319129 | SUBSTRATE, EPITAXIAL LAYER PROVIDED SUBSTRATE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR PRODUCING EPITAXIAL LAYER PROVIDED SUBSTRATE - The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step (S | 2012-12-20 |
| 20120319130 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting device and a method of fabricating the same. The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer. | 2012-12-20 |
| 20120319131 | METHODS OF GROWING NITRIDE SEMICONDUCTORS AND METHODS OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATES - Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate. | 2012-12-20 |
| 20120319132 | SPLIT-GATE STRUCTURE IN TRENCH-BASED SILICON CARBIDE POWER DEVICE - An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region. | 2012-12-20 |
| 20120319133 | OPTICALLY ASSIST-TRIGGERED WIDE BANDGAP THYRISTORS HAVING POSITIVE TEMPERATURE COEFFICIENTS - A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced. | 2012-12-20 |
| 20120319134 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A gate electrode includes a polysilicon film in contact with a gate insulating film, a barrier film provided on the polysilicon film, a metal film provided on the barrier film and made of refractory metal. An interlayer insulating film is arranged so as to cover the gate insulating film and the gate electrode provided on the gate insulating film. The interlayer insulating film has a substrate contact hole partially exposing a silicon carbide substrate in a region in contact with the gate insulating film. A interconnection is electrically connected to the silicon carbide substrate through the substrate contact hole and is electrically insulated from the gate electrode by the interlayer insulating film. | 2012-12-20 |
| 20120319135 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An electrode layer lies on a silicon carbide substrate in contact therewith and has Ni atoms and Si atoms. The number of Ni atoms is not less than 67% of the total number of Ni atoms and Si atoms. A side of the electrode layer at least in contact with the silicon carbide substrate contains a compound of Si and Ni. On a surface side of the electrode layer, C atom concentration is lower than Ni atom concentration. Thus, improvement in electrical conductivity of the electrode layer and suppression of precipitation of C atoms at the surface of the electrode layer can both be achieved. | 2012-12-20 |
| 20120319136 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage. | 2012-12-20 |
| 20120319137 | Electrostatic Discharge Protection Element and Electrostatic Discharge Protection Chip and Method of Producing the Same - An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type. | 2012-12-20 |
| 20120319138 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, in a semiconductor light emitting device, a substrate includes a first surface and a second surface opposite to each other, lateral surfaces intersected with the first surface and the second surface, first regions each provided on the lateral surface, and second regions each provided on the lateral surface. Each of the first regions has a first width and a first roughness. Each of the second regions has a second width smaller than the first width and a second roughness smaller than the first roughness. The first region is provided from a position away from the first surface by a first distance. The first regions and the second regions are alternately arranged. A semiconductor laminated body is provided above the first surface of the substrate, and includes a first semiconductor layer, an active layer and a second semiconductor layer. | 2012-12-20 |
| 20120319139 | ORGANIC ELECTROLUMINESCENT MEMBER AND METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENT ELEMENT - Provided is an organic electroluminescent member comprising: a positive electrode and a negative electrode on a substrate; multiple organic layers which include at least a positive hole transport layer, a light-emitting layer and an electron transport layer, and which are arranged between the positive electrode and the negative electrode; and an electron injection layer arranged between the electron transport layer and the negative electrode. The electron injection layer is formed from at least one selected from the group consisting of alkali metals and compounds containing alkali metals having melting point of less than 90° C., and at least one selected from the group consisting of alkali metals, alkaline earth metals, compounds containing alkali metals, and compounds containing | 2012-12-20 |
| 20120319140 | ORGANIC LIGHT EMITTING DISPLAY MODULE AND PRODUCING METHOD THEREOF - An organic light emitting diode (OLED) display module including a first carrier, a second carrier and an OLED display panel is provided. The second carrier disposed on the first carrier is integrally formed with the first carrier. The OLED display panel is disposed on the second carrier. A continuous joint surface is formed between the first and the second carriers. A producing method of the OLED display module is also provided. | 2012-12-20 |
| 20120319141 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting diode (OLED) display includes a substrate main body, a plurality of organic light emitting elements on the substrate main body, a column spacer on the substrate main body and between two or more of the plurality of organic light emitting elements, and an encapsulation thin film covering at least one of the organic light emitting elements and having regions divided by the column spacer. | 2012-12-20 |
| 20120319142 | GEL UNDERFILL LAYERS FOR LIGHT EMITTING DIODES AND METHODS OF FABRICATING SAME - A light emitting device is fabricated by providing a mounting substrate and an array of light emitting diode dies adjacent the mounting substrate to define gaps. A gel that is diluted in a solvent is applied on the substrate and on the array of light emitting dies. At least some of the solvent is evaporated so that the gel remains in the gaps, but does not completely cover the light emitting diode dies. For example, the gel substantially recedes from the substrate beyond the array of light emitting diode dies and also substantially recedes from an outer face of the light emitting diode dies. Related light emitting device structures are also described. | 2012-12-20 |
| 20120319143 | LIGHT EMITTING DEVICE AND ILLUMINATION APPARATUS INCLUDING SAME - A light emitting device includes a plurality of solid-state light emitting elements mounted on a substrate; and a wavelength converting unit covering the solid-state light emitting elements, the wavelength converting unit containing fluorescent materials. The solid-state light emitting elements include inner solid-state light emitting elements arranged in a central position of the substrate and outer solid-state light emitting elements arranged outwardly of the inner solid-state light emitting elements, and the wavelength converting unit is configured such that a probability that light propagating through the wavelength converting unit is brought into contact with the fluorescent materials in a portion of the wavelength converting unit covering the outer solid-state light emitting elements is lower than a probability that light propagating through the wavelength converting unit is brought into contact with the fluorescent materials in other portions. | 2012-12-20 |
| 20120319144 | DISPLAY PANEL AND DISPLAY DEVICE - Disclosed is a display panel | 2012-12-20 |
| 20120319145 | Non-Common Capping Layer on an Organic Device - A first method comprises providing a plurality of organic light emitting devices (OLEDs) on a first substrate. Each of the OLEDs includes a transmissive top electrode. The plurality of OLEDs includes a first portion of OLEDs and a second portion of OLEDs that is different from the first portion. The first method further includes depositing a first capping layer over at least the first portion of the plurality of OLEDs such that the first capping layer is optically coupled to at least the first portion of the plurality of OLEDs. A second capping layer is deposited over at least the second portion of the plurality of OLEDs such that the second capping layer is optically coupled to the second portion of the plurality of OLEDs but not the first portion of the plurality of OLEDs. | 2012-12-20 |
| 20120319146 | FINE TUNING OF EMISSION SPECTRA BY COMBINATION OF MULTIPLE EMITTER SPECTRA - A first device is provided. The first device includes an anode, a cathode and an emissive layer disposed between the anode and the cathode. The emissive layer includes a first organic emitting material having a first peak wavelength and a second organic emitting material having a second peak wavelength. The emissive layer has a homogenous composition. The second peak wavelength is between 0 and 40 nm greater than the first peak wavelength. | 2012-12-20 |
| 20120319147 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display includes: a substrate; a first electrode on the substrate; a first emission layer on the first electrode; a second emission layer on the first emission layer; a second electrode on the second emission layer; and a light emitting assistance layer selectively positioned between the first emission layer and the second emission layer. | 2012-12-20 |
| 20120319148 | CONFORMAL GEL LAYERS FOR LIGHT EMITTING DIODES AND METHODS OF FABRICATING SAME - Light emitting devices include a light emitting diode die on a mounting substrate and a conformal gel layer on the mounting substrate and/or on the light emitting diode die. The conformal gel layer may at least partially fill a gap between the light emitting diode die and the mounting substrate. A phosphor layer and/or a molded dome may be provided on the conformal gel layer. The conformal gel layer may be fabricated by spraying and/or dispensing the gel that is diluted in the solvent. | 2012-12-20 |
| 20120319149 | Light-Emitting Device Structure and Method for Manufacturing the Same - A light-emitting device structure and a method for manufacturing the same are described. The light-emitting device structure includes a substrate and an illuminant structure. The substrate has a top surface and a lower surface on opposite sides, and two inclined side surfaces on opposite sides. Two sides of each inclined side surface are respectively connected to the top surface and the lower surface. The illuminant structure is disposed on the top surface. | 2012-12-20 |
| 20120319150 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor light emitting device includes: preparing a metal plate including first frames and second frames, the first frames and the second frames being alternately arranged and spaced from each other, a light emitting element being fixed to each of the first frames, the light emitting element being connected to an adjacent one of the second frames via a metal wire; molding a first resin on the metal plate, the first resin covering the first frame, the second frame, and the light emitting element; forming in the first resin a groove defining a resin package including the first frame, the second frame, and the light emitting element; filling a second resin inside the groove; and forming the resin package with an outer edge of the first resin covered with the second resin by cutting the second resin along the groove. | 2012-12-20 |
| 20120319151 | CATHODE FOR ORGANIC LIGHT EMITTING DEVICE AND ORGANIC LIGHT EMITTING DEVICE USING THE CATHODE - In one aspect, a cathode including the first metal layer, the transparent conductive layer formed on the first metal layer, and the second metal layer formed on the transparent conductive layer is applied to the organic light emitting device and thicknesses of the first metal layer, the transparent conductive layer, and the second metal layer are controlled so that the external light reflection of the organic light emitting device is prevented. The cathode may further include the third metal layer formed on the second metal layer. | 2012-12-20 |
| 20120319152 | LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device package, a method of manufacturing the light emitting device package, and a lighting system. The light emitting device package includes a package body, an electrode layer, a reflective layer, a nanopattern metal layer, a light emitting device, and a molding part. The electrode layer is disposed on the package body. The reflective layer is disposed over the electrode layer. The nanopattern metal layer is disposed over the reflective layer. The light emitting device is displayed over the electrode layer. The molding part is disposed over the light emitting device. | 2012-12-20 |
| 20120319153 | ENCAPSULATING SHEET AND OPTICAL SEMICONDUCTOR ELEMENT DEVICE - An encapsulating sheet includes an encapsulating resin layer and a wavelength conversion layer laminated on the encapsulating resin layer. The wavelength conversion layer is formed by laminating a barrier layer formed of a light transmissive resin composition and having a thickness of 200 μm to 1000 μm, and a phosphor layer containing a phosphor. | 2012-12-20 |
| 20120319154 | SILICONE RESIN COMPOSITION, ENCAPSULATING LAYER, REFLECTOR, AND OPTICAL SEMICONDUCTOR DEVICE - A silicone resin composition includes a cage octasilsesquioxane; a polysiloxane containing alkenyl groups at both ends containing an alkenyl group having the number of moles smaller than the number of moles of the hydrosilyl group of the cage octasilsesquioxane; a hydrosilylation catalyst; a hydroxyl group-containing polysiloxane, organohydrogenpolysiloxane, or a polysiloxane containing alkenyl groups at side chain. | 2012-12-20 |
| 20120319155 | LIGHT-EMITTING DEVICE - Disclosed is a light-emitting device that exhibits good color rendering and highly efficiently emits white light in an incandescent bulb color range. The semiconductor light-emitting device ( | 2012-12-20 |
| 20120319156 | NITRIDE SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR - An exemplary nitride-based semiconductor device includes: a nitride-based semiconductor multilayer structure | 2012-12-20 |
| 20120319157 | PHOTOELECTRIC CONVERSION DEVICE - To provide a heterojunction photoelectric conversion device including passivation layers for reducing surface defects of a silicon substrate. The photoelectric conversion device includes a first silicon semiconductor layer which is in contact with one surface of a single crystal silicon substrate; a second silicon semiconductor layer which is in contact with the first silicon semiconductor layer; a third silicon semiconductor layer which is in contact with the other surface of the single crystal silicon substrate; and a fourth silicon semiconductor layer which is in contact with the third silicon semiconductor layer. Further, the fluorine concentration in the first silicon semiconductor layer and the third silicon semiconductor layer is lower than or equal to 1×10 | 2012-12-20 |
| 20120319158 | LED Light Emitting Module and Manufacturing Method thereof - An LED light-emitting module and a manufacturing method thereof are provided. The LED light-emitting module comprises a substrate provided with at least one LED core, wherein the substrate has an interlayer made of ceramic materials and coated with copper foils at two sides; the copper foil at one side of the interlayer is etched to form at least one soldering pad and a conductor; the number of the soldering pads is equal to that of the LED cores; each LED core is fixed on one soldering pad; and one pole of the LED core is welded on the soldering pad while the other pole is connected with an adjacent soldering pad or the conductor through a gold thread. | 2012-12-20 |
| 20120319159 | SUBSTRATE FOR LIGHT-EMITTING ELEMENT, METHOD FOR MANUFACTURING THE SAME AND LIGHT-EMITTING DEVICE - There is provided a substrate for light-emitting element, including a mounting surface on which a light-emitting element is to be mounted, the mounting surface being one of two opposed main surfaces of the substrate. The substrate of the present invention is provided with a protection element for the light-emitting element, the protection element comprising a voltage-dependent resistive layer embedded in a body of the substrate, and comprising a first electrode and a second electrode each of which is in connection with the voltage-dependent resistive layer wherein the light-emitting element is to be mounted such that it is positioned in an overlapping relation with the voltage-dependent resistive layer. | 2012-12-20 |
| 20120319160 | Method for Reducing Stress in Epitaxial Growth - A device and method for making the same are disclosed. The device includes a substrate having a first TEC, a stress relief layer overlying the substrate, and crystalline cap layer. The crystalline cap layer overlies the stress relief layer. The cap layer has a second TEC different from the first TEC. The stress relief layer includes an amorphous material that relieves stress between the crystalline substrate and the cap layer arising from differences in the first and second TECs at a growth temperature at which layers are grown epitaxially on the cap layer. The device can be used to construct various semiconductor devices including GaN LEDs that are fabricated on silicon or SiC wafers. The stress relief layer is generated by converting a layer of precursor material on the substrate after the cap layer has been grown to a stress-relief layer. | 2012-12-20 |
| 20120319161 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING DEVICE WAFER - According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The method can include forming a nitride semiconductor layer including a light emitting layer on a first substrate having an unevenness, bonding the nitride layer to a second substrate, and separating the first substrate from the nitride layer by irradiating the nitride layer with light. The forming the nitride layer includes leaving a cavity in a space inside a depression of the unevenness while forming a thin film on the depression. The film includes a same material as part of the nitride layer. The separating includes causing the film to absorb part of the light so that intensity of the light applied to a portion of the nitride layer facing the depression is made lower than intensity of the light applied to a portion facing a protrusion of the unevenness. | 2012-12-20 |
| 20120319162 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING APPARATUS - Provided is a method for manufacturing a nitride semiconductor device, including the steps of: forming an AlNO buffer layer containing at least aluminum, nitrogen, and oxygen on a substrate; and forming a nitride semiconductor layer on the AlNO buffer layer, wherein, in the step of forming the AlNO buffer layer, the AlNO buffer layer is formed by a reactive sputtering method using aluminum as a target in an atmosphere to and from which nitrogen gas and oxygen gas are continuously introduced and exhausted, and the atmosphere is an atmosphere in which a ratio of a flow rate of the oxygen gas to a sum of a flow rate of the nitrogen gas and the flow rate of the oxygen gas is not more than 0.5%. | 2012-12-20 |
| 20120319163 | SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE BIPOLAR TRANSISTOR AND DIODE - A semiconductor device includes an IGBT forming region and a diode forming region. The IGBT forming region includes an IGBT operating section that operates as an IGBT and a thinned-out section that does not operate as an IGBT. The IGBT operating section includes a channel region, and the thinned-out section includes a first anode region. The diode forming region includes a second anode region. When an area density is defined as a value calculated by integrating a concentration profile of second conductivity type impurities in each of the channel region, the first anode region, and the second anode region in a depth direction, an area density of the channel region is higher than an area density of the first anode region and an area density of the second anode region. | 2012-12-20 |
| 20120319164 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device that has a rectification element includes a semiconductor substrate, a first well region of a first conductivity type formed on the semiconductor substrate, a second well region of a second conductivity type formed on the semiconductor substrate, and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction. In the semiconductor device, the rectification element includes a cathode region, an anode region, a well contact region, and a trigger region that are configured using fins. These regions are connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor. | 2012-12-20 |
| 20120319165 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - Object of the invention is to reduce the on resistance between source and drain of a nitride semiconductor device. Between a nitride semiconductor layer lying between source and drain regions and a nitride semiconductor layer serving as an underlying layer, formed is a material having an electron affinity greater than that of these nitride semiconductor layers and having a lattice constant greater than that of the nitride semiconductor layer serving as an underlying layer. As a result, an electron density distribution of a channel formed below a gate insulating film and that of a two-dimensional electron gas formed in a region other than the gate portion, when a gate voltage is applied, can be made closer in the depth direction, leading to reduction in on resistance. | 2012-12-20 |
| 20120319166 | TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE - A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base. | 2012-12-20 |
| 20120319167 | Mask-less and Implant Free Formation of Complementary Tunnel Field Effect Transistors - A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric. | 2012-12-20 |
| 20120319168 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method therefor includes a Σ-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a Σ-shaped recess. | 2012-12-20 |
| 20120319169 | CMOS COMPATIBLE METHOD FOR MANUFACTURING A HEMT DEVICE AND THE HEMT DEVICE THEREOF - A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode. | 2012-12-20 |
| 20120319170 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING ELECTRONIC DEVICE - Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element. | 2012-12-20 |
| 20120319171 | SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND A METHOD OF PRODUCING A SEMICONDUCTOR WAFER - A semiconductor wafer includes a base wafer, a first crystal layer, a second crystal layer and a third crystal layer. The first crystal layer has a first surface having a same orientation as the base wafer, and a second surface having a different orientation from the first surface, the second crystal layer has a third surface having the same orientation as the first surface, and a fourth surface having the same orientation as the second surface, the third crystal layer is in contact with a part of the third surface and the fourth surface. A thickness ratio of the second crystal layer in a region adjoining the first surface to a region adjoining the second surface is larger than a thickness ratio of the third crystal layer in a region adjoining the third surface to a region adjoining the fourth surface. | 2012-12-20 |
| 20120319172 | CHARGE-TRAP BASED MEMORY - Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described. | 2012-12-20 |
| 20120319173 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is. | 2012-12-20 |
| 20120319174 | CMOS COMPATIBLE MEMS MICROPHONE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a CMOS compatible MEMS microphone, comprising: an SOI substrate, wherein a CMOS circuitry is accommodated on its silicon device layer; a microphone diaphragm formed with a part of the silicon device layer, wherein the microphone diaphragm is doped to become conductive; a microphone backplate including CMOS passivation layers with a metal layer sandwiched and a plurality of through holes, provided above the silicon device layer, wherein the plurality of through holes are formed in the portions thereof opposite to the microphone diaphragm, and the metal layer forms an electrode plate of the backplate; a plurality of dimples protruding from the lower surface of the microphone backplate opposite to the diaphragm; and an air gap, provided between the diaphragm and the microphone backplate, wherein a spacer forming a boundary of the air gap is provided outside of the diaphragm or on the edge of the diaphragm; wherein a back hole is formed to be open in substrate underneath the diaphragm so as to allow sound pass through, and the microphone diaphragm is used as an electrode plate to form a variable capacitive sensing element with the electrode plate of the microphone backplate. | 2012-12-20 |
| 20120319175 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A transistor in which an electron state at an interface between an oxide semiconductor film and an underlayer film in contact with the oxide semiconductor film is favorable is provided. A value obtained by dividing a difference between nearest neighbor interatomic distance of the underlayer film within the interface and a lattice constant of the semiconductor film by the nearest neighbor interatomic distance of the underlayer film within the interface is less than or equal to 0.15. For example, an oxide semiconductor film is deposited over an underlayer film which contains stabilized zirconia which has a cubic crystal structure and has the (111) plane orientation, whereby the oxide semiconductor film including a crystal region having a high degree of crystallization can be provided directly on the underlayer film. | 2012-12-20 |
| 20120319176 | GATED-VARACTORS - In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region. | 2012-12-20 |
| 20120319177 | JUNCTION FIELD EFFECT TRANSISTOR, INTEGRATED CIRCUIT FOR SWITCHING POWER SUPPLY, AND SWITCHING POWER SUPPLY - A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors. | 2012-12-20 |
| 20120319178 | DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS - A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device. | 2012-12-20 |
| 20120319179 | METAL GATE AND FABRICATION METHOD THEREOF - A metal gate includes a substrate, a gate dielectric layer, a work function metal layer, an aluminum nitride layer and a stop layer. The gate dielectric layer is located on the substrate. The work function metal layer is located on the gate dielectric layer. The aluminum nitride layer is located on the work function metal layer. The stop layer is located on the aluminum nitride layer. | 2012-12-20 |
| 20120319180 | LARGE DIMENSION DEVICE AND METHOD OF MANUFACTURING SAME IN GATE LAST PROCESS - An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a gate structure disposed over a substrate; a source region and a drain region disposed in the substrate, wherein the gate structure interposes the source region and the drain region; and at least one post feature embedded in the gate structure. | 2012-12-20 |
| 20120319181 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions. Accordingly, the present invention further provides a method for manufacturing a semiconductor structure, which is favorable for reducing the contact resistance at the source/drain regions, enhancing the device performance, lowering the cost and simplifying the manufacturing process. | 2012-12-20 |
| 20120319182 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device production method includes: forming in a silicon substrate first and second region of first and second conductivity type in contact with each other; forming a gate electrode above the first and the second region; forming an insulation film covering part of the gate electrode and part of the second region; forming a source region and a drain region of the second conductivity type; forming interlayer insulation film covering the gate electrode and the insulation film; and forming in the interlayer insulation film first, second and third contact hole reaching the source region, the drain region, and the gate electrode, respectively, and at least one additional hole reaching the insulation film, and forming a conductive film in the first, the second, and the third contact hole and the additional hole to form first, second and third electrically conductive via and electrically conductive member. | 2012-12-20 |
| 20120319183 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer. | 2012-12-20 |
| 20120319184 | METHODS AND DEVICES FOR SHIELDING A SIGNAL LINE OVER AN ACTIVE REGION - A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line. | 2012-12-20 |
| 20120319185 | NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced. | 2012-12-20 |
| 20120319186 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for forming a memory device includes: forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings. | 2012-12-20 |
| 20120319187 | SEMICONDUCTOR DEVICE - For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level. | 2012-12-20 |
| 20120319188 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP AND A PROCESS OF FORMING THE SAME - An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device. | 2012-12-20 |
| 20120319189 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type. | 2012-12-20 |
| 20120319190 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities. | 2012-12-20 |
| 20120319191 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE - Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases. | 2012-12-20 |
| 20120319192 | Gate Structures - An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening. | 2012-12-20 |
| 20120319193 | MANUFACTURING OF A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE - The disclosed method of manufacturing ( | 2012-12-20 |
| 20120319194 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - A trench gate transistor whose gate changes depth intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The first offset region and the second offset region are shallower where they contact the device isolation film than is the device isolation film in those areas. The first and second offset regions nevertheless extend below the bottom of the trench. | 2012-12-20 |
