51st week of 2013 patent applcation highlights part 67 |
Patent application number | Title | Published |
20130339702 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 2013-12-19 |
20130339703 | RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 2013-12-19 |
20130339704 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 2013-12-19 |
20130339705 | RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION - Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted. | 2013-12-19 |
20130339706 | PROCESSOR ASSIST FACILITY - An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken. | 2013-12-19 |
20130339707 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 2013-12-19 |
20130339708 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 2013-12-19 |
20130339709 | TRANSACTION ABORT INSTRUCTION - A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. | 2013-12-19 |
20130339710 | METHOD AND SYSTEM FOR POLLING NETWORK CONTROLLERS - Improving the performance of multitasking processors are provided. For example, a subset of M processors within a Symmetric Multi-Processing System (SMP) with N processors is dedicated for a specific task. The M (M>0) of the N processors are dedicate to a task, thus, leaving (N-M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher network performance. | 2013-12-19 |
20130339711 | METHOD AND APPARATUS FOR RECONSTRUCTING REAL PROGRAM ORDER OF INSTRUCTIONS IN MULTI-STRAND OUT-OF-ORDER PROCESSOR - A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence. | 2013-12-19 |
20130339712 | SERVICE-PROCESSOR-CENTRIC COMPUTER ARCHITECTURE AND METHOD OF OPERATION THEREOF - A computer system and a method of operating a service-processor-centric computer system. In one embodiment, the computer system includes: (1) a CPU configured to issue control signals and (2) a service processor configured for intercepting and handling the control signals, the handling including delaying, modifying or ignoring the control signals, the service processor further configuring for issuing highest-priority control signals. | 2013-12-19 |
20130339713 | ELECTRONIC DEVICE AND METHOD FOR VERIFYING FIRMWARE OF THE ELECTRONIC DEVICE - In a method for verifying firmware of an electronic device, the electronic device includes a baseboard management controller (BMC) for storing a BMC firmware, and a basic input-output system (BIOS) for storing a BIOS firmware. The method writes a first verification code into the BMC firmware, and writes a second verification code into the BIOS firmware. The method writes the BMC firmware into the BMC, and writes the BIOS firmware into the BIOS. The method further triggers the electronic device to power off if the first verification code of the BMC firmware is not identical to the second verification code of the BIOS firmware, and boots an operating system of the electronic device if the first verification code of the BMC firmware is identical to the second verification code of the BIOS firmware. | 2013-12-19 |
20130339714 | System and Method for Providing a Processing Node with Input/Output Functionality Provided by an I/O Complex Switch - A processing node of a server rack includes a processor to generate processing node management requests and to process responses to the node management requests, and a communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor. | 2013-12-19 |
20130339715 | SYSTEM AND METHOD FOR WIPING ENCRYPTED DATA ON A DEVICE HAVING FILE-LEVEL CONTENT PROTECTION - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for erasing user data stored in a file system. The method includes destroying all key bags containing encryption keys on a device having a file system encrypted on a per file and per class basis, erasing and rebuilding at least part of the file system associated with user data, and creating a new default key bag containing encryption keys. Also disclosed herein is a method of erasing user data stored in a remote file system encrypted on a per file and per class basis. The method includes transmitting obliteration instructions to a remote device, which cause the remote device to destroy all key bags containing encryption keys on the remote device, erase and rebuild at least part of the file system associated with user data, and create on the remote device a new default key bag containing encryption keys. | 2013-12-19 |
20130339716 | PORTABLE DESKTOP DEVICE AND METHOD OF HOST COMPUTER SYSTEM HARDWARE RECOGNITION AND CONFIGURATION - A portable desktop device and method for host computer system hardware recognition and configuration are provided. The portable desktop device causes on a first boot, the host computer system to recognize hardware devices connected thereto, and to configure hardware configuration files of the portable desktop O/S in accordance with the recognized hardware. Once the hardware configuration files have been configured, the system is rebooted. On the second boot, the host computer determines that the portable desktop has been configured for its hardware, and initiates start-up of the portable desktop. | 2013-12-19 |
20130339717 | Virtualized Boot Block with Discovery Volume - A file system independent virtualized boot block with discovery volume and cover files renders a volume visible when accessed by an accessing system which differs from a source system. For example, a downlevel operating system recognizes that data is present on a volume created in an uplevel operating system, even where the uplevel data itself may not be accessible. | 2013-12-19 |
20130339718 | INFORMATION PROCESSING DEVICE AND METHOD FOR CONTROLLING INFORMATION PROCESSING DEVICE - A basic input/output system (BIOS) storage unit stores therein a BIOS. An operating system (OS) storage unit stores therein a plurality of OSs. A boot control unit sequentially starts the OSs stored in the OS storage unit. When each of the OSs booted by the boot control unit starts up, a boot information acquisition unit acquires boot information transferred between the OS and the BIOS. A regression analysis processing unit compares the boot information acquired by the boot information acquisition unit with expected values which are predetermined values for the boot information to determine whether the boot information coincides with the expected values. | 2013-12-19 |
20130339719 | APPARATUS AND METHOD FOR CONTROLLING MODE SWITCH - There is provided an apparatus and method for controlling mode switching in a terminal. A switch unit outputs a signal for mode switching of the terminal in response to a touch operation of a stylus pen, and a controller switches a mode of the terminal in response to the signal output from the switch unit. | 2013-12-19 |
20130339720 | AUTOMATIC SLEEP MODE PREVENTION OF MOBILE DEVICE IN CAR HOLDER - A mobile communications device includes at least one application programmer interface (API) to provide status information from components of the device, where the status information is indicative of the device being operated in an automobile, and a decision unit to modify at least one of screen backlighting and device locking in accordance with a driving state determined in accordance with at least the status information. A method for preventing sleep mode in a mobile communications device includes detecting active charging of the device, establishing that the device is in an automotive vehicle, based on the detecting and establishing, determining that a charging/vehicle state exists; and when the charging/vehicle state exists, instructing a screen backlight of the device to remain on, and disabling key locking for the mobile communications device. | 2013-12-19 |
20130339721 | DATA REWRITING SUPPORT SYSTEM AND DATA REWRITING SUPPORT METHOD FOR VEHICLE CONTROL APPARATUS - A data rewriting support system for a vehicle control apparatus including: a downloading device that downloads data relating to a control program or control data used to control the vehicle control apparatus from outside; and a rewriting data transmission control device that obtains rewriting data on the basis of the data downloaded by the downloading device and transmits the rewriting data to the vehicle control apparatus connected communicably to a vehicle network, wherein the rewriting data transmission control device monitors a transmission condition of data transmitted to the vehicle network and transmits the rewriting data to the vehicle network in accordance with the monitored data transmission condition. | 2013-12-19 |
20130339722 | METHOD FOR PROTECTING DATA USED IN CLOUD COMPUTING WITH HOMOMORPHIC ENCRYPTION - A method for protection of cloud computing includes homomorphic encryption of data. Partially or fully homomorphic encryption allows for data within the cloud to be processed without decryption. A partially or fully homomorphic encryption is provided. The proposed scheme can be used with both an algebraic and analytical approaches. A cloud service is implemented on a server. A client encrypts data using fully homomorphic encryption and sends it to the server. The cloud server performs computations without decryption of the data and returns the encrypted calculation result to the client. The client decrypts the result, and the result coincides with the result of the same calculation performed on the initial plaintext data. | 2013-12-19 |
20130339723 | CLOSED NETWORK PRESENTATION - A system, related methods and computer readable memory device for delivering a presentation are provided. In one example, a method includes establishing a wireless network access point that creates a closed wireless network. An encrypted communication session is established via the closed wireless network with a plurality of client computing devices that each comprise a display. Each of the client computing devices is communicatively coupled to a virtual network server on the host computing device. Frame buffer data is retrieved from a storage subsystem of the host computing device. The frame buffer data is sent to each of the client computing devices to modify the display of the devices. | 2013-12-19 |
20130339724 | SELECTIVE ENCRYPTION IN MOBILE DEVICES - A method, product and system for selective encryption in a mobile device. The method comprising: selectively encrypting requests issued by the mobile device, wherein said selectively encrypting comprises: obtaining a request issued by an application executed by the mobile device, the request having one or more characteristics, the request has a destination; determining, based on the one or more characteristics, whether to encrypt the request; and in response to a determination to encrypt the request, re-routing the request to be transmitted to the destination through a secure channel; whereby the request is encrypted regardless of the destination being a priori associated with the secure channel. | 2013-12-19 |
20130339725 | METHOD AND SYSTEM FOR MONITORING ENCRYPTED DATA TRANSMISSIONS - A method for efficiently decrypting asymmetric SSL pre-master keys is divided into a key agent component that runs in user mode, and an SSL driver running in kernel mode. The key agent can take advantage of multiple threads for decoding keys in a multi-processor environment, while the SSL driver handles the task of symmetric decryption of the SSL encrypted data stream. The method is of advantage in applications such as firewalls with deep packet inspection in which all encrypted data traffic passing through the firewall must be decrypted for inspection. | 2013-12-19 |
20130339726 | FILE SERVER APPARATUS AND FILE SERVER SYSTEM - According to one embodiment, a reception unit receives post-office box's encrypted data, which is obtained by encrypting the data by using a post-office box's public key, from the sending apparatus. A re-encryption key storage unit stores a re-encryption key used for re-encrypting the post-office box's encrypted data into recipient's encrypted data, which is obtained by encrypting the data using a recipient's public key that is different from the post-office box's public key. A re-encryption unit re-encrypts the received post-office box's encrypted data to the recipient's encrypted data using the re-encryption key stored in the re-encryption key storage unit. A transmission unit transmits the re-encrypted recipient's encrypted data to the receiving apparatus. | 2013-12-19 |
20130339727 | WAN Optimization Without Required User Configuration for WAN Secured VDI Traffic - In order for intermediary WAAS devices to process and accelerate ICA traffic, they must decrypt the ICA traffic in order to examine it. Disclosed is a mechanism by which the ICA traffic may be re-encrypted for transport over the WAN in a manner that does not require explicit configuration by the administrator of the WAAS devices. For example, VDI traffic may be intercepted and all data redundancy elimination messages may be encrypted and sent to a peer network device. | 2013-12-19 |
20130339728 | SECURE PRODUCT-SUM COMBINATION SYSTEM, COMPUTING APPARATUS, SECURE PRODUCT-SUM COMBINATION METHOD AND PROGRAM THEREFOR - The efficiency of multiplication in secure function computation is increased to make the secret function computation faster than before. Three or more computing apparatuses cooperate to generate a secret value of a random number, perform secure function computation for secret values of arbitrary values by using a function including addition and multiplication to compute concealed function values, and compute a secret value. If the secret value is [0], a concealed function value is output; otherwise, information indicating that tampering has been detected is output. | 2013-12-19 |
20130339729 | NETWORK BASED MANAGEMENT OF PROTECTED DATA SETS - A system that includes an account management module configured to maintain protected accounts. For instance, a particular protected account includes a protected data set that is not readable outside of the system, and perhaps not even readable outside of the account. The particular data set corresponds to a particular entity assigned to the particular account and that includes keys corresponding to the particular entity. A security processor uses at least some of the plurality of keys to perform cryptographic processes in response to one or more trusted execution environment commands received from the particular entity. | 2013-12-19 |
20130339730 | DEVICE AUTHENTICATION USING RESTRICED MEMORY - A device includes a first memory area being used to store a first key and unique secret identification information, the first memory area being restricted from being read and written from outside; a second memory area being used to store encrypted secret identification information generated by encrypting the secret identification information, the second memory area being allowed to be read-only from outside; a third memory area being readable and writable from outside; a first data generator configured to generate a second key by using the first key; a second data generator configured to generate a session key by using the second key; and a one-way function processor configured to generate an authentication information by processing the secret identification information with the session key in one-way function operation, wherein the encrypted secret identification information and the authentication information are output to outside. | 2013-12-19 |
20130339731 | DEVICE-SPECIFIC SECURE LICENSING - Device-specific secure software licensing techniques are disclosed. In various embodiments, a key/token pair associated with a client requesting license validation is received. It is determined whether the key/token pair matches an entry in a store of currently valid key/token pairs. An affirmative response is sent in the event the key/token pair matches a corresponding entry in the store of currently valid key/token pairs. | 2013-12-19 |
20130339732 | DEVICE - According to one embodiment, a device includes a cell array including an ordinary area, a hidden area, and an identification information record area in which identification information which defines a condition for accessing the hidden area is recorded. An authentication circuit performs authentication. A sensing circuit recognizes information recorded in the identification information storage area, determines the information recorded in the identification information record area when an access request selects the hidden area, validates an access to the hidden area when determined that the identification information is recorded, and invalidates an access to the hidden area when determined that the identification information is not recorded. | 2013-12-19 |
20130339733 | DEVICE - According to one embodiment, a device includes a cell array including an ordinary area, a hidden area, and an identification information record area in which identification information which defines a condition for accessing the hidden area is recorded. An authentication circuit performs authentication. A sensing circuit recognizes information recorded in the identification information storage area, determines the information recorded in the identification information record area when an access request selects the hidden area, validates an access to the hidden area when determined that the identification information is recorded, and invalidates an access to the hidden area when determined that the identification information is not recorded. | 2013-12-19 |
20130339734 | Secure Method and System for Remote Field Upgrade of Power Device Firmware - To protect software to be transferred to programmable electronic devices, a management system for programmable electronic devices includes a plurality of electronic devices, each identified by at least one unique identification parameter and containing at least one encryption key. The system also includes at least one protected site in which a protected database resides, and in which the unique identification parameter the encryption key are stored for each electronic device. A server is programmed to receive a request for transmission of software from a device and to generate an encrypted version of said software, using the encryption key associated in the database with the unique identification parameter (ID) of the device (57) that has requested the transmission of said software. | 2013-12-19 |
20130339735 | AUTHENTICATION METHOD - According to one embodiment, a authentication method comprising: generating a second key by the first key, the first key being stored in a memory and being prohibited from being read from outside; generating a session key by the second key; generating first authentication information, the secret identification information stored in a memory and being prohibited from being read from outside; transmitting encrypted secret identification information to an external device and receiving second authentication information from the external device, the encrypted secret identification information stored in a memory and readable, the second authentication information generated based on the encrypted secret identification information; and determining whether the first authentication information and the second authentication information match. | 2013-12-19 |
20130339736 | PERIODIC PLATFORM BASED WEB SESSION RE-VALIDATION - Systems, apparatus and methods for periodically validating the identity of two or more machines that have established a secure communication connection over a network. A client may initiate a secure communication session with a server by providing an identification certificate. Upon establishing a secure connection with the server, the client may periodically reaffirm its identity by sending a secure heartbeat message that includes a timestamp offset and a client identifier in order to keep the connection open. The server can require periodic receipt of the secure heartbeat message in order to maintain the secure communication session. The client identifier may include a code or value based on a unique physical attribute of the client. The timestamp offset may be calculated by the client based on a timestamp provided by the server. | 2013-12-19 |
20130339737 | System for Efficiently Handling Cryptographic Messages Containing Nonce Values in a Wireless Connectionless Environment - A system for determining the validity of a received cryptographic message while ensuring for out-of-order messages is utilized to provide for secure communications among peers in a network. In particular, a secure communication module may be configured to accept the cryptographic message in response to a received nonce value of the received message is greater than the largest nonce value yet seen, the secure communication module may be configured to compare the received nonce value with a nonce value acceptance window. If the received nonce value falls outside the nonce acceptance window, the secure communication module may be further configured to reject the received message and assume that a replay attack has been detected. If the received nonce value falls within the nonce acceptance window, the secure communication module may be further configured to determine if the received nonce value has been seen before by comparing the received nonce value with a replay window mask. If the received nonce has been seen before, the secure communication module may be further configured to reject the received message and assume a replay attack. Otherwise, the secure communication module may be further configured to accept the message and add the received nonce value to the replay window mask. | 2013-12-19 |
20130339738 | Method for data privacy in a fixed content distributed data storage - A storage cluster of symmetric nodes includes a data privacy scheme that implements key management through secret sharing. The protection scheme preferably is implemented at install time. At install, an encryption key is generated, split, and the constituent pieces written to respective archive nodes. The key is not written to a drive to ensure that it cannot be stolen. Due to the secret sharing, any t of the n nodes must be present before the cluster can mount the drives. To un-share the secret, a process runs before the cluster comes up. It contacts as many nodes as possible to attempt to reach a sufficient t value. Once it does, the process un-shares the secret and mounts the drives locally. Given bidirectional communication, this mount occurs more or less at the same time on all t nodes. Once the drives are mounted, the cluster can continue to boot as normal. | 2013-12-19 |
20130339739 | DEVICE FOR AND METHOD OF HANDLING SENSITIVE DATA - A device for handling sensitive data comprises a first integrated circuitry forming a first trust zone and a second integrated circuitry forming a second trust zone. The first circuitry comprises a secure processing unit adapted for processing sensitive data, the second circuitry comprises a persistent memory area within its trust zone for storing sensitive data. The second integrated circuitry is separated from the first integrated circuitry, the processing unit of the first circuitry transfers sensitive data from the first trust zone to the second trust, the second circuitry transfers sensitive data stored in its persistent memory area to the processing unit of the first trust zone. The first and the second integrated circuitry comprise crypto means for securely transferring sensitive data based on a symmetrical crypto method using a secure key. The second integrated circuitry comprises means for initiating a new key generation to replace the active secure key. | 2013-12-19 |
20130339740 | MULTI-FACTOR CERTIFICATE AUTHORITY - Disclosed herein is a certificate authority server configured to provide multi-factor digital certificates. A processor readable medium may include a plurality of instructions configured to enable a certificate authority server of a certificate authority, in response to execution of the instructions by a processor, to receive a request to provide a multi-factor digital security certificate by digitally signing a certificate request having a plurality of factors and a cryptographic key, wherein a first of the plurality of factors is an identifier of a device and a second of the plurality of factors is an identifier of a user of the device. The instructions are also configured to enable the certificate authority server to associate the cryptographic key with the plurality of factors and issue the digital security certificate based on the certificate request. Also disclosed is a method of using a multi-factor digital certificate as part of the authorization process to implicitly bind the plurality of factors. Other embodiments may be described and claimed. | 2013-12-19 |
20130339741 | AUTHENTICATION METHOD - According to one embodiment, a authentication method comprising: generating a second key by the first key, the first key being stored in a memory and being prohibited from being read from outside; generating a session key by the second key; generating first authentication information, the secret identification information stored in a memory and being prohibited from being read from outside; transmitting encrypted secret identification information to an external device and receiving second authentication information from the external device, the encrypted secret identification information stored in a memory and readable, the second authentication information generated based on the encrypted secret identification information; and determining whether the first authentication information and the second authentication information match. | 2013-12-19 |
20130339742 | SYSTEMS, METHODS AND APPARATUSES FOR SECURE TIME MANAGEMENT - The systems, methods and apparatuses described herein provide a computing environment that includes secure time management. An apparatus according to the present disclosure may comprise a non-volatile storage to store a synchronization time and a processor. The processor may be configured to generate a request for a current time, transmit the request to a trusted timekeeper, receive a digitally signed response containing a current, real-world time from the trusted timekeeper, verify the digital signature of the response, verify that the response is received within a predefined time, compare a nonce in the request to a nonce in the response, determine that the current, real-world time received from the trusted timekeeper is within a range of a current time calculated at the apparatus and update the synchronization time with the current, real-world time in the response. | 2013-12-19 |
20130339743 | MESSAGE SENDING/RECEIVING METHOD - Provided is a message sending method for sending a message by a process of a computer including a processor and a memory. The method includes the steps of: randomizing a signature generation key sk_s with a random number r to calculate a randomized signature generation key sk′_s=SigningKeyRandomize(sk_s, r); encrypting the random number r with a public encryption key pk_e to calculate an encrypted random number R=Enc(pk_e, r); signing a message m with the randomized signature generation key sk′_s to calculate a signed message s′=Sign(sk′_s, m); and sending the signed message s′ and the encrypted random number R to a recipient, where sk_s represents the secret signature generation key of a sender of the message m, pk_e represents the public encryption key of the recipient, r represents the random number, s represents a signature, Sign represents a signature generation function, s=Sign(sk_s, m) represents a signature for the message m, SigningKeyRandomize represents a function for randomizing the secret signature generation key sk_s, and Enc represents an encryption function. | 2013-12-19 |
20130339744 | DEVICE - According to one embodiment, a device includes
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20130339745 | CONTROLLING AN ANALYSIS SYSTEM OF BIOLOGICAL SAMPLES - A method for controlling an analysis system is presented. The method comprises receiving, by an encryption unit, authentication data of a user. In the case of a successful authentication, a user-specific security code is generated by the encryption unit. The security code is outputted by the encryption unit to the authenticated user. The security code and the user-ID are received by an authentication unit coupled to the analysis system via a user-interface coupled to the authentication unit. The security code is decrypted by the authentication unit. If the decrypted security code matches with the user-ID, the user is authenticated at the authentication unit and an authentication signal is generated by the authentication unit for permitting the user to initialize at least one function of the analysis system. | 2013-12-19 |
20130339746 | SECURE PASSWORD MANAGEMENT SYSTEMS, METHODS AND APPARATUSES - The systems, methods and apparatuses described herein provide a computing environment for authenticating a user. An apparatus according to the present disclosure may comprise a non-volatile storage, a user interface, and a password engine. The password engine is configured to retrieve two or more predetermined prompts from the non-volatile storage, present the two or more predetermined prompts on the user interface to a user in a random order, receive a first set of input(s) in response to the two or more predetermined prompts, create an encryption keyword from the received first set of input(s) according to an original order of the two or more predetermined prompts stored in the non-volatile storage, and use the encryption keyword to authenticate the user. | 2013-12-19 |
20130339747 | Secure Identification Card (SID-C) System - In accordance with one embodiment of the present invention a secure electronic identification device is presented. The secure electronic identification device includes a display mode for displaying government furnished information, a display mode for displaying user furnished information, and a public display mode for displaying public information. | 2013-12-19 |
20130339748 | PERSONAL BIOMETRIC SYSTEM AND METHOD FOR WIRELESS DEVICE CONTROL - In one embodiment, a biometric device includes a first portion having a processor and a second portion releasably coupled to the first portion. The processor is configured to determine whether the second portion is coupled to the first portion. The processor is configured to operate in an enrollment mode while the first portion is coupled to the second portion and operate in an authentication mode while the first portion is decoupled from the second portion. In one embodiment, a method of biometric authentication includes, first, coupling two portions of a biometric device to put it into an enrollment mode, collecting a biometric sample, and generating and storing a corresponding enrollment code; and second, decoupling the two portions of the biometric device, collecting a biometric sample, generating a corresponding access code, and granting or denying access to an asset based on comparison of the enrollment code and the access code. | 2013-12-19 |
20130339749 | DISTRIBUTED BIOMETRIC DATA STORAGE AND VALIDATION - Systems and methods for securely storing biometric data for use in a biometric identification system, and accessing such data for validating individuals, are described. One method of securely storing biometric data for use in a biometric identification system includes receiving a template describing biometric data that identifies a person. The method also includes encrypting the template using an encryption key, and separating the encrypted template into at least first and second portions, wherein both the first portion and the second portion are required to reconstruct the template. The method also includes storing the first portion in a database and storing the second portion on an access device issued to the person. | 2013-12-19 |
20130339750 | REDUCING DECRYPTION LATENCY FOR ENCRYPTION PROCESSING - In a storage system, using a pool of encryption processing cores, the encryption processing cores are assigned to process either encryption operations, decryption operations, and decryption and encryption operations, that are scheduled for processing. A maximum number of the encryption processing cores are set for processing only the decryption operations, thereby lowering a decryption latency. A minimal number of the encryption processing cores are allocated for processing the encryption operations, thereby increasing encryption latency. Upon reaching a throughput limit for the encryption operations that causes the minimal number of the plurality of encryption processing cores to reach a busy status, the minimal number of the plurality of encryption processing cores for processing the encryption operations is increased. | 2013-12-19 |
20130339751 | Method for Querying Data in Privacy Preserving Manner Using Attributes - A client queries a set of encrypted data instances located at a server with a query attribute of the client. The set of encrypted data instances is associated with a set of ciphertexts, wherein a ciphertext is an encrypted function of a representation of a corresponding data instance and a data instance attribute extracted from the corresponding data instance. The client decrypts the ciphertext from the set of ciphertexts based on a distance function of the query attribute and the data instance attribute to produce the representation, and accesses the corresponding data instance using the representation. | 2013-12-19 |
20130339752 | REMOTE CIRCUIT LOCKING SWITCH SYSTEM - A method and apparatus for remotely controlling access to the components of an optically interconnected information processing infrastructure is presented. Access to the infrastructure is controlled independently of the infrastructure operating system. | 2013-12-19 |
20130339753 | ENCRYPTION PROCESSING DEVICE, ENCRYPTION PROCESSING METHOD, AND PROGRAM - Miniaturization of an encryption processing configuration is achieved. Included is an encryption processing unit configured to divide and input configuration bits of data to be data processed into a plurality of lines, and to repeatedly execute data conversion processing of data for each line, wherein the encryption processing unit includes an F function execution unit to input data from one line configuring the plurality of lines and generate converted data, an XOR calculation unit to execute an XOR calculation with other lines of data corresponding to the output from the F function, an intermediate data storage register to store intermediate data during the process of generating converted data in the F function execution unit, and an inverse calculation executing unit to calculate input data regarding the F function execution unit on the basis of the data stored in the intermediate storage register. The input values for the F function execution unit are calculable by the inverse calculation in the inverse calculation executing unit, which enables a reduction in registers for storing this data. | 2013-12-19 |
20130339754 | CRYPTOGRAPHIC PROCESSING SYSTEM, KEY GENERATION DEVICE, ENCRYPTION DEVICE, DECRYPTION DEVICE, CRYPTOGRAPHIC PROCESSING METHOD, AND CRYPTOGRAPHIC PROCESSING PROGRAM - A decentralized multi-authority functional encryption according to which the security of the whole system does not depend on a single party. Among a plurality of key generation devices, arbitrary one key generation device generates gparam, and each key generation device generates an authority public key and an authority secret key based on gparam. At least some key generation devices among the plurality of key generation devices generate a part of a decryption key of the user based on the authority secret key ask. The user forms one decryption by putting together the decryption keys generated by at least some of the key generation devices, and decrypts a ciphertext. | 2013-12-19 |
20130339755 | Method for Enhancing Data Reliability in a Computer - A method for enhancing reliability of data is provided. A computer configured to provide output datum (Ds) from input datum (De), includes at least two data processing modules, and a computing member connected to each module. The method includes computing, with each module, intermediate datum (D | 2013-12-19 |
20130339756 | MANUFACTURING METHOD OF A MEMORY DEVICE TO BE AUTHENTICATED - According to one embodiment, a manufacturing method of a device to be authenticated, wherein the device includes a first memory area which is prohibited from data-reading and data-writing after shipping from a memory vendor; a second memory area which is allowed to data-read from outside after shipping from the memory vendor; and a third memory area which is allowed to data-read and data-write from outside after sipping from the memory vendor. | 2013-12-19 |
20130339757 | SYSTEMS AND METHODS FOR PROVIDING SUPPLEMENTAL POWER TO BATTERY POWERED INFORMATION HANDLING SYSTEMS - Systems and methods are disclosed for providing supplemental power to a battery powered information handling systems. The disclosed systems and methods may be implemented to intelligently control the selected use of supplemental power so as to reduce or substantially prevent an increase in battery usage cycle count by only allowing use of supplemental power above a given minimum supplemental battery charge level threshold. Battery cycle count may be further enhanced by only again allowing recharging of the system battery pack when its charge level drops below the minimum supplemental battery charge level threshold, and then recharging to a maximum recharge battery charge level threshold which also may be selectable by a user and/or provider of the information handling system. | 2013-12-19 |
20130339758 | UTILIZATION OF SHARED WAKE PINS IN COMPUTING DEVICES - Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin. | 2013-12-19 |
20130339759 | METHOD AND SYSTEM FOR AUTOMATED APPLICATION LAYER POWER MANAGEMENT SOLUTION FOR SERVERSIDE APPLICATIONS - According to the one aspect of the present disclosure, a method for automated datacenter power management comprises, monitoring a metrics of an entity such as a virtual machine, an application level, a host level and an application platform. The method further comprises forecasting an application power usage by using monitored information from the entity. The monitored information can be but not restricted to a forecasted data, a historical data or a real-time data. Furthermore, the method also comprises the step of applying at least one control to the entity to manage the application power usage. The at least one control can be but not restricted to changing resource pool size at application platform level, changing resource allocations the virtual machine level and changing a processor clock speed at the host level to manage application power usage. | 2013-12-19 |
20130339760 | INTELLIGENT MIDSPAN POE INJECTOR - Adding a separate communication link between an intelligent midspan Power Source Equipment (PSE) device and a network device (or between the midspan PSE device and a powered device (PD)) enables data communication from the network device to the intelligent midspan PSE device. The communication link provides a communication channel that the intelligent midspan PSE device may use to perform additional functions such as reallocating power, budgeting power, enabling or disabling Power over Ethernet (PoE) for a particular PD, prioritizing PoE management, and the like. | 2013-12-19 |
20130339761 | POWER MANAGEMENT SYSTEM FOR ELECTRONIC CIRCUIT - A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal. | 2013-12-19 |
20130339762 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 2013-12-19 |
20130339763 | CONTRTOL APPARATUS OF AN ELECTRONIC SYSTEM AND THE METHOD THEREIN - The invention relates to a control apparatus of an electronic system comprising a setting module, an input module, a judging module, a comparing module, a control module and a power module. The setting module is used for setting a first predetermined condition and a second predetermined condition. When at least one input information executed via the input module by the user matches the second predetermined condition, the power module provides a second power mode corresponding to the second predetermined condition, if not, the power module provides a first power mode corresponding to the first predetermined module. | 2013-12-19 |
20130339764 | METHOD AND APPARATUS FOR POWER MANAGEMENT - The disclosure discloses a power management method, for setting a power supply arrangement of an electronic device intelligently, comprising providing at least two sensors, corresponding to at least one threshold respectively; detecting a state of the electronic device for generating a detecting signal respectively; comparing the at least two detecting signals with the at least one threshold corresponding to the at least two sensors respectively; generating at least two situation signals when the at least two detecting signals meet the at least one threshold corresponding to the at least two sensors respectively; looking up a look-up table according to the at least two detecting signals for generating a control command; and writing in at least one independent bit of a register according to the control command for changing or maintaining a power supply arrangement of at least one peripheral component. | 2013-12-19 |
20130339765 | Physical Layer Device Auto-Adjustment Based on Power Over Ethernet Magnetic Heating - Physical layer device auto-adjustment based on power over Ethernet (PoE) magnetic heating. In one embodiment, information generated by a PoE module that is indicative of the PoE operation over the network cable (e.g., level of current, heating, etc.) is made available to the physical layer device (PHY). This information enables the PHY to infer a change in the level of inductance on the line. In response, the PHY can then adjust a characteristic of transmission by the PHY. | 2013-12-19 |
20130339766 | POWER SUPPLY DOCK WITH WIRELESS NETWORK AND POWER MANAGEMENT FUNCTIONS - A power supply dock with wireless network and power management functions, comprising an enclosure, a wireless base station module and a control unit disposed in the enclosure, and a plurality of power supply sockets disposed on the enclosure. The wireless base station module communicates with an external first electric appliance via a wireless network. The power supply sockets are electrically connected to and supply power to the first electric appliance or an external second electric appliance. The power supply dock is connected with the utility power to power the wireless base station module so that the wireless network can be deployed quickly, and the coverage of the wireless network can be quickly enlarged through disposition of a plurality of such power supply docks. | 2013-12-19 |
20130339767 | VARIABLE POWER OVER ETHERNET BASED ON LINK DELAY MEASUREMENT - According to example implementations, a power source device provides power to a powered device over a network link. The power source device may include a controller and a transceiver configured to transmit and receive data via a network link with the powered device. The controller may be configured to receive one or more network data packets from the powered device indicating a network delay associated with the network link, determine an amount of power to be supplied to the powered device based on the network delay indicated by the one or more network data packets, and control a power supply to supply the determined amount of power to the powered device through the network link. | 2013-12-19 |
20130339768 | IP POWER CONTROLLER - An IP power controller for linking with multiple computers to a central control system is disclosed to include a control system consisting of a MCU, an input unit, a time calculator, a memory, a signal transmission interface, a power manager and an AC/DC converter, and a power supply system consisting of a power control, a power receiving interface and a plurality of power supply interfaces. When the computers are powered off, the MCU of the control system controls the power control of the power supply system to shut off power supply, stopping transmission of power supply from the power receiving interface to the power supply interfaces, and therefore the power supply interfaces are off after the computers are turned off. | 2013-12-19 |
20130339769 | POLICY ENGINE STARTUP PROCEDURE FOR A DEFAULT PROVIDER IN USB POWER DELIVERY - An electronic device including a universal serial bus power delivery (USB-PD) port for at least the delivery of power, and a USB-PD controller to control a state of power delivery by the USB-PD port out of a plurality of states, wherein the USB-PD controller transitions the USB-PD port from an unpowered state to a check internal power state when the USB-PD port is ready to power the USB cable. | 2013-12-19 |
20130339770 | MECHANISM FOR FACILITATING POWER EXTENSION SERVICE AT COMPUTING DEVICES - A mechanism is described for facilitating power extension service at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes calculating potential power saving by one or more of a plurality of power-saving techniques supported by a computing device. The calculating includes identifying the one or more of the plurality of power-saving techniques that are available for selection and an expected amount of power to be saved with the one or more of the plurality of power saving techniques. The method may further include generating a list identifying the one or more of the plurality of power-saving techniques and relevant information resulting from the calculation, and | 2013-12-19 |
20130339771 | MULTI-CLUSTER PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME - A multi-cluster processing system and a method of operating a multi-cluster processing system are provided. The multi-cluster processing system includes: a first cluster including a plurality of first-type cores: a second cluster including a plurality of second-type cores; and a control unit configured to monitor loads of the first-type cores and the second-type cores, wherein when utilization of at least one of enabled first-type cores exceeds a predetermined threshold utilization of each of the first-type cores, the control unit enables at least one of disabled first-type cores in a first mode, and the control unit enables at least one of the disabled second-type cores and disables the first cluster in a second mode, wherein an amount of computation per unit of time of each of the second-type cores is greater than an amount of computation per unit of time of each of the first-type cores. | 2013-12-19 |
20130339772 | METHOD FOR SAVING POWER CONSUMPTION AND AN ELECTRONIC DEVICE THEREOF - An apparatus and method for signal saving power consumption in an electronic device includes determining a current battery consumption amount, and if the current battery consumption amount is greater than or equal to a threshold, determining whether to enter a low power mode based on the level of a signal strength level. | 2013-12-19 |
20130339773 | AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 2013-12-19 |
20130339774 | IMAGE FORMING APPARATUS AND POWER MANAGEMENT METHOD THEREOF - A power management method of an image forming apparatus in a home network system including the image forming apparatus and a terminal device. The power management method includes setting power save mode information which includes a plurality of levels corresponding to a predetermined home network protocol to the image forming apparatus; storing the set power save mode information; receiving a command to enter a first power save mode among the plurality of levels from the terminal device; comparing the received command to enter the first power save mode with the stored power save mode information; and entering a power save mode by the image forming apparatus corresponding to the received command to enter the first power save mode. | 2013-12-19 |
20130339775 | POWER-MANAGEMENT FOR INTEGRATED CIRCUITS - An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path. | 2013-12-19 |
20130339776 | SYSTEM AND METHOD FOR AUTOMATED SERVICE PROFILE PLACEMENT IN A NETWORK ENVIRONMENT - A method includes ranking a plurality of servers in a network environment according to power characteristics, and choosing a server from the plurality of servers for placement of a service profile according to at least a priority specified in the service profile and the server's rank. The ranking includes identifying power groups into which the plurality of servers are partitioned, identifying respective power group caps of the power groups, determining respective power ranges and respective power supply multipliers of the plurality of servers, calculating a score of each server in the plurality of servers, and assigning ranks to the scores. Choosing the server includes partitioning the servers into priority sets according to respective ranks of servers, and searching the priority sets beginning with a priority set having the priority specified in the service profile until a suitable server is found. | 2013-12-19 |
20130339777 | MICROPROCESSOR-ASSISTED AUTO-CALIBRATION OF VOLTAGE REGULATORS - Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system. | 2013-12-19 |
20130339778 | COMMUNICATION BETWEEN DOMAINS OF A PROCESSOR OPERATING ON DIFFERENT CLOCK SIGNALS - Implementations of the present disclosure involve an apparatus and/or method for communicating between domains of a computing system, where at least one of the domains operates on a skipped clock signal. Communication from a skipped clock domain to a non-skipped clock domain, or free running domain, may include a valid signal component configured to indicate when a new data packet is available and one or more counters associated with the domains to count received data packets for acknowledgement or credit purposes. The free running domain may receive data packets from any number of skipped clock domains through the communication scheme described herein. Communication from a free running domain to a skipped clock domain may include delaying transmitted data packets to correspond with the cycles of the skipped clock signal to ensure that transmitted data packets arrive at the skipped clock domain to be properly read on a skipped clock cycle. | 2013-12-19 |
20130339779 | SYSTEMATIC FAILURE REMEDIATION - Aspects of the present invention provide a tool for analyzing and remediating an update-related failure. In an embodiment, a failure state of a computer system that has been arrived at as a result of an update is captured. A semantic diff that includes the difference between the failure state and at least one of an original state or a completion state is then computed. This semantic diff is transformed into a feature vector format. Then the transformed semantic diff is analyzed to determine a remediation for the update. Failure and/or resolution signatures can be constructed using the semantic diff and contextual data, and these signatures can be used in comparison and analysis of failures and resolutions. | 2013-12-19 |
20130339780 | COMPUTING DEVICE AND METHOD FOR PROCESSING SYSTEM EVENTS OF COMPUTING DEVICE - In a method for processing system events of a computing device, the computing device includes a basic input and output system (BIOS) and a baseboard management controller (BMC). The method allocates revised storage blocks in the BMC, for storing normal system events of the computing device, and a backup storage block in the BMC for storing error system events of the computing device. The method detects a error system event via the BMC, and records the error system event into the backup storage block of the BMC. The method obtains the error system event from the backup storage block of the BMC via the BIOS when the computing device is rebooted, and processes the error system event to reboot the computing device using a normal system event stored in the revised storage blocks of the BMC. | 2013-12-19 |
20130339781 | High Availability Conferencing Architecture - Providing high availability multi-way conferencing. Separate signaling and media components may be provided within an MCU or among a cluster of MCUs. A signaling server may control signaling aspects of a conference while a media server may provide media support for the conference. In the event of media server failure, the signaling server may assign a new media server to provide media support for the conference. A backup signaling server may also monitor the signaling server and may provide signaling support for the conference in the event of signaling server failure. | 2013-12-19 |
20130339782 | REMOTE ACCESS DIAGNOSTIC MECHANISM FOR COMMUNICATION - A method for diagnosing and correcting errors at a data processing system is disclosed includes detecting at a first device of the system, such as a network interface device, an error at a second device of the system, such as a data processor. In response to detecting the error, the first device communicates a help request via a network. In response to the help request, the first device receives diagnostic and error correction routines from a remote system. The first device executes the routines and provides information to the remote system to diagnose and correct errors at the second device. | 2013-12-19 |
20130339783 | Recovery of a System for Policy Control and Charging, Said System Having a Redundancy of Policy and Charging Rules Function - A first Policy and Charging Rules Function “PCRF” server for recovery of a Policy and Charging Control “PCC” system. The PCC system also has a second PCRF server previously in charge of controlling an Internet Protocol Connectivity Access Network “IP-CAN” session previously established with a UE, and a PCRF-client. The first PCRF server includes a network interface unit of the first PCRF server arranged for receiving a modification request of the IP-CAN session from the PCRF-client after failure of the second PCRF server which was in active mode. The first PCRF server has a PCRF identifier which is shared with the second PCRF server that has failed. The first PCRF server now in active mode. The modification request requesting new rules for the IP-CAN session, including modification data and excluding access data and supported features for the IP-CAN session. The first PCRF server includes a processing unit of the first PCRF server arranged for determining that the IP-CAN session is unknown, and arranged for submitting a request from the network interface unit of the first PCRF server to the PCRF-client to provide all information that the PCRF-client has regarding the IP-CAN session. The information includes all data required to be sent for the IP-CAN session establishment and synchronization data. A Policy and Charging Rules Function “PCRF”-client for recovery of a Policy and Charging Control “PCC” system. Methods for recovery of a Policy and Charging Control “PCC” system with a first Policy and Charging Rules Function “PCRF” server in standby mode, a second PCRF server in active mode, and a PCRF-client, wherein an IP-CAN session is already established with a UE and controlled by the second PCRF server. A computer program embodied on a computer readable medium for recovery of a Policy and Charging Control “PCC” system. | 2013-12-19 |
20130339784 | ERROR RECOVERY IN REDUNDANT STORAGE SYSTEMS - Embodiments relate to providing error recovery in a storage system that utilizes data redundancy. An aspect of the invention includes monitoring plurality of storage devices of the storage system and determining that one of the plurality of storage devices has failed based on the monitoring. Another aspect of includes suspending data reads and writes to the failed storage device and determining that the failed storage device is recoverable. Based on determining that the failed storage device is recoverable, initiating a rebuilding recovery process of the failed storage device based on determining that the failed storage device is recoverable and restoring data reads and writes to the failed storage device upon completion of the rebuilding recovery process. | 2013-12-19 |
20130339785 | DYNAMIC CACHE CORRECTION MECHANISM TO ALLOW CONSTANT ACCESS TO ADDRESSABLE INDEX - A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold. | 2013-12-19 |
20130339786 | SMART ACTIVE-ACTIVE HIGH AVAILABILITY DAS SYSTEMS - A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active system. Each node in the duster may include a solid state cache that stores hot I/O in an active-active mode, which allows the data to be read from or written to the underlying dual-active or active/passive DAS RAID system only when access to the “hot Region” cools down or in the case of Cache Miss. The hot I/O data includes hot read data that accumulated dynamically regardless of ownership of the drives where the hot read data is permanently stored. The hot I/O data also includes hot write data that is mirrored across the solid state cache memories to avoid potential dirty write data conflicts and also to provide High Availability in case of server failures. | 2013-12-19 |
20130339787 | SYSTEMATIC FAILURE REMEDIATION - Aspects of the present invention provide a tool for analyzing and remediating an update-related failure. In an embodiment, a failure state of a computer system that has been arrived at as a result of an update is captured. A semantic diff that includes the difference between the failure state and at least one of an original state or a completion state is then computed. This semantic diff is transformed into a feature vector format. Then the transformed semantic diff is analyzed to determine a remediation for the update. Failure and/or resolution signatures can be constructed using the semantic diff and contextual data, and these signatures can be used in comparison and analysis of failures and resolutions. | 2013-12-19 |
20130339788 | SYSTEM AND METHOD FOR FAULT TOLERANT COMPUTING USING GENERIC HARDWARE - A dual redundant process controller is provided. The controller comprises a first processor, memory, and instance of a process control application stored in the first memory. The controller further comprises a second processor, memory, and instance of the process control application stored in the second memory. When executed by the first processor, the first application instance writes a first synchronization information to the second memory, reads a second synchronization information from the first memory, and, when the second synchronization information disagrees with the first synchronization information after passage of a predetermined time-out interval, performs a resynchronization function; and wherein, when executed by the second processor, the second application instance writes the second synchronization information to the first memory, reads the first synchronization information from the second memory, and, when the first synchronization information disagrees with the second synchronization information after passage of the predetermined time-out interval, performs the resynchronization function. | 2013-12-19 |
20130339789 | METHOD AND APPARATUS FOR OUTPUT OF HIGH-BANDWIDTH DEBUG DATA/TRACES IN ICS AND SOCS USING EMBEDDED HIGH SPEED DEBUG - Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces. | 2013-12-19 |
20130339790 | APPARATUS, SYSTEM AND METHOD FOR A COMMON UNIFIED DEBUG ARCHITECTURE FOR INTEGRATED CIRCUITS AND SoCs - A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data. | 2013-12-19 |
20130339791 | DATA POLLING METHOD AND DIGITAL INSTRUMENTATION AND CONTROL SYSTEM FOR ATOMIC POWER PLANT USING THE METHOD - The CPU includes: a data transmission instruction output processor; a failure detection signal input processor to which a failure detection signal is input from a failure detection processor for detecting a failure of an input unit; a data storage memory for, each time an input data update processor of the input unit updates data, storing the updated data; and a CPU operation processor for obtaining input data from the data storage memory and obtaining a detection signal from the failure detection signal input processor to perform operation processing. The CPU operation processor obtains periodic data as of an amount of time given by the following expression ago: | 2013-12-19 |
20130339792 | PUBLIC SOLUTION MODEL TEST AUTOMATION FRAMEWORK - Methods and apparatus, including computer program products, are provided for testing data structures, such as for example business objects. In some implementations, there is provided a method. The method may include generating, at a test system, a test script including a test business object generated based on metadata describing aspects of a deployed business object at a target system; receiving, at the test system, a request to test the target system including the deployed business object; testing, based on the generated test script including the test business object, at least one of a data and an action of the deployed business object; and generating, at the test system, at least a result of the testing. Related systems, methods, and articles of manufacture are also disclosed. | 2013-12-19 |
20130339793 | TESTING INTEGRATED BUSINESS SYSTEMS - A method of testing a first business system and a second business system is provided herein. The first business system is integrated with the second business system. The method includes performing a test of the first business system. The method further includes recording, during the test of the first business system, one or more calls from the first business system to the second business system. Also, the method includes identifying the one or more calls from the first business system far testing of the second business system. | 2013-12-19 |
20130339794 | METHOD AND SYSTEM FOR INTER-PROCESSOR COMMUNICATION - A system including a DCU with a DMS located on the first node, where the DMS is associated with an interrupt receive register. The system further includes a second DCU located on second node that includes a GMS located on the second node, where the GMS is associated with an interrupt dispatch register. The GMS is configured to identify the DMS, determine a payload to transmit to DMS, issue cross-calls using the interrupt dispatch register, where a cross-call is issued for each non-zero bit in the payload, and issue a cross-call including a completion vector. The DCU is configured to receive the cross-calls from the GMS, in response to each of the cross-calls, set a corresponding bit-location in the second interrupt receive register to one, and after receiving the completion vector, use a current state of the interrupt receive register to determine a physical address. | 2013-12-19 |
20130339795 | Failure Analysis Validation And Visualization - A system is provided for integrating failure data for different failure analysis layouts. The system includes a data validator and layout engine. The data validator is configured to validate failure analysis data for a complex system including a plurality of systems. The failure analysis data includes failure data identifying failed systems, and design data describing the complex system and possible failures of at least some of its systems. In this regard, the data validator is configured to perform one or more consistency checks between the failure data and design data to thereby integrate the failure data for a plurality of different failure analysis layouts. The layout engine is in turn configured to selectively generate and communicate any one or more of the plurality of different layouts of the failure analysis data, with at least some of the failure analysis data being shared between at least some of the different layouts. | 2013-12-19 |
20130339796 | TRANSACTIONAL EXECUTION BRANCH INDICATIONS - Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure. | 2013-12-19 |
20130339797 | METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES - A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger. | 2013-12-19 |
20130339798 | METHODS FOR AUTOMATED SOFTWARE TESTING AND DEVICES THEREOF - Methods and devices for automated software testing. This includes identifying objects present in an application under test and identifying actions supported the objects present in application under test. Based on objects selected for testing, actions are also selected and some actions require input data to be received. Verification points, which are conditions for testing objects, are set. A test script is generated based on selected objects, actions and verification points. | 2013-12-19 |
20130339799 | METHOD AND SYSTEM FOR IDENTIFYING ERRORS IN CODE - A method for identifying errors in code is provided. The method may include rebuilding object dependencies from a heap dump, calculating memory usage of each object, identifying top consumers of memory by object class, analyzing how much memory each class consumes with respect to how much other classes consume, building a corpus of data that may be used in a progressive machine learning algorithm, and identifying suspect classes. Additionally, the suspect classes and the memory usage statistics of the suspect classes may then be used as an identifying signature of the associated out of memory error. The identifying signature of the associated out of memory error may then be used to compare with the signatures of other out of memory occurrences for identifying duplicate error occurrences. | 2013-12-19 |
20130339800 | FAILOVER ESTIMATION USING CONTRADICTION - A failover guaranty estimator module performs a proof by contradiction method showing that a cluster failover guaranty can be met for the cluster. For potential failures for which failover is guaranteed, the method assumes a particular host set of one or more hosts fails, leaving one or more working hosts. The method performs a per-failure host set method for the failure host set. The per-failure host set method determines an amount of memory usage within each working host of the assumed working host set that would guaranty that a largest of the virtual machines in the failure host set would be orphaned. The per-failure host set method determines if the virtual machines in the failure set, other than the largest virtual machine in that set, would force the determined amount of memory usage within working hosts, resulting in, the failover guaranty not being met. | 2013-12-19 |
20130339801 | SYSTEM AND METHOD FOR LOG AND TRACE DIAGNOSTICS AND ANALYTICS - A system maintains a plurality of system logs and a plurality of system traces. The system extracts data from the plurality of system logs and system traces, and combines the extracted data into a centralized history of system logs and system traces. The system examines the centralized history of system logs and system traces to identify issues and problems in the system, and further identifies the issues and problems that require attention. The system also identifies a person or a group that is responsible for the identified issues and problems, and transmits a message to the identified person or group informing the identified person or group of the identified issues and problems. | 2013-12-19 |