51st week of 2009 patent applcation highlights part 41 |
Patent application number | Title | Published |
20090311823 | SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREOF - A solid-state image pickup device is provided in which a pixel forming region | 2009-12-17 |
20090311824 | METHOD FOR FABRICATING ORGANIC LIGHT EMITTING DISPLAY DEVICE - A fabricating method of an organic light emitting display device including performing a sheet test as a sheet unit on a mother board formed with panels and sheet wires for supplying test signals to the panels on the mother board, the method including: forming drive elements for driving the panels in each of the panels and forming sheet wires electrically coupled to at least a portion of the drive elements and shorting bar electrically coupling all of the sheet wires; forming organic light emitting diodes in each of the panels and isolating the sheet wires from each other by etching open regions of the shorting bar apart from contact regions of the shorting bar for coupling the shorting bar to the sheet wires; performing the sheet test on the plurality of panels by supplying the test signals to the sheet wires; and separating the panels by scribing the mother board. | 2009-12-17 |
20090311825 | METALLIZATION METHOD FOR SOLAR CELLS - A method for the production of a contact structure of a solar cell allows p-contacts and n-contacts to be produced simultaneously. | 2009-12-17 |
20090311826 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 2009-12-17 |
20090311827 | Adhesive for electronic components, method and for manufacturing semiconductor chip laminate, and semiconductor device - It is an object of the present invention to provide: an adhesive for electronic parts that makes it possible to accurately maintain a distance between electronic parts upon joining electronic parts such as two or more semiconductor chips and also to obtain reliable electronic parts such as a semiconductor device; a method for producing a semiconductor chip laminated body using the adhesive for electronic parts; and a semiconductor device using the adhesive for electronic parts. | 2009-12-17 |
20090311828 | APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS - Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration. | 2009-12-17 |
20090311829 | Performing Die-to-Wafer Stacking by Filling Gaps Between Dies - An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die. | 2009-12-17 |
20090311830 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip. | 2009-12-17 |
20090311831 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated. | 2009-12-17 |
20090311832 | Flex Chip Connector For Semiconductor Device - A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure. | 2009-12-17 |
20090311833 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate | 2009-12-17 |
20090311834 | SOI TRANSISTOR WITH SELF-ALIGNED GROUND PLANE AND GATE AND BURIED OXIDE OF VARIABLE THICKNESS - Method for making a transistor with self-aligned gate and ground plane, comprising the steps of:
| 2009-12-17 |
20090311835 | NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN - A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy. | 2009-12-17 |
20090311836 | EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN - An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor. | 2009-12-17 |
20090311837 | Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys - This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices. | 2009-12-17 |
20090311838 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer. | 2009-12-17 |
20090311839 | Method for manufacturing silicon carbide semicondutor device having trench gate structure - A manufacturing method of a SiC device includes: forming a drift layer on a substrate having an orientation tilted from a predetermined orientation with an offset angle; obliquely implanting a second type impurity with a mask on the drift layer so that a deep layer is formed in the drift layer, wherein the impurity is implanted to cancel the offset angle; forming a base region on the deep layer and the drift layer; implanting a first type impurity on the base region so that a high impurity source region is formed; forming a trench having a bottom shallower than the deep layer on the source region to reach the drift layer; forming a gate electrode in the trench via a gate insulation film; forming a source electrode on the source region and the base region; and forming a drain electrode on the substrate. | 2009-12-17 |
20090311840 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming, over a substrate, a gate insulating film containing a high-k insulating film which is composed of a material having a dielectric constant larger than that of silicon dioxide film; forming a gate electrode containing a metal over the gate insulating film; forming extension regions by implanting an dopant into the substrate using the gate electrode as a mask; and annealing the substrate, having the dopant implanted therein, by flash lamp annealing or laser annealing; wherein the annealing further includes: a first step irradiating a substrate with a light pulse having a predetermined peak intensity; and a second step irradiating a substrate with light pulses having peak intensities lower than that of the light pulse used in the first step. | 2009-12-17 |
20090311841 | Method of Manufacturing a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter - A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer. | 2009-12-17 |
20090311842 | METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY DEVICE - A method for fabricating a semiconductor memory device includes providing a substrate having thereon a conductive layer, forming an etching stop layer, a first dielectric layer and a second dielectric layer on the substrate, etching high aspect ratio hole into the etching stop layer, the first dielectric layer and the second dielectric layer to expose a portion of the conductive layer, thereafter selectively removing the first dielectric layer from the hole, thereby forming a bottle-shaped hole, then forming a conductive layer on interior surface of the bottle-shaped hole, and then stripping the first and second dielectric layers. | 2009-12-17 |
20090311843 | CONTAINER CAPACITOR STRUCTURE AND METHOD OF FORMATION THEREOF - Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via. | 2009-12-17 |
20090311844 | ALIGNMENT MARK AND METHOD FOR FABRICATING THE SAME AND ALIGNMENT METHOD OF SEMICONDUCTOR - An alignment mark, disposed on a substrate, is provided. The alignment mark includes a first dielectric layer and a metal layer. The first dielectric layer is disposed on the substrate and includes an alignment trench and a contact hole. The metal layer is disposed in the alignment trench and the contact hole, wherein a surface of the metal layer is even with a surface of the first dielectric layer. Because the metal layer and the first dielectric layer have different reflection indexes and different refraction indexes, an alignment light detects the alignment mark according to these differences. | 2009-12-17 |
20090311845 | One Transistor Memory Cell with Bias Gate - One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held. | 2009-12-17 |
20090311846 | METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS - A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region. | 2009-12-17 |
20090311847 | Method for producing a semiconductor component - Presented is a method for producing an optoelectronic component. The method includes separating a semiconductor layer based on a III-V-compound semiconductor material from a substrate by irradiation with a laser beam having a plateau-like spatial beam profile, where individual regions of the semiconductor layer are irradiated successively. | 2009-12-17 |
20090311848 | OPTICAL DEVICE WAFER DIVIDING METHOD - An optical device wafer dividing method includes a rear surface grinding step for grinding a rear surface of the optical device wafer; a dicing tape sticking step for sticking the front surface of the optical device wafer bonded with the reinforcing substrate to the front surface of a dicing tape; a laser processing step for emitting a laser beam along the streets formed on the optical device wafer from the rear surface of the reinforcing substrate to perform laser processing on the reinforcing substrate along the streets to form fracture starting points; and a wafer dividing step for applying an external force along the fracture starting points of the reinforcing substrate to fracture the reinforcing substrate along the fracture starting points to fracture the optical device wafer along the streets. | 2009-12-17 |
20090311849 | METHODS OF SEPARATING INTEGRATED CIRCUIT CHIPS FABRICATED ON A WAFER - Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips. | 2009-12-17 |
20090311850 | METHOD FOR SURFACE TREATMENT OF SEMICONDUCTOR SUBSTRATES - Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate having at least one of a defect or a contaminant disposed on or near a surface of the substrate; and selectively annealing a portion of the substrate with a laser beam in the presence of a process gas comprising hydrogen. The laser beam may be moved over the substrate or continuously, or in a stepwise fashion. The laser beam may be applied in a continuous wave or pulsed mode. The process gas may further comprise an inert gas, such as, at least one of helium, argon, or nitrogen. A layer of material may be subsequently deposited atop the annealed substrate. | 2009-12-17 |
20090311851 | NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD FORMING SAME - A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material. | 2009-12-17 |
20090311852 | BORON-DOPED DIAMOND SEMICONDUCTOR - First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead. | 2009-12-17 |
20090311853 | CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. | 2009-12-17 |
20090311854 | METHOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE - A method for forming a triple gate of a semiconductor device is provided. The method includes: forming a buffer layer and a hard mask over a substrate; etching the hard mask and the buffer layer to form a hard mask pattern and a buffer pattern; forming first and second trenches spaced apart within the substrate by partially etching the substrate by a vapor etching process using the hard mask pattern as an etching barrier layer; forming a buried insulation layer to fill the first and second trenches; removing the hard mask pattern and the buffer pattern; forming a gate insulation layer over the substrate between the first trench and the second trench; forming a conductive layer to cover the gate insulation layer; and etching the conductive layer to form a gate electrode. | 2009-12-17 |
20090311855 | METHOD OF FABRICATING A GATE STRUCTURE - A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure. | 2009-12-17 |
20090311856 | FLASH MEMORY DEVICE HAVING RECESSED FLOATING GATE AND METHOD FOR FABRICATING THE SAME - A flash memory device and a method for fabricating the same are provided. The flash memory device includes: an active region having a plurality of surface regions and a plurality of recess regions formed lower than the surface regions; a tunnel oxide layer formed over the recess regions; a plurality of recessed floating gates formed over the tunnel oxide layer to be buried into the recess regions; a plurality of dielectric layers over the recessed floating gates; and a plurality of control gates over the dielectric layers. | 2009-12-17 |
20090311857 | METHOD TO FORM ULTRA HIGH QUALITY SILICON-CONTAINING COMPOUND LAYERS - Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed. | 2009-12-17 |
20090311858 | PROGRAMMABLE VIA STRUCTURE AND METHOD OF FABRICATING SAME - A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material. | 2009-12-17 |
20090311859 | METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY - A method of fabricating an interconnect structure on a substrate includes steps of: providing a dielectric with at least one etched opening; filling the at least one etched opening with at least one conductive material; planarizing the conductive material to provide a planarized structure; subjecting the planarized structure to a plasma preclean process; and exposing the planarized structure to a silylating repair agent which is a silane derivative; and forming a dielectric cap layer on the planarized structure. | 2009-12-17 |
20090311860 | BLOCKING CONTACTS FOR N-TYPE CADMIUM ZINC TELLURIDE - A process for applying blocking contacts on an n-type CdZnTe specimen includes cleaning the CdZnTe specimen; etching the CdZnTe specimen; chemically surface treating the CdZnTe specimen; and depositing blocking metal on at least one of a cathode surface and an anode surface of the CdZnTe specimen. | 2009-12-17 |
20090311861 | Methods of forming fine patterns in the fabrication of semiconductor devices - In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region. | 2009-12-17 |
20090311862 | Method for manufacturing a semiconductor wafer - By removing residual mechanical stress generated during processing, wafers can be manufactured while suppressing deformation and cracking of the wafer even if the wafer is a large-diameter wafer. A method for manufacturing a wafer, includes: a slicing step (S | 2009-12-17 |
20090311863 | METHOD FOR PRODUCING SEMICONDUCTOR WAFER - A semiconductor wafer is produced by a method comprising a slicing step of cutting out a thin disc-shaped semiconductor wafer from a crystalline ingot; a fixed grain bonded abrasive grinding step of sandwiching the semiconductor wafer between a pair of upper and lower plates each having a pad of fixed grain bonded abrasive to simultaneously grind both surfaces of the semiconductor wafer; and a one-side polishing step subjected to both surfaces of the semiconductor wafer after the fixed grain bonded abrasive grinding step. | 2009-12-17 |
20090311864 | Polishing slurry - A polishing slurry used in chemical mechanical polishing of a barrier layer and an interlayer dielectric film in a semiconductor integrated circuit includes an abrasive, an oxidizer, an anticorrosive, an acid, a surfactant and an inclusion compound. The polishing slurry has a pH of less than 5. The resulting polishing slurry contains a solid abrasive used in barrier CMP for polishing a barrier layer made of a metallic barrier material, has excellent storage stability, achieves a good polishing rate in various films to be polished such as the barrier layer, and is capable of independently controlling the polishing rate with respect to the various films to be polished while further suppressing agglomeration of the abrasive particles. | 2009-12-17 |
20090311865 | Method for double patterning lithography - A method for double patterning lithography includes: (a) forming a first pattern on a first material layer that is formed on a semiconductor substrate, the first pattern having a plurality of first parts extending in a first direction and spaced apart along a second direction transverse to the first direction, and a plurality of first gaps among the first parts; (b) forming a second pattern on the first pattern, the second pattern having a plurality of second parts extending in the second direction and spaced apart along the first direction, and a plurality of second gaps among the second parts, the first and second gaps intersecting each other and cooperatively defining a plurality of uncovering regions where the first and second gaps intersect each other; and (c) etching portions of the first material layer exposed via the uncovering regions. | 2009-12-17 |
20090311866 | METHOD AND APPARATUS FOR PRODUCTION OF METAL FILM OR THE LIKE - In a metal film production apparatus, a copper plate member is etched with a Cl | 2009-12-17 |
20090311867 | METHOD FOR FORMING FINE PITCH STRUCTURES - A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels. The rows on different levels can crisscross one another. Selectively removing material from some of the rows can from openings to form, e.g., contact vias. | 2009-12-17 |
20090311868 | Semiconductor device manufacturing method - In a semiconductor device manufacturing method according to this invention, an SiO | 2009-12-17 |
20090311869 | SHOWER PLATE AND MANUFACTURING METHOD THEREOF, AND PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD AND ELECTRONIC DEVICE MANUFACTURING METHOD USING THE SHOWER PLATE - Provided is a shower plate capable of more securely preventing the occurrence of backflow of plasma and enabling efficient plasma excitation. A shower plate | 2009-12-17 |
20090311870 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - Provided is a plasma etching method capable of controlling an etching shape readily and properly during a plasma etching process. The plasma etching method includes: holding a semiconductor substrate W on a holding table | 2009-12-17 |
20090311871 | ORGANIC ARC ETCH SELECTIVE FOR IMMERSION PHOTORESIST - A method for forming etch features in an etch layer over a substrate and below an organic ARC layer, which is below an immersion lithography photoresist mask is provided. The substrate with the etch layer, organic ARC layer, and immersion lithography photoresist mask is placed into a processing chamber. The organic ARC layer is opened. The organic ARC layer opening comprises flowing an organic ARC open gas mixture into the processing chamber, wherein the organic ARC open gas mixture comprises an etchant gas and a polymerization gas comprising CO, forming an organic ARC open plasma from the organic ARC open gas mixture, etching the organic ARC layer with the organic ARC open plasma until the organic ARC layer is opened, and stopping the flow of organic ARC open gas mixture into the processing chamber before the etch layer is completely etched. | 2009-12-17 |
20090311872 | GAS RING, APPARATUS FOR PROCESSING SEMICONDUCTOR SUBSTRATE, THE APPARATUS INCLUDING THE GAS RING, AND METHOD OF PROCESSING SEMICONDUCTOR SUBSTRATE BY USING THE APPARATUS - A gas ring has a ring shape and includes: a gas inlet hole through which a gas is introduced from outside the gas inlet hole into the gas ring; a plurality of gas jets that ejects the gas transferred from the gas inlet hole; and a plurality of branched paths extending along the ring shape from the gas inlet hole to each of the plurality of gas jets. Here, distances between each of the plurality of gas jets to central parts, which are branch points of each of the plurality of branched paths, are identical to each other. | 2009-12-17 |
20090311873 | Substrate processing apparatus and semiconductor device producing method - Disclosed is a substrate processing apparatus, including a reaction tube to process a substrate therein, wherein the reaction tube includes an outer tube, an inner tube disposed inside the outer tube, and a support section to support the inner tube, the inner tube and the support section are made of quartz or silicon carbide, and a shock-absorbing member is provided between the support section and the inner tube. | 2009-12-17 |
20090311874 | METHOD OF TREATING SURFACE OF SEMICONDUCTOR SUBSTRATE - A method of treating the surface of a semiconductor substrate has cleaning the semiconductor substrate having a pattern formed thereon by using a chemical solution, removing the chemical solution by using pure water, forming a water repellent protective film on the surface of the semiconductor substrate, rinsing the semiconductor substrate by using pure water, and drying the semiconductor substrate. | 2009-12-17 |
20090311875 | SELECTIVE ACTIVATION OF HYDROGEN PASSIVATED SILICON AND GERMANIUM SURFACES - A method of selectively attaching a capping agent to an H-passivated Si or Ge surface is disclosed. The method includes providing the H-passivated Si or Ge surface, the H-passivated Si or Ge surface including a set of covalently bonded Si or Ge atoms and a set of surface substitutional atoms, wherein the set of surface substitutional atoms includes at least one of boron atoms, aluminum atoms, gallium atoms, indium atoms, tin atoms, lead atoms, phosphorus atoms, arsenic atoms, sulfur atoms, and bismuth atoms. The method also includes exposing the set of surface functional atoms to a set of capping agents, each capping agent of the set of capping agents having a set of functional groups bonded to a pair of carbon atoms, wherein the pair of carbon atoms includes at least one pi orbital bond, and further wherein a covalent bond is formed between at least some surface substitutional atoms of the set of surface substitutional atoms and at least some capping agents of the set of capping agents. | 2009-12-17 |
20090311876 | Manufacturing method of semiconductor device and substrate processing apparatus - A manufacturing method of a semiconductor device, including the steps of: loading into a processing chamber a substrate having a high dielectric gate insulating film and a metal electrode, with a side wall exposed by etching; applying oxidation processing to the substrate by supplying thereto hydrogen-containing gas and oxygen-containing gas excited by plasma, with the substrate heated to a temperature not allowing the high dielectric gate insulating film to be crystallized, in the processing chamber; and unloading the substrate after processing from the processing chamber. | 2009-12-17 |
20090311877 | POST OXIDATION ANNEALING OF LOW TEMPERATURE THERMAL OR PLASMA BASED OXIDATION - Embodiments of the present invention provide methods of forming oxide layers on semiconductor substrates. In some embodiments, a method of forming an oxide layer on a semiconductor substrate includes forming an oxide layer on a substrate using an oxidation process having a first process gas at a first temperature less than about 800 degrees Celsius; and annealing the oxide layer formed on the substrate in the presence of a second process gas and at a second temperature. The oxidation process may be a plasma or thermal oxidation process performed at a temperature of about 800 degrees Celsius or below. In some embodiments, the post oxidation annealing process may be a spike or soak rapid thermal process, a laser anneal, or a flash anneal performed at a temperature of at least about 700 degrees Celsius, at least about 800 degrees Celsius, or at least about 950 degrees Celsius. | 2009-12-17 |
20090311878 | METHOD FOR DEPOSITING A DIELECTRIC MATERIAL - A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant. | 2009-12-17 |
20090311879 | METHOD OF FORMING HIGH-K DIELECTRIC FILMS BASED ON NOVEL TITANIUM, ZIRCONIUM, AND HAFNIUM PRECURSORS AND THEIR USE FOR SEMICONDUCTOR MANUFACTURING - A method of forming on at least one support at least one metal containing dielectric films having the formula (M | 2009-12-17 |
20090311880 | Method of Annealing Using Two Wavelengths of Continuous Wave Laser Radiation - A thermal processing apparatus and method in which a first laser source, for example, a CO | 2009-12-17 |
20090311881 | Split Plug Electrical Connector for Towing - An apparatus is provided for simultaneously coupling a towing vehicle energizing circuit to a tow-dolly lighting circuit and a towed-vehicle lighting circuit. The apparatus includes a unitary connector body having a first portion for mating with an output plug of the towing vehicle energizing circuit, a second portion for mating with an input plug of the tow-dolly lighting circuit, and a third portion for mating with an input plug of the towed-vehicle lighting circuit. The connector body includes a plurality of conductors, each of which connects a terminal in the connector body first portion to corresponding terminals in each of the connector body second portion and third portion. The apparatus of the invention can be used to simultaneously connect the towing vehicle energizing circuit to two trailer end 4-flat plugs, one to power-tow-dolly lights and a second to power vehicle-in-tow lights. | 2009-12-17 |
20090311882 | ELECTRICAL CONNECTOR ASSEMBLY WITH PICK-UP CAP - An electrical connector assembly includes an electrical connector with an insulative housing and a pick-up cap assembled to the electrical connector. The insulative housing defines a substantially rectangular cavity in middle thereof and a number of contacts received in the cavity. The pick-up cap includes a main portion with a planar top surface and a plurality of spring arms extending from opposite edges of the main portion for engaging with the electrical connector. Each spring arm has a locking portion for engaging with the main portion if excessive deformation of the spring arm is encountered. | 2009-12-17 |
20090311883 | ELECTRICAL CONNECTOR - An electrical connector includes a printed circuit board, a plug fixedly and electrically connected to the printed circuit board, an electromagnetic shielding cover configured for encompassing the printed circuit board, a reinforced frame configured for framing the plug and the electromagnetic shielding cover to the circuit board and, a housing configured for housing the printed circuit board, the plug, the electromagnetic shielding cover and the reinforced frame therein. | 2009-12-17 |
20090311884 | CIRCUIT DEVICE, CIRCUIT DEVICE MANUFACTURING METHOD AND CONNECTING MEMBER - A circuit device which can form terminal portions at narrow pitches a manufacturing method of the circuit device, and a connecting member are provided. A circuit device | 2009-12-17 |
20090311885 | ELECTRICAL CONNECTOR ASSEMBLY HAVING IMPROVED CLIP MECHANISM - An electrical connector assembly for electrically connecting a printed circuit board and an electronic package, comprises an electrical connector on which the electronic package is mounted, a heat sink module mounted upon the electronic package and a clip positioned upon the heat sink module. The printed circuit board defines a connector mounting area surrounded by a plurality of through holes thereof. The clip has a base portion downwardly pressing against the heat sink module, a pair of mounting portions mounted to the corresponding holes, and a pair of pressing portions extending from the mounting portions and disposed on opposite sides of the clip for pressing against the heat sink module. | 2009-12-17 |
20090311886 | ELECTRICAL CONTACT WITH OVERLAPPING STRUCTURE - An electrical contact includes a first contact pin, a second contact pin and an elastic member surrounding the first contact pin and the second contact pin. Both of the first contact pin and the second contact pin include contacting portions. The first contact pin has a guiding portion including two lead-in arms and a stop portion between the two leading arms. The second contact has a main body and a protrusion on a top end of the main body. The leading arms define a guiding groove therebetween for the main body of the second contact pin moving up and down. The protrusion abuts against the stop portion of the first contact pin to prevent the second contact from sliding out of the guiding groove. | 2009-12-17 |
20090311887 | ELECTRICAL CONNECTOR PROVIDED WITH RETAINING MEMBER - An electrical connector electrically mounted on a circuit board for connecting with a complementary connector, which comprises an insulative housing, a plurality of contacts received in the housing and a retaining member fixed in the insulative housing for fastening the connector onto the circuit board. The insulative housing includes a base portion, an inserting portion extending forwardly from the base portion and a bottom wall extending forwardly from the bottom of the base portion. Said retaining member comprises two first retaining patches fixed in two opposite sides of the insulative housing. On the front end of the bottom, there defined a plurality of receiving slot, said retaining member further comprises several second retaining patches correspondingly received in said receiving slots. The connector is stably fastened onto the circuit board through the second retaining patch, therefore, can avoid the connector dropping from the circuit board when the inserting force is too large or the inserting direction is slat. | 2009-12-17 |
20090311888 | INSULATION DISPLACEMENT CONTACT AND ELECTRIC CONNECTOR USING THE SAME - An electric connector for mating with a complementary connector includes an insulation housing, at least an insulation displacement contact, and at least an insulated wire. The insulation housing includes two rows of contact holding portions which are respectively arranged on an upper and lower side of the insulation housing, and two rows of cable holding portions. The cable holding portions are arranged in correspondence with the contacting holding portions and each connected to its corresponding contacting holding portion for forming a passageway along a mating direction. The insulation displacement contact is holed in one of the contact holding portion. The insulated wire extends along the mating direction. And the wire includes a front portion inserted into one of the insulation displacement contact along a vertical direction and a sub-front portion received in one of the cable holding portions along the vertical direction. | 2009-12-17 |
20090311889 | SOCKET CONNECTOR HAVING CONTACT TERMINALS WITH RELIABLE AND DURABLE INTERCONNECTION WITH PIN LEGS OF A CPU - An electrical connector for electrically connecting a pin leg of a CPU with a trace of a PCB includes an insulative housing ( | 2009-12-17 |
20090311890 | Conductive Contact Holder - A conductive contact holder includes an insulating holder member and a conductive block member. The insulating holder member is made of an insulating material and includes a first insertion hole through which a signal conductive contact inputting and outputting a signal to and from a circuit is directly inserted over substantially its full length. The conductive block member His made of a conductive material and includes a second insertion hole through which the ground conductive contact is inserted in partial contact therewith. | 2009-12-17 |
20090311891 | Voltage tap apparatus for series connected conductive case battery cells - A voltage tap apparatus functions as both a voltage tap and a cell isolator for conductive case battery cells that are joined end-to-end in a series chain. The apparatus includes conductive leadframe elements partially encased in a plastic frame that engages the joined cells about their juncture, with portions of the lead-frame elements exposed to electrically contact the conductive cases of the cells. In a first embodiment, the plastic frame is in the form of a hinged clamp that closes about the juncture of the cells, and the lead-frame elements are routed to terminals formed on one end of the frame. In a second embodiment, the plastic frame and a connector are mounted on a printed circuit board and the leadframe elements in the plastic frame couple the battery cells to the connector. | 2009-12-17 |
20090311892 | PROTECTIVE DEVICE WITH TAMPER RESISTANT SHUTTERS - The present invention is directed to a modular shutter assembly for use within various types of electrical wiring devices having differing amperage ratings. Each of the electrical wiring devices includes a housing assembly. The housing assembly further includes a cover assembly and a rear body member. The cover assembly includes at least one set of receptacle openings configured to receive a corded plug blade set having a hot plug blade and a neutral plug blade. The modular shutter assembly includes a first shutter member having a first blade engagement structure. The first shutter member is configured to be disposed within an interior portion of the cover assembly and disposed between the at least one set of receptacle openings and the at least one set of receptacle contacts. A second shutter member includes a second blade engagement structure. The second shutter member is slidably disposed within the first shutter member. An interface is formed in either the first shutter member or the second shutter member or both. The interface is configured to connect a third shutter member to the modular shutter assembly. The interface is configured to drive the third shutter into an open position only when the first shutter member and the second shutter member move relative to each other in response to the first blade engagement structure and the second blade engagement structure being substantially simultaneously engaged by a set of plug blades. The interface does not interfere with the operation of the first shutter member and the second shutter member when the modular shutter assembly is used without the third shutter member. | 2009-12-17 |
20090311893 | LEVER-TYPE CONNECTOR - A lever type connector comprises a first connector housing; a second connector housing including a projection; and a lever pivotally engaged with the first connector housing and including two arm plates and an interconnecting bar which connects the two arm plates. The each arm plate comprises a provisional-retaining projection projecting from the arm plate toward the other arm plate, which abuts to the projection and causes to deform the arm plate so that the arm plate recedes to the other arm plate when the projection is inserted into the cam groove; and a cancellation lever extending from an edge of the arm plate and positioned at a counter side of the inlet with respect to the pivotal support, which cause to deform the arm plate so that the arm plate recedes to the other arm plate when the cancellation lever is pressed to come close to the other cancellation lever. | 2009-12-17 |
20090311894 | SOCKET FOR TESTING MAIN BOARD HAVING WATER-COOLED COOLER FIXING STRUCTURE - Provided is a socket for testing a main board having a water-cooled cooler fixing structure that fixes a water-cooled cooler to the top surface of a central processing unit (CPU) mounted to a main board for a computer during testing of the fraction defective of the main board. The socket for testing a main board includes a socket body having a size larger than a CPU mounted on a main board and having a cooler positioning recess of a predetermined size into which a water-cooled cooler is inserted to be positioned therein, the socket body being installed over the CPU mounted on the main board, a cooler fixing unit installed across an upper portion of the cooler positioning recess of the socket body, and having one end pivotally coupled to a top end of the socket body using a hinge to fix the water-cooled cooler inserted into and positioned in the cooler positioning recess, a cooler pressing unit, a bottom surface of which is attached to a top surface of the CPU mounted on the main board by resiliently pressing a top surface of the water-cooled cooler positioned in the cooler positioning recess of the socket body through fixation of the cooler fixing unit, and a socket fixing unit fixing the socket body onto the main board. | 2009-12-17 |
20090311895 | ELECTRICAL CONNECTOR AND INSERTING METHOD THEREOF - An electrical connector includes an insulating body with a main body portion in which a first receiving space is concavely formed. Spaced first terminal passages extend in a top surface of the first receiving space. A second receiving space is formed in the front end of the main body portion and connected with the first receiving space. A tongue plate extends forwards from a front end face of the main body portion and has a working surface in which spaced second terminal passages extend. The second receiving space is located above the tongue plate. First and second conductive terminals are respectively correspondingly received in the first and the second terminal passages. When a memory card is inserted into the connector, there is no other in-series disturbed signal noise for stable signal transmission; and when the memory card is inserted to its position, it cannot swing and can be connected stably. | 2009-12-17 |
20090311896 | ELECTRICAL CONNECTOR HAVING FLOATING ALIGNMENT MEMBER - An electrical connector includes a dielectric housing having a mating cavity extending to a base wall and at least one terminal cavity through the base wall to the mating cavity. The terminal cavity being configured to receive a terminal therein having a pin extending into the mating cavity. A primary terminal lock extends from an interior wall of the housing and is configured to engage the terminal to retain the terminal in the terminal cavity. An alignment member is received within the mating cavity and has an alignment plate having at least one opening aligned with a corresponding terminal cavity. The alignment member is movable within the mating cavity between a seated position in which the alignment plate is proximate to the base wall and a supporting position in which the alignment plate is positioned remote from the base wall. A tip of the terminal is held within the opening when the alignment member is in the supporting position, and a pin base of the terminal is held within the opening when the alignment member is in the seated position. | 2009-12-17 |
20090311897 | Submersible Electrical Set-Screw Connector - Disclosed herein is a submersible electrical set-screw connector. The submersible electrical set-screw connector includes a connector body section and a first sealing member. The connector body section includes a first opening and a second opening. The first opening is substantially perpendicular to the second opening. The first opening is adapted to receive a portion of an electrical conductor. The first sealing member is removably connected to the submersible electrical set-screw connector. The sealing member is adapted to receive the electrical conductor. The sealing member includes an outer cylindrical surface and an inner cylindrical surface. The outer cylindrical surface includes a first centerline axis. The inner cylindrical surface includes a second centerline axis. The first centerline axis is offset from the second centerline axis. | 2009-12-17 |
20090311898 | Hermaphroditic electrical contact - Electrical contact having a longitudinal axis along which a first central body and at least one first blade are produced, characterized in that this electrical contact is intended to be mated with a complementary electrical contact which itself has a second central body and at least one second blade extending generally in the longitudinal direction of the second contact, so that when the contact and the complementary contact are mated the first blade is in electrical contact with the second central body and the second blade is in electrical contact with the first central body. | 2009-12-17 |
20090311899 | Connector - A connector includes a male connector including plural male terminals, a first body provided with the plural male terminals, and a first terminal housing formed with a first housing opening facing respective ends of the plural male terminals, and a female connector including plural female terminals paired with the plural male terminals, a female terminal box formed with plural female terminal openings facing ends of the plural female terminals respectively, and a second body provided with the plural female terminals and the female terminal box. The connector further includes foreign body preventing means for preventing a foreign body from being mixed into the specified receiving space of the first terminal housing. The foreign body preventing means includes a blocking sheet member enclosed in the specified receiving space of the first terminal housing for blocking or substantially blocking the first housing opening, and plural male terminal openings through which the male terminals pass at specified positions respectively in the blocking sheet member. | 2009-12-17 |
20090311900 | SOCKET WITH OPPOSITELY ARRAYED TERMINALS | 2009-12-17 |
20090311901 | LAND GRID ARRAY SOCKET HAVING SIMPLIFIED FASTENING STRUCTURE - A land grid array (LGA) connector includes an insulative housing, a number of contacts received in the insultive housing, a stiffener disposed around the insulative housing, a metallic clip rotatably mounted to the stiffener, and a lever rotatably mounted to the stiffener to lock the metallic clip to the stiffener. The insulative housing defines a substantially rectangular cavity in a middle thereof adapted for receiving an electronic package therein. The metallic clip is disposed against the housing to press the electronic package upon the contacts. The metallic clip is configured by a single strip with a predetermined arrangement and then formed through bending. | 2009-12-17 |
20090311902 | SOCKET ASSEMBLY WITH EASILY ASSEMBLED LOADING MECHANISM - A socket assembly for electrically connecting an IC package to a printed circuit board, comprises an insulative housing, at least two retainers mounted on the printed circuit board and a loading plate. The insulative housing defines a receiving space for the IC package. The retainers are mounted on the printed circuit board and located on two sides of the insulative housing, and the retainer has a latching portion with a latching slot. The loading plate is mounted above the insulative housing and has two opposite lateral portions retained in the latching slot of the retainer, respectively, to retain the loading plate. | 2009-12-17 |
20090311903 | PUSH-TO-INSERT, PUSH-TO-EJECT AND PULL-TO-EXTRACT CARD CONNECTOR - An assembly for a receptacle for an electrical connector plug, including a chassis for inserting an electrical connector plug therein, two slideable grooved latches mounted on two opposite sides of the chassis, that slide along the two opposite sides under applied force, two springs fastened to respective ones of the two slideable latches, mounted on the two opposite sides of the chassis, a bar mounted between the two slideable latches, and a receptacle for the connector plug, mounted on the bar and including a plurality of contact pins for electrical contact with the connector plug, wherein (i) the two slideable latches are pushed away from respective ones of the two springs, causing the two springs to stretch and to exert tensions thereon, when the connector plug is pushed into the receptacle, and (ii) the two slideable latches are pulled towards respective ones of the springs, when the connector plug is extracted from the receptacle. | 2009-12-17 |
20090311904 | COMMUNICATION JACK - A communication is jack adapted to connect a cable that has an exposed ground wire mesh. The communication jack includes a first member, a second member, and a clamping component. The second member and the first member are capable of pivotally rotating relatively to be combined to form a clamping area. The cable is gripped by the clamping component and the second member in the clamping area, and the clamping component and the second member keep in contact with the ground wire mesh of the cable. Thus, the cable is fixed and grounded by simply combining the first and second members. | 2009-12-17 |
20090311905 | INTERLOCKING DEVICE FOR PLUG CONNECTOR HOUSINGS - The invention proposes an interlocking device ( | 2009-12-17 |
20090311906 | CABLE ASSEMBLY WITH JUMPER FUNCTION - A cable assembly, comprises a housing with a plurality of terminal receiving passages extending from a front surface to a rear surface thereof and arranged into an upper row and a lower row. A plurality of insulation displacement terminals are received into the corresponding terminal receiving passages; each insulation displacement terminal defines a connecting portion beyond the rear surface of the housing. A flat cable is defined by a plurality of conductors arranged side by side in a transverse direction and an insulative layer surrounding the conductors, and is pressed to the rear surface of the housing and insulation displacement connected with the insulation displacement terminals, each conductor of the flat cable electrically connects with two insulation displacement terminals in a vertical direction. And a cover is assembled to the housing and hold the flat cable to the housing. | 2009-12-17 |
20090311907 | ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector assembly of the invention comprises a butt plug with a contact portion and an electrical connector capable of matching the butt plug. One side of the contact portion has at least one engaging point. The electrical connector comprises an insulating body and a shield casing with at least one bottom wall. A side wall extends upward from at least one side of the bottom wall and the side wall covers at least one part of the insulating body. An opening, which is located at the front of the bottom wall and the side wall, is used for receiving the contact portion. The bottom wall has at least one fastening hole matching the engaging point. Enable the engaging point to slide into the corresponding fastening hole in parallel. When the butt plug is inserted into the shield casing once, the invention can ensure good electrical connection. | 2009-12-17 |
20090311908 | ELECTRICAL CONNECTOR WITH GROUND CONTACT MODULES - A connector assembly includes a housing and a contact module assembly including first and second contact modules loaded into the housing. The first contact module has a plurality of ground leads extending between mating contacts and mounting contacts. The ground leads extend along separate paths within a first plane. The second contact module has a plurality of signal leads extending between mating contacts and mounting contacts. The signal leads extend along separate paths within a second plane. The ground leads are aligned with the signal leads in a direction transverse to the first plane, and the ground leads have a width and a thickness defining a cross-sectional area that is larger than a cross sectional area of the signal leads. | 2009-12-17 |
20090311909 | CABLE ASSEMBLY WITH GROUNDING PIECES - A cable assembly comprises a housing defining a first cavity, a second cavity and at least one third cavity extending rearwardly from a front surface thereof, each third cavity communicated with the first cavity or the second cavity. At least one first and second electrical connector are respectively received into the first and second cavity, each first and second electrical connector defines a metallic shell thereof. At least one first cable and second cable electrically are respectively connected with the first and second electrical connector. At least one plastic piece assembled with at least one grounding piece is received into each third cavity, the grounding piece contact with the metallic shell of the first or second electrical connector. A shielding member is assembled to the housing and contacted with the grounding piece. | 2009-12-17 |
20090311910 | PLUG TYPE CONNECTOR - The invention relates to a plug-type connector with a cable, which has at least one line, a contact carrier, which has at least one contact element, which is connected to the at least one line of the cable, and an encapsulation, which is injected around the cable and the contact carrier, wherein a sealing element for sealing the encapsulation off from the outer sheath of the cable is provided. | 2009-12-17 |
20090311911 | ELECTRONIC DEVICE AND RECEPTACLE CONNECTOR THEREOF - A receptacle connector is provided for connection with a plug having two hooks. The receptacle connector includes a first tongue segment, a second tongue segment, and a housing forming an opening and two holes. The first and second tongue segments are disposed in the housing and opposite to each other. The first tongue segment includes a main body, a plurality of first contacts and two stoppers, wherein the two stoppers are located at opposite sides of the contacts and fixed to the main body. When the plug is inserted into the housing through the opening with a normal posture, the hooks are engaged in the holes. When the plug is wrongly inserted into the housing with an inverted posture (upside down), the stoppers obstruct the hooks to prevent insertion of the plug. | 2009-12-17 |
20090311912 | CONNECTOR - An ultrathin connector that is easy to assemble has a base in which a plurality of positioning concavities are provided side by side in a lower surface thereof, connection terminals having a shape obtained by bending a needle-like metal material in two and joining it under pressure, these connection terminals being positioned in the positioning concavities so that two free end portion project from the base, a pressure-sensitive adhesive tape that is pasted on, and integrated with, the lower surface of the base and fixes the connection terminals to the base, and a control lever in which a pair of rotary shafts that protrude coaxially from the end surfaces on both sides are rotatably supported on the base and which lifts wider portions of the connection terminals. | 2009-12-17 |
20090311913 | TEST HOLDER FOR MICROCHIP - The invention relates to a test holder for fixing the position of a microchip in a microchip contactor, having a base frame and a pressing unit, which is connected to the base frame such that it can be pivoted open or shut and which comprises a pressure body designed to interact with the microchip. In order to press the microchip all over with a uniform pressure onto the contactor, even if the microchip is inclined with respect to the pressing means when it is contacted with the contactor, the invention provides that the pressure body may be tilted about a first and a second tilting axis. | 2009-12-17 |
20090311914 | SENSING FAUCET - A sensing faucet used in sanitary wares is provided. The sensing faucet has a sensor and a battery compartment fixed onto the faucet shell. A valve body control system has valve control components fixed onto the valve body. There is a plug seat in the faucet shell, and a corresponding plug is installed on the valve body. During installation, the faucet shell is aligned with the valve body and the plug can be seated within the plug seat. The plug is provided with a spring-loaded electrical pin to make contact with an electrical panel in the plug seat. | 2009-12-17 |
20090311915 | LOW PROFILE PLUGS - Apparatus, systems, and methods for assembling a plug with a low profile for use with an electronic device are provided. In some embodiments, a 4-pin plug may include a diameter similar to the diameter of a 3-pin plug. In some embodiments, the fourth pin may be coupled to the plug such that a portion of the fourth pin may be coupled to any suitable device on an internal surface of the plug. In some embodiments, the fourth pin may dive into the plug at the same depth as one of the other three pins of the plug. The pins within the plug may be coupled (e.g., soldered) at the ends that may emerge underneath an overmold to any other suitable device to form electrical connections. The plug may be used to transmit audio or transfer data to a user of the electronic device. | 2009-12-17 |
20090311916 | SUBASSEMBLY CONTAINING CONTACT LEADS - A subassembly for incorporation within a communications connector jack includes a contact support member and a pair of electrical contacts mounted with respect thereto in side-by-side relation. The contact support member includes a proximal end portion and a body portion extending therefrom. The proximal end portion defines a planar rear face allowing the contact support member to be securely mounted in a cantilever fashion with respect to a corresponding planar mounting surface of a printed circuit board (PCB). An upper region of the body portion defines a sufficiently small profile as viewed along the longitudinal direction of extension of the contact support member from in front of its distal end to permit the incorporation of multiple respective instances of the contact support member within a common connector jack housing to define a desired contact layout geometry for interaction with a cooperative plug member. | 2009-12-17 |
20090311917 | Socket for Bulb - An electric bulb socket is provided, which includes a socket body ( | 2009-12-17 |
20090311918 | Electrical connector having alternative inner housings - An outer housing is configured to receive alternative first and second housings. The first inner housing is configured to receive clean body contacts where the inner housing includes integral locking latches extending into the contract receiving cavity where the locking latch may be positioned against the shoulder of the contract retaining the contact in position in the cavity. Alternatively, a second inner housing may be provided with a locking shoulder against which a locking lance of an electrical contact having a locking lance may be provided. | 2009-12-17 |
20090311919 | Clamp for Electrically Coupling to a Battery Contact - A clamp that is capable of attaching to a battery post and also to a female receptacle terminal. The clamp includes a post-grasping portion that is capable of attaching to the battery post. The clamp also includes a male plug feature that is configured to fit into a female receptacle terminal. | 2009-12-17 |
20090311920 | FLEX CONNECT - The present invention relates generally to connectors for terminating and connecting electrical wires and cables. More particularly, the connector of the present invention permits ease of connection at any angle, with regard to the electrical wire or cable equal to that of heavy gauge. Termination of an electrical wire is provided in the present invention using a connector assembly including a barrel connector, a terminal lug connector, and a flexible cable. The terminal lug connector and the barrel connector mechanically and electrically engage the electrical wire. The flexible cable mechanically and electrically connects the barrel connector to the terminal lug connector and permits angular movement between the barrel connector and the terminal lug connector. | 2009-12-17 |
20090311921 | Submersible Electrical Set-Screw Connector - Disclosed herein is an electrical connector sealing member. The electrical connector sealing member includes an outer surface and an inner channel. A portion of the outer surface includes a stepped outer diameter. The sealing member is adapted to be received by an electrical connector at the outer surface. A portion of the inner channel includes a stepped inner diameter. The sealing member is adapted to receive an electrical conductor at the inner channel. The stepped inner diameter is offset from the stepped outer diameter. | 2009-12-17 |
20090311922 | LOW PROFILE CONTACT - The invention provides a modular housing assembly system having a first housing assembly and second housing assembly. The first housing assembly has first contacts mounted thereon. The first contacts have elongated contact sections. The second housing assembly has second contacts mounted thereon. Each of the second contacts has more than one resilient contact sections spaced apart from each other along the longitudinal axis of the second contact. As the first housing assembly and the second housing assembly are moved into engagement, at least one resilient contact section of each of the second contacts are positioned in electrical engagement with the elongated contact sections of the first contacts. This configuration of the first contacts and second contacts allows the first contacts to make electrical engagement with second contacts of housing assembly or second contacts of housing assembly even though the housing assemblies have different configurations which causes the second contacts to be positioned at a different height than second contacts. | 2009-12-17 |