50th week of 2021 patent applcation highlights part 53 |
Patent application number | Title | Published |
20210391213 | INTERPOSER BOARD WITHOUT FEATURE LAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad. | 2021-12-16 |
20210391214 | METHODS AND APPARATUS FOR SEMI-DYNAMIC BOTTOM UP REFLOW - A method of filling structures on a substrate uses a semi-dynamic reflow process. The method may include depositing a metallic material on the substrate at a first temperature, heating the substrate to a second temperature higher than the first temperature wherein heating of the substrate causes a static reflow of the deposited metallic material on the substrate, stopping heating of the substrate, and depositing additional metallic material on the substrate causing a dynamic reflow of the deposited additional metallic material on the substrate. RF bias power may be applied during the dynamic reflow to facilitate in maintaining the temperature of the substrate. | 2021-12-16 |
20210391215 | FULLY SELF-ALIGNED SUBTRACTIVE ETCH - Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle. | 2021-12-16 |
20210391216 | DIE CORNER PROTECTION BY USING POLYMER DEPOSITION TECHNOLOGY - A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners. | 2021-12-16 |
20210391217 | PROCESSING METHOD OF WAFER - There is provided a processing method of a wafer for processing the wafer that includes, on a front surface side, a device region in which a device is formed in each of plural regions marked out by plural planned dividing lines and includes a recess part on the back surface side and includes an annular reinforcing part at a peripheral part. The processing method of a wafer includes a holding step of holding the bottom surface of the recess part, a cutting step of cutting the wafer along the planned dividing lines by a cutting blade to divide the device region into plural device chips and form grooves on the front surface side of the reinforcing part, and a dividing step of dividing the reinforcing part along the planned dividing lines with the grooves being the points of origin by giving an external force to the reinforcing part. | 2021-12-16 |
20210391218 | SEMICONDUCTOR DEVICE MANUFACTURING BY THINNING AND DICING - A method of manufacturing a semiconductor device is described. A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate layer and a semiconductor device layer. The method includes transforming areas of the semiconductor device layer into dicing areas which can be removed by etching, and removing the semiconductor substrate layer and the dicing areas by using etching. | 2021-12-16 |
20210391219 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer. | 2021-12-16 |
20210391220 | DOPANT PROFILE CONTROL IN GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively. | 2021-12-16 |
20210391221 | METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR - The present application provides a method for manufacturing a fin field-effect transistor, comprising steps of: forming a plurality of strip fins and dummy gates on a substrate, wherein side walls are formed on both sides of the dummy gate; forming a source or a drain on the plurality of strip fins; depositing an interlayer dielectric layer, and performing chemical mechanical planarization (CMP) on the interlayer dielectric layer to expose the top surfaces of the dummy gates; forming a single diffusion break in a single diffusion region; and replacing the dummy gates other than the dummy gate in the single diffusion region with metal gates. | 2021-12-16 |
20210391222 | Semiconductor FET Device with Bottom Isolation and High-k First - Semiconductor FET devices with bottom dielectric isolation and high-κ first are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; source and drains alongside the active layers; and gates, offset from the source and drains by inner spacers, surrounding a portion of each of the active layers, wherein the gates include a gate dielectric that wraps around the active layers but is absent from sidewalls of the inner spacers. A method of forming a semiconductor FET device is also provided. | 2021-12-16 |
20210391223 | Nanopore Structures - Nanopore structures are provided. In one aspect, a nanopore structure includes: an oxide shell surrounding a nanopore, wherein openings on both ends of the nanopore have a diameter D1, and a center of the nanopore has a diameter D2, wherein D1>D2. In another aspect, the nanopore structure includes: a first film disposed on a substrate; a second film disposed on the first film; at least one pore extending through the first film and the second film; a dielectric material disposed in the at least one pore; and a nanopore at a center of the dielectric material in the at least one pore, wherein a top opening to the nanopore has a first diameter d1, and a bottom opening to the nanopore has a second diameter d2, wherein d2>d1. Methods of forming the nanopore structures are also provided. | 2021-12-16 |
20210391224 | SILICIDE FORMATION FOR SOURCE/DRAIN CONTACT IN A VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR - A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions. | 2021-12-16 |
20210391225 | GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer | 2021-12-16 |
20210391226 | SEMICONDUCTOR DEVICE PACKAGES HAVING CAP WITH INTEGRATED ELECTRICAL LEADS - One or more embodiments are directed to semiconductor device packages having a cap with integrated metal interconnects or conductive leads. One embodiment is directed to a semiconductor device package that includes a cap having a cover extending along a first direction and sidewalls extending from the cover along a second direction that is transverse to the first direction. A plurality of electrical leads are disposed on inner surfaces of the sidewalls and extend over lower surfaces of the sidewalls. A semiconductor die is attached to an inner surface of the cover of the cap, and the semiconductor die is electrically coupled to the plurality of electrical leads. | 2021-12-16 |
20210391227 | SUPPORT SUBSTRATE FOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, AND CORRESPONDING PRODUCTION AND PACKAGING METHODS - An electronic device includes a support substrate. A face is covered with a soldermask layer. At least part of the soldermask layer includes roughnesses providing a rough grip surface. An electronic die is mounted on the support substrate. A molding resin encapsulates the electronic die and partially or completely covers the soldermask layer. | 2021-12-16 |
20210391228 | Materials and Methods for Passivation of Metal-Plated Through Glass Vias - A through-glass via (TGV) formed in a glass substrate may comprise a metal plating layer formed in the TGV. The TGV may have a three-dimensional (3D) topology through the glass substrate and the metal plating layer conformally covering the 3D topology. The TGV may further comprise a barrier layer disposed over the metal plating layer, and a metallization layer disposed over the barrier layer. The metallization layer may be electrically coupled to the metal plating layer through the barrier layer. The barrier layer may comprise a metal-nitride film disposed on the metal plating layer that is electrically coupled to the metallization layer. The barrier layer may comprise a metal film disposed over the metal plating layer and over a portion of glass surrounding the TGV, and an electrically-insulating film disposed upon the metal film, the electrically-insulating film completely overlapping the metal plating layer and partially overlapping the metal film. | 2021-12-16 |
20210391229 | POWER ELECTRONIC CIRCUIT DEVICE WITH A PRESSURE DEVICE - A power electronic circuit device has a substrate, with multiple conductive tracks, and a power semiconductor component on these conductive tracks has a connection device with a metal sheet which electrically connects a contact pad of the power semiconductor component to a contact pad of a further power semiconductor component or a conductive track, and has a pressure device. The connection device includes a contact section for connection to an assigned contact pad and a connecting section arranged between the two contact sections. The pressure device includes a two-dimensional resilient pressure element that comprises pressure element sections, and first pressure element sections press with a first pressure surface section onto a contact section and second pressure element section presses with a second pressure surface section press onto the connecting section. | 2021-12-16 |
20210391230 | Methods and Apparatus for Package with Interposers - An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure. | 2021-12-16 |
20210391231 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip. | 2021-12-16 |
20210391232 | PACKAGE WITH UNDERFILL CONTAINMENT BARRIER - An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed. | 2021-12-16 |
20210391233 | SEMICONDUCTOR DEVICE - A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film. | 2021-12-16 |
20210391234 | ADVANCED INTEGRATED PASSIVE DEVICE (IPD) WITH THIN-FILM HEAT SPREADER (TF-HS) LAYER FOR HIGH POWER HANDLING FILTERS IN TRANSMIT (TX) PATH - A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD. | 2021-12-16 |
20210391235 | LIDDED MICROELECTRONIC DEVICE PACKAGES AND RELATED SYSTEMS, APPARATUS, AND METHODS OF MANUFACTURE - A microelectronic device package may include one or more semiconductor dice coupled to a substrate. The microelectronic device package may further include a lid coupled to the substrate, the lid defining a volume over and around the one or more semiconductor die. The microelectronic device package may further include a thermally conductive dielectric filler material substantially filling the volume defined around the semiconductor die. | 2021-12-16 |
20210391236 | SEMICONDUCTOR MODULE, POWER CONVERSION DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - A semiconductor module | 2021-12-16 |
20210391237 | OVERSIZED VIA AS THROUGH-SUBSTRATE-VIA (TSV) STOP LAYER - The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via. | 2021-12-16 |
20210391238 | FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS WITH REDISTRIBUTION LAYER PACKAGING AND METHODS OF ASSEMBLING SAME - Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus. | 2021-12-16 |
20210391239 | SEMICONDUCTOR CHIP PACKAGE DEVICE - Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves. | 2021-12-16 |
20210391240 | LEADFRAME CAPACITORS - An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate. | 2021-12-16 |
20210391241 | ELECTRONIC DEVICE AND WIRING BOARD - An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected. | 2021-12-16 |
20210391242 | Fan-Out Package Structure and Method - A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion. | 2021-12-16 |
20210391243 | PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE COMPRISING SAME - A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having a 1.2 or more aspect ratio in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via. | 2021-12-16 |
20210391244 | THERMALLY ENHANCED SILICON BACK END LAYERS FOR IMPROVED THERMAL PERFORMANCE - Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors. | 2021-12-16 |
20210391245 | SEMICONDUCTOR PACKAGE DEVICE - A semiconductor package device includes a substrate, a memory chip, and a decoupling array. The substrate has a top surface, a power end, and a grounding end. The memory chip is located on the top surface of the substrate and has a power pad in which the power pad is electrically connected to the power end at a node to receive electric power. A decoupling array is located on the top surface of the substrate, and the decoupling array has a plurality of decoupling capacitors connected in parallel. Each decoupling capacitor is electrically connected between the node and the grounding end. | 2021-12-16 |
20210391246 | Package and Lead Frame Design for Enhanced Creepage and Clearance - A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure. | 2021-12-16 |
20210391247 | SUBSTRATE COMPRISING A HIGH-DENSITY INTERCONNECT PORTION EMBEDDED IN A CORE LAYER - A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects. | 2021-12-16 |
20210391248 | Increasing Contact Areas of Contacts for MIM Capacitors - A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening. | 2021-12-16 |
20210391249 | MIMCAP ARCHITECTURE - A cell on an IC includes a first set of M | 2021-12-16 |
20210391250 | VIA STRUCTURES FOR USE IN SEMICONDUCTOR DEVICES - The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. The present disclosure provides a semiconductor device including a first device region and a second device region. The first device region includes a first metal layer, a first via structure over the first metal layer, a second via structure over the first via structure, and a second metal layer over the second via structure. The first via structure and the second via structure electrically couple the second metal layer to the first metal layer. The second device region includes a third metal layer, a contact structure over the third metal layer, a memory cell structure over the contact structure, and a fourth metal layer over the memory cell structure. The first via structure and the contact structure are made of the same material. | 2021-12-16 |
20210391251 | EXTENDED VIA SEMICONDUCTOR STRUCTURE, DEVICE AND METHOD - A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via. | 2021-12-16 |
20210391252 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal. | 2021-12-16 |
20210391253 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND RESISTOR - A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process. | 2021-12-16 |
20210391254 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring. | 2021-12-16 |
20210391255 | METAL LOSS PREVENTION IN CONDUCTIVE STRUCTURES - The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer. | 2021-12-16 |
20210391256 | E-Fuse with Dielectric Zipping - E-fuses and techniques for fabrication thereof using dielectric zipping are provided. An e-fuse device includes: a first dielectric layer disposed on a substrate; at least one first electrode of the e-fuse device present in the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; vias present in the second dielectric layer, wherein at least one of the vias is present over the at least one first electrode and has a critical dimension CDA″, wherein the vias adjacent to the at least one via having the critical dimension CDA″ each have a critical dimension of CDB″, and wherein CDB″>CDA″; a liner disposed in each of the vias; and a metal that serves as a second electrode of the e-fuse device disposed in each of the vias over the liner. A method of operating an e-fuse device is also provided. | 2021-12-16 |
20210391257 | MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS - A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias. | 2021-12-16 |
20210391258 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a first stack structure with first insulating patterns and first conductive patterns, alternately stacked, the first stack structure with a first stepped structure that is defined by the first insulating patterns and the first conductive patterns; a second stack structure with second insulating patterns and second conductive patterns, alternately stacked on the first stack structure; and a first protrusion stack structure protruding laterally toward the first stepped structure from the second stack structure, the first protrusion stack structure with first protrusion insulating patterns and first protrusion conductive patterns, alternately stacked on the first stack structure. A sidewall of the first protrusion stack structure includes side surfaces of the first protrusion insulating patterns and side surfaces of the first protrusion conductive patterns, which form a common surface. | 2021-12-16 |
20210391259 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer. | 2021-12-16 |
20210391260 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance. | 2021-12-16 |
20210391261 | SELF-ALIGNED CAVITY STRUCUTRE - The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer. | 2021-12-16 |
20210391262 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, having a silicon layer on top. A device structure is disposed on the substrate. A dielectric layer is disposed on the substrate and covering over the device structure. The dielectric layer has a first air gap above the device structure. The first air gap is enclosed by a dielectric wall constituting as a part of the dielectric layer and the dielectric wall is disposed on the device structure. The dielectric layer has a second air gap, exposing a top of the device structure and adjacent to the dielectric wall. | 2021-12-16 |
20210391263 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391264 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391265 | SEMICONDUCTOR PACKAGE HAVING AN INTERPOSER AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer in a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings. | 2021-12-16 |
20210391266 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391267 | SEMICONDUCTOR DEVICES HAVING INTEGRATED OPTICAL COMPONENTS - Semiconductor devices having optical routing layers, and associated systems and methods, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming conductive pads on a first side of a substrate and electrically coupled to conductive material of vias extending partially through the substrate. The method further includes removing material from a second side of the substrate so that the conductive material of the vias projects beyond the second side of the substrate to define projecting portions of the conductive material. The method also includes forming an optical routing layer on the second side of the substrate and at least partially around the projecting portions of the conductive material. | 2021-12-16 |
20210391268 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391269 | INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer. | 2021-12-16 |
20210391270 | Segregated Power and Ground Design for Yield Improvement - A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks. | 2021-12-16 |
20210391271 | SUBSTRATE STRUCTURES, AND METHODS FOR FORMING THE SAME AND SEMICONDUCTOR PACKAGE STRUCTURES - A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component. | 2021-12-16 |
20210391272 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation. | 2021-12-16 |
20210391273 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391274 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the first aluminum-containing layer and the active region, wherein the confinement layer includes a thickness smaller than the thickness of one of the barrier layers; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies in the electron blocking region. | 2021-12-16 |
20210391275 | DIFFUSION BARRIER FOR SEMICONDUCTOR DEVICE AND METHOD - A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material. | 2021-12-16 |
20210391276 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern. | 2021-12-16 |
20210391277 | SEMICONDUCTOR DEVICE ASSEMBLIES WITH CONDUCTIVE UNDERFILL DAMS FOR GROUNDING EMI SHIELDS AND METHODS FOR MAKING THE SAME - A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam. | 2021-12-16 |
20210391278 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body. | 2021-12-16 |
20210391279 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure on the semiconductor substrate, the multilevel wiring structure including at least an intermediate metal layer over the semiconductor substrate and an uppermost metal layer over the intermediate metal layer, and the multilevel wiring structure being divided into a main circuit portion and a scribe portion surrounding the main circuit portion; wherein the scribe portion of the multilevel wiring layer includes at least a metal pad exposed in the intermediate metal layer. | 2021-12-16 |
20210391280 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a package substrate, a molded interposer package (MIP) and a first stiffener. The MIP may be arranged on the package substrate. The MIP may include an interposer, at least one first semiconductor chip and at least one second semiconductor chip molded by a molding member. The first stiffener may be attached to any one of outer surfaces of the MIP. The first stiffener may be spaced apart from the upper surface of the package substrate to suppress a warpage of the MIP. Thus, central conductive bumps between the MIP and the package substrate may not be upwardly floated to improve an electrical connection between the central conductive bumps and the package substrate. Further, a short between edge conductive bumps between the MIP and the package substrate may not be generated. | 2021-12-16 |
20210391281 | WARPAGE CONTROL FOR MICROELECTRONICS PACKAGES - Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package. | 2021-12-16 |
20210391282 | SEMICONDUCTOR STRUCTURE HAVING DUMMY PATTERN AROUND ARRAY AREA AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer. | 2021-12-16 |
20210391283 | PACKAGE SUBSTRATE, ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire. | 2021-12-16 |
20210391284 | PACKAGE SUBSTRATE, ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire. | 2021-12-16 |
20210391285 | SEMICONDUCTOR DEVICE WITH WAVEGUIDE AND METHOD THEREFOR - A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly. | 2021-12-16 |
20210391286 | BUMPED PAD STRUCTURE - A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad. | 2021-12-16 |
20210391287 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads. | 2021-12-16 |
20210391288 | MEMORY PACKAGE STRUCTURE - A memory package structure includes a substrate, a memory chip and a plurality of resistors. The substrate has a plurality of pins. The pins include a plurality of data pins used to transfer data signal. The memory chip is located on the substrate. A plurality of bonding pads is located on the memory chip. The bonding pads include a plurality of data pads used to receive the data signal from data pins or transfer the data signal from the memory chip. The resistors is located on the substrate. Each data pad is connected to a corresponding one of the data pins through a corresponding one of the resistors. | 2021-12-16 |
20210391289 | SEMICONDUCTOR DEVICE - A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer. | 2021-12-16 |
20210391290 | SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE INCLUDING STACKED PILLAR PORTIONS AND METHOD FOR FABRICATING THE SAME - A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided. | 2021-12-16 |
20210391291 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure includes a substrate, a chip and a dielectric structure. The substrate includes a first portion and a second portion surrounding the first portion. The second portion defines a cavity over the first portion. The chip includes a terminal on an upper surface of the chip. The dielectric structure fills the cavity and laterally encroaches over the upper surface of the chip. The dielectric structure is free from overlapping with the terminal of the chip. | 2021-12-16 |
20210391292 | METHOD OF MANUFACTURING SUBSTRATE LAYERED BODY AND LAYERED BODY - A method of manufacturing a substrate layered body includes: a step of applying a bonding material to the surface of at least one of a first substrate or a second substrate; a step of curing the bonding material applied on the surface to form a bonding layer having a reduced modulus at 23° C. of 10 GPa or less; and a step of bonding the first substrate and the second substrate via the bonding layer formed. | 2021-12-16 |
20210391293 | DISPLAY DEVICE - A display device includes a substrate; a plurality of pixels on the substrate; a light emitting element in each of the plurality of pixels; a first electrode electrically coupled with the light emitting element; a transistor on the substrate and electrically coupled with the first electrode; and a coupling layer between the first electrode and the light emitting element in a direction perpendicular to the substrate and containing a plurality of first conductive nanoparticles. | 2021-12-16 |
20210391294 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391295 | MICROELECTRONIC STRUCTURES INCLUDING BRIDGES - Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. | 2021-12-16 |
20210391296 | SELF-ALIGNED INTERCONNECT STRUCTURE - The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material. | 2021-12-16 |
20210391297 | METHODS OF BONDING OF SEMICONDUCTOR ELEMENTS TO SUBSTRATES, AND RELATED BONDING SYSTEMS - A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate. | 2021-12-16 |
20210391298 | Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package - A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound. | 2021-12-16 |
20210391299 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE - The semiconductor device includes: an insulating substrate having metal layers provided at a front surface and a back surface; a semiconductor element having a lower surface joined onto the metal layer on a front surface side, and having an electrode on an upper surface; a base plate; a case member; a terminal member; a wiring member that connects the terminal member and the semiconductor element; a metal thin film member that continuously covers a surface of the terminal member and a surface of the electrode connected by the wiring member, and a surface of the wiring member; and a filling member that covers a surface of the metal thin film member and the insulating substrate exposed from the metal thin film member, and is filled in a region surrounded by the base plate and the case member. | 2021-12-16 |
20210391300 | SEMICONDUCTOR PACKAGING STRUCTURE - Packaging structure is provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings. | 2021-12-16 |
20210391301 | HIGH SPEED MEMORY SYSTEM INTEGRATION - Embodiments disclosed herein include multi-die electronic packages. In an embodiment, an electronic package comprises a package substrate and a first die electrically coupled to the package substrate. In an embodiment, an array of die stacks are electrically coupled to the first die. In an embodiment the array of die stacks are between the first die and the package substrate. In an embodiment, individual ones of the die stacks comprise a plurality of second dies arranged in a vertical stack. | 2021-12-16 |
20210391302 | BACKSIDE CONTACT TO IMPROVE THERMAL DISSIPATION AWAY FROM SEMICONDUCTOR DEVICES - In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures. | 2021-12-16 |
20210391303 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate and at least one stacked structure. The package substrate has an upper surface. The stacked structure is disposed on the upper surface of the package substrate, and the stacking direction of the stacked structure is perpendicular to the upper surface. The stacked structure includes at least one non-volatile memory die, at least one dynamic random access memory die, and at least one memory control die. | 2021-12-16 |
20210391304 | REDISTRIBUTION STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via. | 2021-12-16 |
20210391305 | APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES - Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices. | 2021-12-16 |
20210391306 | METHODS OF FORMING INTEGRATED CIRCUIT PACKAGES - Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die. | 2021-12-16 |
20210391307 | THREE-DIMENSIONAL MEMORY DEVICE WITH THREE-DIMENSIONAL PHASE-CHANGE MEMORY - Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface. | 2021-12-16 |
20210391308 | LIGHT-EMITTING ELEMENT INK, DISPLAY DEVICE, AND METHOD OF FABRICATING THE DISPLAY DEVICE - A light-emitting element ink, a display device, and a method of fabricating the display device are provided. The light-emitting element ink includes a light-emitting element solvent, light-emitting elements dispersed in the light-emitting element solvent, each of the light-emitting elements including a plurality of semiconductor layers and an insulating film that surrounds parts of outer surfaces of the semiconductor layers, and a surfactant dispersed in the light-emitting element solvent, the surfactant including a fluorine-based and/or a silicon-based surfactant. | 2021-12-16 |
20210391309 | LIGHT UNIT AND DISPLAY DEVICE INCLUDING THE SAME - A display device includes a display panel and a light unit. The light unit includes a substrate, a circuit layer disposed on the substrate and including a line, an insulation layer covering the circuit layer, light emitting elements including a first electrode, a second electrode, and a light emitting layer, and a conductive layer electrically connected to one of the first electrode and the second electrode to cover at least a portion of the line. | 2021-12-16 |
20210391310 | Batch Soldering of Different Elements in Power Module - A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature. | 2021-12-16 |
20210391311 | MODULE CONFIGURATIONS FOR INTEGRATED III-NITRIDE DEVICES - An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion. | 2021-12-16 |
20210391312 | TILED LIGHT EMITTING DIODE (LED) DISPLAY PANEL - A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding flexible back plate. A printed circuit board (PCB) is disposed at a second side of the flexible back plates. A third side of the PCB faces the second side of the flexible back plates and has multiple signal lines formed thereon. The LEDs and the TFT circuits of the pixels are electrically connected to the corresponding signal lines via multiple conductive structures formed in the through holes. A resistance per unit length of each flexible back plates is greater than a resistance per unit length of the PCB. | 2021-12-16 |