50th week of 2010 patent applcation highlights part 39 |
Patent application number | Title | Published |
20100317125 | Detection Apparatus - IMS apparatus has a preconcentrator outside its inlet aperture. Analyte vapor is adsorbed during a first phase when substantially no gas is admitted to the reaction region. The preconcentrator is then energized to desorb the analyte molecules and create a volume of desorbed molecules outside the IMS housing. Next, a pressure pulser is energized momentarily to drop pressure in the housing and draw in a small sip of the analyte molecules from the desorbed volume through the aperture. This is repeated until the concentration of analyte molecules in the desorbed volume is too low for accurate analysis, following which the apparatus enters another adsorption phase. | 2010-12-16 |
20100317126 | AGGLUTINATION ASSAY METHOD IN POROUS MEDIUM LAYER - An agglutination assay method for quantitatively determination of an analyte in an aqueous liquid sample using particles bearing an anti-analyte. The agglutination is conducted in the porous medium layer of the analysis element. A speedy quantitative analysis of the analyte can be conveniently attained with high sensitivity. When the particle-labeled anti-analyte is contained in the porous medium layer, the anti-analyte can be stored with higher stability in the dry state. A dry analysis element for enabling such analysis method is also provided. | 2010-12-16 |
20100317127 | DIAGNOSIS OF LIVER PATHOLOGY THROUGH ASSESMENT OF PROTEIN GLYCOSYLATION - Methods for diagnosing pathology of the liver in a subject suspected of having such pathology are disclosed. The methods comprise quantifiably detecting lectin binding on proteins in biological fluids, and comparing the detected lectin binding with reference values for the binding of lectin of such proteins in healthy or disease states. | 2010-12-16 |
20100317128 | METHOD FOR DETERMINATION OF TARGET SUBSTANCE - A method for highly sensitive determination of a target substance by means of an aptamer includes: causing an aptamer capable of specific binding with a target substance to bind competitively with said target substance and a nucleic acid strand having a base sequence complementary to at least a portion of said target substance, detecting at least either of the physical change and the chemical change that results from said aptamer binding with said nucleic acid strand, and determining said target substance based on the result of detection. | 2010-12-16 |
20100317129 | COMPOSITION CONTROL FOR PHOTOVOLTAIC THIN FILM MANUFACTURING - The present invention relates to methods and apparatus for providing composition control to thin compound semiconductor films for radiation detector and photovoltaic applications. In one aspect of the invention, there is provided a method in which the molar ratio of the elements in a plurality of layers are detected so that tuning of the multi-element layer can occur to obtain the multi-element layer that has a predetermined molar ratio range. In another aspect of the invention, there is provided a method in which the thickness of a sub-layer and layers thereover of Cu, In and/or Ga are detected and tuned in order to provide tuned thicknesses that are substantially the same as pre-determined thicknesses. | 2010-12-16 |
20100317130 | METHOD FOR MANUFACTURING LIQUID DISCHARGE HEAD - A method for manufacturing a liquid discharge head includes providing a first layer containing a metal nitride to at least a portion on one surface of a silicon substrate corresponding to a supply port; providing a second layer on the first layer, the second layer including any one of aluminum, copper, and gold, or an alloy thereof; etching a portion of the silicon substrate corresponding to the supply port by reactive ion etching in a direction from the reverse surface towards the one surface so that the etched region reaches the first layer; and removing a portion of the first layer corresponding to the supply port and then removing a portion of the second layer corresponding to the supply port, thus forming the supply port. | 2010-12-16 |
20100317131 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - An embodiment of this invention relates to a method for manufacturing a light emitting device. The disclosed method for manufacturing a light emitting device includes the steps of: preparing a substrate wherein the crystal growth surface is a-plane or an m-plane; forming a buffer layer on said substrate; forming a semiconductor layer on said buffer layer, and separating said semiconductor layer from said substrate by removing said buffer layer. | 2010-12-16 |
20100317132 | Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays - Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems. | 2010-12-16 |
20100317133 | METHOD FOR MANUFACTURING A REFLECTIVE SURFACE SUB-ASSEMBLY FOR A LIGHT-EMITTING DEVICE - A method for manufacturing a reflective surface sub-assembly for a light-emitting device, comprising a substrate, at least one area reserved for placement of a light-emitting device assembly on the substrate, and a diffusive reflective layer applied on selected regions on the substrate, wherein if the light-emitting device assembly were placed onto the at least one area then the diffusive reflective layer would reflect photons emitted by the light-emitting device assembly is disclosed. | 2010-12-16 |
20100317134 | Nitride semiconductor laser device and method of producing the same - A method of producing a nitride semiconductor laser device includes: forming a wafer including a nitride semiconductor layer of a first conductivity type, an active layer of a nitride semiconductor, a nitride semiconductor layer of a second conductivity type, and an electrode pad for the second conductivity type stacked in this order on a main surface of a conductive substrate and also including stripe-like waveguide structures parallel to the active layer; cutting the wafer to obtain a first type and a second type of laser device chips; and distinguishing between the first type and the second type of chips by automatic image recognition. The first type and the second type of chips are different from each other in position of the stripe-like waveguide structure with respect to a width direction of each chip and also in area ratio of the electrode pad to the main surface of the substrate. | 2010-12-16 |
20100317135 | METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A method of manufacturing a display substrate includes forming a first metallic pattern including gate and storage conductors and a gate electrode of a switching device on a base substrate, forming a gate insulation layer, forming a second metallic pattern and a channel portion including a source line, source and drain electrodes of the switching device, forming a passivation layer and a photoresist film on the second metallic pattern, patterning the photoresist film to form a first pattern portion corresponding to the gate and source conductors and the switching device, and a second pattern portion formed on the storage line, etching the passivation layer and the gate insulation layer, and forming a pixel electrode using the first pattern portion. Therefore, excessive etching of the stepped portion may be prevented, so that a short-circuit defect between a metallic pattern and a pixel electrode may be prevented | 2010-12-16 |
20100317136 | METHOD FOR PRODUCING SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING DEVICE, METHOD FOR GROWING NITRIDE TYPE III-V GROUP COMPOUND SEMICONDUCTOR LAYER, METHOD FOR GROWING SEMICONDUCTOR LAYER, AND METHOD FOR GROWING LAYER - A method for producing a semiconductor light emitting device is disclosed. The method comprises the step of growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density. The nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate. | 2010-12-16 |
20100317137 | METHOD FOR RELEASING THE SUSPENDED STRUCTURE OF A NEMS AND/OR NEMS COMPONENT - A method for making a microelectronic device comprising at least one electromechanical component provided with a mobile structure,
| 2010-12-16 |
20100317138 | METHOD FOR FABRICATING MEMS STRUCTURE - A method for fabricating a MEMS is described as follows. A substrate is provided, including a circuit region and an MEMS region separated from each other. A first metal interconnection structure is formed on the substrate in the circuit region, and simultaneously a first dielectric structure is formed on the substrate in the MEMS region. A second metal interconnection structure is formed on the first metal interconnection structure, and simultaneously a second dielectric structure, at least two metal layers and at least one protection ring are formed on the first dielectric structure. The metal layers and the protection ring are formed in the second dielectric structure and the protection ring connects two adjacent metal layers to define an enclosed space between two adjacent metal layers. The first dielectric structure and the second dielectric structure outside the enclosed space are removed to form an MEMS device in the MEMS region. | 2010-12-16 |
20100317139 | THREE-DIMENSIONAL FORCE INPUT CONTROL DEVICE AND FABRICATION - The present invention provides three-dimensional force input control devices for use in sensing vector forces and converting them into electronic signals for processing, and methods of fabricating three-dimensional force input control devices for sensing vector forces and converting them into electronic signals for processing. In some embodiments, methods of fabricating provide a semiconductor substrate having a side one and a side two; fabricate stress-sensitive IC components and signal processing IC on side one of the substrate; fabricate closed trenches on side two of the substrate, the trenches forming boundaries defining elastic elements, frame areas, and rigid islands, and remove additional substrate material from side two of the substrate in the frame area leaving the dimension of the rigid island protruding outward from side two. | 2010-12-16 |
20100317140 | TECHNIQUES FOR FORMING THIN FILMS BY IMPLANTATION WITH REDUCED CHANNELING - Embodiments of the present invention relate to the use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. Then, a thin film of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. To improve uniformity of depth of implantation, channeling effects are reduced by one or more techniques. In one technique, a miscut bulk substrate is subjected to the implantation, such that the lattice of the substrate is offset at an angle relative to the impinging particle beam. According to another technique, the substrate is tilted at an angle relative to the impinging particle beam. In still another technique, the substrate is subjected to a dithering motion during the implantation. These techniques may be employed alone or in combination. | 2010-12-16 |
20100317141 | SYSTEMS, METHODS AND APPARATUSES FOR MAGNETIC PROCESSING OF SOLAR MODULES - Provided herein are methods, apparatuses and systems for fabricating photovoltaic cells and modules. In certain embodiments, the methods, apparatuses and systems involve coating ferromagnetic substrates with thin film solar cell materials and using magnetic force to constrain, move or otherwise manipulate partially fabricated cells or modules. According to various embodiments, the methods, apparatuses and systems provide magnetically actuated handling throughout a photovoltaic cell or module fabrication process, from forming photovoltaic cell layers on a substrate to packaging the module for transport and installation. The magnetically manipulated processing provides advantages over conventional photovoltaic module processing operations, including fewer mechanical components, greater control over placement and tolerances, and ease of handling. As a result, the methods, apparatuses and systems provide highly efficient, low maintenance photovoltaic module fabrication processes. | 2010-12-16 |
20100317142 | LIGHT GUIDE ARRAY FOR AN IMAGE SENSOR - An image sensor pixel that includes a photoelectric conversion unit supported by a substrate and an insulator adjacent to the substrate. The pixel includes a light guide that is located within an opening of the insulator and extends above the insulator such that a portion of the light guide has an air interface. The air interface improves the internal reflection of the light guide. Additionally, the light guide and an adjacent color filter are constructed with a process that optimizes the upper aperture of the light guide. These characteristics of the light guide eliminate the need for a microlens. | 2010-12-16 |
20100317143 | PROCESS OF FORMING A SILICON SOLAR CELL - A process for the production of a silicon solar cell comprising application and firing of an aluminum paste which comprises magnesium oxide and/or magnesium compounds capable of forming magnesium oxide on firing on the back-side of a silicon wafer provided with a silicon nitride antireflective coating on its front-side and being contaminated with silicon nitride on its back-side, and firing the aluminum paste after its application. | 2010-12-16 |
20100317144 | TECHNIQUE AND APPARATUS FOR DEPOSITING LAYERS OF SEMICONDUCTORS FOR SOLAR CELL AND MODULE FABRICATION - The present invention advantageously provides for, in different embodiments, low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities. It also provides methods to monolithically integrate solar cells made on such compound thin films to form modules. In one embodiment, there is provided a method of growing a Group IBIIIAVIA semiconductor layer on a base, and includes the steps of depositing on the base a nucleation and/or a seed layer and electroplating over the nucleation and/or the seed layer a precursor film comprising a Group IB material and at least one Group IIIA material, and reacting the electroplated precursor film with a Group VIA material. Other embodiments are also described. | 2010-12-16 |
20100317145 | SELECTIVE ETCH FOR DAMAGE AT EXFFOLIATED SURFACE - Ions are implanted into a silicon donor body, defining a cleave plane. A first surface of the donor body is affixed to a receiver element, and a lamina is exfoliated at the cleave plane, creating a second surface of the lamina. There is damaged silicon at the second surface, which will compromise the efficiency of a photovoltaic cell formed from the lamina. A selective etchant, having an etch rate which is positively correlated with the concentration of structural defects in silicon, is used to remove the damaged silicon at the second surface, while removing very little of the relatively undamaged lamina. | 2010-12-16 |
20100317146 | LOW-COST SOLAR CELLS AND METHODS FOR FABRICATING LOW COST SUBSTRATES FOR SOLAR CELLS - Substrates for solar cells are prepared by etching a plurality of metallurgical grade wafers; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride without disturbing the aluminum layer. A solar cell is then fabricated on the front surface of the wafer while the aluminum remain to serve as the back contact of the cell. | 2010-12-16 |
20100317147 | METALLIZING DEVICE AND METHOD - A metallization device configured to metallize a semiconductor device, including: a closed enclosure of variable volume configured to contain a metallization paste, a screen for screen printing forming a wall of the enclosure integral with the other walls of the enclosure, configured to be in contact with the semiconductor device during its metallization, and a mechanism applying uniform pressure over a mobile sealed wall of the enclosure opposite to the wall formed by the printing screen and reducing the volume of the enclosure. The volume reduction of the enclosure is configured to cause the metallization paste to uniformly pass through the printing screen. | 2010-12-16 |
20100317148 | METHODS FOR MANUFACTURING A CONTACT GRID ON A PHOTOVOLTAIC CELL - Processes for fabricating a contact grid for a photovoltaic cell generally includes providing a photovoltaic cell having an antireflective coating disposed on a sun facing side, the photovoltaic cell comprising a silicon substrate having a p-n junction; soft stamping a pattern of a UV sensitive photoresist and/or polymer onto the antireflective coating; exposing the UV sensitive photoresist and/or polymer to ultraviolet radiation to cure the UV sensitive photoresist and/or polymer; etching the pattern to form openings in the antireflective coating that define the contact grid; stripping the UV sensitive photoresist and/or polymer; and depositing a conductive metal into the openings defined by the pattern. The metal based paste can be aluminum based, which can be annealed at a relatively low temperature. | 2010-12-16 |
20100317149 | Method of forming a memory device incorporating a resistance variable chalcogenide element - A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. | 2010-12-16 |
20100317150 | ANTIMONY AND GERMANIUM COMPLEXES USEFUL FOR CVD/ALD OF METAL THIN FILMS - Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films. | 2010-12-16 |
20100317151 | WARPAGE RESISTANT SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes. | 2010-12-16 |
20100317152 | METHOD FOR ASSEMBLING STACKABLE SEMICONDUCTOR PACKAGES - A method for assembling a stackable semiconductor package includes providing a substrate having a first surface and a second surface. The first surface includes bond pads and one or more die pads. Conductive bumps are formed on the bond pads and one or more semiconductor dies are attached to the one or more die pads. The first surface of the substrate, the semiconductor dies and the conductive bumps are placed in a side-gate molding cast and a mold material is supplied to the first surface of the substrate to form a stackable semiconductor package. Similarly formed semiconductor packages may be stacked, one on another to form a stacked semiconductor package. | 2010-12-16 |
20100317153 | Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street - A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs. | 2010-12-16 |
20100317154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed. | 2010-12-16 |
20100317155 | MULTIFUNCTIONAL DIE ATTACHMENT FILM AND SEMICONDUCTOR PACKAGING USING THE SAME - A multifunctional die attachment film used in a semiconductor packaging process includes a first die attachment film attached to a surface of a wafer having fine circuit patterns and solder bump patterns and having a first adhesive strength; and a second die attachment film attached on the first die attachment film and having a second adhesive strength with a wafer, a die chip, PCB and a flexible board, and the multifunctional die attachment film serves as a backgrinding tape in a backgrinding process, and after the backgrinding process is completed, the multifunctional die attachment film is not removed, but is used to attach a die chip to a connection member. And, the present invention utilizes the die attachment film as a backgrinding tape in the backgrinding process and concurrently a wafer protection means in a wafer dicing process, thereby preventing sawing burr, scratches or cracks. | 2010-12-16 |
20100317156 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT - A method for separating an integrated circuit formed by a thin film having a novel structure or a method for transferring the integrated circuit to another substrate, that is, so-called transposing method, has not been proposed. According to the present invention, in the case that an integrated circuit having a thin film having a novel structure formed over a substrate via a release layer is separated, the release layer is removed in the state that the thin film integrated circuit is fixated, the thin film integrated circuit is transposed to a supporting substrate having an adhesion surface, and the thin film integrated circuit is transposed to another substrate having an adhesion surface with higher strength of adhesion than that of the supporting substrate. | 2010-12-16 |
20100317157 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING THE SAME - A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region. | 2010-12-16 |
20100317158 | Method for Forming Nanotube Semiconductor Devices - A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure. | 2010-12-16 |
20100317159 | Vertical Coffee-Stain Method For Forming Self-Organized Line Structures - A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 2010-12-16 |
20100317160 | HORIZONTAL COFFEE-STAIN METHOD USING CONTROL STRUCTURE TO PATTERN SELF-ORGANIZED LINE STRUCTURES - A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 2010-12-16 |
20100317161 | METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER - To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H | 2010-12-16 |
20100317162 | METHOD FOR PRODUCING AN INTEGRATED FIELD-EFFECT TRANSISTOR - A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region. | 2010-12-16 |
20100317163 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof - A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body. The channel-forming region within the isolated castellated-gate MOSFET region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. One or more of the trench isolated regions may contain at least one type or polarity of logic and/or memory computing device. Alternately or additionally, one or more type of Logic and/or memory device may be incorporated within vertically displaced regions above the active body region of the semiconductor wafer, embedded within Interlevel Dielectric Layers. | 2010-12-16 |
20100317164 | SEMICONDUCTOR DEVICE FABRICATION METHOD - The present invention is a method for fabricating a semiconductor device including the steps of: a first silicon nitride film having a refractive index of 2.2 or higher on a semiconductor layer made of a GaN- or InP-based semiconductor; forming, on the first silicon nitride film, a second silicon nitride film having a refractive index lower than that of the first silicon nitride; forming a source electrode and a drain electrode in areas in which the semiconductor layer is exposed; annealing the source electrode and the drain electrode in a state in which the first silicon nitride film and the second silicon nitride film are formed; and forming a gate electrode on the semiconductor layer between the source electrode and the drain electrode. | 2010-12-16 |
20100317165 | HIGH-GAIN BIPOLAR JUNCTION TRANSISTOR COMPATIBLE WITH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) PROCESS AND METHOD FOR FABRICATING THE SAME - A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor transistor of the second conductive type within the first well of the second conductive type, wherein the second well of the first conductive type is formed deeper than the device isolation layers, forming a shallow third well of the first conductive type for a base region within the first well of the second conductive type, wherein the shallow third well of the first conductive type is formed shallower than the device isolation layers, and simultaneously forming an emitter region within the shallow third well of the first conductive type and a plurality of collector contacts within the first well of the second conductive type by performing an ion implantation process for forming source/drain regions of the metal-oxide-semiconductor transistor of the second conductive type. | 2010-12-16 |
20100317166 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 2010-12-16 |
20100317167 | METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE - A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block. | 2010-12-16 |
20100317168 | LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL - A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body. | 2010-12-16 |
20100317169 | METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES USING INCLINED ION IMPLANTATION - Provided is a method of manufacturing a non-volatile memory device by performing ion implantation at an angle such that active regions of memory cell transistors in a cell region and peripheral transistors in a peripheral region each have different doping concentrations. The method includes forming a plurality of memory cell transistor gates on a cell region of a substrate surface and a plurality of peripheral transistor gates on a peripheral region of the substrate surface, where a distance between adjacent ones of the peripheral transistor gates is greater than a distance between adjacent ones of the memory cell transistor gates, and performing an ion implantation process at an implantation angle that is selected based on a height of the memory cell transistor gates and the distance between the adjacent ones thereof to implant ions into portions of the peripheral region between the peripheral transistor gates without implanting the ions into portions of the cell region between the memory cell transistor gates. | 2010-12-16 |
20100317170 | METHOD FOR IMPROVING THE THERMAL STABILITY OF SILICIDE - An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer | 2010-12-16 |
20100317171 | Method of Manufacturing a Capacitor - An etching composition for preventing from leaning a capacitor contains hydrofluoric acid (HF), ammonium fluoride (NH | 2010-12-16 |
20100317172 | LASER PROCESSING APPARATUS AND LASER PROCESSING METHOD - A laser processing apparatus including a laser beam applying unit. The laser beam applying unit includes a laser beam generating unit, a focusing unit, and an optical system for guiding a laser beam from the laser beam generating unit to the focusing unit. The optical system includes a first polarization beam splitter for splitting the laser beam generated from the laser beam generating unit into a first laser beam and a second laser beam, a half-wave plate inserted between the laser beam generating unit and the first polarization beam splitter, a first mirror for reflecting the first laser beam transmitted through the first polarization beam splitter to an optical path parallel to the optical path of the second laser beam, a second mirror for reflecting the second laser beam in a direction perpendicular to the direction of incidence of the second laser beam, and a second polarization beam splitter located at a position where the first laser beam reflected by the first mirror intersects the second laser beam reflected by the second mirror. | 2010-12-16 |
20100317173 | Dicing Tape and Process for Manufacturing a Semiconductor Device - A process for manufacturing a semiconductor device through an inlined operation includes the step of attaching a dicing tape to the ground surface immediately after the completion of the grinding of the reverse side. The dicing tape includes a base material and, undetachably laminated thereon, an adhesive layer that includes an adhesive component and an epoxy group-containing compound being free but that does not contain any hardener for epoxy resins. | 2010-12-16 |
20100317174 | Manufacturing method of semiconductor device and substrate processing apparatus - A manufacturing method of a semiconductor device is provided, comprising: loading a substrate into a processing chamber; forming a first film on the substrate by supplying silicon atom-containing gas, boron atom-containing gas, and germanium atom-containing gas into the processing chamber; forming a second film on the first film by supplying the silicon atom-containing gas and the boron atom-containing gas into the processing chamber; and unloading the substrate from the processing chamber. | 2010-12-16 |
20100317175 | METHODS OF MAKING QUANTUM DOT FILMS - Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. | 2010-12-16 |
20100317176 | METHOD AND SYSTEM FOR THE SYNTHESIS OF SEMICONDUCTOR NANOWIRES - The invention provides a system and method for producing semiconductor nanowires, for example germanium or Silicon, grown by solution decomposition comprising the steps of heating at least one high boiling point solvent to its reaction temperature in a chamber and injecting a precursor directly into the chamber to react with the at least one high boiling solvent to produce a refluxing solvent. Subsequent vapour deposition of a monomer, achieved by the refluxing solvent, onto a locally heated substrate contained within the chamber produces the semiconductor nanowires. The system and method removes the dependency upon the incorporation of metal catalyst for the production of silicon and germanium nanowire, thereby nullifying the adverse effects of metal contamination in the resulting semiconductor nanowires. | 2010-12-16 |
20100317177 | METHODS FOR FORMING SILICON GERMANIUM LAYERS - Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method may include depositing a first layer comprising silicon and germanium (e.g., a seed layer) atop the substrate using a first precursor comprising silicon and chlorine; and depositing a second layer comprising silicon and germanium (e.g., a bulk layer) atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H | 2010-12-16 |
20100317178 | REMOTE PLASMA PROCESSING OF INTERFACE SURFACES - Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal. | 2010-12-16 |
20100317179 | METHOD FOR MAKING INTEGRATED CIRCUIT DEVICE - A method for making an integrated circuit device by: forming a plurality of transistors on a semiconductor substrate; forming multilayer interconnects by depositing a layer of metal; patterning the metal layer; depositing a first dielectric material, depositing a second dielectric material, patterning the first and second dielectric materials; and depositing a via filling metal material into the patterned areas; or, alternatively, by forming transistors on a substrate; depositing one of an electrically insulating or electrically conducting material; patterning said one of an electrically insulating or electrically conducting material; and depositing the other of the electrically insulating or electrically conducting material, so as to form a layer over said transistors having both electrically insulating and electrically conducting portions; wherein the first dielectric material, which is an organosiloxane material, and the electrically insulating material each has a carbon to silicon ratio of 1.5 to 1 or more. | 2010-12-16 |
20100317180 | Method of Doping P-type Impurity Ions in Dual Poly Gate and Method of Forming Dual Poly Gate Using the Same - A method of doping p-type impurity ions in a dual poly gate, comprising: forming a polysilicon layer doped with n-type impurity ions on a substrate with a gate insulation layer being interposed between the polysilicon layer and the substrate; exposing a region of the polysilicon layer; implementing a first doping of p-type impurity ions into the exposed region of the polysilicon layer by ion implantation so with a projection range Rp to a predetermined depth of the polysilicon layer; and implementing a second doping of p-type impurity ions into the exposed region of the polysilicon layer doped with the p-type impurity ions by plasma doping with a sloped doping profile. | 2010-12-16 |
20100317181 | Gate Stack Integration of Complementary MOS Devices - A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer. | 2010-12-16 |
20100317182 | METHOD FOR MAKING SEMICONDUCTOR ELEMENT STRUCTURE - A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal. | 2010-12-16 |
20100317183 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - By removing an interlayer insulating film from a memory cell region in which a plurality of bit line diffusion layers and a plurality of word lines are formed, a trench which exposes the plurality of word lines and the sidewall insulating film is formed on the memory cell region. Thereafter, an ultraviolet light blocking film is formed on the exposed word lines and sidewall insulating film to fill the trench. Here, in the step of forming the trench, the trench is formed so that an end of the trench in a direction in which the bit line diffusion layers are extended is located on a word line located at an outermost portion of the memory cell region. | 2010-12-16 |
20100317184 | METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material. | 2010-12-16 |
20100317185 | SUBSTRATE TREATING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A substrate treating method comprising a step of preparing a semiconductor substrate (W, | 2010-12-16 |
20100317186 | ENHANCING NAND FLASH FLOATING GATE PERFORMANCE - Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process. | 2010-12-16 |
20100317187 | DEVICE STRUCTURE OF CARBON FIBERS AND MANUFACTURING METHOD THEREOF - An aggregate structure of carbon fibers, organized by a plurality of carbon fibers, includes, an aggregate of the carbon fibers aligned in a lengthwise direction, in which a density of the carbon fibers at one side end is different from a density of the carbon fibers at the other side end. | 2010-12-16 |
20100317188 | FLUORINE DOPED CARBON FILMS PRODUCED BY MODIFICATION BY RADICALS - A film forming method includes the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio larger than 1 and smaller than 2, the F/C ratio being defined as a ratio of a number of F atoms to a number of C atoms in a source gas molecule. | 2010-12-16 |
20100317189 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device which is decreased in resistance of a copper wiring containing a ruthenium-containing film and a copper-containing film, thereby having improved reliability. Also disclosed is an apparatus for manufacturing a semiconductor device. Specifically, an Ru film is formed on a substrate having a recessed portion by a CVD method using a raw material containing an organic ruthenium complex represented by the general formula and a reducing gas (step S | 2010-12-16 |
20100317190 | CONDUCTIVE INTERCONNECT STRUCTURES AND FORMATION METHODS USING SUPERCRITICAL FLUIDS - Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via. | 2010-12-16 |
20100317191 | COPPER INTERCONNECTION FOR FLAT PANEL DISPLAY MANUFACTURING - A method of depositing a copper interconnection layer on a substrate for use in a flat panel display interconnection system, comprising the steps of: a) coating said substrate with a photoresist layer; b) patterning said photoresist layer to obtain a patterned photoresist substrate comprising at least one trench patterned into said photoresist layer; c) providing a first catalyzation layer onto the patterned photoresist substrate; d) providing an electroless plated layer of an insulation layer deposited onto said first catalyzation layer; e) removing the successively superimposed photoresist layer, catalyzation layer and insulation layer except in the at least one trench, to obtain a pattern of the first catalyzation layer with an insulation layer deposited thereon. | 2010-12-16 |
20100317192 | MASKING METHOD - The invention relates to a method for masking a semiconductor substrate comprising the following steps: providing a planar semiconductor substrate having a first side and a second side lying opposite thereto, applying a mask to at least one of the sides, an extrusion printing method being envisaged for applying the mask. | 2010-12-16 |
20100317193 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 2010-12-16 |
20100317194 | METHOD FOR FABRICATING OPENING - A method for fabricating openings is provided. A dielectric layer is formed on a substrate, and a first patterned mask layer is formed on the dielectric layer along a first direction. A second patterned mask layer is then formed on the dielectric layer along a second direction which intersects with the first direction. A portion of the dielectric layer is removed using the first patterned mask layer and the second patterned mask layer as a mask so as to from the openings. The dielectric layer, the first patterned mask layer and the second patterned mask layer have different etching selectivities. | 2010-12-16 |
20100317195 | METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing C | 2010-12-16 |
20100317196 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: forming a first resist on a workpiece; patterning the first resist by performing selective exposure, baking, and development on the first resist; forming a second resist on the workpiece after the patterning the first resist; patterning the second resist by performing selective exposure, baking, and development on the second resist to selectively remove a part of the second resist and remove the first resist left on the workpiece; and processing the workpiece by using the patterned second resist as a mask. | 2010-12-16 |
20100317197 | Heat Shield for Heater in Semiconductor Processing Apparatus - A heat shield employed in semiconductor processing apparatus comprises a high performance insulation that has low thermal conductivity, such as, below the thermal conductivity of still air over a wide range of temperatures utilized in operation of the apparatus. As an example, the thermal conductivity of the insulation may be in the range of about 0.004 W/m·h to about 0.4 W/m·h over a temperature range of about 0° C. to about 600° C. or more. The deployment of the high performance heat shield reduces the power consumption necessary for the heater by as much as 20% to reach a desired processing temperature as compared to a case of heater power consumption required to reach the same desired temperature without the shield. Further, the heat shield significantly reduces the amount of undesired depositions from gas-entrained constituents on components in the chamber of the apparatus, particularly below or beyond the heat shield, by as much as 90% since the temperature drop is as much as ten orders of magnitude difference. | 2010-12-16 |
20100317198 | REMOTE PLASMA PROCESSING OF INTERFACE SURFACES - Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, and a remote plasma source configured to provide a remote plasma to the load lock. | 2010-12-16 |
20100317199 | Substrate processing apparatus and manufacturing method of semiconductor device - To reduce a residual amount of chlorine atoms and oxygen atoms in a metal nitride film, and improve oxidation resistance of the metal nitride, film, in a temperature range of not deteriorating the characteristics of other film adjacent to the metal nitride film. A substrate processing apparatus is provided, comprising: a processing chamber into which a substrate is loaded, having thereon a substrate containing oxygen atoms, chlorine atoms, and metal atoms; a substrate support part for supporting and heating the substrate in the processing chamber; a gas supply part for supplying nitrogen atoms-containing gas and hydrogen atoms-containing gas into the processing chamber; a gas exhaust part for exhausting inside of the processing chamber; a plasma generation part for exciting the nitrogen atoms-containing gas and the hydrogen atoms-containing gas supplied into the processing chamber; and a control part for controlling the substrate support part, the gas supply part, and the plasma generation part. | 2010-12-16 |
20100317200 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order. | 2010-12-16 |
20100317201 | Machine Tool or Production Machine or Robot - A machine tool or a production machine, such as e.g. a multispindle machine, or a robot, is described, wherein a liquid metal lubricated slide bearing is not only used to transmit feed currents for electrical consumers but also to transmit currents for producing control signals. Accordingly, it is possible to apply via the liquid metal lubricated slide bearings a voltage of 600 volts in order to produce feed currents and a voltage of 24 volts in order to produce control signals. | 2010-12-16 |
20100317202 | ARRANGEMENT FOR THE SECURE CONNECTION OF AN ELECTRONIC DEVICE - An arrangement for electrically connecting a motor vehicle accessory to an electrical energy source and to at least one electronic device of the vehicle, including: at least one power connector capable of being mounted on the accessory in a connected position for connecting the accessory to the electrical energy source, and at least one signal connector capable of being mounted on the accessory in a connected position for connecting the accessory to the electric device of the vehicle. The electrical connection of the accessory is performed on a support arranged below the steering column close to the region of a driver's feet. A motor vehicle electric power-assisted steering column equipped with such an arrangement of connectors for the electrical connection thereof. | 2010-12-16 |
20100317203 | COMPUTING DEVICES HAVING POP-OUT CONNECTOR PORT ARRAYS - A pop-out connector port array for provision in a computing device. The array includes an extensible connector port array member that can be transitioned from an initial retracted position in which the array member is contained within the computing device to an extended position in which the array member extends outward from the computing device, the array member comprising multiple integrated connector ports that are accessible when the array member is in the extended position. | 2010-12-16 |
20100317204 | CONTROL APPARATUS FOR ELECTRICAL DEVICES - A control apparatus for controlling a plurality of electrical devices is provided. The control apparatus includes a first body member, a second body member hingedly attached to the first body member, a power outlet strip, a power key lock, and an electronic timer. The control apparatus is capable of assuming one of a plurality of positions between an open position and a closed position. The power outlet strip includes a plurality of electrical receptacles and each of the plurality of electrical receptacles is capable of receiving an electric socket of an electrical device of the plurality of electrical devices. The power key lock and the electronic timer are disposed on the first body member. The electronic timer is capable of activating the power key lock for controlling power supply to the plurality of electrical devices connected to the plurality of electrical receptacles of the power outlet strip. | 2010-12-16 |
20100317205 | ELECTRONIC CARD WITH PROTECTING MECHANISM FOR PROTECTING CONTACTS THEREOF - An electronic card includes a housing, a plurality of contacts retain on the housing and a slider movably retained on the housing. The housing has a mating surface. The contacts are arranged in two rows along a length direction of the housing. Each contact in a first row has a flat first contact portion exposed to the mating surface. Each contact of a second row has a raised elastic second contact portion behind the first contact portion. The slider can move along the length direction of the housing to drive the second contact portions alternatively hiding below the mating surface or protruding out of the mating surface. | 2010-12-16 |
20100317206 | WATERPROOF SIMPLEX RECEPTACLE WITH ADDITIONAL WATERSHEDDING - A waterproof simplex receptacle ( | 2010-12-16 |
20100317207 | Power Outlet Socket Safety Shield Device - A power outlet socket safety shield device comprises a left slider comprising a left transverse baffle and a left inclined stopper. A right slider comprises a right transverse baffle and a right inclined stopper. At least one elastic element is positioned between the left slider and the right slider. The left inclined stopper is inclined in a direction opposite to the inclination of the right inclined stopper. When the device is in a rest state, the left inclined stopper is above the right transverse baffle and the right inclined stopper is above the left transverse baffle. When the device is in an active state, the elastic element is compressed, the left slider and the right slider are moved in opposite directions to displace the left inclined stopper away from the right transverse baffle and to displace the right inclined stopper away from the left transverse baffle. | 2010-12-16 |
20100317208 | SAFETY DOOR FOR A ROTATABLE POWER SUPPLY SOCKET - A safety door for a rotatable power supply socketincludes a mounting base with composite plugging holes, first, second and third sliding parts, and an elastic assembly. The composite plugging holes include a left-hand, middle and right-hand plugging hole, and an upper and lower ground plugging hole. While sliding in a rail slot of the mounting base, the first sliding part can block the left-hand plugging hole while sliding along the left-right direction, the second sliding part can block the right-hand plugging hole while sliding along the left-right direction; the third sliding part can block or expose the middle plugging hole while sliding along the left-right direction. The elastic assembly includes a first elastic part for providing returning elastic force to the first sliding part and a second elastic part for providing returning elastic force to the second sliding part. | 2010-12-16 |
20100317209 | SUPPLY HUB SAFETY SHIELD - A supply hub safety shield device for a power socket comprises left and right slide blocks comprising sloped shields and platform shields. A slide platform is configured to house the left and right slide blocks such that the left and right slide blocks slide along a surface of the slide platform. The slide platform comprises first and second perforations configured to receive a hot blade and a neutral blade of an attaching plug. First and second elastic components push against the left and right slide blocks. Position blocks in a middle position of the slide platform, are configured to receive surfaces of the elastic components and are further configured to limit sliding distances of the left and right slide blocks. First and second perforations are under the sloped shields when the sloped shields are in initial positions and are configured to be over the hot and neutral line output conductive plug bushes of the power supply when the device is installed in a power socket. | 2010-12-16 |
20100317210 | Auxiliary Power Cord Disconnecting Apparatus - An auxiliary power cord disconnecting apparatus is disclosed. The disconnecting apparatus may include a planar body having apertures spatially aligned to fit prongs on a power cord, a first strip extending from one end of the planar body and having a first fastening mechanism, and a second strip extending from another end of the planar body and having a second fastening mechanism. The first fastening mechanism may mate with the second mechanism to form a loop extending away from the planar body. The loop may provide a user a method to disconnect the power cord from an electrical outlet without placing strain on the power cord itself. | 2010-12-16 |
20100317211 | Card Connector - A card connector | 2010-12-16 |
20100317212 | END CAP ASSEMBLY FOR A LIGHT TUBE - An end cap assembly for a light tube that has a circuit board with lighting devices mounted thereto includes an end cap body coupled to the light tube. The end cap body has an external mating face configured to mate with a socket connector of a fixture. The end cap body includes contact bores therethrough extending along parallel bore axes between inner ends and outer ends. Contacts are received in the contact bores along the bore axes. The contacts have socket mating ends extending from the contact bores beyond the outer ends for mating with the socket connector. The contacts have wire termination ends opposite to the socket mating ends. Wires are terminated to the wire termination ends of the contacts. The wires are configured to be electrically connected to the circuit board. Optionally, the contacts may be crimped to the wires. Alternatively, the contacts may be poke-in wire contacts that receive the wires. | 2010-12-16 |
20100317213 | ELECTRICAL CONNECTOR - An electrically conductive fork includes first and second arm members each having an electrical contact and a pivot portion, the pivot portion configured to receive a portion of a rod, where the first and second arm members are configured to pivot around the rod, and a connector mechanically connecting the first and second arm members in fixed relation to each other prior to insertion of a busbar between the electrical contacts, where the connector is configured to yield to a force imparted on the connector and allow the first and second arm members to pivot around the rod in response to insertion of the busbar between the electrical contacts, and the insertion of the bus bar causes the electrical contacts to separate and pivot the first and second arm members around the rod and impart the force on the connector. | 2010-12-16 |
20100317214 | ELECTRICAL CONNECTOR SYSTEM WITH POWER AND COMMAND CONNECTORS - The present relates to an electrical connector system which includes a first connector assembly having a first connector and a second connector to be coupled one to the other; a second connector assembly having a third connector and a housing contiguous to the first connector, the housing having an open connecting face for receiving within a complementary part of the third connector so as to perform a coupling one to the other. This connector system may include a movable element which is movable between two positions, i.e.: a “first position” in which it masks at least partially the open connecting face, so that it makes impossible the coupling with the third connector; a “second position” in which it does not mask the front open connecting face, so that it makes possible the coupling with the third connector; the movable element being able to be moved into the “second position” only when said first and second connectors are fully coupled together. | 2010-12-16 |
20100317215 | ELECTRONIC TYPE REMOVAL PREVENTING CONNECTOR - An electronic type removal preventing connector includes a joint and an electronic switch. The joint includes a port, and at least one through hole formed on an external surface of the joint and interconnected to the port. At least one set of electronic switches is installed onto the through hole, and includes a tongue passed through the through hole and having an oblique surface. If a metal plug of a portable electronic device is inserted into the port of the connector, the tongue of the electronic switch will be entered into a bolt hole of the metal plug to prevent the portable electronic device from being stolen. If the electronic switch is electrically conducted for an operation, the tongue will be separated from the through hole and the bolt hole, such that a user can remove the metal plug of the portable electronic device from the joint of the connector. | 2010-12-16 |
20100317216 | Multiple Function RJ Connector with Split Internal Housing Opening Cavity - A multi-purpose modular RJ connector includes a female receptacle having an opening in which a printed circuit board having contact pads on opposite surfaces thereof is positioned. A male plug has a cavity operative for receiving the printed circuit board therein when the male plug is inserted in the opening of the female receptacle. The male plug includes contact pins on opposite sides of the cavity for contacting the contact pads disposed on opposite surfaces of the printed circuit board when the male plug is inserted into the opening of the female receptacle. | 2010-12-16 |
20100317217 | CABLE ASSEMBLY WITH LATCHING MEMBER - A cable assembly ( | 2010-12-16 |
20100317218 | ELECTRICAL CONNECTOR ASSEMBLY WITH LATCHING MECHANISM - An electrical connector ( | 2010-12-16 |
20100317219 | MULTI-POSITION CONNECTOR - A connector assembly includes a housing that includes one or more slots for inserting a component defined in a top side of the connector housing. Each slot includes a first and a second interior surface separated by a distance. Channels are defined in each surface and are adapted to receive a portion of a terminal. Openings for receiving a terminal are defined in a bottom surface of the housing. When the terminal is fully inserted into the opening the terminal portion is substantially adjacent to a surface within the channel and a contact region of the terminal is substantially centered between the first and second interior surfaces of the slot so as to enable lateral movement of the contact portion between the first and second surfaces when the component is inserted. | 2010-12-16 |
20100317220 | ELECTRICAL CONNECTOR HAVING GROUNDING DEVICE - An electrical connector ( | 2010-12-16 |
20100317221 | CONNECTING BLOCK IMPROVED IN CROSSTALK-CHARACTERISTICS - A connecting block includes a housing having a plurality of slots extending from an upper surface thereof to an inside thereof with intervals, a plurality of terminal pins installed in the slots, a dielectric cover made of an insulating resin and coupled to the housing to cover a side of the housing, and a coupling pin electrically contacted with a terminal pin of any one pair among terminal pins belonging to different terminal pin pairs and extending opposite to a terminal pin of the other pair. The coupling pin is molded in a body of the dielectric cover such that the insulating resin is interposed between the coupling pin and the terminal pin opposite to the coupling pin. | 2010-12-16 |
20100317222 | ELECTRICAL POWER EXTENSION CORD HAVING CONTINUOUS ELECTRICAL CURRENT AND GROUND MONITOR - An electrical power extension cord having a male plug end, a female receptacle end, and an insulated flexible cordset extending between the male and female ends of the extension cord. The male end has a first prong electrically connected to a hot wire contained in the cordset, a second prong electrically connected to a neutral wire in the cordset, and a third prong electrically connected to a ground wire in the cordset. The female end has a first receptacle electrically connected to a hot wire contained in the cordset, a second receptacle electrically connected to the neutral wire in the cordset, and a third receptacle electrically connected to the ground wire in the cordset. Continuous electrical current and ground monitoring circuits are contained in the male and female ends of the extension cord. Activation of indicator lamps contained in the monitoring circuits continuously indicates both electrical current and ground continuity between the male and female ends of the extension cord and electrical current at the male plug end. | 2010-12-16 |
20100317223 | POWER AND DATA ADAPTER ASSEMBLY - A power and data adapter assembly includes an electrical receptacle assembly ( | 2010-12-16 |
20100317224 | In-Desk USB HUB and Connectivity System - A connectivity system capable of use with a desk having a surface containing an aperture includes a grommet and a connection hub. The grommet has an interior surface. The connection hub includes a connection port and a perimeter. The surface of the desk defines a first plane that forms a division between a first side of the first plane and a second side of the first plane. A portion of the perimeter of the connection hub is spaced apart from the interior surface of the grommet such that the perimeter and the interior surface define a passageway therebetween through which a cable may be passed from the first side to the second side of the surface of the desk. | 2010-12-16 |