50th week of 2012 patent applcation highlights part 28 |
Patent application number | Title | Published |
20120314455 | ISOLATED SEPIC POWER CONVERTER FOR LIGHT EMITTING DIODES AND OTHER APPLICATIONS - A system includes a load and a single-ended primary-inductance converter (SEPIC) power converter configured to provide power to the load. The SEPIC power converter includes a primary side and a secondary side that are electrically isolated by a transformer. The transformer includes a primary coil and a secondary coil. The primary side includes (i) a capacitor coupled to a first end of the primary coil and (ii) an inductor and a switch coupled to a second end of the primary coil. The primary side of the SEPIC power converter could also include a diode coupled between the inductor and the switch, where the diode is coupled to the second end of the primary coil. The capacitor could be configured to transfer energy to the secondary side of the SEPIC power converter through the transformer during valleys associated with a rectified input voltage. | 2012-12-13 |
20120314456 | SYNCHRONOUS AC RECTIFIED FLYBACK CONVERTER UTILIZING BOOST INDUCTOR - A flyback converter utilizes a boost inductor coupled between a source of AC power and a synchronous rectifier to provide power factor correction. The synchronous rectifier includes four field-effect transistors configured in a bridge arrangement. Control circuitry controls the on/off states of opposite pairs of the FETs to provide synchronous rectification of the AC power. A primary winding of the flyback transformer is coupled in series with a storage capacitor across the output of the synchronous rectifier. A circuit, which includes a switching transistor, is also coupled across the output of the synchronous rectifier to provide a low resistance path when the switch is closed. The cores of the boost inductor and the transformer are loaded with energy when the switch is closed. When the switch opens, the energy stored in the magnetic cores is transferred to the output via the transformer secondary winding and rectification circuitry. In one embodiment, a separate switching transistor is not used and its function is performed by the rectifier FETs. | 2012-12-13 |
20120314457 | CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER - A resonant mode converter includes a PFC power converter having an input coupled to receive an input voltage. An LLC power converter is cascaded with the PFC power converter. The LLC power converter includes a transformer coupled to generate an output of the resonant mode converter. A feedback circuit is coupled to generate a first current representative of the output of the resonant mode converter. A control unit includes a current limiting circuit coupled to receive the first current and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. The control unit further includes an oscillator coupled to generate a control signal having a control frequency in response to the first current. The resonant mode converter output is controlled in response to the control frequency. | 2012-12-13 |
20120314458 | SWITCHING POWER SUPPLY APPARATUS - A switching control IC conducts on-off control on a first switching element. A second switching control circuit is provided between a high-side driving winding of a transformer T and a second switching element. The second switching control circuit discharges a capacitor in a negative direction with a constant current during an on period of the first switching element, and then after the second switching element is turned on, charges the capacitor in a positive direction with a constant current. A transistor controls the on period of the second switching element in accordance with the ratio of a charging current to a discharge current such that the ratio of the on period of the second switching element to the on period of the first switching element is substantially always constant. | 2012-12-13 |
20120314459 | FEEDBACK CIRCUIT AND POWER SUPPLY DEVICE INCLUDING THE SAME - Disclosed are a feedback circuit and a power supply device including the same. The power supply device converts input voltage into output voltage suitable for load condition according to a switching operation of a power switch. The feedback circuit includes a first diode connected to a first sensing voltage corresponding to output voltage and a second diode connected to the output voltage. The feedback circuit generates feedback voltage by using voltage passing through a conducted diode of the first and the second diodes. The power supply device controls a switching operation of the power switch depending on the feedback voltage. | 2012-12-13 |
20120314460 | HIGH YIELD AC-AC POWER CONVERTER AND METHOD THEREFOR - An AC to AC power converter has a rectifier configured to receive an AC signal. An H-Bridge is coupled to the rectifier and the DC Filter. A processor is coupled to the rectifier and to the H-Bridge, wherein the processor is configured to produce a pulse to modulate a rectified input or a constant DC input to the H-Bridge. A wave filter is coupled to the H-Bridge and configured to modulate an output of the H-Bridge to an AC voltage of a desired frequency, wherein an output of the wave filter is coupled to the processor. | 2012-12-13 |
20120314461 | POWER CONVERTER - A power converter that is able to lower the level of switching noise in a wide frequency range is disclosed. In detail, the power converter converts an input power by controlling a switching element on the basis of a switching frequency discrete pattern. The switching frequency discrete pattern is composed in such a manner that a main discrete pattern and a sub discrete pattern are synthesized. The main discrete pattern is regulated by a plurality of transitionally discrete frequencies. Also the sub discrete pattern is regulated by a plurality of transitionally discrete frequencies in which a gap of the magnitude among consequent frequencies is smaller than that of the main discrete pattern. | 2012-12-13 |
20120314462 | OFFLINE POWER SUPPLY AND APPARATUS FOR CHARGING A PLUG-IN VEHICLE - An offline power supply includes a power supply circuit including a primary-side circuit for connecting to a first power source, a secondary-side circuit for connecting to a load, and a transformer connecting the primary-side circuit and the secondary-side circuit. A switch operates to selectively connect the primary-side circuit to the first power source. A second power source is charged during operation of the power supply circuit. A controller powered by the second power source has at least one input, and an output to selectively operate the switch based on the at least one input. | 2012-12-13 |
20120314463 | POWER SUPPLY WITH RESTART CIRCUIT - A power supply protected against open circuit conditions at its output terminals, and methods for so protecting, are disclosed. A front end circuit receives an input voltage and provides a regulated front end DC voltage to a voltage converter circuit, which in turn provides a DC output voltage to the output terminals to drive a light source. An open circuit protection circuit is coupled between the voltage converter circuit and the output terminals. It has a non-conducting state to couple the DC output voltage to the output terminals, and a conducting state to establish a short circuit across the output terminals in response to charging of a capacitor during an open circuit condition at the output terminals. A restart circuit intermittently discharges the capacitor during the open circuit condition to place the open circuit protection circuit in the non-conducting state when the open circuit condition is resolved. | 2012-12-13 |
20120314464 | Solar Module and Method for its Operation - A solar module has a solar cell which generates a DC voltage. The module has a converter for converting a DC voltage fed into its input. The module contains a semiconductor switch and a controller which drives a switching input of the semiconductor switch. The controller drives the semiconductor switch variably so that the semiconductor switch switches more slowly during the transition operation than during normal operation, thereby reducing a dynamic overvoltage on the switch such that the voltage present on the switch does not exceed the blocking voltage of the switch. | 2012-12-13 |
20120314465 | CONTACTLESS ELECTRICITY-SUPPLYING DEVICE - There is provided a contactless electricity-supplying device that can safely and efficiently supply power to a load. | 2012-12-13 |
20120314466 | CONTROL OF A MODULAR CONVERTER HAVING DISTRIBUTED ENERGY STORES WITH THE AID OF AN OBSERVER FOR THE CURRENTS AND AN ESTIMATING UNIT FOR THE INTERMEDIATE CIRCUIT ENERGY - Methods and configurations controlling a converter having controllable power semiconductors, compare actual and target state values to obtain control difference values for a control unit producing setting voltage values. Control electronics provide control signals according to setting voltage values and transmit them to power semiconductors. The control unit generates voltage values so control difference values become small. Current and converter energy controls and energy balancing are performed jointly, actual state values are calculated by an observing unit based on setting voltage values considering measured current values and actual state intermediate-circuit energy values are calculated by an estimating unit considering measured intermediate-circuit energy values of positive and negative voltage sources. The observing and estimating units model the converter so actual state current and intermediate-circuit steady-state energy values correspond to error-free current and intermediate-circuit energy values. A periodic time-variant gain controller receives error-free values. | 2012-12-13 |
20120314467 | POWER CONVERSION SYSTEM AND METHOD - Embodiments of the invention relate to a power system for converting direct current (“DC”) power on a DC bus into alternating current (“AC”) power with a regulated voltage output and for feeding the AC power to an electrical system which may include a power utility or an electric grid, for example. A power conversion control system is used for controlling the power conversion and for maintaining the DC bus voltage (“DC voltage”) at a certain level. | 2012-12-13 |
20120314468 | Memory array with local bitlines and local-to-global bitline pass gates and gain stages - A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. | 2012-12-13 |
20120314469 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and second bit lines. A plurality of storage elements respectively has a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line. Both of the first and second bit lines are connected to the same active area via the storage elements. | 2012-12-13 |
20120314470 | MEMORY DEVICE - A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data. | 2012-12-13 |
20120314471 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second region is provided along one side of the first region and includes a first power supply generation circuit that generates the first voltage, based on a second voltage. The second voltage being supplied to the first power supply circuit by a first power supply interconnect extends on the first region in a first direction parallel to the one side of the first region. | 2012-12-13 |
20120314472 | Multiple-Bit Programmable Resistive Memory Using Diode as Program Selector - A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2 | 2012-12-13 |
20120314473 | Multiple-State One-Time Programmable (OTP) Memory to Function as Multi-Time Programmable (MTP) Memory - A circuit, method, and system for using multiple-state One-Time Programmable (OTP) memory to function as a multiple-bit programmable (MTP) memory are disclosed. The OTP memory can have N(N>2) distinct resistance states, that can be differentiated by at least N−1 reference resistances, can be functionally equivalent programmed N−1 times. The multiple-state OTP memory can have a plural of multiple-state OTP cells that can be selectively programmed to a resistance state. The reference resistance can be set to determine a state of the from the programmed multiple-state OTP cells. | 2012-12-13 |
20120314474 | NON-VOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME - The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region. | 2012-12-13 |
20120314475 | LOW VOLTAGE PROGRAMMABLE MOSFET ANTIFUSE WITH BODY CONTACT FOR DIFFUSION HEATING - An antifuse can include an insulated gate field effect transistor (“IGFET”) having an active semiconductor region including a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body contact is electrically connected with the body. The first regions have opposite conductivity (i.e., n-type or p-type) from the body. The IGFET can be configured such that a programming current through at least one of the first regions and the body contact causes heating sufficient to drive dopant diffusion from the at least one first region into the body and cause an edge of the at least one first region to move closer to an adjacent edge of at least one other of the first regions. In such way, the programming current can permanently reduce electrical resistance by one or more orders of magnitude between the at least one first region and the at least one other first region. | 2012-12-13 |
20120314476 | ORGANIC FERROELECTRIC MATERIAL BASED RANDOM ACCESS MEMORY - Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell (see definition above) provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit and silicon nanowire as the memory read out unit. | 2012-12-13 |
20120314477 | Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal. | 2012-12-13 |
20120314478 | RESISTIVE MEMORY DEVICE AND SENSING MARGIN TRIMMING METHOD THEREOF - A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered. | 2012-12-13 |
20120314479 | MEMORY ELEMENT AND MEMORY DEVICE - A memory element includes: a memory layer disposed between a first electrode and a second electrode. The memory layer includes: an ion source layer containing one or more metallic elements, and one or more chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se); and a resistance change layer disposed between the ion source layer and the first electrode, the resistance change layer including a layer which includes tellurium and nitrogen (N) and is in contact with the ion source layer. | 2012-12-13 |
20120314480 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit. | 2012-12-13 |
20120314481 | CELL-STATE MEASUREMENT IN RESISTIVE MEMORY - Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (S | 2012-12-13 |
20120314482 | SEMICONDUCTOR MEMORY DEVICE - An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained. | 2012-12-13 |
20120314483 | SEMICONDUCTOR DEVICE - A semiconductor device includes a bit line, a memory cell, and a control circuit. The memory cell includes a switch circuit coupled to the bit line and a memory element configured to store either one of first and second data. The control circuit controls a voltage of the bit line to turn on the switch element in a first time period and to turn off the switch element in a second time period following the first time period when the control circuit writes the first data to the memory element. The control circuit controls the voltage of the bit line to turn on the switch element in the first time period and to maintain an on-state of the switch circuit in the second time period when the control circuit writes the second data to the memory element. | 2012-12-13 |
20120314484 | Multilevel DRAM - A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell. | 2012-12-13 |
20120314485 | COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM - An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element. | 2012-12-13 |
20120314486 | Semiconductor Memory Device for Reducing Charge/Discharge Power of Write Bitlines - It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit which is capable of reading retention data from read bitline (RBL) of each memory cell of a memory cell group in a column direction and drives the write bitlines only for the memory cells of a half-selected column according to the read data, 2) a selection signal circuit to which an enable signal and a column selection signal of the bitline half driver circuit are input and which activates the bitline half driver circuit, and 3) an equalizer circuit which equalizes the write bitlines of the memory cell group in the column direction and does not precharge the write bitlines. | 2012-12-13 |
20120314487 | Magnetic Random Access Memory Devices Including Multi-Bit Cells - A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. | 2012-12-13 |
20120314488 | Magnetic Random Access Memory Devices Including Multi-Bit Cells - A magnetic random access memory (MRAM) cell includes a storage layer, a sense layer, and a spacer layer between the storage layer and the sense layer. A field line is magnetically coupled to the MRAM cell to induce a magnetic field along a magnetic field axis, and at least one of the storage layer and the sense layer has a magnetic anisotropy axis that is tilted relative to the magnetic field axis. During a write operation, a storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, where at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. During a read operation, a sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer. | 2012-12-13 |
20120314489 | SYSTEMS AND METHODS FOR DIRECT COMMUNICATION BETWEEN MAGNETIC TUNNEL JUNCTIONS - Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction. | 2012-12-13 |
20120314490 | MAGNETIC MEMORY SYSTEM AND METHODS IN VARIOUS MODES OF OPERATION - A magnetic memory system includes a superconductor circuit and one or more magnetic memory elements to store data. To write data, a driver circuit in the superconductor circuit generates a magnetic signal for transmission over a superconductor link extending between the superconductor circuit and the magnetic memory element. To read data, a sensing circuit in the superconductor circuit monitors a superconductor link extending from sensing circuit to the magnetic memory element. The magnetic memory element can be a spin-transfer type magnetic memory element. | 2012-12-13 |
20120314491 | SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory. | 2012-12-13 |
20120314492 | NON-VOLATILE MEMORY DEVICE HAVING PHASE-CHANGE MATERIAL AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks. | 2012-12-13 |
20120314493 | PHASE CHANGE MEMORY AND METHOD FOR FABRICATING PHASE CHANGE MEMORY - A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole. | 2012-12-13 |
20120314494 | SEMICONDUCTOR STORAGE DEVICE - In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines. | 2012-12-13 |
20120314495 | APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB - The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. | 2012-12-13 |
20120314496 | NONVOLATILE MEMORY DEVICES HAVING IMPROVED READ RELIABILITY - Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages. | 2012-12-13 |
20120314497 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. | 2012-12-13 |
20120314498 | Method for Detecting Flash Program Failures - One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid. | 2012-12-13 |
20120314499 | INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE - A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage. | 2012-12-13 |
20120314500 | NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation. | 2012-12-13 |
20120314501 | SEMICONDUCTOR DEVICE AND METHOD OF PROGRAMMING THE SAME - A method of programming a semiconductor device includes performing a Least Significant Bit (LSB) program operation on selected memory cells, performing a soft program operation on the remaining memory cells other than memory cells on which the LSB program operation has been performed, and performing a Most Significant Bit (MSB) program operation on memory cells, selected from among the memory cells on which the LSB program operation has been performed and the memory cells on which the soft program operation has been performed. | 2012-12-13 |
20120314502 | PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING - A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming. | 2012-12-13 |
20120314503 | COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage. | 2012-12-13 |
20120314504 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes units each including memory cells, a data bus connected to each of the units and having data lines, holding circuits configured to hold fail information supplied from the unit through the data bus as a verify result after writing data, and provided in association with the data lines, respectively, daisy chain circuits configured to shift a flag includes a logical sum of the fail information held in the holding circuits, and provided in association with the data lines, respectively, and a search circuit configured to search for fail bits in the units based on the flag. | 2012-12-13 |
20120314505 | ROW DECODER AND NON-VOLATILE MEMORY DEVICE - A non-volatile memory device and a row decoder, the non-volatile memory device including: a memory cell array comprising a plurality of memory cells and each memory cell includes a first cell transistor and a second cell transistor; and a row decoder comprising a first driver and a second driver for generating first and second control signals. The first cell transistor is connected to the row decoder to receive the first control signal and the second cell transistor is connected to the row decoder to receive the second control signal. The first driver includes a first NMOS transistor and a first PMOS transistor formed adjacent to the first NMOS transistor. The second driver includes a second NMOS transistor and a second PMOS transistor formed adjacent to the second NMOS transistor. The first and second NMOS transistors are disposed between the first PMOS transistor and the second PMOS transistor. | 2012-12-13 |
20120314506 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes cell strings that each include a plurality of memory cells, a page buffer having latches coupled to bit lines and precharge the bit lines in response to page buffer control signals, a page buffer control circuit configured to generate the page buffer control signals using a high voltage source, and a controller configured to generate control signals for controlling the page buffer control circuit. | 2012-12-13 |
20120314507 | REDUCED VOLTAGE NONVOLATILE FLASH MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to flash memory. | 2012-12-13 |
20120314508 | CONTROL CIRCUITRY FOR MEMORY CELLS - Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination. | 2012-12-13 |
20120314509 | NON-VOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SAME - A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer. | 2012-12-13 |
20120314510 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier. | 2012-12-13 |
20120314511 | SEMICONDUCTOR DEVICE - A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer. | 2012-12-13 |
20120314512 | CACHE MEMORY AND METHOD FOR DRIVING THE SAME - A cache memory which can operate with less power consumption and has an improved cache hit rate and a method for driving the cache memory are provided. Two data storage portions (a first storage portion and a second storage portion) and one data transfer portion are provided in one memory cell in a memory set included in a cache memory, and arranged so that data can be transferred between the two storage portions via the data transfer portion. One of the two data storage portions can store data input from the outside and output data to a comparison circuit paired with the memory set. | 2012-12-13 |
20120314513 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified. | 2012-12-13 |
20120314514 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes word lines stacked over a substrate having a plurality of memory block regions, select lines arranged over the word lines, vertical channel layers formed to penetrate through the select lines and the word lines and extending to the substrate, and a charge trap layer disposed between the word lines and the vertical channel layers, wherein the stacked word lines are separated by memory block groups that each include two or more memory block regions. | 2012-12-13 |
20120314515 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell. | 2012-12-13 |
20120314516 | Performing Stuck-At Testing Using Multiple Isolation Circuits - A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals. | 2012-12-13 |
20120314517 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 2012-12-13 |
20120314518 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address. | 2012-12-13 |
20120314519 | WORD LINE DRIVING SIGNAL CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME, AND WORD LINE DRIVING METHOD - A word line driving signal control circuit of a semiconductor memory apparatus provided with a sub-redundancy cell array includes a fuse unit configured to generate a redundancy enable signal in response to a bank active signal and an address signal, and a repair determination unit configured to activate one of a normal word line driving signal, a redundancy word line driving signal, and a sub-redundancy word line driving signal in response to the bank active signal and the redundancy enable signal. | 2012-12-13 |
20120314520 | Memory Architecture With Redundant Resources - A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses. | 2012-12-13 |
20120314521 | MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT - Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed. | 2012-12-13 |
20120314522 | CONTROLLING CLOCK INPUT BUFFERS - An integrated circuit may have a clock input pin coupled to a buffer ( | 2012-12-13 |
20120314523 | MULTI-PORT MEMORY DEVICES AND METHODS - Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks. | 2012-12-13 |
20120314524 | SEMICONDUCTOR DEVICE - An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed. | 2012-12-13 |
20120314525 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level. | 2012-12-13 |
20120314526 | APPARATUS AND METHOD FOR MIXING OF CORROSIVE AND NON-CORROSIVE GAS - Present application relates to a mixing device ( | 2012-12-13 |
20120314527 | STIRRER FOR ALL TYPES OF CONTAINERS, AND ESPECIALLY FOR A BABY BOTTLE - A mixer for a container, the mixer including a gripping portion, a motor integrated into the gripping portion, a rotary shaft driven by the motor, and a mixing element having a flexible body. The mixing element has a first flexible body portion having a first end and a second flexible body portion having a second end, the first end and the second end being connected to the rotary shaft. | 2012-12-13 |
20120314528 | DEVICE, FLUIDIC MODULE AND METHOD FOR PRODUCING A DILUTION SERIES - A device for producing a dilution series from a solution to be diluted, which contains a substance to be diluted, and a dilution solution, includes a body of rotation, a drive configured to subject the body of rotation to rotations having different rotation protocols, and a controller configured to control the drive so as to subject the body of rotation to the different rotational frequencies. A first mixing chamber and a second mixing chamber are connected via a fluidic connection which enables producing, in the first mixing chamber, a first mixture having a first dilution ratio, transferring a partial volume of the first mixture into the second mixing chamber, and there producing a second mixture having a second dilution ratio. | 2012-12-13 |
20120314529 | VENTURI APPARATUS - An improved venturi apparatus for facilitating the mixture of fluid substances. The apparatus comprises a first funnel section operative to receive a fluid and channel the same through a first cylindrical section or passageway. The first cylindrical section is fluidly connected to an intermediate passageway having a diameter larger than the first cylindrical section. At least one sidearm passageway is fluidly connected to the intermediate passageway into which at least one second fluid is introduced. The sidearm passageway is preferably configured to fluidly interconnect with the intermediate passageway at approximately the medial portion of the intermediate passageway. Fluidly connected to the intermediate passageway is a second cylindrical section operative to direct the flow of the intermixed fluids to a second exit funnel section. The improved venturi apparatus is exceptionally efficient at drawing in a second fluid and effective in facilitating mixture of two or more gasses, liquids or combinations thereof. | 2012-12-13 |
20120314530 | REHYDRATION CAPSULE AND METHOD OF USING THE SAME - A rehydration capsule, and a method of rehydrating media within such capsule, the capsule including a capsule body having an inlet and an outlet, a member proximate the inlet having at least an opening therethrough, a filter proximate the outlet, and a hollow flow tube corresponding to each of said at least one opening mounted to the member and having an inlet at one end aligned with the at least one opening and having at least one opening through its body. | 2012-12-13 |
20120314531 | CARTRIDGE, CENTRIFUGE AND METHOD FOR MIXING A FIRST AND SECOND COMPONENT - A cartridge is configured for insertion and centrifugation in a centrifuge. The cartridge includes a mixing chamber, which comprises a container that is configured for at least one first component and at least one second component and electromagnetic particles. The electromagnetic particles are movable by an electromagnetic force to mix the first and second components. | 2012-12-13 |
20120314532 | CARTRIDGE, CENTRIFUGE AND METHOD - A cartridge includes a first drum having a first chamber and a displacement device that is configured to rotate the first drum about a central axis to connect the first chamber to a second chamber in a conductive manner. The cartridge further includes an electric switch that is configured to be actuated by the displacement device between a closed switching state and an open switching state. | 2012-12-13 |
20120314533 | STIRRING BLADE GROUP STRUCTURE AND STIRRING DEVICE USING THE SAME - A stirring blade group structure comprises a stirring blade base and at least three groups of stirring blades attached to the stirring blade base. Each stirring blade group includes a stirring shaft, a lower stirring blade, and an upper stirring blade. The upper stirring blade and the lower stirring blade cross and are attached to one end of the stirring shaft. The upper stirring blade is U-shaped. | 2012-12-13 |
20120314534 | ACOUSTIC WAVE IMAGING APPARATUS AND ACOUSTIC WAVE IMAGING METHOD - An acoustic wave imaging apparatus having: a phase aligning unit which aligns phases of received signals obtained by a plurality of acoustic wave receiving elements; a complex signal acquiring unit which generates complex signals out of the phase aligned received signals; a correlation matrix calculating unit which calculates a correlation matrix of the complex signals; and an electric power calculating unit which calculates constrained minimum power of the received signals, using the correlation matrix and a predetermined constraint vector, wherein the correlation matrix calculating unit calculates the correlation matrix at a predetermined cycle, and sequentially outputs the calculated correlation matrix to the electric power calculating unit at a predetermined cycle, and the electric power calculating unit calculates a plurality of constrained minimum powers in parallel using the calculated correlation matrices, the plurality of constrained minimum powers are corresponding to the correlation matrices respectively. | 2012-12-13 |
20120314535 | SYSTEM AND METHOD OF A MARINE SURVEY USING VERTICALLY ORIENTED SENSOR STREAMERS - Marine surveys using vertically oriented sensor streamers. At least some embodiments are vertically oriented sensor streamers where each sensor streamer includes: an elongated outer jacket; a plurality of hydrophones coupled to the outer jacket, each hydrophone of the plurality of hydrophones longitudinally spaced along the outer jacket; a plurality of three-axis motion detectors, each three-axis motion detector of the plurality of three-axis motion detectors longitudinally spaced along the outer jacket; and a plurality of electrodes coupled to the outer jacket, each electrode of the plurality of electrodes longitudinally spaced along the outer jacket, and the plurality of electrodes electrically exposed outside the outer jacket. Other embodiments may also comprise a plurality of electrodes on each sensor streamer, the electrodes for measuring electromagnetic energy. | 2012-12-13 |
20120314536 | ENHANCING LOW FREQUENCY CONTENT IN MARINE SIMULTANEOUS VIBROSEIS ACQUISITION - A technique is designed for conducting a seismic survey. The technique utilizes a plurality of vibrator arrays employed to conduct a seismic survey utilizing low frequency and high frequency vibrators in each vibrator array. The plurality of vibrator arrays continuously sweeps low frequency signals via low frequency vibrators. While sweeping low frequency signals, high-frequency vibrators emit high-frequency signals in an alternating pattern between vibrator arrays to enhance the seismic survey. | 2012-12-13 |
20120314537 | Methods and Systems for Seismic Signal Detection - Methods and systems utilizing seismic sensors configured or designed for use in seismic signal detection. An electrical current is applied to a seismic sensor such that the moving coil is located at a neutral position relative to the magnetic field in the seismic sensor to compensate for gravitational acceleration. | 2012-12-13 |
20120314538 | SYSTEM AND METHOD FOR SEISMIC DATA INVERSION - A system and computer-implemented method for determining properties of a subsurface region of interest from seismic data is disclosed. In an embodiment, the method includes obtaining seismic data representative of the subsurface region and an initial earth property model for the subsurface region, performing forward modeling using the initial earth property model to create modeled seismic data with similar acquisition specifications as the actual seismic data, transforming the modeled and actual seismic data to a temporal Fourier frequency domain to create frequency domain modeled and actual seismic data wherein the frequency domain modeled and actual seismic data include an amplitude portion and a phase portion, measuring the misfit between the frequency domain modeled seismic data and frequency domain actual seismic data to produce frequency domain residual seismic data, performing phase unwrapping of the phase portion of certain observed frequency components of the frequency domain residual seismic data to create an unwrapped residual phase portion, and inverting the unwrapped residual phase portion to determine desired properties of the subsurface region of interest, wherein the inverting minimizes an objective function defined to measure the misfit. The method may also include phase extrapolation. Additionally, the method may include a second inverting step using the result of the first inverting step as a starting model. The system includes a data source, a user interface, and a processor configured to execute computer modules designed to perform the method. | 2012-12-13 |
20120314539 | Method to Look Ahead of the Bit - The present disclosure is direct to method of performing measurements while drilling in an earth formation. The method may include estimating a location of a seismic reflector using signals from one or more of seismic sensors located at a plurality of locations in a borehole and the drilling depth of the one or more seismic sensors in a borehole. The signals may include information about times when the seismic sensors detect a direct wave and a reflected wave. The method may include storing the information in a memory using a processor. | 2012-12-13 |
20120314540 | HOLLOW REBAR FOR CROSSHOLE SONIC LOGGING ACCESS TUBES AND LONGITUDINAL CONCRETE REINFORCING IN DRILLED SHAFTS - Hollow rebar may be used for structural reinforcement in a drilled shaft and to provide access tubes for a sonic integrity testing probe. Rebar (short for reinforcing bar) is steel bar used as a tensioning device in reinforced concrete that holds the concrete in compression. According to the system described herein, hollow rebar may provide high strength reinforcement in the drilled shaft while at the same time providing an access tube for a sonic integrity testing process, such as crosshole sonic logging (CSL). The high strength hollow rebar, having ridges, threads and/or other appropriate surface deformations, provides improved adhesion to concrete, thus eliminating the problem of debonding associated with non-structural access tubes made of smooth PVC or steel pipe. | 2012-12-13 |
20120314541 | OBJECT DETECTION APPARATUS - An object detection apparatus disposed in a moving body generates a transmission signal of multiple pulse sequences as a plurality of sequences of multiple pulses. A modulation signal of the transmission signal is generated by performing digital modulation on each of the multiple pulse sequences of the transmission signal according to a code sequence. A transmission wave based on the modulation signal is transmitted and a reflected wave of the transmission wave is received by the apparatus. The apparatus further detects a speed of the moving body to determine a length of the code sequence. The apparatus calculates a code correlation value between the modulation signal and a received signal, which is derived from the reflected wave, and performs pulse compression on the received signal based on the code correlation value to generate a pulse-compressed received signal. The apparatus detects an object based on the pulse-compressed received signal. | 2012-12-13 |
20120314542 | SYSTEM AND METHOD FOR ESTIMATING PROJECTILE TRAJECTORY AND SOURCE LOCATION - Systems and methods for estimating projectile trajectory and projectile source location are provided. A method for estimating location information associated with a supersonic projectile propelled from a source includes recording sound at a first location using a single microphone during travel of the supersonic projectile to produce an acoustic recording. The method further includes estimating a miss distance between the first location and a trajectory of the projectile based on the shockwave length. Locating a projectile source includes concurrently recording sound at multiple locations and generating data sets associated with the locations, each of the plurality of data sets including a miss distance, a range, a time of arrival of a muzzle blast from the source, and a time of arrival of a shockwave produced by the projectile. Additionally, the method includes calculating an approximate location of the source at each of the locations based on the data sets. | 2012-12-13 |
20120314543 | SIGNAL GENERATION DEVICE - Provided is a signal generation device used for an information input method using an ultrasonic signal. Contact electrodes which are formed in a flexible printed circuit board to be in contact with an ultrasonic wave generation unit and reference signal generation units are disposed in a row, so that a length of the flexible printed circuit board can be reduced. Accordingly, in comparison with a signal generation module in the related art, a length of the signal generation module can be reduced, so that the signal generation device can be miniaturized. In addition, in order to maintain the contact between contact electrodes of the flexible printed circuit board and the ultrasonic wave generation unit, the contact electrodes which are in contact with the ultrasonic wave generation unit and the flexible printed circuit board are surrounded by a contact maintaining member which is constructed with a cylindrical elastic member. | 2012-12-13 |
20120314544 | CALENDAR MECHANISM AND TIMEPIECE HAVING THE SAME - A calendar mechanism of a timepiece includes a date indicator having a date wheel portion provided with a notched portion. An operation lever attached to the date indicator is pivotable between a pre-feed allowing position, where a tooth-shaped engaged portion thereof is inserted into the notched portion whereby excess feeding of the date indicator is possible, and a normal feed allowing position, where the tooth-shaped engaged portion retreats from the notched portion whereby normal feeding is possible. The date indicator is rotated by a day earlier than the normal feeding when set to the pre-feed allowing position. A driving lever structure includes a cam follower engaged with a month cam and is driven in response to rotation of the month cam to allow the operation lever to be pivoted between the normal feed allowing position and the pre-feed allowing position. | 2012-12-13 |
20120314545 | METHOD AND SYSTEM FOR UPDATING OF DISPLAYS SHOWING DETERMINISTIC CONTENT - A method and apparatus for displaying image data on a display device is disclosed. In some embodiments, the method includes updating at least a portion of the display device based on image update data identifying pixels that changed from the preceding image to the following image. | 2012-12-13 |
20120314546 | TIMEPIECE WITH TWIST RESTRICTED FLEXIBLE DISPLAY - A digital wrist watch includes a flexible digital display having an axis of curvature around which the display bends that is electrically connected to a microcontroller unit and is also electrically connected to a power source. Some of the plurality of electrical connections are positioned over at least one of a plurality of links that are configured to restrict twisting of the flexible digital display. The power source includes a battery positioned in an opening defined by one of the plurality of links The battery at least partially overlaps the plane of that link, The flexible digital display is selected from the group consisting of an electrophoretic display, a liquid crystal display, or an organic light emitting diode display. | 2012-12-13 |
20120314547 | HAMR Recording Head Having a Sloped Wall Pole - An apparatus includes a waveguide having an end adjacent to an air bearing surface, first and second poles positioned on opposite sides of the waveguide, and wherein the first pole includes a first portion spaced from the waveguide and a second portion extending from the first portion to the air bearing surface, with the second portion being structured such that an end of the second portion is closer to the waveguide than the first portion. | 2012-12-13 |
20120314548 | Head Gimbal Assembly With Heat Assist Laser - An apparatus and associated method for a head gimbal assembly for data transduction in a data storage device with a heat assist laser. Various embodiments of the present invention are generally directed to a slider supporting at least a transducing element on an air bearing surface (ABS) and a laser assembly directly attached to a top side of the slider opposite the ABS. The laser assembly is positioned on the top side with no portion of the laser assembly extending past a longitudinal centerline of the slider. | 2012-12-13 |
20120314549 | Near-Field Transducers for Focusing Light - An apparatus includes a waveguide shaped to direct light to a focal point, and a near-field transducer positioned adjacent to the focal point, wherein the near-field transducer includes a dielectric component and a metallic component positioned adjacent to at least a portion of the dielectric component. An apparatus includes a waveguide shaped to direct light to a focal point, and a near-field transducer positioned adjacent to the focal point, wherein the near-field transducer includes a first metallic component, a first dielectric layer positioned adjacent to at least a portion of the first metallic component, and a second metallic component positioned adjacent to at least a portion of the first dielectric component. | 2012-12-13 |
20120314550 | OPTICAL DISK DEVICE - An optical disk device is configured such that when an optical disk including three or more recording layers on one side is inserted into the optical disk device, a movable lens position adjustment device performs adjustment using as an index a tracking error signal provided with a limit to an amount of movement of a movable lens for spherical aberration correction at start-up of the optical disk device and sets an upper limit to the number of retries of the adjustment at the recording layer farthest away from the side on which the laser beam is incident to 1 or more. | 2012-12-13 |
20120314551 | OPTICAL DISC APPARATUS - Before tracking control is turned on, there is determined a correction formula for correcting a balance value of a tracking error signal depending on a position of a movable lens for spherical aberration correction. Then, after the tracking control has been turned on, using an RF signal as an index, the adjustment of the position of the movable lens for spherical aberration correction is performed, while the balance value of the tracking error signal is corrected by use of the correction formula. An adjustment value for adjusting the balance value of the tracking error signal at a time point of completing the adjustment of the position of the movable lens for spherical aberration correction is stored. | 2012-12-13 |
20120314552 | OPTICAL DISC APPARATUS - An optical disc apparatus includes an optical pickup, a signal generation section which generates a control signal from an electrical signal, and a main control section which controls the optical pickup such that, during a spin-up operation of an optical disc, the optical disc is discriminated to be a multiple-layer disc with three or more layers and address information is successfully acquired from the optical disc, the optical pickup irradiates the optical disc with a light beam at a light emission power for a multiple-layer disc with three or more layers. However, if disc information is not successfully acquired, the main control section controls the optical pickup to try again to acquire the disc information at the light emission power for a multiple-layer disc with three or more layers. | 2012-12-13 |
20120314553 | OPTICAL INFORMATION REPRODUCTION DEVICE, OPTICAL INFORMATION RECORDING DEVICE, OPTICAL INFORMATION REPRODUCTION METHOD, AND OPTICAL INFORMATION RECORDING METHOD - The present invention accurately operates a tilt servo even if a gap servo is operated with a small gap. A condensing unit ( | 2012-12-13 |
20120314554 | OPTICAL DISC DEVICE AND METHOD FOR SETTING PLAYBACK POWER OF OPTICAL DISC DEVICE - A focus search is performed on a mounted optical-disc recording medium once the optical-disc recording medium has been mounted in an optical disc device. The type of the mounted optical-disc recording medium is determined on the basis of results of the focus search. When a determination has been made that the mounted optical-disc recording medium is a multilayer optical-disc recording medium having three or more recording layers, a playback power is for an optical-disc recording medium being of a specification identical to the multilayer optical-disc recording medium and having one or two recording layers. A playback operation at the set playback power is used to read optical disc information from the mounted optical-disc recording medium, the optical disc information indicating the type of the mounted optical-disc recording medium. | 2012-12-13 |