50th week of 2019 patent applcation highlights part 50 |
Patent application number | Title | Published |
20190378707 | ELECTRICAL POTENTIAL ENERGY TO ELECTRICAL KINETIC ENERGY CONVERTER, OZONE GENERATOR, AND LIGHT EMITTER - Embodiments of the present invention describe electrical potential energy to electrical kinetic energy converters, ozone generators, and light emitters. A system for energy conversion from electrical potential energy to electrical kinetic energy may include a discharge device and a power supply. The power supply can be coupled with the discharge device, and supplies energy to the discharge device to form an initial electric field. The discharge device may further include at least two electrodes that are either mesh electrodes or wire-array electrodes. Furthermore, a space between the at least two electrodes is filled with a gas medium and an electric field is created by the power supply in a normal direction relative to planes formed by the elements of electrodes. | 2019-12-12 |
20190378708 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming an ohmic electrode including Al on a semiconductor substrate; forming a SiN film covering the ohmic electrode; forming a first photoresist on the SiN film, the first photoresist having an opening pattern overlapping the ohmic electrode; performing ultraviolet curing of the first photoresist; forming an opening in the SiN film exposed through the opening pattern and causing a surface of the ohmic electrode to be exposed inside the opening; forming a barrier metal layer on the first photoresist and on the ohmic electrode exposed through the opening; forming a second photoresist in the opening pattern; performing a heat treatment on the second photoresist and covering the barrier metal layer overlapping the opening with the second photoresist; and etching the barrier metal layer using the second photoresist. | 2019-12-12 |
20190378709 | DEPOSITION OF BORON AND CARBON CONTAINING MATERIALS - Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film. | 2019-12-12 |
20190378710 | ULTRATHIN ATOMIC LAYER DEPOSITION FILM ACCURACY THICKNESS CONTROL - Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature. | 2019-12-12 |
20190378711 | FORMATION OF SiN THIN FILMS - Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyly halide, such as H | 2019-12-12 |
20190378712 | LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK - A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material. | 2019-12-12 |
20190378713 | Method for lower thermal budget multiple cures in semiconductor packaging - A multilayer structure comprises: a substrate; and, a plurality of polymerizable layers successively deposited on the substrate, with each successive layer having a greater dielectric polarizability than the preceding layer(s), so that each successive layer will absorb microwave energy preferentially to the preceding layer(s). In this way, successive layers can be cured without over-curing the preceding layers. The individual layers are preferably materials from a single chemical family (e.g., epoxies, polyimides, PBO, etc.) and have similar properties after curing. The dielectric polarizabilities may be adjusted by modifying such factors as chain endcap dipole strength, cross-linker dipole strength, promoter, solvent, and backbone type. The invention is particularly suitable for producing various polymer layers on silicon for electronic applications. An associated method is also disclosed. | 2019-12-12 |
20190378714 | METHOD FOR CONTROLLING PLASMA IN SEMICONDUCTOR FABRICATION - A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member. | 2019-12-12 |
20190378715 | FORMING SEMICONDCUTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS - The current disclosure describes semiconductor devices, e.g., transistors, include a substrate, a semiconductor region including, at the surface, MoS | 2019-12-12 |
20190378716 | INFRARED OPTICAL SENSOR AND MANUFACTURING METHOD THEREOF - Provided is an infrared optical sensor including a substrate, a channel layer on the substrate, optical absorption structures dispersed and disposed on the channel layer, and electrodes disposed on the substrate, and disposed on both sides of the channel layer, wherein the channel layer and the optical absorption structures include transition metal dichalcogenides. | 2019-12-12 |
20190378717 | INTEGRATION OF DEVICE REGIONS - The present disclosure relates to a method for creating regions of different device types on a substrate having different pitches. The method includes dividing a substrate into a first device type region and a second device type region. The method further includes forming a target etch layer on the substrate. The method further includes forming a bottom mandrel layer on the target etch layer. The method further includes forming a plurality of alternating first pillars of a top mandrel material and first trenches between the first pillars on the bottom mandrel layer in the first device type region. The plurality of first pillars has a first pitch. The method further includes forming a plurality of alternating second pillars of the top mandrel material and second trenches between the second pillars on the bottom mandrel layer in the second device type region. The plurality of second pillars has a second pitch. The method further includes depositing tone inversion material in the first trenches. | 2019-12-12 |
20190378718 | MULTIPLE PATTERNING SCHEME INTEGRATION WITH PLANARIZED CUT PATTERNING - A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a plurality of mandrels from a base structure, forming a plurality of non-mandrels including a hard mask material having an etch property substantially similar to that of the plurality of mandrels, forming photo-sensitive material or a memorization layer over the plurality of mandrels and the plurality of non-mandrels, and applying an exposure scheme to the photo-sensitive material or the memorization layer to create at least one mandrel cut pattern and at least one non-mandrel cut pattern. | 2019-12-12 |
20190378719 | CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION - Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array. | 2019-12-12 |
20190378720 | CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION - Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array. | 2019-12-12 |
20190378721 | METHODS OF FABRICATING HIGH VOLTAGE SEMICONDUCTOR DEVICES - A method includes forming a blocking pattern on a buffer insulation layer disposed over a first region in a semiconductor region of a second conductivity type, forming an ion implantation mask pattern having an opening over the buffer insulation layer to expose the blocking pattern by the opening of the ion implantation mask pattern, and implanting impurity ions of a first conductivity type for forming a body region of the first conductivity type into the first region using the ion implantation mask pattern. | 2019-12-12 |
20190378722 | SEMICONDUCTOR DEVICE WITH IMPROVED GATE-SOURCE/DRAIN METALLIZATION ISOLATION - A method of forming a semiconductor device such as a FinFET device includes forming a gate stack over a channel region of a semiconductor fin between spacer layers, recessing the gate stack and the spacer layers, and forming a gate conductor layer over both the recessed gate stack and the spacer layers. The gate conductor layer is adapted to inhibit etch damage to the spacer layers during a subsequent etching step used to form contact openings over source/drain regions of the fin. The resulting structure exhibits improved electrical isolation between gate and source/drain contacts. | 2019-12-12 |
20190378723 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming method includes: repeatedly performing a source gas adsorption process including supplying a source gas containing a metal element to form a nitride film on a substrate in a chamber and purging a residual gas, and a nitriding process including supplying a nitriding gas onto the substrate and purging a residual gas; and supplying a hydrazine-based compound gas as a part or all of the nitriding gas. | 2019-12-12 |
20190378724 | ETCHING METHOD AND ETCHING APPARATUS - There is provided an etching method which includes: providing a substrate inside a chamber, the substrate including a silicon oxide-based material and other material, the silicon oxide-based material including an etching target portion having a width of 10 nm or less and an aspect ratio of 10 or more; and selectively etching the etching target portion with respect to the other material by supplying an HF gas and an OH-containing gas to the substrate. | 2019-12-12 |
20190378725 | METHOD FOR TRANSFERRING A PATTERN FROM AN ORGANIC MASK - A method for patterning a stack having a patterned organic mask with a plurality of mask features including sidewalls and tops, a hardmask and an etch layer, wherein the patterned organic mask is positioned over the hardmask which is positioned over the etch layer is provided. An atomic layer deposition is deposited, wherein the depositing the atomic layer deposition controllably trims the plurality of mask features of the patterned organic mask. The atomic layer deposition is broken through. The hardmask is selectively etched with respect to the patterned organic mask, wherein the atomic layer deposition reduces faceting of the plurality of mask features of the patterned organic mask during the selective etching. | 2019-12-12 |
20190378726 | PRE-CUT PLATING LINES ON LEAD FRAMES AND LAMINATE SUBSTRATES FOR SAW SINGULATION - Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame. | 2019-12-12 |
20190378727 | MULTILAYER CIRCUIT BOARD MANUFACTURING METHOD - There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate. | 2019-12-12 |
20190378728 | MULTILAYER CIRCUIT BOARD MANUFACTURING METHOD - There is a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween, wherein an unoccupied region without the soluble adhesive layer is provided within a facing area where the reinforcing sheet faces the multilayer laminate; allowing a liquid capable of dissolving the soluble adhesive layer to infiltrate the unoccupied region to dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced to generate no large local warpage, thereby improving the reliable connection and the surface flatness (coplanarity) of the multilayer wiring layer. The used reinforcing sheet can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate. | 2019-12-12 |
20190378729 | REMOVAL OF PROCESS EFFLUENTS - Various embodiments comprise apparatuses and related method for cleaning and drying a substrate. In one embodiment, an apparatus includes a vertical substrate holder to hold and rotate the substrate at various speeds. An inner shield and outer shield, when in a closed position, surround the vertical substrate holder during operation of the apparatus. Each of the shields can operate independently in at least one of rotational speed and direction from the other shield. A front-side and back-side spray jet are arranged to spray at least one fluid onto both sides of the substrate and edges of the substrate substantially concurrently. A gas flow, combined with a high rotational-speed of the shields and substrate, assists in drying the substrate. At least one turbine disk is coupled in proximity to at least one of the shields to remove excess amounts of fluid. Additional apparatuses and methods of forming the apparatuses are disclosed. | 2019-12-12 |
20190378730 | PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A substrate processing method includes: selectively forming a first film on a surface of a substrate disposed in a processing container by plasma enhanced vapor deposition (PECVD); and forming a second film by atomic layer deposition (ALD) in a region of the substrate where the first film does not exist. The second film is formed by repeatedly performing a sequence including: forming a precursor layer on the surface of the substrate; purging an interior of the processing container after forming of the precursor; converting the precursor layer into the second film; and purging a space in the processing container after the converting. A plasma processing apparatus performing the method is also provided. | 2019-12-12 |
20190378731 | HEATING ELEMENT, SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Described herein is a technique capable of processing a substrate uniformly using microwaves. According to one aspect of the technique of the present disclosure, there is provided a heating element used in a substrate processing apparatus configured to heat a substrate supported by a substrate retainer by microwaves and process the substrate, the heating element including a dielectric material of an annular shape capable of generating heat by the microwaves. An inner circumferential portion of the heating element is located outer than an outer circumferential portion of the substrate, and the heating element is supported by the substrate retainer without contacting the substrate. | 2019-12-12 |
20190378732 | TREATMENT APPARATUS FOR TREATING WORKPIECE - A treatment apparatus including a chuck table, a table base, a servo motor that rotates the table base, and a determination unit that determines the kind of the chuck table mounted to the table base is provided. The determination unit includes a torque recording section in which a torque outputted by the servo motor when rotating the table base is recorded on the basis of the kind of the chuck table, and a determination section that collates the torque outputted by the servo motor with the torque recording section, to thereby determine the kind of the chuck table. | 2019-12-12 |
20190378733 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND CLEANING APPARATUS - The method of manufacturing a semiconductor device according to the embodiment includes a step of performing cleaning. The cleaning step includes a step of preparing a cleaning apparatus having a first rotation mechanism including a first motor, a second rotation mechanism including a second motor, a second central shaft, and a cylindrical roller brush including an outer peripheral surface; a step of rotating the semiconductor wafer around the first central axis by the first rotation mechanism; and a step of rotating the roller brush around the second central axis by the second rotation mechanism and contacting the outer peripheral surface with the surface. An abnormality in the cleaning step is detected based on the current output from the second motor. | 2019-12-12 |
20190378734 | WAFER TRANSFER UNIT AND WAFER TRANSFER SYSTEM - A wafer transfer unit includes at least one data processing unit, which is configured at least for a registration and/or processing of sensor data of at least one sensor, allocated to at least one sub-component of a wafer transfer system, of a sensor module, in particular includes at least one wafer processing module of the wafer transfer system, includes at least one wafer interface system of the wafer transfer system with a wafer transport container and a loading and/or unloading station for a loading and/or unloading of the wafer transport container and/or of the wafer processing module, includes at least one wafer transport container transport system of the wafer transfer system and/or includes at least one wafer handling robot of the wafer transfer system. | 2019-12-12 |
20190378735 | SUBSTRATE TRANSFER APPARATUS, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE MISALIGNMENT COMPENSATION METHOD - A substrate misalignment compensation method includes obtaining first coordinates for an amount of movement of a substrate transfer apparatus and second coordinates measured by a plurality of sensors installed on the substrate transfer apparatus while moving the substrate transfer apparatus in one direction, calculating a calibration value of the substrate transfer apparatus by using an equation of a circle for the first coordinates and an equation of a line for the second coordinates, and calculating the center of a circle for a substrate based on the calibration value of the substrate transfer apparatus and compensating for misalignment of the substrate by using the center of the circle. | 2019-12-12 |
20190378736 | Semiconductor Apparatus With Inner Wafer Carrier Buffer and Method - The present disclosure provides one embodiment of a semiconductor processing apparatus. The semiconductor processing apparatus includes a load lock designed to receive a wafer carrier; an inner wafer carrier buffer configured to hold the wafer carrier received from the load lock and to perform a nitrogen purge to the wafer carrier; and a processing module designed to perform a semiconductor process to wafers from the wafer. | 2019-12-12 |
20190378737 | Overlay Measurement Using Phase and Amplitude Modeling - Methods and systems are disclosed for determining overlay in a semiconductor manufacturing process. Radiation reflected from a diffraction pattern in a metrology target may include +1 and −1 diffraction patterns at different wavelengths and focal positions. The different wavelengths of radiation may be in a waveband where the sensitivity of contrast to wavelength is at a maximum. The reflected radiation may be analysed to obtain measured values of overlay as well as amplitude and/or phase corresponding to points distributed over the target, for different wavelengths and focal positions. The measured values of overlay may undergo a series of operations to determine the overlay. The determination may use an assumption that the amplitude and phase are unequal in the +1 and −1 diffraction orders. | 2019-12-12 |
20190378738 | ALIGNMENT APPARATUS - Disclosed is an alignment apparatus that aligns a treatment object having a notch. The alignment apparatus includes a support member on which the treatment object is positioned, a driving unit configured to rotate the support member, a pushing member configured to move the treatment object to a proper location on the support member by applying a force to a side surface of the treatment object positioned on the support member, a notch detecting unit configured to detect whether the notch of the treatment object is located at a specific location, and a controller configured to control the driving unit such that the notch of the treatment object is located at the specific location by rotating the support member. | 2019-12-12 |
20190378739 | COATING FILM FORMING APPARATUS AND ADJUSTMENT METHOD THEREFOR - A coating film forming apparatus includes a carry-in/out section in which a substrate is carried in and carried out; a periphery coating module configured to form a ring-shaped coating film by supplying a coating liquid along a periphery of the substrate based on a processing parameter for controlling a coating state by the coating film; an imaging module configured to image the substrate on which the ring-shaped coating film is formed; a transfer mechanism configured to transfer the substrate; and a controller configured to output a control signal to perform a process of forming the ring-shaped coating film on the substrate based on the processing parameter having different values and imaging the substrate by the imaging module, and configured to determine, based on an imaging result of the substrate, a value of the processing parameter for forming the ring-shaped coating film on the substrate in the periphery coating module. | 2019-12-12 |
20190378740 | TEACHING APPARATUS AND TEACHING METHOD FOR SUBSTRATE TRANSFER SYSTEM - There is provided a teaching apparatus for a substrate transfer system including a substrate transfer device and a substrate receiving device. The substrate transfer device is configured to hold a substrate. The substrate receiving device is configured to receive the substrate from the substrate transfer device. The teaching apparatus includes a teaching substrate configured to be held to the substrate transfer device, a camera mountable to the teaching substrate, and a controller that controls an operation of the substrate transfer device holding the teaching substrate and/or the substrate receiving device. | 2019-12-12 |
20190378741 | CHIP BONDING DEVICE - A chip bonding apparatus includes a chip separation unit, a chip alignment unit, a chip bonding unit and a bonding robotic arm unit. The bonding robotic arm unit includes a first bonding robotic arm unit and a second bonding robotic arm unit. The first bonding robotic arm unit includes a first motion stage, a first driver configured to drive the first motion stage and at least one first bonding robotic arm arranged on the first motion stage. The first bonding robotic arm is configured to suck up a chip from the chip separation unit and deliver it to the chip alignment unit. The second bonding robotic arm unit includes a second motion stage, a second driver configured to drive the second motion stage and at least one second bonding robotic arm arranged on the second motion stage. | 2019-12-12 |
20190378742 | CARRIER FOR USE IN A VACUUM SYSTEM, SYSTEM FOR VACUUM PROCESSING, AND METHOD FOR VACUUM PROCESSING OF A SUBSTRATE - The present disclosure provides a carrier ( | 2019-12-12 |
20190378743 | SEMICONDUCTOR PRODUCT TESTING DEVICE USING AN ELECTRIC STATIC CARRIER - A semiconductor product testing device using an electric static carrier includes a movable carrier plate serving to carry at least one semiconductor product for transferring or testing process; the movable carrier plate being arranged with at least one electric static circuit to suck the at least one semiconductor product; a movable detecting probe set including: a probe set includes at one probe or a plurality of probes; a robot being connected to the probe set for deriving the probe set to a predetermined test position; a control device connected to the robot and including a control circuit for controlling movements of the robot and a testing circuit; and a computer connected to the control device for getting testing data from the testing circuit; the computer providing functions to cause the user to determine test items and ways of the testing circuit and the moving paths of the robot. | 2019-12-12 |
20190378744 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device is provided. Multiple light-emitting elements are formed on a substrate in a first density. A first transferring process is performed to transfer the light emitting elements to a transition carrier. The light-emitting elements are disposed on the transition carrier in a second density. The first density is greater than the second density. Multiple electronic devices are disposed on the transition carrier in correspondence with the light-emitting elements. An encapsulation layer is formed on the transition carrier to cover the light emitting elements and the electronic devices. Portions of the encapsulation layer are removed to form multiple package units including the light-emitting elements and the electronic devices. A second transferring process is performed to transfer the package units to an array substrate. The encapsulation layer is removed to expose the light emitting elements and the electronic devices. The light emitting elements and the electronic devices are electrically connected to the array substrate. | 2019-12-12 |
20190378745 | WAFER PROCESSING METHOD - A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of blowing out air to push up each device chip and picking up each device chip from the polyester sheet. | 2019-12-12 |
20190378746 | WAFER PROCESSING METHOD - A wafer processing method includes a wafer providing step of placing a polyolefin or polyester sheet on an upper surface of a substrate for supporting a wafer and placing the wafer on an upper surface of the sheet in a condition where a back side of the wafer is exposed upward, a thermocompression bonding step of setting the wafer placed through the sheet on the substrate in an enclosed environment, next evacuating the enclosed environment, and next heating the sheet as applying a pressure to the wafer, thereby uniting the wafer through the sheet to the substrate by thermocompression bonding, a back processing step of processing the back side of the wafer supported through the sheet to the substrate, and a separating step of separating the wafer from the sheet bonded to the substrate. | 2019-12-12 |
20190378747 | MASK-INTEGRATED SURFACE PROTECTIVE TAPE, AND METHOD OF PRODUCING A SEMICONDUCTOR CHIP USING THE SAME - A mask-integrated surface protective tape, which has at least a substrate film and a mask material layer, wherein the mask material layer is provided directly on the substrate film, or is provided on the substrate film through a temporary-adhesive layer, and wherein a parallel ray transmittance of the mask material layer at a wavelength region of 355 nm is 30% or less; and a method of producing a semiconductor chip. | 2019-12-12 |
20190378748 | METHOD AND APPARATUS FOR MULTIPLE DIRECT TRANSFERS OF SEMICONDUCTOR DEVICES - An apparatus for a direct transfer of a semiconductor device die from a wafer tape to a substrate. A first frame holds the wafer tape and a second frame secures the substrate. The second frame holds the substrate such that a transfer surface is disposed facing the semiconductor device die on a first side of the wafer tape. Two or more needles are disposed adjacent a second side of the wafer tape opposite the first side. A length of the two or more needles extends in a direction toward the wafer tape. A needle actuator actuates the two or more needles into a die transfer position at which at least one needle of the two or more needles presses on the second side of the wafer tape to press a semiconductor device die of the one or more semiconductor device die into contact with the transfer surface of the substrate. | 2019-12-12 |
20190378749 | MICRO-VACUUM MODULE FOR SEMICONDUCTOR DEVICE TRANSFER AND METHOD FOR TRANSFERRING SEMICONDUCTOR DEVICE USING THE MICRO-VACUUM MODULE - The present disclosure provides a method for transferring a semiconductor device using a micro-vacuum module, wherein the micro-vacuum module includes: a vacuum-forming substrate having a plurality of through-holes, which are connected to an external pump module and a vacuum control unit, formed; and a pattern-forming unit equipped with a single channel or a plurality of independent channels, which is coupled to the vacuum-forming substrate, wherein the plurality of channels are formed to be communicated respectively to a plurality of vacuum holes which have a smaller size than the size of a semiconductor device to be transferred, and the plurality of vacuum holes, having a diameter smaller than 100 μm, are contacted to a micro semiconductor device having a width and a length of 100 μm or smaller and the micro semiconductor device is transferred using vacuum adsorption. | 2019-12-12 |
20190378750 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A method for treating a substrate using a substrate treating apparatus that includes a treating module and an index module that transfers the substrate between a container and the treating module, in which a plurality of process chambers and a main transfer robot are provided in the treating module and a container mounting table and an index robot that transfers the substrate between the container and the treating module are provided in the index module, includes executing a power failure after-treatment operation and thereafter stopping an operation of the substrate treating apparatus when a power failure occurs in the substrate treating apparatus. When the main transfer robot or the index robot is transferring the substrate in the event of the power failure, the power failure after-treatment operation includes an operation of continually maintaining the transfer of the main transfer robot or the index robot until the transfer is completed. | 2019-12-12 |
20190378751 | FINFET DEVICE COMPRISING A SINGLE DIFFUSION BREAK WITH AN UPPER SURFACE THAT IS SUBSTANTIALLY COPLANAR WITH AN UPPER SURFACE OF A FIN - A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin. | 2019-12-12 |
20190378752 | FINFET WITH CURVED STI - A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface. | 2019-12-12 |
20190378753 | METHOD FOR TRANSFER OF A THIN LAYER OF SILICON - A method for preparing semiconductor on insulator structures comprises transferring a thin layer of silicon from a donor substrate onto a handle substrate. | 2019-12-12 |
20190378754 | DOPING CONTROL OF METAL NITRIDE FILMS - Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping. | 2019-12-12 |
20190378755 | CONTROLLING GRAIN BOUNDARIES IN HIGH ASPECT-RATIO CONDUCTIVE REGIONS - Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level. | 2019-12-12 |
20190378756 | Method For Creating A Fully Self-Aligned Via - Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a liner that is selectively removable when compared to conductive lines. The liner may be selectively removed by utilizing one or more of a base (e.g. sodium hydroxide) and hydrogen peroxide. | 2019-12-12 |
20190378757 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature. | 2019-12-12 |
20190378758 | WAFER PROCESSING METHOD - A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of blowing out air to push up each device chip and picking up each device chip from the polyolefin sheet. | 2019-12-12 |
20190378759 | METHOD OF PROCESSING WAFER AND GRINDING APPARATUS - A method of processing a wafer includes a cutting step of cutting the face side of the wafer with a cutting blade to form grooves therein along projected dicing lines, a first inspecting step of capturing an image of the grooves formed in the cutting step and inspecting a state of a chip in the captured image of the grooves, a protecting member sticking step of sticking a protective member to the face side of the wafer, a grinding step of holding the protective member side of the wafer on a chuck table and grinding a reverse side of the wafer to thin the wafer to a finished thickness, thereby dividing the wafer into device chips, a second inspecting step of capturing an image of the grooves exposed on the reverse side of the wafer and inspecting a state of a chip in the captured image of the grooves. | 2019-12-12 |
20190378760 | DISPLAY DEVICE MANUFACTURING METHOD - An embodiment provides a display device manufacturing method comprising the steps of: preparing a substrate having a plurality of semiconductor chips arranged thereon (S | 2019-12-12 |
20190378761 | METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED STRUCTURES - The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures. | 2019-12-12 |
20190378762 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming at least one gate structure having a gate dielectric layer on a surface of the semiconductor substrate; forming first sidewall spacers on a first sidewall surface region of the gate structure and covering sidewall surfaces of the gate dielectric layer; forming second sidewall spacers on a second sidewall surface region of the gate structure and top surfaces of the first sidewall spacers and made of a material different from a material of the first sidewall spacers; forming conductive plugs in the dielectric layer at both sides of the gate structure, the first sidewall spacers and the second sidewall spacers; and removing the second sidewall spacers to form air gap spacers above the first sidewall spacers and between the second sidewall surface region of the gate structure and the conductive plugs. | 2019-12-12 |
20190378763 | HYBRID FIN CUT WITH IMPROVED FIN PROFILES - The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile. | 2019-12-12 |
20190378764 | SELF-LIMITING LINERS FOR INCREASING CONTACT TRENCH VOLUME IN N-TYPE AND P-TYPE TRANSISTORS - Embodiments of the invention are directed to a method of forming a protective liner of a semiconductor device, wherein the method includes forming a source or a drain (S/D) region, forming a first layer of protective material over a top surface of the S/D region, and forming a second layer of protective material over the first layer of protective material, wherein the second layer of protective material includes an oxide of a first type of material. An anneal is applied to the first layer and the second layer to drive the first type of material into the first layer, drive a second type of material from the first layer into the second layer, and convert at least a portion of the second layer of protective material to an oxide of the second type of material, wherein the oxide of the second type of material is the protective liner. | 2019-12-12 |
20190378765 | VERTICAL TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - A semiconductor structure includes a first fin and a second fin vertically disposed on a substrate. The first fin is adjacent to and parallel to the second fin. A first source/drain is disposed on the substrate, and a first dielectric spacer is disposed on the first source/drain. A gate is disposed on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin. A trench is adjacent to and parallel to the first fin and the second fin. The trench extends through a portion of the substrate and includes a top portion being narrower than a bottom portion. A dielectric material is disposed within the trench and pinches off the top portion of the trench to form an air gap spacer within the trench. The air gap spacer is parallel to and between the first fin and the second fin. | 2019-12-12 |
20190378766 | SEMICONDUCTOR DEVICE WITH HIGH-K GATE DIELECTRIC LAYER - Semiconductor device is provided. The semiconductor device includes a base substrate having a PMOS region and an NMOS region; a plurality gate structures formed on the base substrate, the gate structures including an interface layer formed on the base substrate, a high-K gate dielectric layer formed on the interface layer, a cap layer formed on the high-K gate dielectric layer and a metal layer formed over the high-K gate dielectric layer; an interlayer dielectric layer covering side surfaces of the gate structures formed over the base substrate; and source/drain doping regions formed in the base substrate at two sides of the gate structures. The gate structure is formed in an opening in the interlayer dielectric layer. The high-K gate dielectric layer is formed on side and bottom surfaces of the opening. The high-K dielectric layer contains additional oxygen ions diffused therein at a bottom portion. | 2019-12-12 |
20190378767 | REDUCED STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE FOOT PRINT THROUGH CONTROLLED BOTTOM SOURCE/DRAIN PLACEMENT - A method of reducing the distance between co-linear vertical fin field effect devices is provided. The method includes forming a first vertical fin on a substrate, forming a second vertical fin on the substrate, and depositing a masking block in the gap between the first vertical fin and second vertical fin. The method further includes depositing a spacer layer on the substrate, masking block, first vertical fin, and second vertical fin, depositing a protective liner on the spacer layer, and removing a portion of the protective liner from the spacer layer on the masking block and substrate adjacent to the first vertical fin. The method further includes removing a portion of the spacer layer from a portion the masking block and a portion of the substrate adjacent to the first vertical fin, and growing a first source/drain layer on an exposed portion of the substrate and first vertical fin. | 2019-12-12 |
20190378768 | DISPLAY PANEL PRODUCING SYSTEM AND METHOD OF PRODUCING DISPLAY PANEL - A display panel producing system for producing a display panel including a substrate on which films are laminated includes a measuring device, an ink-jet coating device, and a control device. The measuring device is configured to measure an uneven shape of a front face of the substrate in production. The ink-jet coating device is configured to apply a film formation material with an ink-jet technology to form the films on the substrate. The control device is configured to control the measuring device and the ink-jet coating device. The control device controls the measuring device to measure the uneven shape for formation of the films by the ink-jet coating device and to determine a control target for the formation of the films by the ink-jet coating device appropriate for the substrate on which measurement of the uneven shape is performed based on a result of the measurement. | 2019-12-12 |
20190378769 | METHOD OF AND SYSTEM FOR DETERMINING AN OVERLAY OR ALIGNMENT ERROR BETWEEN A FIRST AND A SECOND DEVICE LAYER OF A MULTILAYER SEMICONDUCTOR DEVICE - The present document relates to a method of determining an overlay or alignment error between a first and a second device layer of a multilayer semiconductor device ( | 2019-12-12 |
20190378770 | IMAGE DISPLAY DEVICE - A base substrate include a first substrate ( | 2019-12-12 |
20190378771 | Component Carrier With a Stepped Cavity and a Stepped Component Assembly Embedded Within the Stepped Cavity - Described are component carriers including a stepped cavity into which a stepped component assembly is embedded. The component carriers have (a) fully cured electrically insulating material originating from at least one electrically insulating layer structure of the component carrier and circumferentially surrounding the stepped component assembly and/or (b) an undercut in a transition region between a narrow recess and a wide recess of the stepped cavity. Further described are methods for manufacturing such component carriers. | 2019-12-12 |
20190378772 | WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE - A wiring substrate includes an insulating substrate being square in plan view, the insulating substrate including one main surface with a recess, and the other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate. The external electrodes are arranged in a row in a peripheral section of the insulating substrate. In plan view, an area of one of the external electrodes located at a center of each side of the insulating substrate is larger than an area of one of the external electrodes located at an edge of the each side. | 2019-12-12 |
20190378773 | GLASS ARTICLE HAVING A METALLIC NANOFILM AND METHOD OF INCREASING ADHESION BETWEEN METAL AND GLASS - An article including a glass or glass ceramic substrate, a noble metal layer, an adhesion promoting layer positioned between and bonded to the substrate and the noble metal layer, and a conductive metal layer positioned on and bonded to the noble metal layer. The adhesion promoting layer includes a siloxy group bonded with the substrate and a thiol group bonded to the noble metal layer. A method for manufacturing an article including applying an adhesion promoting layer comprising mercaptosilane to at least a portion of a glass or glass ceramic substrate, wherein siloxane bonds are formed between the mercaptosilane and the substrate, applying a noble metal layer to the adhesion promoting layer, the noble metal layer bonds with a thiol present in the mercaptosilane, thermally treating the noble metal layer, and applying a conductive metal layer to the noble metal layer. | 2019-12-12 |
20190378774 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE - An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands. | 2019-12-12 |
20190378775 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a core member having first and second through-holes, a passive component disposed in the first through-hole of the core member, a semiconductor chip disposed in the second through-hole of the core member and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, a first encapsulant encapsulating at least a portion of the passive component and having a first thermal conductivity, a second encapsulant encapsulating at least a portion of the semiconductor chip and having a second thermal conductivity higher than the first thermal conductivity, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. | 2019-12-12 |
20190378776 | APPARATUS HAVING A FUNCTIONAL STRUCTURE DELIMITED BY A FRAME STRUCTURE AND METHOD FOR PRODUCING SAME - An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure. | 2019-12-12 |
20190378777 | CHIP ON FILM PACKAGE - A chip on film package is disclosed, including a flexible film, a patterned circuit layer, a chip, and a dummy metal layer. The flexible film includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the first surface and electrically connected to the patterned circuit layer. The dummy metal layer covers the second surface capable of dissipating heat of the chip. The dummy metal layer is electrically insulated from the patterned circuit layer. | 2019-12-12 |
20190378778 | Metal Nanowire Based Thermal Interface Materials - A high-performance thermal interface material comprising a heterogeneous copper-tin nanowire array that is ultra-compliant and that can reduce thermal resistance by two times as compared with the state-of-the-art thermal interface materials. The high-performance thermal interface material can be further used in electronic systems, ranging from microelectronics to portable electronics to massive data centers, to operate at lower temperatures, or at the same temperature but with higher performance and higher power density. | 2019-12-12 |
20190378779 | MODULE - A module that has excellent heat dissipation performance and enables height reduction easily is provided. The module includes a wiring substrate, a plurality of components mounted on the top surface of the wiring substrate, a plurality of heat dissipation members, a sealing resin layer laminated on the top surface of the wiring substrate, and a shield film that covers surfaces of the sealing resin layer. The heat dissipation member is formed into a strip-shaped sheet. In addition, both end portions of the heat dissipation member are in contact with the top surface of the wiring substrate and also with the components disposed between the both end portions. The heat dissipation member thereby forms a heat dissipation path that transmits heat generated by the component to the wiring substrate. | 2019-12-12 |
20190378780 | HEAT-DISSIPATING ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF - A heat dissipating assembly is created, wherein the heat dissipating assembly comprises at least one power module that contains a printed circuit board ( | 2019-12-12 |
20190378781 | ENHANCED ADHESIVE MATERIALS AND PROCESSES FOR 3D APPLICATIONS - The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art. | 2019-12-12 |
20190378782 | ELECTRONIC DEVICE AND CONNECTION BODY - An electronic device has a sealing part | 2019-12-12 |
20190378783 | QFN Device Having A Mechanism That Enables An Inspectable Solder Joint When Attached To A PWB And Method Of Making Same - An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a UN device when it is attached to a printed wiring board (PWB). | 2019-12-12 |
20190378784 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element made up of a semiconductor substrate, an element electrode formed on the substrate, and a wiring layer electrically connected to the element electrode. The semiconductor device further includes a lead frame supporting the semiconductor element, a first conductive member electrically connecting the semiconductor element and the lead frame, a second conductive member overlapping with the semiconductor element as seen in plan view, and a sealing resin covering the semiconductor element, a part of the lead frame, and the first and second conductive member. The wiring layer includes a first pad portion and a second pad portion. The second conductive member has a first connecting portion bonded to the first pad portion and a second connecting portion bonded to the second pad portion. | 2019-12-12 |
20190378785 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode | 2019-12-12 |
20190378786 | POWER MODULE COMPRISING A HOUSING WHICH IS FORMED IN LEVELS - The invention relates to a power module. The power module has at least one power semiconductor and at least one further electronic component. The power module has a housing which is formed by a shaped body and is formed by an encapsulation compound. According to the invention, the housing is formed in at least two levels. At least one power semiconductor component is arranged in a first level and the at least one further electronic component is arranged in the second level. At least one electrically conductive layer, which forms an electrically conductive connecting structure, is formed on a surface of an inner boundary of the power module which extends between the levels. The connecting structure is applied directly to the surface. The at least one further electronic component is electrically conductively connected, in particular soldered or sintered, to the wiring structure. The power semiconductor component in the first level is electrically connected to the further component in the second level by means of the connecting structure. | 2019-12-12 |
20190378787 | SEMICONDUCTOR DEVICE - A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. | 2019-12-12 |
20190378788 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING CANTILEVERED PROTRUSION ON A SEMICONDUCTOR DIE - A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die. | 2019-12-12 |
20190378789 | PATTERNING OF DUAL METALLIZATION LAYERS - Embodiments may relate to a semiconductor package that includes a routing trace coupled with a substrate. The routing trace may be linear on a side of the routing trace between the substrate and a top of the routing trace. The semiconductor package may further include a power trace coupled with the substrate. The power trace may be concave on a side of the power trace between the substrate and a top of the power trace. Other embodiments may be described and/or claimed. | 2019-12-12 |
20190378790 | DEVICE LAYER INTERCONNECTS - Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array. | 2019-12-12 |
20190378791 | ELECTRONIC COMPONENT MOUNTING PACKAGE - An electronic component mounting package includes a semiconductor element which is disposed such that an active surface faces a main surface of a wiring portion, and which is electrically connected to the wiring portion via a first terminal; and a thin film passive element which is disposed between the active surface of the semiconductor element and the main surface of the wiring portion when seen in a lamination direction, and which is electrically connected to the semiconductor element. A part of the first terminal is disposed on an outer side with respect to the thin film passive element in a plan view. A length of the first terminal in the lamination direction disposed on the outer side with respect to the thin film passive element is larger than a thickness of the thin film passive element in the lamination direction. | 2019-12-12 |
20190378792 | SWITCHING DEVICE - A switching device includes first to third layers laminated in sequence above a principal surface of a substrate, a plurality of input terminals, a plurality of output terminals, a plurality of switching circuits, and a plurality of channels. Each of the channels electrically connecting one of the plurality of input terminals and one of the plurality of output terminals with one of the plurality of switching circuits interposed therebetween. The plurality of channels include a first channel and a second channel that intersect with each other when the principal surface of the substrate is seen in a plan view. In an intersection area where the first and second channels intersect with each other, the first channel is disposed on the first layer, the second channel is disposed on the third layer, and none of the plurality of channels is disposed on the second layer. | 2019-12-12 |
20190378793 | INTEGRATION OF GUARD RING WITH PASSIVE COMPONENTS - Aspects generally relate to forming components in an area inside a guard ring structure in an integrated circuit. | 2019-12-12 |
20190378794 | BANDGAP REFERENCE DIODE USING THIN FILM TRANSISTORS - Bandgap reference diodes and bandgap reference circuits are used to provide voltage references for a wide range of integrated circuit (IC) functions. Many bandgap reference diodes are fabricated directly on the substrate surface during the front-end-of-line (FEOL), and require a significant substrate footprint. Embodiments described herein are directed to bandgap reference diodes comprised of thin film transistors and methods of forming the same. The bandgap reference diodes described herein need not be fabricated during the FEOL, and can instead be formed during the back-end-of-line (BEOL) metallization workflow, freeing the substrate surface for other devices. | 2019-12-12 |
20190378795 | SEMICONDUCTOR PACKAGE, PACKAGE-ON-PACKAGE DEVICE, AND METHOD OF FABRICATING THE SAME - A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided. | 2019-12-12 |
20190378796 | SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE - A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse. | 2019-12-12 |
20190378797 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area. | 2019-12-12 |
20190378798 | SEAL RING BONDING STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to seal ring structures with channels and methods of manufacture. The structure includes: a first wafer having a channel formed within a passivation layer; a second wafer having a protuberance which is insertable into the channel and which is bonded to the first wafer with eutectic bonding materials; and a plurality of stoppers or tabs extending within the channel and which provides a gap that has a dimension smaller than a gap formed in other portions of the channel. | 2019-12-12 |
20190378799 | METHOD FOR ARRANGING TWO SUBSTRATES - A method and device for the alignment of substrates that are to be bonded. The method includes detecting and storing positions of alignment mark pairs located on surfaces of the substrates. and aligning the substrates with respect to each other in accordance with the detected positions. | 2019-12-12 |
20190378800 | OVERLAY MARK - An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance. | 2019-12-12 |
20190378801 | RF Functionality and Electromagnetic Radiation Shielding in a Component Carrier - A component carrier including i) an electronic component embedded in the component carrier, ii) an antenna structure arranged at a region of a first main surface of the component carrier, iii) a shielding structure made of an electrically conductive material and configured for shielding electromagnetic radiation from propagating between the antenna structure and the electronic component. Hereby, the shielding structure is arranged at least partially between the antenna structure and the electronic component. Furthermore, the component carrier includes an electrically conductive structure to electrically connect the electronic component and the antenna structure through the shielding structure. The shielding structure is non-perforated at least in a plane between the antenna structure and the electronic component. | 2019-12-12 |
20190378802 | ELECTRONIC COMPONENT MODULE - An electronic component module includes: electronic components mounted on a substrate, each of the electronic components having terminals located on a side, upper, and/or lower surface thereof; and a shield that is located on the substrate, has side plates surrounding the electronic components, and is supplied with a ground potential, wherein in an electronic component closest to one side plate of the side plates among one or more electronic components, in each of which at least one terminal of the terminals is located on the side and/or upper surface, a terminal a first distance of which to the one side plate is shortest among the at least one terminal is a first terminal supplied with the ground potential, and a second distance each of second terminals not supplied with the ground potential to the one side plate is greater than the first distance. | 2019-12-12 |
20190378803 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A package structure including at least one semiconductor chip, an insulating encapsulant, a conductive frame, a supporting frame, a conductive layer and a redistribution layer is provided. The at least one semiconductor chip has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the at least one semiconductor chip. The conductive frame is surrounding the insulating encapsulant. The supporting frame is surrounding the conductive frame. The conductive layer is disposed on the backside surface of the semiconductor chip. The redistribution layer is disposed on and electrically connected to the active surface of the semiconductor chip. | 2019-12-12 |
20190378804 | WIRING SUBSTRATE - A wiring substrate includes: a wiring member that includes a first surface and a second surface, the wiring member including a plurality of wiring layers between the first surface and the second surface; and a carrier that is bonded to the first surface via an adhesive and that includes a plurality of layers whose coefficients of thermal expansion are different from each other. A pitch of wires included in the plurality of wiring layers is narrower on the second surface side than on the first surface side. When being heated, a direction in which the wiring member tends to warp and a direction in which the carrier tends to warp are opposite. | 2019-12-12 |
20190378805 | FOIL COMPOSITE CARD - Composite cards formed include a security layer comprising a hologram or diffraction grating formed at, or in, the center, or core layer, of the card. The hologram may be formed by embossing a designated area of the core layer with a diffraction pattern and depositing a thin layer of metal on the embossed layer. Additional layers may be selectively and symmetrically attached to the top and bottom surfaces of the core layer. A laser may be used to remove selected portions of the metal formed on the embossed layer, at selected stages of forming the card, to impart a selected pattern or information to the holographic region. The cards may be ‘lasered’ when the cards being processed are attached to, and part of, a large sheet of material, whereby the “lasering” of all the cards on the sheet can be done at the same time and relatively inexpensively. | 2019-12-12 |
20190378806 | FILM SCHEME FOR BUMPING - A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad. | 2019-12-12 |