50th week of 2014 patent applcation highlights part 41 |
Patent application number | Title | Published |
20140363924 | STACKED MULTI-DIE PACKAGES WITH IMPEDANCE CONTROL - A microelectronic assembly may include microelectronic devices arranged in a stack and having device contacts exposed at respective front surfaces. Signal conductors having substantial portions extending above the front surface of the respective microelectronic devices connect the device contacts with signal contacts of an underlying interconnection element. A rear surface of a microelectronic device of the stack overlying an adjacent microelectronic device of the stack is spaced a predetermined distance above and extends at least generally parallel to the substantial portions of the signal conductors connected to the adjacent device, such that a desired impedance may be achieved for the signal conductors connected to the adjacent device. | 2014-12-11 |
20140363925 | Method for Producing a Semiconductor Module by Using an Adhesion Carrier - A method for producing a semiconductor module includes providing an adhesion carrier and a plurality of circuit carriers. The adhesion carrier has an adhesive upper side and a lower side opposite the adhesive upper side. Each of the circuit carriers includes a ceramic carrier and an upper conductor layer applied to the ceramic carrier, and a circuit carrier lower side. By placing the circuit carriers onto the adhesive upper side, the circuit carrier lower side of the circuit carriers contacts and adheres to the adhesive upper side, so that a quasi-panel is formed, in which the circuit carriers are processed while preserving the quasi-panel and can then be removed from the adhesive upper side. | 2014-12-11 |
20140363926 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package. | 2014-12-11 |
20140363927 | Novel Terminations and Couplings Between Chips and Substrates - A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder. | 2014-12-11 |
20140363928 | MICRO DEVICE STABILIZATION POST - A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. | 2014-12-11 |
20140363929 | BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION - The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer. | 2014-12-11 |
20140363930 | LATCH-UP FREE VERTICAL TVS DIODE ARRAY STRUCTURE USING TRENCH ISOLATION - A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types. | 2014-12-11 |
20140363931 | INSULATED GATE BIPOLAR TRANSISTORS INCLUDING CURRENT SUPPRESSING LAYERS - An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region. | 2014-12-11 |
20140363932 | ZINC TARGET INCLUDING FLUORINE, METHOD OF FABRICATING ZINC NITRIDE THIN FILM BY USING THE SAME, AND METHOD OF FABRICATING THIN FILM TRANSISTOR BY USING THE SAME - Provided are fluorine-containing zinc targets, methods of fabricating a zinc oxynitride thin film by using the zinc targets, and methods of fabricating a thin film transistor by using the zinc oxynitride thin film. The methods include mounting a fluorine-containing zinc target and a substrate in a sputtering chamber, supplying nitrogen gas and inert gas into the sputtering chamber, and forming a fluorine-containing zinc oxynitride thin film on the substrate. | 2014-12-11 |
20140363933 | COPPER-ALLOY BARRIER LAYERS FOR METALLIZATION IN THIN-FILM TRANSISTORS AND FLAT PANEL DISPLAYS - In various embodiments, electronic devices such as thin-film transistors incorporate electrodes featuring a conductor layer and, disposed below the conductor layer, a barrier layer comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni. | 2014-12-11 |
20140363934 | THIN FILM SEMICONDUCTORS MADE THROUGH LOW TEMPERATURE PROCESS - Embodiments disclosed herein relate to a TFT and methods for manufacture thereof. Specifically, the embodiments herein relate to methods for forming a semiconductor layer at a low temperature for use in a TFT. The semiconductor layer may be formed by depositing a nitride or oxynitride layer, such as zinc nitride or oxynitride, and then converting the nitride layer into an oxynitride layer with a different oxygen content. The oxynitride layer is formed by exposing the deposited nitride layer to a wet atmosphere at a temperature between about 85 degrees Celsius and about 150 degrees Celsius. The exposure temperature is lower than the typical deposition temperature used for forming the oxynitride layer directly or annealing, which may be performed at temperatures of about 400 degrees Celsius. | 2014-12-11 |
20140363935 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess. | 2014-12-11 |
20140363936 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor (TFT) and an organic light emitting diode (OLED) display device. The TFT and the OLED display device include a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate electrode insulated from the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer is formed from a polycrystalline silicon layer crystallized by a metal catalyst and the metal catalyst is removed by gettering using an etchant. In addition, the OLED display device includes an insulating layer disposed on the entire surface of the substrate, a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes, an organic layer, and a second electrode. | 2014-12-11 |
20140363937 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode. | 2014-12-11 |
20140363938 | ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers. | 2014-12-11 |
20140363939 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device includes an active region, a gate conductor and a source electrode. The active region includes a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region. The active region is formed of a silicon semiconductor layer. The gate conductor is embedded within a trench, which is formed from the source region to the drain region penetrating through the channel region. The source electrode is formed to come in contact with the source region and includes an adhesion layer. The source electrode is formed of a metal layer having a film thickness of 150 Å or smaller. The interface between the source electrode and the source region is silicidized. | 2014-12-11 |
20140363940 | Method of Manufacturing a Semiconductor Device - A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion. | 2014-12-11 |
20140363941 | REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER - A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. | 2014-12-11 |
20140363942 | Method for forming a low resistivity tungsten silicide layer for metal gate stack applications - Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer. The tungsten silicide layer can be annealed at or above a critical temperature to optimize the resistivity of the tungsten silicide layer. In some embodiments, the concentration of as-deposited tungsten silicide can be between 50 at % silicon to 80 at % silicon. The critical temperatures can be lower at higher silicon concentration, such as 700 C. at 63 at % silicon to 600 C. at 74 at % silicon. | 2014-12-11 |
20140363943 | Contact Structure of Semiconductor Device Priority Claim - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer. | 2014-12-11 |
20140363944 | Aqua Regia and Hydrogen Peroxide HCl Combination to Remove Ni and NiPt Residues - A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate. | 2014-12-11 |
20140363945 | METHODS FOR FABRICATING IMPROVED BIPOLAR TRANSISTORS - Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface. A multilevel collector structure of a second opposite conductivity type is formed in the base region. The multilevel collector includes a first collector part extending to a collector contact, a second collector part Ohmically coupled to the first collector part underlying the upper substrate surface by a first depth, a third collector part laterally spaced apart from the second collector part and underlying the upper substrate surface by a second depth and having a first vertical thickness, and a fourth collector part Ohmically coupling the second and third collector parts and having a second vertical thickness different than the first vertical thickness. | 2014-12-11 |
20140363946 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 2014-12-11 |
20140363947 | RESISTIVE MEMORY CELL FABRICATION METHODS AND DEVICES - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 2014-12-11 |
20140363948 | Method of forming anneal-resistant embedded resistor for non-volatile memory application - Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer. | 2014-12-11 |
20140363949 | Electrical Signal Isolation in Semiconductor Structures - Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer. | 2014-12-11 |
20140363950 | Materials and Methods of Forming Controlled Void - The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof. | 2014-12-11 |
20140363951 | METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE ON A SUBSTRATE - The invention relates to a method for manufacturing a multilayer structure on a first substrate made of a material having a first Young's modulus. The method includes: providing a second substrate covered with the multilayer structure, the multilayer structure having a planar surface opposite the second substrate, the second substrate being made of a material having a second Young's modulus; applying first deformations to said surface; molecularly boding the first substrate to said surface, the molecular bonding resulting in the appearance of second deformation in said surface in the absence of the first deformations, the first deformations being opposite the second deformations; and removing the second substrate, the resulting deformations in said surface being less than 5 ppm. | 2014-12-11 |
20140363952 | LASER, PLASMA ETCH, AND BACKSIDE GRIND PROCESS FOR WAFER DICING - Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs. | 2014-12-11 |
20140363953 | METHOD FOR FORMING COMPONENTS ON A SILICON-GERMANIUM LAYER - A method for manufacturing components on an SOI layer coated with a silicon-germanium layer formed by epitaxial deposition, wherein the heat balance of the anneals performed after the epitaxial deposition is such that the germanium concentration remains higher in the silicon-germanium layer than in the SOI layer. | 2014-12-11 |
20140363954 | Method for Etching a Group III Nitride Semiconductor, Method for Producing a Group III Nitride Semiconductor Crystal, and Method for Producing a GaN Substrate - A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions. | 2014-12-11 |
20140363955 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units derived from a phenolphthalein, Phenol Red, Cresolphthalein, Cresol Red, or Thymolphthalein is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 2014-12-11 |
20140363956 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units of hydroxycoumarin is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 2014-12-11 |
20140363957 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units of fluorescein is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 2014-12-11 |
20140363958 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units derived from a naphtholphthalein is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 2014-12-11 |
20140363959 | SILICON CARBIDE SCHOTTKY-BARRIER DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n− epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n− epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n− epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer. | 2014-12-11 |
20140363960 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate. | 2014-12-11 |
20140363961 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area. | 2014-12-11 |
20140363962 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of making a semiconductor device includes forming a high-k dielectric layer over a substrate; and forming a titanium nitride layer over the high-k dielectric layer. The method further includes performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer. The method further includes annealing the semiconductor device to form a TiSiON layer over a remaining portion of the titanium nitride layer. | 2014-12-11 |
20140363963 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method includes forming workpiece, first and second films on a substrate, processing the second films to form first and second core patterns, forming third and fourth sidewall patterns on side surfaces of the first and second core patterns via first and second sidewall patterns, and removing the first core patterns and first sidewall patterns so that the second core pattern and second to fourth sidewall patterns remain. The method includes processing the first films by transferring the second core pattern and second to fourth sidewall patterns to form third and fourth core patterns, forming fifth and sixth sidewall patterns on side surfaces of the third and fourth core patterns, removing the third core patterns so that the fourth core pattern and fifth and sixth sidewall patterns remain, and processing the workpiece film by transferring the fourth core pattern and fifth and sixth sidewall patterns. | 2014-12-11 |
20140363964 | GATE ELECTRODE WITH STABILIZED METAL SEMICONDUCTOR ALLOY-SEMICONDUCTOR STACK - A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer. | 2014-12-11 |
20140363965 | DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING - Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly. | 2014-12-11 |
20140363966 | Pillar Bumps and Process for Making Same - Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. | 2014-12-11 |
20140363967 | THROUGH SILICON VIAS FOR SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad. | 2014-12-11 |
20140363968 | METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE - A method of forming a semiconductor device package includes bonding a front surface of a first substrate to a second substrate, and thinning a back surface of the first substrate. The method includes depositing and patterning a dielectric layer on the thinned back surface of the first substrate, and etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable electrical connection with a first level metal of the first substrate. The method includes depositing an isolation layer to line the through silicon via is formed, and etching the isolation layer at the bottom of the through silicon via. The method includes depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched, and deposited a copper film over the conductive layer. | 2014-12-11 |
20140363969 | DOUBLE SELF ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 2014-12-11 |
20140363970 | METHOD OF MAKING A PILLAR STRUCTURE HAVING A NON-METAL SIDEWALL PROTECTION STRUCTURE - A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material. | 2014-12-11 |
20140363971 | MANGANESE OXIDE FILM FORMING METHOD - A manganese oxide film as a barrier film is formed on a structure in which a lower copper wiring layer is formed on a substrate, a silicon-containing oxide film as an interlayer film is formed on the lower copper wiring layer, and a recess is formed in the silicon-containing oxide film to reach the lower copper wiring layer. Further, this manganese oxide film is formed by an ALD process, and is controlled to have a thickness by adjusting the repetition number of times such that the manganese oxide film has a predetermined barrier property on the silicon-containing oxide film and copper buried in the recess has a preset resistance value on the exposed lower copper wiring layer. | 2014-12-11 |
20140363972 | METHODS OF FORMING METAL SILICIDE REGIONS ON SEMICONDUCTOR DEVICES USING MILLISECOND ANNEALING TECHNIQUES - In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure. | 2014-12-11 |
20140363973 | CMP POLISHING LIQUID AND POLISHING METHOD - The CMP polishing liquid containing a medium and silica particles as an abrasive grain dispersed into the medium. The silica particles have a silanol group density of 5.0/nm | 2014-12-11 |
20140363974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The device includes first and second line pattern units configured to extend substantially parallel to one another in a first direction and alternately disposed such that end portions of the first and second line pattern units are arranged in a diagonal direction, third and fourth pattern units configured to respectively extend from the end portions of the first and second line pattern units in a second direction crossing the first direction, first contact pad units respectively formed in the third line pattern units disposed a first distance from the end portions of the first line pattern units, and fourth contact pad units respectively formed in the fourth line pattern units disposed a second distance from the end portions of the second line pattern units. Here, the second distance is different from the first distance. | 2014-12-11 |
20140363975 | SUBSTRATE ETCHING METHOD AND SUBSTRATE PROCESSING DEVICE - A substrate etching method and a substrate processing device, the substrate etching method includes: S1: placing a substrate to be processed into a reaction chamber; S2: supplying etching gas into the reaction chamber; S3: turning on an excitation power supply to generate plasma in the reaction chamber; S4: turning on a bias power supply to apply bias power to the substrate; S5: turning off the bias power supply, and meanwhile, starting to supply deposition gas into the reaction chamber; S6: stopping supply of the deposition gas into the reaction chamber, and meanwhile, turning on the bias power supply; S7: repeating steps S5-S6, until the etching process is completed. In the whole etching process, the etching operation is always performed, and the deposition operation is performed sometimes. Therefore, during the deposition operation, the plasma in the reaction chamber can etch away at least a part of deposited polymers formed by the deposition operation on a sidewall of an etched section, so that the sidewall of the etched section of the substrate is smooth. | 2014-12-11 |
20140363976 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM - A substrate processing method is performed to improve surface roughness of a pattern mask formed on a substrate by being exposed and developed. The method includes supplying a first solvent in a gaseous state to a surface of the substrate to dissolve the pattern mask, and supplying a second solvent to the surface of the substrate, which is supplied with the first solvent, to dissolve the pattern mask, wherein a permeability of the second solvent is lower than a permeability of the first solvent. | 2014-12-11 |
20140363977 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - In a plasma processing apparatus including a first radio-frequency power supply which supplies first radio-frequency power for generating plasma in a vacuum chamber, a second radio-frequency power supply which supplies second radio-frequency power to a sample stage on which a sample is mounted, and a matching box for the second radio-frequency power supply, the matching box samples information for performing matching during a sampling effective period which is from a point of time after elapse of a prescribed time from a beginning of on-state of the time-modulated second radio-frequency power until an end of the on-state and maintains a matching state attained during the sampling effective period from after the end of the on-state until a next sampling effective period. | 2014-12-11 |
20140363978 | Electron Beam-Induced Etching - Beam-induced etching uses a work piece maintained at a temperature near the boiling point of a precursor material, but the temperature is sufficiently high to desorb reaction byproducts. In one embodiment, NF | 2014-12-11 |
20140363979 | DIRECTIONAL SIO2 ETCH USING LOW-TEMPERATURE ETCHANT DEPOSITION AND PLASMA POST-TREATMENT - Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH | 2014-12-11 |
20140363980 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method is provided that includes etching with a plasma a multilayer film including a first film and a second film with differing dielectric constants alternately stacked on a substrate using a photoresist layer arranged on the multilayer film as a mask, and forming the multilayer film into a stepped configuration. The semiconductor device manufacturing method includes repetitively performing a first step of etching the first film using the photoresist layer as the mask; a second step of adjusting a pressure within a processing chamber to 6-30 Torr, generating the plasma by applying a first high frequency power for biasing and a second high frequency power for plasma generation to the lower electrode, and etching the photoresist layer using the generated plasma; and a third step of etching the second film using the photoresist layer and the first film as the mask. | 2014-12-11 |
20140363981 | Selective Etching of Titanium Nitride - Provided are methods for processing semiconductor substrates having titanium nitride (TiN) structures as well as aluminum (Al) structures and, in some embodiments, other structures, such as silicon germanium (SiGe), tantalum nitride (TaN), hafnium oxide (HfOx), silicon nitride (SiN), and/or silicon oxide (SiO | 2014-12-11 |
20140363982 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ◯ atoms and hexa-coordinated Al atoms each surrounded by six ◯ atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms. | 2014-12-11 |
20140363983 | Method For Filling Recesses Using Pre-Treatment With Hydrocarbon-Containing Gas - A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule. | 2014-12-11 |
20140363984 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes forming a first resist film above a substrate, placing a first photomask, that includes a first mask pattern, in a first position above the first resist film, transferring the first mask pattern to the first resist film to form a first resist pattern above the substrate, forming a second resist film above the substrate after forming the first resist pattern, placing the first photomask in a second position above the second resist film, and transferring the first mask pattern to the second resist film to form a second resist pattern above the substrate. | 2014-12-11 |
20140363985 | Novel Amino-Silyl Amine Compound, Method for Preparing the Same and Silicon-Containing Thin-Film Using the Same - Provided are a novel amino-silyl amine compound, a method for preparing the same, and a silicon-containing thin-film using the same, wherein the amino-silyl amine compound has thermal stability and high volatility and is maintained in a liquid state at room temperature and under a pressure where handling is easy to thereby form a silicon-containing thin-film having high purity and excellent physical and electrical properties by various deposition methods. | 2014-12-11 |
20140363986 | LASER SCANNING FOR THERMAL PROCESSING - A system is provided for thermal processing of a semiconductor substrate including a laser configured for emitting a laser beam towards the semiconductor substrate and a scanning means configured for scanning the laser beam along a first plurality of paths on the semiconductor substrate such that the paths are spaced apart from each other by predetermined distances. Further, a method for thermal processing of a semiconductor substrate is provided including scanning a laser beam along a first plurality of paths on the semiconductor substrate such that the paths are spaced apart from each other by predetermined distances. | 2014-12-11 |
20140363987 | POWER CONNECTOR - A connector system includes a first connector with a housing. The housing supports a terminal with an aperture that is positioned adjacent a pocket. A ball is positioned in the pocket and is restrained by the terminal but is configured to partially extend through the aperture. A second connector includes a contact and a magnet attraction member. In operation, when the first and second connector are in a mated position, the ball is urged toward the magnetic attraction member due to a magnetic force and partially extends through the aperture so as to engage the contact, electrically connecting the terminal and the contact. | 2014-12-11 |
20140363988 | TABLET PC HAVING NON-INSERTION TYPE PORT AND CRADLE CONNECTED TO SAME - Provided is a tablet personal computer (PC) having a non-insertion type port, the tablet PC including a non-insertion type port to which a non-insertion type connector of a cradle is connected using magnetism and which supplies input signals of a peripheral device connected to a non-insertion type port of the cradle using magnetism to a control unit or which supplies output signals of the control unit to the peripheral device, wherein the non-insertion type port includes: a magnetic coupling member that is formed on a contact surface of a body and comes into surface contact with a magnetic coupling member formed on a contact surface of the non-insertion type connector using magnetism; and a contact terminal that is formed on the contact surface of the body and causes a contact terminal of the non-insertion type connector to come into non-insertion contact with the contact terminal when the magnetic coupling members are coupled to each other using magnetism, thereby enabling reciprocal power supply and data transmission. | 2014-12-11 |
20140363989 | CONNECTOR ASSEMBLY - A connector assembly includes a circuit board, a socket attached to the circuit board, and a mounting tray. The mounting tray includes a clipping portion and a clamping arm. The clipping portion is clipped to the circuit board and the socket, to secure the mounting tray to the circuit board and the socket. The clamping arm is deformable to clamp a plug in the socket. | 2014-12-11 |
20140363990 | MOUNTING STRUCTURE AND METHOD OF CONNECTOR FOR FLEXIBLE CABLE - The flexible cable mounting structure of the Present Disclosure is a flexible cable connector comprising a housing, whereon a contact terminal is mounted that enables insertion and withdrawal of the flexible cable and contact with the flexible cable. An actuator that opens/closes is installed in such a way as to enable rotation on the housing. A fitting nail is furnished on the housing and fixes the housing to the PCB. The fully-assembled flexible cable connector, wherein the contact terminal, actuator, and fitting nail have each been mounted to the housing, passes through from the bottom to the top of the PCB, and the bottom of the contact terminal and bottom of the fitting nail are soldered to the lower surface of the PCB. | 2014-12-11 |
20140363991 | ULTRA LOW-PROFILE CONNECTORS - A connector system includes a first connector including first contacts arranged around a pass-through hole or a recess, the first connector being configured to be located in a cut-out of a first substrate such that the first contacts are connected to the first substrate, and a second connector including second contacts arranged around a beam, the second connector configured to be connected to a second substrate such that the second contacts are connected to the second substrate. The pass-through hole or the recess extends in a mating direction of the first connector and the second connector, and the beam of the second connector is configured to extend into the pass-through hole or the recess of the first connector when the first connector and the second connector are mated such that the first contacts engage with respective ones of the second contacts. | 2014-12-11 |
20140363992 | Physical Infrastructure Management System Having an Integrated Cabinet - A data center physical infrastructure management system has a cabinet having rack spaces and a sensor. A data communication system transmits signals to a management database. Personal or automated intervention is determined algorithmically by a data processor. A human interface for the data center management system is provided. Removable electronic assets contained in the rack spaces each have an identifier tag. An identifier tag reader is installed on the cabinet body. A door sensor provides a signal responsive to whether a cabinet door is closed, open, locked, or unlocked. Also, a secure contact arrangement has a base terminal formed of electrically conductive material, and first and second electrically conductive elements. A resilient non-conductive element is interposed between the first and second electrically conductive elements, and a compression element compresses the resilient non-conductive element to cause the first and second electrically conductive elements to communicate with one another. | 2014-12-11 |
20140363993 | CONNECTION STRUCTURE OF ELECTRONIC COMPONENTS - Bus bars each having a terminal portion formed on one end thereof is spaced from each other and arranged in parallel within a housing. Each terminal portion is formed with a pair of first right and left contact spring pieces each having a bulge protruded horizontally outward at a side of leading portions abutted against each other. The bulges of the two adjacent inside pieces among the first right and left contact spring pieces elastically contact with a pair of light emitting element contact portions disposed on both lateral surfaces of a semiconductor light emitting element arranged between the pair of bus bars and the respective bulges of the two outside pieces among the first right and left contact spring pieces elastically contact with inner walls of the housing. | 2014-12-11 |
20140363994 | CARD EDGE CONNECTOR WITH MOVABLE EJECTOR - A card edge connector includes a longitudinal insulative housing ( | 2014-12-11 |
20140363995 | CONNECTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THEREOF - A connector device comprises a tray, a connector body, a lock member and a pressing member. The lock member is unmovable beyond a second position along an ejection direction. The pressing member applies a force toward the second position directly or indirectly to the lock member. The tray is formed with a locked portion. The lock member is provided with a lock portion and a pressed portion. The lock portion locks the locked portion to prevent the tray from moving beyond a lock position along the ejection direction when the tray is accommodated in the connector body. The pressing member presses the pressed portion against the case when the connector device is attached in the case. The tray located at the locked position is positioned relatively to the case by this pressing. | 2014-12-11 |
20140363996 | ANTI-ROTATION DEVICE FOR ELECTRICAL CONNECTORS - In one embodiment, an anti-rotation device is designed to prevent de-coupling of an electrical connector pair. The connector pair includes (i) a first electrical connector having a barrel with male threads formed thereon and (ii) a second electrical connector having a nut with female threads formed therein that mate with the male threads of the first connector. The anti-rotation device includes a barrel-locking portion connected by an interconnecting portion to a nut-locking portion. The barrel-locking portion engages the barrel of the first electrical connector to prevent rotation of the anti-rotation device circumferentially around the barrel. The nut-locking portion engages the nut of the second electrical connector to prevent the nut from rotating and backing out. The anti-rotation device inhibits rotation of the nut relative to the barrel, thereby preventing de-coupling of the second electrical connector from the first electrical connector. | 2014-12-11 |
20140363997 | CONNECTOR WITH RESILIENT LATCHES TO ACCOMMODATE MOUNTING TO CURVED OR ARCUATE SURFACES - An electrical connector and method for mounting to mating member with an arcuate cylindrical member. The electrical connector includes a housing and a mounting member extending from the housing. The mounting member has latching members and a mating member receiving section. The mating member receiving section has an arcuate configuration which cooperates with the arcuate cylindrical member to maintain the electrical connector on the arcuate cylindrical member. The latching members have latching arms, with each latching arm having an arcuate configuration which cooperates with the a surface of the mating member to prevent unwanted rotation of the electrical connector relative to the mating member. | 2014-12-11 |
20140363998 | MOUNTING ASSEMBLY FOR CONNECTOR - A mounting assembly is configured for plugging a plug connector into a socket connector of a circuit board. The mounting assembly comprises a mounting seat and an operating member. The mounting seat is configured for mounting the circuit board and includes a sliding slot and a gap located at an end of the sliding slot. The operating member includes a pair of clamping arms for clamping the plug connector. Each clamping arm includes a sliding tab capable of sliding along the sliding slot. When the sliding tab is slid towards the gap along a first direction, the plug connector is capable of being plugged into the socket connector. In addition, the sliding tab is capable of moving away from the gap along a second direction that is substantially perpendicular to the first direction for detaching the operating member from the mounting seat and the plug connector. | 2014-12-11 |
20140363999 | PERIPHERAL COMPONENT INTERCONNECT (PCI) CARD FIXING SYSTEM - A fixing system for fixing a PCI card includes: a module having a substrate including carrier portion, a pivot portion and a securing portion; and a press rod having a pivot section connected pivotally to the pivot portion of the substrate, an extension section and a securing section; wherein, the press rod is pivotable relative to the module between a locked position, in which the securing section of the press rod engages the securing portion of the substrate such that the extension section thereof compresses so as to fix the PCI card on the carrier portion of the substrate and an open position, in which the press rod is rotatable about a common axis defined by the pivot section and the pivot portion, thereby permitting the press rod to rotate away from the substrate. | 2014-12-11 |
20140364000 | CARD EDGE CONNECTOR WITH A LOCK MECHANISM - A card edge connector assembly includes a connector with a central slot and a daughter card having an inserted end for being inserted into the central slot. The connector includes an elongated housing, a plurality of terminals retained in the elongated housing, and at least one lock mechanism for locking the daughter card. The lock mechanism has a locking portion for locking the daughter card and an elastic projection projects from the locking portion for downwardly pressing the daughter card. It can prevent the daughter card from shaking shake. | 2014-12-11 |
20140364001 | PLUG FOR A DATA CABLE - A plug for a data cable, has a conventional front plug element with a latching tongue, a plug element with a front sub-body which is attached to the plug element at the front end of the data cable in a tension-resistant manner to provide a high tensile strength, a rear sub-body, a forward-facing latching tongue protection element and a flexible kink protection element. An angularly curved actuating lever pushes onto the latching tongue and is guided at the other end inside an actuating lever guide, wherein, the plug is connected, an actuation side of the actuating lever lies on a front area of the latching tongue protection element, and wherein, pulling out at an area of the rear sub-body, the actuating lever is actuated, creating pressure on the latching tongue and releasing the lock connection, so that the data cable plug can be pulled out in an unlocked state. | 2014-12-11 |
20140364002 | ELECTRICAL CONNECTOR HAVING ALIGNMENT KEY ASSEMBLED THEREON - An electrical connector includes an insulating housing, a plurality of contacts retained in the insulating housing and an alignment key assembled the insulating housing. The insulating housing includes an accommodating portion defining a plurality of through holes. The alignment key is assembled on the accommodating portion. The alignment key includes a post and an extending portion extending downwardly from the post. The extending portion extends into the through holes optionally | 2014-12-11 |
20140364003 | ELECTRICAL CONNECTOR - An electrical connector is to be connected to a mating connector. The electrical connector includes a plurality of terminals; a housing for holing the terminals in a terminal arrangement direction; and a guide member for guiding the mating connector. The housing includes a sidewall portion and an edge wall portion connected to the sidewall portion. The guide member includes a first attaching portion, a second attaching portion, and a connecting portion connecting the first attaching portion and the second attaching portion. The first attaching portion is attached to the sidewall portion. The second attaching portion is attached to the edge wall portion. | 2014-12-11 |
20140364004 | TRANSMISSION MODULE, SHIELDING METHOD, TRANSMISSION CABLE, AND CONNECTOR - A transmission module includes a connector component including a connector side substrate having a terminal component including a ground terminal and a data terminal, and a signal processing component mounted on the connector side substrate for processing a high frequency signal having a frequency higher than that of a data signal inputted or outputted via the data terminal; and a transmission cable component for transmitting the high frequency signal including a cable side substrate having a flexibility on which a cable side ground layer electrically connected to the ground terminal and a signal line to which the high frequency signal is transmitted are formed, the cable side ground layer being disposed at least at lower and upper sides of the signal line as a part including the cable side ground layer of the cable side substrate is folded. | 2014-12-11 |
20140364005 | CONNECTOR HOUSING - A housing used for an electric connector, includes a terminal space into which an electric terminal is to be inserted, and a lance for preventing the electric terminal from being slipped out of the terminal space, the lance including a flexible portion, and a protrusion extending from the flexible portion and engaging with the electric terminal, the lance defining an escape space in which the flexible portion can be bent in a direction in which the protrusion and the electric terminal are disengaged with each other, the flexible portion having a passage along which a jig can move and which extends in a direction in which the jig is inserted into the lance, the jig being used for disengaging the protrusion and the electric terminal from each other. | 2014-12-11 |
20140364006 | ELECTRICAL CONNECTOR - An electrical connector includes a body, two rows of terminals, and a grounding sheet. The body has a base and a tongue extending forwards from the base. The two rows of terminals are disposed in the tongue. At least one row of terminals includes a differential signal terminal pair and a grounding terminal that are disposed neighboring to each other. The grounding sheet is disposed in the tongue and located between the two rows of terminals. The grounding sheet has an open slot located between the differential signal terminal pair and the grounding terminal that are in the same row. | 2014-12-11 |
20140364007 | ELECTRICAL CONNECTOR WITH METAL PLATE - An electrical connector comprises an insulative housing having a base portion with a rear room depressed thereof, a top and a lower tongue portions extending forwardly, a plurality of contacts retained to the insulative housing, a spacer received in the rear room, and a metal shell having two side walls covering two sides of the insulative housing. The spacer has a base, a front portion and a rear portion extending upwardly from the base, and a groove depressed between the front and the rear portion. A metal plate received in the groove. The metal plate has a pair of cantilever arms extending downwardly from two side edges of the main portion. The pair cantilever arms are mirror and coplanar to each other, each of the cantilever arm having a protruding portion protruding beyond a side of the insulative housing to abut against the side wall of the metal shell. | 2014-12-11 |
20140364008 | SELF-REGISTERED CONNECTORS FOR DEVICES HAVING A CURVED SURFACE - Connector receptacles may be provided, where a multiple of such connector receptacles may be readily aligned to openings in a device enclosure, particularly where the openings are located on a curved or otherwise non-planar surface of the device enclosure. One example may provide a connector assembly that includes a plurality of connector receptacles. The connector receptacles in a connector assembly may be accurately aligned or registered to each other, and the connector assembly may be accurately aligned to a device enclosure. In this way, several connector receptacles may be accurately aligned to openings in the device enclosure. In another example, two or more connector receptacles may have faces that are at an oblique angle relative to each other. | 2014-12-11 |
20140364009 | CONNECTOR WITH ELECTRONIC COMPONENT - A connector includes a holder ( | 2014-12-11 |
20140364010 | CONNECTOR DEVICE - A connector device comprises a first connector, a first detection connector, a second connector and an operation member. The first connector includes a first housing holding a first power terminal. The first detection connector includes a first detection-terminal. The first detection connector is held by the first housing and is movable between a first position and a second position along a first direction. The second connector includes a second housing holding a second power terminal and a second detection-terminal. The operation member is attached to the first housing. When the operation member is turned, the first connector is moved along the first direction, and the first power terminal is connected to the second power terminal. Subsequently, when the operation member is moved along a second direction, the first detection connector is moved from the first position to the second position, and the first detection-terminal is connected to the second detection-terminal. | 2014-12-11 |
20140364011 | Connector - Provided is a connector capable of holding a plurality of contacts in alignment. The connector includes a main body, a plurality of contacts to be electrically connected to a connection object and a contact holder holding the plurality of contacts in juxtaposition. The main body includes a fixing portion for fixing the contact holder. The plurality of contacts are fixedly held to the contact holder through integral molding therewith. | 2014-12-11 |
20140364012 | Method for Producing a Control Unit Housing and Control Unit Housing Produced According to Said Method - A control unit housing has connector pins arranged therein. Each pin has a first contact end directed to the housing interior for a press-fit connection to a circuit board insertable therein, and a second contact end directed out of the housing for connecting an electrical plug connector or the like. The housing is designed as a header that is open on one side and has an access opening for inserting the circuit board. The access opening can be closed by a cover after mounting the circuit board. The connector pins are substantially right-angled pins arranged in the region of a side wall of the housing. The pins are anchored in the housing by the second contact ends running approximately at right angles to the first contact ends, such that the mounting forces acting on the first contact ends during press-fit connecting are received by the housing. | 2014-12-11 |
20140364013 | ELECTRICAL CONNECTOR ASSEMBLY - A receptacle connector adapted for mating with a plug connector, includes a receptacle housing defining a receiving space, a number of receptacle contacts received in the receptacle housing and partially exposed into the receiving space, and a receptacle shell including a top wall, a bottom wall and a pair of sidewalls connecting with the top wall and the bottom wall. Each sidewall defines an opening and forms a trapezoidal-shape elastic arm extending rearward from one edge of the opening and curved toward the receiving space. The bottom wall forms at least one protruding rib protruding toward the top wall and extending along a mating direction between the plug connector and the receptacle connector for assuring the contact journal between the plug connector and the receptacle connector. | 2014-12-11 |
20140364014 | POWER PLUG - A plug includes male contacts, a core and an envelope. Each of the male contacts includes a stopper. The core includes a first member and a second member. The stoppers are in contact with the first member and the male contacts are in contact with the second member, so that the male contacts are prohibited from being displaced with respect to the core in a first direction along which the male contacts protrude from an end face of the core. | 2014-12-11 |
20140364015 | BATCH FABRICATED MICROCONNECTORS - Connectors and interconnects for high power connectors which may operate at frequencies up to approximately 110 GHz and fabrication methods thereof are provided. | 2014-12-11 |
20140364016 | CONNECTION UNIT - The present invention provides a connection unit capable of accommodating nuts and showing sealing ability in a state installed on a housing. | 2014-12-11 |
20140364017 | CONNECTOR - A connector which dispenses with an actuator and lowers profile while prevent damage to conducive path portions. A metal plate of the connector includes a first supporting portion mounted on a printed wiring board, and a second supporting portion connected to the first supporting portion via a linking portion in a manner movable in an FPC sandwiching direction. The second supporting portion includes a spring portion for urging a movable portion against FPC, a pair of locking pieces for increasing distance between contact point portions of the supporting portions by moving the movable portion away from the first supporting portion using an FPC inserting force, and suppressing removal of completely inserted FPC. Connection portions of conductive path portions are arranged on first and second protuberance portions at opposite ends of the first supporting portion in a connector left-right direction, along the connector front-back direction. | 2014-12-11 |
20140364018 | Ship Steering Device And Ship Steering Method - A ship steering device capable of steering a hull in an intended direction by correcting an unintended rotation that occurs during an oblique sailing operation regardless of the type and size of the hull. A ship steering device is provided with an elevation angle sensor for detecting the elevation angle α of a hull, a hull speed sensor for detecting the speed V of the hull, a storage means storing the relation among the elevation angle α of the hull, the speed V of the hull, and a correction value K, and a calculation means serving as a correction value determination means, and an operation amount by which a joystick is operated such that the hull does not turn in the state in which the hull is obliquely sailed is determined by the calculation means and used as the correction value K. | 2014-12-11 |
20140364019 | OUTBOARD MOTOR CONTROL SYSTEM - An outboard motor control system includes a plurality of outboard motors, a vibration detecting section, and a control section. The outboard motors are mounted on a stern of a watercraft. Each of the outboard motors includes a propeller. The outboard motors are configured to be steered independently of one another. The vibration detecting section is configured to detect a vibration of the outboard motors. The control section is configured and programmed to execute a vibration suppression control when the vibration detecting section detects a vibration of the outboard motors. With the vibration suppression control, the control section is configured and programmed to change a propeller rotational axis direction and/or a propeller position of at least one of the outboard motors. | 2014-12-11 |
20140364020 | KAYAK MOTOR ATTACHMENT DEVICE - A kayak motor attachment device for fastening a motor to a kayak comprising an elongated frame, where the elongated frame includes a pair of slots; a pair of fishing pole supports inserted into a pair of receiving holes positioned at a back of the kayak, where the pair of fishing pole supports attach to the elongated frame with a plurality of bolts through the pair of slots; an attachment housing secured to an end of the elongated frame; a support shaft attached to the attachment housing, where the support shaft rotates within the attachment housing to guide a propeller at a bottom end of the support shaft; and a motor attached atop the support shaft to power the propeller. | 2014-12-11 |
20140364021 | MOORING RETRIEVAL DEVICE - A mooring retrieval device for retrieving a mooring rope in water, the device comprising a buoyant member adapted to be tethered to the end of the mooring rope. An elongate retrieval member having an end adapted to engage with the buoyant member whereby, in use, the end of a mooring rope tethered to the buoyant member can be more easily retrieved. Advantageously the end of the retrieval member engages with the buoyant member by magnetic attraction. | 2014-12-11 |
20140364022 | STIFFENER FOR INFLATABLE DROP-STITCH STAND-UP PADDLE BOARD AND METHOD OF MANUFACTURING SAME - An inflatable board, which can be used for floating or paddling on water, with a thin layer of inelastic material, such as acrylic, bonded between the layers of material forming the top or bottom surfaces of an inflatable board. The thin layer of inelastic material is bonded between the inner material and the outer material. The thin layer of inelastic material is bendable, so that the un-inflated board may be rolled-up for storage or transportation. When inflated, the thin layer of inelastic material bonded between the layers of the top or bottom surfaces of the board increases the rigidity of the board and the board's ability to resist flexing and bending. | 2014-12-11 |
20140364023 | BOARD - A surfboard core and a stringer array embedded in the core to modify handling characteristics of the board. | 2014-12-11 |