50th week of 2008 patent applcation highlights part 38 |
Patent application number | Title | Published |
20080305549 | LIPOPROTEIN ANALYSIS BY DIFFERENTIAL CHARGED-PARTICLE MOBILITY - The invention provides methods of preparation of lipoproteins from a biological sample, including HDL, LDL, Lp(a), IDL, and VLDL, for diagnostic purposes utilizing differential charged particle mobility analysis methods. Further provided are methods for analyzing the size distribution of lipoproteins by differential charged particle mobility, which lipoproteins are prepared by methods of the invention. Further provided are methods for assessing lipid-related health risk, cardiovascular condition, risk of cardiovascular disease, and responsiveness to a therapeutic intervention, which methods utilize lipoprotein size distributions determined by methods of the invention. | 2008-12-11 |
20080305550 | Targets for Detection of Ischemia - The subject application comprises methods for determining the occurrence of an ischemic event in a subject by determining an ischemia score based on the amount of at least two ischemia modified albumin markers. The ischemia modified albumin markers include complexes of fatty acids bound to albumin, albumin molecules with open Cys34 sites, albumin molecules that are products of oxidation at Cys34, albumin molecules with altered conformation or altered divalent metal binding due to the conformational change or oxidation at Cys34, and albumin molecules that have been oxidized at the N-terminus. Also included in the invention are ligands to each of the foregoing ischemia modified albumin markers. Further included are methods of determining the occurrence of an ischemic event by determining the amount of fatty acid that is complexed to albumin in a patient sample. In another embodiment, an ischemic event is determined by quantitating the relative amounts of reduced and oxidized forms of albumin Cys34. In an additional embodiment, an ischemic event is determined by observing whether a shift in albumin conformation has occurred which would reflect oxidized Cys34. Further, the invention comprises a method of determining an ischemic event by determining the amount of metal ion bound to the albumin metal ion binding sites. | 2008-12-11 |
20080305551 | Method for Diagnosing a Pervasive Developmental Disorder - A method for diagnosing a pervasive developmental disorder, such as autism, comprising obtaining a sample of cerebrospinal fluid from a subject; obtaining a sample of serum from a subject; testing the cerebrospinal fluid of the subject for a concentration of TNF-α; testing the serum of the subject for a concentration of TNF-α; and positively diagnosing a pervasive developmental disorder when the concentration ratio of TNF-α in the cerebrospinal fluid of the subject to TNF-α in the serum of the subject exceeds approximately 2:1 over normal control concentrations. | 2008-12-11 |
20080305552 | ASSAYS FOR PREIMPLANTATION FACTOR AND PREIMPLANTATION FACTOR PEPTIDES - The present invention relates to assay methods used for detecting the presence of PIF, and to PIF peptides identified using this assay. In particular, the present invention relates to flow cytometry assays for detecting PIF. It is based, at least in part, on the observation that flow cytometry using fluorescently labeled anti-lymphocyte and anti-platelet antibodies demonstrated an increase in rosette formation in the presence of PIF. It is further based on the observation that flow cytometry demonstrated that monoclonal antibody binding to CD2 decreased in the presence of PIF. The present invention further relates to PIF peptides which, when added to Jurkat cell cultures, have been observed to either (i) decrease binding of anti-CD2 antibody to Jurkat cells; (ii) increase expression of CD2 in Jurkat cells; or (iii) decrease Jurkat cell viability. In additional embodiments, the present invention provides for ELISA assays which detect PIF by determining the effect of a test sample on the binding of anti-CD2 antibody to a CD2 substrate. | 2008-12-11 |
20080305553 | Kinetic determination of peracid and/or peroxide concentrations - A use composition monitor determines the concentration of peracid and/or peroxide in a use composition using a kinetic assay procedure. A sample mixture containing a sample of the use composition, a diluent and at least one reagent is prepared and analyzed using, for example, an optical detector. Response data obtained by the detector is indicative of the optical absorbance of the sample mixture as a function of time. A processor analyzes the response data to determine a corresponding best fit linear relationship. The initial absorbance of the sample mixture is indicative of the concentration of peracid in the use composition, while the slope of the best fit equation is indicative of the concentration of peroxide in the use composition. | 2008-12-11 |
20080305554 | Automated yield monitoring and control - A system is adapted to automatically maintain a desired yield level for a slurry flow. Measurements of the electrical conductivity of a slurry are taken and corrected for the effects of temperature and pressure. The corrected conductivity measurements are used to arrive at a value for system yield. The system automatically determines if the yield is too high or too low relative to a desired level, and controls the rate at which accelerator is added to the slurry in order to increase or decrease yield. | 2008-12-11 |
20080305555 | Methods, Compositions and Devices For Performing Ionization Desorption on Silicon Derivatives - A device for the presentation of samples for MALDI or DIOS ion source, comprising a semiconductor wafer body having at least one first surface and at least one second surface, the first surface being chemically modified to repel said aqueous sample toward said second surface. | 2008-12-11 |
20080305556 | CHEMICAL REACTION CARTRIDGE AND METHOD OF USING THE SAME - The invention provides a chemical reaction cartridge which can be treated with safety upon introduction of a sample into the cartridge and a method of using the same. An opening section of the chemical reaction cartridge is openable and closable by a rail fastener provided inside an elastic body. When the rail fastener is released, the elastic body can be opened across the entire width. The opening section provides the cartridge with an opening having a large sectional area, which is larger than a flow path and a chamber inside the cartridge, owing to elasticity of the elastic body. | 2008-12-11 |
20080305557 | Novel Applications of Acridinium Compounds and Derivatives in Homogeneous Assays - Chemiluminescent acridinium compounds are used in homogeneous assays to determine the concentration of an analyte in a sample without strong acid or strong base treatment. The chemiluminescent acridinium compounds include acridinium esters with electron donating functional groups at the C2 and/or C7 position on the acridinium nucleus to inhibit pseudo-base formation, or acridinium sulfonamides with or without electron donating functional groups at the C2 and/or C7 position on the acridinium nucleus. | 2008-12-11 |
20080305558 | Cancer Screening Test - The invention provides a cancer screening test, to identify patients having an increased likelihood of cancer, comprising the step of determining the presence or absence of members of a test group of tumour associated antigens in the blood of a patient. The test group comprises a plurality of tumour-associated antigens. Antigens of particular interest include Vascular Endothelial Growth Factor-A (VEGF A); CEA 125 (Carcinoembryonic antigen 125); Prostate Specific Antigen (PSA); CA15-3 (Cancer antigen 15-3); CA125 (Cancer Antigen 125); CYFRA21-1 (Cytokeratin-19 fragments); Soluble ectodomain of c-erbB2; CA27.29 (Cancer Antigen 27.29); IGF-I (Insulin-like growth factor-1); IGF-2 (Insulin-like growth factor-2); and IGFBP-3 (Insulin-like growth factor binding protein 3). The invention also provides an antibody-based test kit to implement the screening method. | 2008-12-11 |
20080305559 | Non-Competitive Immunoassays to Detect Small Molecules - The present invention provides noncompetitive immunoassays to detect small molecules. | 2008-12-11 |
20080305560 | Method for eliminating defects from semiconductor materials - Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature. A typical temper hold segment is around 3 hours and depends upon the material, thickness, and diameter size of the substrate wafer. | 2008-12-11 |
20080305561 | Methods of controlling film deposition using atomic layer deposition - Methods of manufacturing semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a method of forming a material layer. The method includes providing a semiconductor wafer, forming a first portion of a material layer over the semiconductor wafer at a first pressure, and forming a second portion of the material layer over the first portion of the material layer at a second pressure, the second pressure being less than the first pressure. | 2008-12-11 |
20080305562 | Passive alignment of photodiode active area in three axes using microscopic focus - A fixturing system and microscope/video camera setup enables an operator to manipulate a photodiode into position optically using known good targets for the X and Y location and using microscope focus/defocus/refocus for locating the active area of the avalanche photodiode exactly at the focal point of the lens. | 2008-12-11 |
20080305563 | Method and system for controlling copper chemical mechanical polish uniformity - A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of metrological data for at least one layer of the semiconductor substrate may be estimated, and an optimum CMP process recipe may be selected based on the set of metrological data. The optimum CMP process recipe may be implemented on the semiconductor substrate. | 2008-12-11 |
20080305564 | MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solation, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated. | 2008-12-11 |
20080305565 | Fabrication method for semiconductor device - A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product. | 2008-12-11 |
20080305566 | Silicon Nanocrystal Embedded Silicon Oxide Electroluminescence Device with a Mid-Bandgap Transition Layer - A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced. | 2008-12-11 |
20080305567 | NITRIDE-BASED LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device according to an exemplary embodiment of the present invention includes: an n-type cladding layer; a p-type cladding layer; an active layer interposed between the n-type cladding layer and the p-type cladding layer; and an ohmic contact layer contacting the p-type cladding layer or the n-type cladding layer and comprising a first film that comprises a transparent conductive zinc oxide having a one-dimensional nano structure, wherein the one-dimensional nano structure is at least one selected from a nano-column, a nano rod, and a nano wire. | 2008-12-11 |
20080305568 | Method for promoting light emission efficiency of LED using nanorods structure - Method for the light emitting diode (LED) having the nanorods-like structure is provided. The LED employs the nanorods are subsequently formed in a longitudinal direction by the etching method and the PEC method. In addition, the plurality of the nanorods is arranged in an array so that provide the LED having much greater brightness and higher light emission efficiency than the conventional LED. | 2008-12-11 |
20080305569 | Semiconductor Device and a Method of Manufacturing the Same - A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained. | 2008-12-11 |
20080305570 | LED CHIP PRODUCTION METHOD - An LED chip production method in which the sapphire substrate used in the process for formation of a nitride semiconductor can be easily and efficiently removed. The LED chip production method is a method for LED chips that has at least one nitride semiconductor layer. An LED chip structure assembly with a construction in which a nitride buffer layer is formed on the sapphire substrate and the at least one nitride semiconductor layer is formed on the nitride buffer layer which is then subjected to a chemical etching process to remove the nitride buffer layer, thereby facilitating removal of the sapphire substrate. | 2008-12-11 |
20080305571 | METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE SUBSTRATE - A method of fabricating a substrate for semiconductor light emitting devices is provided. The method includes forming a nanocrystal structure on a surface of the substrate which is a single crystal material, wherein the nanocrystal structure has an etched region and an unetched region. Next, a nitride semiconductor material is grown on the surface of the single crystal material with an epitaxial process, so as to form a substrate. Due to the periodicity of the nanocrystal structure, the semiconductor material grown on the substrate has fewer defects, and the material stress is reduced. Besides, the nanocrystal structure is capable of diffracting an electromagnetic wave, such that a higher light emitting efficiency and a higher output power may be obtained accordingly. | 2008-12-11 |
20080305572 | METHOD OF FABRICATING IMAGE DEVICE HAVING CAPACITOR AND IMAGE DEVICE FABRICATED THEREBY - There are provided a method of fabricating an image device having a capacitor and an image device fabricated thereby. The method comprises preparing a substrate having a pixel region and a peripheral circuit region. A lower electrode containing silicon is formed on the substrate of the peripheral circuit region. A capacitor dielectric layer is formed by sequentially stacking a first dielectric layer and a second dielectric layer on the lower electrode, and the first dielectric layer and the second dielectric layer have a different dielectric constant from each other. In this case, one of the first and second dielectric layers is a dielectric layer grown from a material layer formed thereunder and has a lower dielectric constant than that of the other. An upper electrode is formed on the capacitor dielectric layer. | 2008-12-11 |
20080305573 | Photovoltaically Active Semiconductor Material and Photovoltaic Cell - The invention relates to a photovoltaically active semiconductor material and a photovoltaic cell comprising a photovoltaically active semiconductor material, wherein the photovoltaically active semiconductor material contains a crystal lattice composed of zinc telluride and, in the zinc telluride crystal lattice, ZnTe is substituted by—0.01 to 10 mol % CoTe, —0 to 10 mol % Cu | 2008-12-11 |
20080305574 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE USING CONDUCTIVE ORGANIC POLYMER HAVING NANOCRYSTALS EMBEDDED THEREIN - The method of manufacturing a nonvolatile memory device includes forming a lower conductive layer on a substrate; forming a first conductive organic layer on the substrate using spin coating; forming a metal layer for forming nanocrystals on the first conductive organic layer, the metal layer partially overlapping the first conductive organic layer; forming a second conductive organic layer on the first conductive organic layer using spin coating; transforming the metal layer into nanocrystals by curing; and forming an upper conductive layer on the second conductive organic layer, the upper conductive layer partially overlapping the nanocrystals. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS). | 2008-12-11 |
20080305575 | THIN FILM TRANSISTOR HAVING OXIDE SEMICONDUCTOR LAYER AND MANUFACTURING METHOD THEREOF - A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film. | 2008-12-11 |
20080305576 | METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL - A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process. | 2008-12-11 |
20080305577 | METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL - A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages. | 2008-12-11 |
20080305578 | METHOD OF MACHINING WAFER - A method of machining a wafer, wherein a wafer provided with devices each having a low dielectric constant insulating film (low-k film) stacked on the face side thereof is divided into the individual devices, the devices thus divided are mounted on a wiring board, and then a grindstone is brought into contact with each of the mounted devices from the side of a side surface of the devices, to grind the back side of the device by a desired amount. Since no vertical load is exerted on the low-k film, the low-k film can be prevented from being broken, and device quality is not lowered. | 2008-12-11 |
20080305579 | Method for fabricating semiconductor device installed with passive components - A method for fabricating a semiconductor device installed with passive components is provided. The method includes: having at least a passive component make a bridge connection between a ground circuit and a power circuit of each of a plurality of substrate units; electrically connecting a conductive circuit on a cutting path between substrate units to the ground circuit and the power circuit, and forming a short circuit loop; or electrically connecting the conductive circuit on the cutting path between the substrate units to the power circuit and the ground circuit via bonding wires, and forming a short circuit loop; or applying a wire bonding machine to form a stud bump on the power circuit, and then forming a short circuit loop via the power circuit and ground loop of the wire bonding machine; therefore, via the short circuit loop, the passive component is capable of releasing electricity filled therein from previous plasma clean process of substrate units and chips; and grounding the chips and the substrate units and electrically connecting powers and signals to prevent the chips from being damaged due to sudden current impulses resulting from the discharging of the passive components when the passive components are electrically connected to the chips. | 2008-12-11 |
20080305580 | BONDING OF STRUCTURES TOGETHER INCLUDING, BUT NOT LIMITED TO, BONDING A SEMICONDUCTOR WAFER TO A CARRIER - An expandable membrane ( | 2008-12-11 |
20080305581 | Reducing stress in a flip chip assembly - In one embodiment, the present invention includes a method for depositing lead-free bumps on a package substrate, depositing an alloy material on the lead-free bumps, attaching a semiconductor die including conductive bumps to the package substrate so that the conductive bumps contact the alloy material, and heating attached components to reflow the alloy material to form a joint therebetween. Other embodiments are described and claimed. | 2008-12-11 |
20080305582 | POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE - A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads. | 2008-12-11 |
20080305583 | Adhesive sheet, dicing tape integrated type adhesive sheet, and method of producing semiconductor device - The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing tape integrated type adhesive sheet formed by lamination of the adhesive sheet and a dicing tape; and a method of producing a semiconductor device using them. In order to achieve this object, the invention is characterized by specifying the breaking strength, breaking elongation, and elastic modulus of the adhesive sheet in particular numerical ranges. | 2008-12-11 |
20080305584 | HEAT SPREADER FOR CENTER GATE MOLDING - A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels. | 2008-12-11 |
20080305585 | Method for Direct Heat Sink Attachment - A system and method of attaching a heat sink to an integrated circuit chip includes providing a compliant material for constraining the heat sink's mechanical motion while simultaneously allowing for thermal expansion of the heat sink. | 2008-12-11 |
20080305586 | METHOD OF MANUACTURING A SEMICONDUCTOR DEVICE - According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead | 2008-12-11 |
20080305587 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument - A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes. | 2008-12-11 |
20080305588 | Nand-type semiconductor storage device and method for manufacturing same - According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs. | 2008-12-11 |
20080305589 | Semicondustor device and method for manufacturing the same - A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate. | 2008-12-11 |
20080305590 | HIGH PERFORMANCE CMOS DEVICES AND METHODS FOR MAKING SAME - An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant. | 2008-12-11 |
20080305591 | METAL OXIDE ALLOY LAYER, METHOD OF FORMING THE METAL OXIDE ALLOY LAYER, AND METHODS OF MANUFACTURING A GATE STRUCTURE AND A CAPACITOR INCLUDING THE METAL OXIDE ALLOY LAYER - A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such that the first metal oxide is allowed to move into the second layer and a value of the second thickness is such that the second metal oxide is allowed to move into the first layer to form a single-layered structure in which the first and second metal oxides are mixed. | 2008-12-11 |
20080305592 | MENUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY - A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure. | 2008-12-11 |
20080305593 | MEMORY STRUCTURE AND METHOD OF MAKING THE SAME - A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench. | 2008-12-11 |
20080305594 | METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers. | 2008-12-11 |
20080305595 | METHODS OF FORMING A SEMICONDUCTOR DEVICE INCLUDING OPENINGS - There is provided a method of forming a semiconductor device. According to the method, a gate pattern having a capping insulating layer is formed on a substrate, a first etch stop layer is conformably formed. A first interlayer insulating layer having a planarized upper surface, a second etch stop layer and a second interlayer insulating layer are sequentially formed on the first etch stop layer. A first opening and a second opening are formed. The first opening penetrates the second interlayer insulating layer, the second etch stop layer, the first interlayer insulating layer, the first etch stop layer and the capping insulating pattern to expose the gate electrode, and the second opening penetrates the second interlayer insulating layer, the second etch stop layer, the first interlayer insulating layer and the first etch stop layer to expose the substrate. The forming the first and second openings includes at least one selective etching process and a nonselective etching process. | 2008-12-11 |
20080305596 | METHOD OF FABRICATING NON-VOLATILE MEMORY - A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a number of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer. | 2008-12-11 |
20080305597 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film | 2008-12-11 |
20080305598 | ION IMPLANTATION DEVICE AND A METHOD OF SEMICONDUCTOR MANUFACTURING BY THE IMPLANTATION OF IONS DERIVED FROM CARBORANE MOLECULAR SPECIES - An ion implantation device and a method of manufacturing a semiconductor device is described, wherein ionized carborane cluster ions are implanted into semiconductor substrates to perform doping of the substrate. The carborane cluster ions have the chemical form C | 2008-12-11 |
20080305599 | Gate Control and Endcap Improvement - A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed. | 2008-12-11 |
20080305600 | METHOD AND APPARATUS FOR FABRICATING HIGH TENSILE STRESS FILM - A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature. | 2008-12-11 |
20080305601 | METHOD FOR FORMING SEMICONDUCTOR DEVICE USING MULTI-FUNCTIONAL SACRIFICIAL DIELECTRIC LAYER - A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The need to form and remove two separate dielectric material layers is obviated. The nitride layer protects the oxide layer to alleviate oxide damage during a pre-silicidation PAI (pre-amorphization implant) process thereby preventing oxide attack during a subsequent HF dip operation and preventing nickel silicide spiking through the attacked oxide layer during silicidation. | 2008-12-11 |
20080305602 | Transistor Manufacture - An oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor). | 2008-12-11 |
20080305603 | Forming carbon nanotube capacitors - A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes. | 2008-12-11 |
20080305604 | DEEP TRENCH AND FABRICATING METHOD THEREOF, TRENCH CAPACITOR AND FABRICATING METHOD THEREOF - A method of fabricating a deep trench is provided, by which a trench is formed in the substrate initially. Then, a block layer is formed on the substrate surface of the upper portion of the trench. After that, a pad oxide layer is formed on the substrate surface of the lower portion of the trench. Next, a plurality of hemispherical silicon grains is formed on the substrate and exposes a portion of the pad oxide layer. Then, by using the hemispherical silicon grains as a mask, a portion of the pad oxide layer is removed so as to form a patterned pad oxide layer. Continually, the hemispherical silicon grains and the substrate exposed by the patterned pad oxide layer are removed. Finally, the patterned pad oxide layer is removed. | 2008-12-11 |
20080305605 | METHOD FOR FORMING SURFACE STRAP - A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap. | 2008-12-11 |
20080305606 | HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS - Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent. | 2008-12-11 |
20080305607 | Thin film capacitor and fabrication method thereof - A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.12008-12-11 | |
20080305608 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region. | 2008-12-11 |
20080305609 | METHOD FOR FORMING A SEAMLESS SHALLOW TRENCH ISOLATION - A method for fabricating a seamless shallow trench isolation includes providing a semiconductor substrate having at least a shallow trench that is filled by a dielectric layer with a seam, forming a dielectric layer filling the shallow trench with a seam, forming at least one healing layer on the dielectric layer, and performing a low-temperature steam annealing process to eliminate the seam. | 2008-12-11 |
20080305610 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE - A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed. | 2008-12-11 |
20080305611 | COATING COMPOSITION FOR FORMING OXIDE FILM AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE USING THE SAME - A coating composition for forming an oxide film, which can suppress the phenomenon of an increased wet etching rate caused by a part of the SOG film embedded inside a groove becoming low-density, and which can suppress the volume expansion coefficient to a low level, and a method for producing a semiconductor device using the same are provided. An oxide film is formed inside a groove by: coating a coating composition for forming an oxide film, which contains a polysilazane or a hydrogenated silsesquioxane, and a polysilane, on a substrate having a groove; and thereafter heat treatment in an oxidizing atmosphere. This method is suitable for forming a device isolation region and a wiring interlayer dielectric film. | 2008-12-11 |
20080305612 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating films so that parts of the polycrystalline silicon film on the respective gate insulating films are on a level with each other and serving as a gate electrode. The substrate is formed with a recess defined by a bottom and sidewalls substantially perpendicular to the bottom, the recess corresponding to the part of the gate insulating film with the first film thickness. | 2008-12-11 |
20080305613 | METHOD FOR FABRICATING AN SOI DEFINED SEMICONDUCTOR DEVICE - Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the remaining SOI material in the semiconductor layer as an etch mask. N— and P-type ions are implanted into the substrate through the openings to form to form N-doped and P-doped regions therein, such as an anode and a cathode of a semiconductor diode structure. The N-doped and P-doped regions are closely spaced and precisely aligned to each other by the SOI material in the semiconductor layer. Electrical contacts are then made to the N-doped and P-doped regions. | 2008-12-11 |
20080305614 | PRECISION TRENCH FORMATION FOR SEMICONDUCTOR DEVICE - Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen. | 2008-12-11 |
20080305615 | Method of Scribing and Breaking Substrate Made of a Brittle Material and System for Scribing and Breaking Substrate - An object of the present invention is to provide a method of scribing and breaking a substrate made of a brittle material by which good-quality cutting surface of the substrate can be obtained without any defects such as chippings on the substrate. | 2008-12-11 |
20080305616 | Die Singulation Methods - Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against the surface, the semiconductor substrate is thinned, and then cut into a plurality of dice. The surface may be a pliable material, and may be stretched after the cutting to increase separation between at least some of the dice. While the pliable surface is stretched, at least some of the dice may be picked from the surface. In some embodiments, the semiconductor substrate is retained to the surface with a radiation-curable material. The material is in an uncured and tacky form during the thinning of the substrate, and is subsequently cured into a less tacky form prior to the picking of dice from the surface. | 2008-12-11 |
20080305617 | Method for depositing a conductive capping layer on metal lines - In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance. | 2008-12-11 |
20080305618 | METHOD OF FORMING POLYCRYSTALLINE SEMICONDUCTOR FILM - A method of forming a polycrystalline semiconductor film, which includes irradiating an amorphous semiconductor film formed on an insulating substrate with light to convert the amorphous semiconductor into a polycrystalline semiconductor with laterally grown crystal grains, thus forming a polycrystalline semiconductor film, wherein crystal growth in the semiconductor is controlled such that first crystal grains laterally grow in the first direction along a X-axis from the first group of initial nuclei, the second crystal grains laterally grow in the second direction opposite to the first direction along the X-axis from the second group of initial nuclei arranged apart from the first group of initial nuclei along the X-axis, and the first crystal grains collide against the second crystal grains at different points in time along a Y-axis. | 2008-12-11 |
20080305619 | METHOD OF FORMING GROUP IV SEMICONDUCTOR JUNCTIONS USING LASER PROCESSING - A method forming a Group IV semiconductor junction on a substrate is disclosed. The method includes depositing a first set Group IV semiconductor nanoparticles on the substrate. The method also includes applying a first laser at a first laser wavelength, a first fluence, a first pulse duration, a first number of repetitions, and a first repetition rate to the first set Group IV semiconductor nanoparticles to form a first densified film with a first thickness, wherein the first laser wavelength and the first fluence are selected to limit a first depth profile of the first laser to the first thickness. The method further includes depositing a second set Group IV semiconductor nanoparticles on the first densified film. The method also includes applying a second laser at a second laser wavelength, a second fluence, a second pulse duration, a second number of repetitions, and a second repetition rate to the second set Group IV semiconductor nanoparticles to form a second densified film with a second thickness, wherein the second laser wavelength and the second fluence are selected to limit a second depth profile of the second laser to the second thickness. | 2008-12-11 |
20080305620 | METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS - Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer. | 2008-12-11 |
20080305621 | CHANNEL STRAIN ENGINEERING IN FIELD-EFFECT-TRANSISTOR - There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material. | 2008-12-11 |
20080305622 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming at least two gate insulating layers having different thickness on a substrate having low, medium and high voltage regions; and then depositing a gate layer material on the gate insulating layers; and then forming a first etch mask on the gate layer material; and then forming gate electrodes in the low, medium and high voltage regions by etching the gate layer material using the first etch mask; and then forming a second etch mask to expose a thickest one of the gate insulating layers, the gate electrode and the first etch mask each formed in the high voltage region while covering the remaining gate insulating layers, the gate electrodes and the first etch masks formed in the low and medium voltage regions; and then etching the thickest gate insulating layer using the second etch mask; and then removing the first and second etch masks. Thereby, the first etch mask used for forming the gates remains without being removed even after the gate is formed to perform a role of a barrier during etching the gate insulating layer. | 2008-12-11 |
20080305623 | Semiconductor device manufacturing methods - Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask. | 2008-12-11 |
20080305624 | Bonding Structure With Buffer Layer And Method Of Forming The Same - A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated. | 2008-12-11 |
20080305625 | POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS - A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth. | 2008-12-11 |
20080305626 | METHOD OF FORMING SOLID BLIND VIAS THROUGH THE DIELECTRIC COATING ON HIGH DENSITY INTERCONNECT SUBSTRATE MATERIALS - A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material. | 2008-12-11 |
20080305627 | METHOD OF FORMING A CONTACT PLUG AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a contact plug includes the following processes. A dummy film is formed over a substrate. The dummy film may include amorphous carbon as a main material. At least one contact hole is formed in the dummy film. At least one contact plug is formed in the at least one contact hole. | 2008-12-11 |
20080305628 | SEMICONDUCTOR DEVICE WITH CONNECTING VIA AND DUMMY VIA AND METHOD OF MANUFACTURING THE SAME - An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an opening for a first via, and an opening for a second via having a larger bottom area than the first via opening, so as to form a first via hole and a second via hole in the interlayer dielectric. Since the second via hole has a larger diameter than the second via hole, the second via hole is opened up prior to the second via hole, and the underlying interconnect is exposed first at the bottom of the second via hole. | 2008-12-11 |
20080305629 | TUNGSTEN NITRIDE ATOMIC LAYER DEPOSITION PROCESSES - In one embodiment, a method for forming a tungsten barrier material on a substrate is provided which includes depositing a tungsten layer on a substrate during a vapor deposition process and exposing the substrate sequentially to a tungsten precursor and a nitrogen precursor to form a tungsten nitride layer on the tungsten layer. Some examples provide that the tungsten layer may be deposited by sequentially exposing the substrate to the tungsten precursor and a reducing gas (e.g., diborane or silane) during an atomic layer deposition process. The tungsten layer may have a thickness of about 50 Å or less and tungsten nitride layer may have an electrical resistivity of about 380 μΩ-cm or less. Other examples provide that a tungsten bulk layer may be deposited on the tungsten nitride layer by a chemical vapor deposition process. | 2008-12-11 |
20080305630 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film to form a plurality of gate electrodes; filling a third insulating film between the plurality of gate electrodes; exposing an upper portion of the second conductive film by removing the third insulating film; covering surfaces of the exposed upper portion of the second conductive film with fluoride (F) or carbon (C) or oxygen (O); and forming a metal film on an upper surface of the second conductive film; and forming silicide layers on the upper portion of the second conductive films by thermally treating the metal film. | 2008-12-11 |
20080305631 | METHOD FOR FORMING ELECTRODE STRUCTURE FOR USE IN LIGHT EMITTING DEVICE AND METHOD FOR FORMING STACKED STRUCTURE - A method for forming an electrode structure in a light emitting device is disclosed. The method includes the steps of: forming a mask material layer having an opening; depositing a first material layer on the mask material layer and on a portion of a compound semiconductor layer exposed through the bottom of the opening by a physical vapor deposition method reducing the particle density so that the mean free path for collision is long; depositing a second material layer on the first material layer on the mask material layer, on the first material layer deposited on the bottom of the opening, and on a portion of the compound semiconductor layer exposed through the bottom of the opening by a vapor deposition method other than the physical vapor deposition method; and removing the mask material layer and the first and second material layers deposited on the mask material layer. | 2008-12-11 |
20080305632 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM - A substrate processing apparatus is provided to enable to efficiently remove an oxide layer and an organic material layer. A third process unit ( | 2008-12-11 |
20080305633 | Manufacturing method of a semiconductor device and substrate processing apparatus - A method of manufacturing a semiconductor device comprises carrying a substrate into a processing chamber, forming a film containing ruthenium on the substrate by supplying a material gas into the processing chamber, carrying the film-formed substrate out of the processing chamber; and cleaning an inside of the processing chamber by executing, alternately plural times, removing deposits containing ruthenium deposited in the processing chamber by supplying a cleaning gas whose molecule has a fluorine atom or a chlorine atom into the processing chamber and exposing surfaces of the deposits by removing a by-product generated so as to cover the surfaces of the deposits in removing the deposits. | 2008-12-11 |
20080305634 | Metal Film Separation Prevention Structure in Metal Film Forming Device, and Semiconductor Device Manufacturing Method Using Said Structure - The object of this invention is to prevent unwanted separation of a deposited metal film from a member, such as an anti-adhesion plate, in the chamber of a metal film forming device. In a sputtering device, metal particles sputtered from the surface of a target | 2008-12-11 |
20080305635 | METHOD FOR FABRICATING A PATTERN - A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask. | 2008-12-11 |
20080305636 | METHOD OF FORMING FINE PATTERN EMPLOYING SELF-ALIGNED DOUBLE PATTERNING - There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns is reacted using a chemical attachment process, thereby forming sacrificial layers along outer walls of the first mask patterns. The reactive layer that is not reacted is removed to expose the sacrificial layers. Second mask patterns are formed between the sacrificial layers adjacent to sidewalls of the first mask patterns facing each other. The sacrificial layers are removed to expose the first and second mask patterns and the substrate exposed between the first and second mask patterns. The substrate is etched using the first and second mask patterns as an etching mask. | 2008-12-11 |
20080305637 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device which includes sequentially forming a non-etching layer and a sacrificial layer on a semiconductor substrate; and then forming a plurality of photo-resist layer patterns having a plurality of openings exposing the sacrificial layer; and then forming a plurality of first pattern grooves in the sacrificial layer etching the exposed sacrificial layer using the photo-resist patterns as an etching barrier; removing the photo-resist layer; and then forming an oxidation layer having a plurality of second pattern grooves on the sacrificial layer and in the first pattern grooves by performing a thermal oxidation process on the sacrificial layer; and then forming a plurality of first through-holes exposing the non-etching layer by completely removing the sacrificial layer remaining in oxidation layer; and then forming a plurality of patterns in the non-etching layer by etching the exposed portions of the non-etching layer using the oxidation layer as an etching barrier. | 2008-12-11 |
20080305638 | Coating compositions for use in forming patterns and methods of forming patterns - A coating composition for forming etch mask patterns may include a polymer and an organic solvent. The polymer may have an aromatic ring substituted by a vinyl ether functional group. The polymer may be, for example, a Novolak resin partially substituted by a vinyl ether functional group or poly(hydroxystyrene) partially substituted by a vinyl ether functional group. | 2008-12-11 |
20080305639 | DUAL DAMASCENE PROCESS - A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching. | 2008-12-11 |
20080305640 | METHOD FOR PREPARING TRENCH POWER TRANSISTORS - A method for preparing a trench power transistor comprises the steps of forming a mask layer having a plurality of openings on a semiconductor substrate, removing a portion of the semiconductor substrate under the openings to form a plurality of trenches in the semiconductor substrate in an array manner, coating a photoresist layer covering the surface of the mask layer, patterning the photoresist layer, and removing a portion of the mask layer not covered by the photoresist layer to form a mask block exposing a portion of the semiconductor substrate in the array region. | 2008-12-11 |
20080305641 | REVERSE MASKING PROFILE IMPROVEMENTS IN HIGH ASPECT RATIO ETCH - A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of photodefinable material which is deposited over the array portion of the substrate. The photodefinable material is removed along with the inorganic hard mask overlaying the periphery. A portion of the amorphous carbon layer is etched in the exposed periphery. The inorganic hard mask is removed and normal high aspect ratio etching continues. The amount of amorphous carbon layer remaining in the periphery results in a more uniform mask height between the array and periphery at the end of high aspect ratio etching. The more uniform mask height mitigates twisting at the edge of the array. | 2008-12-11 |
20080305642 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer. | 2008-12-11 |
20080305643 | Method For the Removal of Doped Surface Layers on the Back Faces of Crystalline Silicon Solar Wafers - The invention relates to a method for the one-sided removal of a doped surface layer on rear sides of crystalline silicon solar wafers. In accordance with the object set, doped surface layers should be able to be removed from rear sides of such solar wafers in a cost-effective manner and with a handling which is gentle on the substrate. In addition, the front side should not be modified. In accordance with the invention, an etching gas is directed onto the rear side surface of silicon solar wafers with a plasma atmospheric pressure. | 2008-12-11 |
20080305644 | Method of manufacturing semiconductor device including trench-forming process - In a manufacturing method of a semiconductor device, a trench is formed in a semiconductor substrate by an anisotropic dry etching so as to have an aspect ratio greater than or equal to 10, and a damaged layer that is generated in a wall and a bottom of the trench due to the anisotropic dry etching is removed by an isotropic dry etching. The isotropic dry etching is performed with a first gas including carbon and fluorine and a second gas including oxygen. A temperature of the semiconductor substrate is controlled so that the damaged layer is removed from a whole surface of the wall and the bottom in the isotropic dry etching. | 2008-12-11 |
20080305645 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH | 2008-12-11 |
20080305646 | Atomic layer deposition - An atomic layer deposition with hydroxylation pre-treatment is provided. The atomic layer deposition comprises the steps of (a) performing a hydroxylation pre-treatment on a silicon substrate to create a predetermined number of hydroxyl groups thereon; (b) performing a precursor pulse on the pre-treated silicon substrate, wherein the precursor react with the hydroxyl groups, forming a layer; (c) purging the silicon substrate with an inert carrier gas; (d) performing a water pulse on the layer sufficiently so as to create a predetermined number of hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b)˜(e) until the atomic layer deposition is completed. Each layer overlying the silicon substrate has a minimum of 70 percent surface hydroxyl groups. | 2008-12-11 |
20080305647 | Method for Manufacturing a Semiconductor Device - It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower. | 2008-12-11 |
20080305648 | METHOD FOR FORMING INORGANIC SILAZANE-BASED DIELECTRIC FILM - A method of forming an inorganic silazane-based dielectric film includes: introducing a gas constituted by Si and H and a gas constituted by N and optionally H into a reaction chamber where an object is placed; controlling a temperature of the object at −50° C. to 50° C.; and depositing by plasma reaction a film constituted by Si, N, and H containing inorganic silazane bonds. | 2008-12-11 |