50th week of 2008 patent applcation highlights part 18 |
Patent application number | Title | Published |
20080303548 | SEMICONDUCTOR DEVICE - An I/O buffer section is provided with a status setting circuit. The status setting circuit arbitrarily sets a signal state of an I/O terminal according to a combination of control signals stored in a setting register. Thus, the I/O buffer section is temporarily set to a Hi-Z state by the status setting circuit even in the case of the I/O terminal originally set to a signal holding state. Consequently, a leak test for testing whether the I/O buffer section is good or bad, can be performed, and the reliability of a semiconductor device can be enhanced. | 2008-12-11 |
20080303549 | Data transmitting method and electronic device using the same - A data transmitting method for transmitting a software version data from a power IC to a controlling IC is provided. Firstly, a request signal is transmitted to a second pin of the power IC from a data pin of the controlling IC. Next, an acknowledge signal is transmitted to the data pin from the second pin. Then, a first pin of the power IC is enabled by a clock pin of the controlled IC. Lastly, the software version data is transmitted to the data pin from the second pin of the power IC. | 2008-12-11 |
20080303550 | INTEGRATED CIRCUIT WITH PLURAL LEVEL SHIFTERS - An integrated circuit is provided. The integrated circuit includes N level shifting devices. Each level shifting device receives a first digital signal and a second digital signal, and includes a first level shifter converting a first voltage of the first digital signal into a third voltage and converting a second voltage of the first digital signal into a fourth voltage, and a second level shifter converting a first voltage of the second digital signal into a fifth voltage and converting a second voltage of the second digital signal into a sixth voltage. | 2008-12-11 |
20080303551 | Semiconductor device - A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state. | 2008-12-11 |
20080303552 | Clock Distribution Network Architecture for Resonant-Clocked Systems - Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry. | 2008-12-11 |
20080303553 | METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER - A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate. | 2008-12-11 |
20080303554 | STRUCTURE FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER - A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate. | 2008-12-11 |
20080303555 | Tone detector - A tone detector is disclosed that is realizable in digital embodiment on a single integrated circuit die and does not require external components, such as a discrete capacitor. An input connects to a comparator, which in turn connects to one or more edge detectors and a flip flop. The edge detector outputs a pulse responsive to a detected edge. A counter is reset by the pulses from the edge detectors thereby preventing the counter from reaching a maximum value, which would otherwise be output from the counter and provided to a flip flop to clock in the comparator output at the D input to the flip flop. In operation, the comparator generates a rail to rail signal responsive to a received tone, which in turn is clocked through the flip flop as a logic high output indicating presence of a tone. | 2008-12-11 |
20080303556 | POWER SUPPLY GROUND CROSSING DETECTION CIRCUIT - A detecting circuit for detecting an input signal crossing a ground level is disclosed. The circuit comprises two PMOS transistors and two NMOS transistors connected, respectively. The PMOS transistors have source terminals connected to a power voltage, the gate terminals connected together and the drain terminal of the second PMOS transistors. The first NMOS transistor has the source terminal as an input terminal to retrieve an input signal, and the drain terminal to be act as output terminal and the second NMOS transistor has the source terminal grounded. The gate terminals of the two NMOS transistors are connected together and to a biased voltage. The circuit can also be used to detect the power voltage if the input terminal is set at the source terminal of the first PMOS transistor and the source terminal of the first NMOS transistor grounded. | 2008-12-11 |
20080303557 | CIRCUITS FOR FORMING THE INPUTS OF A LATCH - Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal. | 2008-12-11 |
20080303558 | DATA OUTPUT DRIVER CIRCUIT - A data output driver circuit can be configured to comprise a predriver control unit generate a plurality of pullup output load control signals and a plurality of pulldown output load control signals depending upon a sensed external voltage, and a predriver is configured to output a signal by adjusting a slew rate of an inputted data in response to the plurality of pullup output load control signals and the plurality of pulldown output load control signals. | 2008-12-11 |
20080303559 | ELECTRONIC DEVICE AND RELATED METHOD FOR PERFORMING COMPENSATION OPERATION ON ELECTRONIC ELEMENT - The present invention discloses an electronic device and related method for performing a compensation operation on an electronic element, wherein the electronic device includes: a control module, for outputting a control signal according to an input signal; a driver module, coupled to the control module and the electronic element, for providing a driving current to the electronic element according to the control signal; a sensor module, for outputting at least a sensor signal according to a variation of an operation environment; a compensation control module, coupled to the sensor module, for outputting at least a compensation control signal according to the at least a sensor signal and the input signal; and a compensation driver module, coupled to the electronic element and the compensation control module, for providing at least a compensation driving current to the electronic element according to the at least a compensation control signal. | 2008-12-11 |
20080303560 | DRIVE CIRCUIT FOR VOLTAGE DRIVEN ELECTRONIC ELEMENT - A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal. | 2008-12-11 |
20080303561 | Frequency divider including latch circuits - A frequency divider is disclosed herein. The frequency divider includes a first latch circuit and a second latch circuit coupled to the first latch circuit. Each of the first latch circuit and the second latch circuit includes a first level for generating a source current, a second level for receiving a pair of input signals and for generating a pair of output signals, and a third level for receiving the source current and a pair of clock signals. The second level is coupled between the first level and the third level. The first level includes a first transistor having a source terminal and a substrate both coupled to a source voltage. The third level includes a plurality of transistors controlled by the pair of clock signals. Each transistor in the third level has a source terminal and a substrate both coupled to ground. | 2008-12-11 |
20080303562 | DIVIDER - A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate. | 2008-12-11 |
20080303563 | Triangular wave generator - Triangular wave oscillation circuits generate A-wave and B-wave with phases opposite to each other, and are capable of independently controlling oscillation levels of the A-wave and the B-wave. A slope switching circuit including an output voltage monitoring circuit, a slope switching control circuit, and an inverter, monitors output voltages of the triangular wave oscillation circuits, to switch an output voltage generation mode of one triangular wave oscillation circuit whose triangular wave reaches a high level, from an up-slope waveform mode to a down-slope waveform mode, and to switch an output voltage generation mode of the other triangular wave oscillation circuit, from the down-slope waveform mode to the up-slope waveform mode. An oscillation level control circuit controls an oscillation level of the other triangular wave oscillation circuit so that the output voltage of the other of the triangular wave oscillation circuit becomes a reference lower limit crest value during the switching. | 2008-12-11 |
20080303564 | ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER - A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences. | 2008-12-11 |
20080303565 | DLL CIRCUIT AND RELATED METHOD FOR AVOIDING STUCK STATE AND HARMONIC LOCKING UTILIZING A FREQUENCY DIVIDER AND AN INVERTER - Disclosed is a DLL circuit for avoiding stuck and harmonic locking errors by utilizing a frequency divider and an inverter. This DLL circuit includes: a delay line, a control circuit, a first frequency divider, a second frequency divider and an inverter. The delay line is utilized for receiving a first clock signal and delaying the first clock signal by a delay amount to generate a second clock signal. Additionally, the control circuit, which is coupled to the delay line, is utilized for controlling the delay line. The first frequency divider, which is coupled to the delay line and the control circuit, is utilized for receiving the first clock signal and dividing a frequency of the first clock signal according to a first frequency dividing factor to form a third clock signal. | 2008-12-11 |
20080303566 | SPREAD SPECTRUM CLOCK GENERATOR WITH LOW JITTER - A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N−a)(P−S) through receiving the frequency divided signal and a control word; wherein N, P, and S are integers, and a, b are fractional numbers, and S can be adjusted by the delta-sigma modulator. | 2008-12-11 |
20080303567 | DELAY LOCKED LOOP CIRCUIT - A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal. | 2008-12-11 |
20080303568 | Clock distribution network supporting low-power mode - A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift. | 2008-12-11 |
20080303569 | Delay locked loop circuit - The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off. | 2008-12-11 |
20080303570 | METHOD AND APPARATUS FOR SYNCHRONOUS CLOCK DISTRIBUTION TO A PLURALITY OF DESTINATIONS - Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described. | 2008-12-11 |
20080303571 | Delay Circuit - A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals. | 2008-12-11 |
20080303572 | Spread Spectrum Device and Related Random Clock Generator for a Switching Amplifier - A random clock generator for a spread spectrum modulating device includes a random number generator for generating a plurality of random number signals according to a first square wave signal and a control signal, a reference wave generator coupled to the random number generator for generating a triangular signal and a second square wave signal according to the plurality of random number signals, and a trigger signal generator coupled to the random number generator and the reference wave generator, for generating the first square wave signal according to the second square wave signal. | 2008-12-11 |
20080303573 | DATA-RETENTION LATCH FOR SLEEP MODE APPLICATION - A latch includes a data input terminal for receiving a data signal; a data output terminal for outputting the data signal; a first control terminal for receiving a control signal to set or reset the data signal derived from the data output terminal; a sleep signal input terminal for receiving a sleep signal to determine a sleep mode; a first logic circuit having input terminals coupled to the data input terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data output terminal; and a second logic circuit having input terminals coupled to the data output terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data input terminal; wherein the first logic circuit or the second logic circuit ignores the first control signal in response to the sleep signal when the latch is operated in the sleep mode. | 2008-12-11 |
20080303574 | INTERNAL CLOCK DRIVER CIRCUIT - An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal. | 2008-12-11 |
20080303575 | PULSE GENERATING CIRCUIT AND UWB COMMUNICATION SYSTEM - A pulse generating circuit includes a starting circuit which generates m (two or larger integer) starting signals at predetermined time intervals based on a generation starting signal, and m pulse wave generating sub circuits which have the same characteristics and generate pulse waves having pulse width Pw for n cycles (n: 1 or larger integer) based on the respective m starting signals. | 2008-12-11 |
20080303576 | Clock Distribution Network Architecture with Resonant Clock Gating - Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal. | 2008-12-11 |
20080303577 | ARRANGEMENT FOR CANCELING OFFSET OF DRIVER AMPLIFIER CIRCUITRY - In an offset canceling arrangement, an offset of an operational amplifier may be canceled even in case capacitive or resistive element is connected outside of the operational amplifier per se, and a signal may be output even during the offset canceling operation. IC chips include respective sets of plural output circuits. Each of the IC chips is provided with an offset canceling function, for which the respective sets of output circuits are grouped into plural groups. A reference signal for offset canceling is generated from a reference output circuit. One of the groups, each constituting one IC chip, is selected, and the reference signal for offset canceling generated by the group is used as a reference signal for offset canceling for the remaining group(s). | 2008-12-11 |
20080303578 | BOOST CIRCUIT AND LEVEL SHIFTER - A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input signal to generate an inverted input signal. The second boost circuit is coupled to an output terminal of the inverter to receive the inverted input signal, and a second amplification factor for the inverted input signal is determined based on the control signal. The level shift circuit has a first input terminal and a second input terminal respectively coupled to output terminals of the first boost circuit and second boost circuit to change the voltage level of output signals from the first boost circuit and second boost circuit to a first voltage level. | 2008-12-11 |
20080303579 | MIXER WITH CARRIER LEAKAGE CALIBRATION - A mixer circuit. The mixer circuit comprises a double-balanced mixer and a carrier-leakage calibration cell. The double-balanced mixer has first and second input pairs whereby the first input pair receives the first differential input signal. The carrier-leakage calibration cell receives the second differential input signal and a differential calibration current and generates first and second output voltages to the second input pair of the double-balanced mixer. | 2008-12-11 |
20080303580 | CONTROL CIRCUIT FOR A HIGH-SIDE SEMICONDUCTOR SWITCH FOR SWITCHING A SUPPLY VOLTAGE - A high-side semiconductor switch control circuit for switching a positive supply voltage is provided, having a circuit to provide a drive voltage for the high-side semiconductor switch, a driver circuit for driving the high-side semiconductor switch based on the control circuit, wherein both the circuit for providing the drive voltage as well as the driver circuit operate in relation to a floating switching point, an input circuit portion that receives a control signal related to ground, and a level shift circuit portion that is connected between the input circuit portion and the driver circuit portion and set up so as to transform the control signal related to ground into a floating voltage level for the driver circuit portion. | 2008-12-11 |
20080303581 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a driver provided for a semiconductor element having a control electrode to which a drive voltage is applied, the semiconductor element being switched between the conduction state and the non-conduction state based on the drive voltage, the driver operative to apply the drive voltage to the control electrode; a detector operative to supply a voltage detection signal oscillating at a certain frequency to the control electrode to detect a first voltage having a certain relation to a voltage applied to the semiconductor element; and a controller operative to control the detector based on the first voltage detected at the detector. | 2008-12-11 |
20080303582 | INPUT DEVICE FOR PORTABLE TERMINAL - Disclosed is an input device of a portable terminal, which includes at least one key groove at an outer peripheral surface of the portable terminal, a push detector in the key groove, and a sliding pad. The sliding pad is in the key groove and disposed on the push detector, and the sliding pad is movable within the first key groove. The input device generates an input signal according to movement of the sliding pad or an operation of the push detector. | 2008-12-11 |
20080303583 | Electronics module, method for the manufacture thereof and applications - This publication concerns electronics modules comprising at least one first material zone formed of first material which can be structurally transformed by means of electric interaction in order to increase its conductivity at least locally, the first material having a first transformation threshold, and at least one second material zone in the vicinity of the first material zone. According to the invention, the second material zone is formed from second material, which can also be structurally transformed in order to increase its conductivity, the second material having a second transformation threshold, which is lower than the transformation threshold of the first material zone. With the aid of the invention, post-processing electrical programmability and non-volatility of printable memories can be achieved. | 2008-12-11 |
20080303584 | CHARGE CIRCUIT FOR OPTIMIZING GATE VOLTAGE FOR IMPROVED EFFICIENCY - A charge circuit for providing a gate driver supply voltage for a gate driver of a switching power supply in accordance with an embodiment of the present application includes a first voltage source providing a first voltage and a charge pump circuit connected to the first voltage source and operable to be turned ON and OFF to improve efficiency such that an increased output voltage of the charge circuit is provided when the charge pump circuit is ON, and wherein the output voltage is the gate driver supply voltage. | 2008-12-11 |
20080303585 | Charge pump circuit and nonvolatile memory - A charge pump circuit is provided for stably obtaining a stepped-up voltage even if a temperature varies. The charge pump circuit has a structure in which a voltage corresponding to a voltage which is dropped by a charge transfer device is generated by a charge transfer device for correction, and the generated voltage is applied to an input voltage of the charge pump circuit. In addition, a voltage amplitude of a clock pulse for a step-up operation is adapted to be an amplitude based on the input voltage. | 2008-12-11 |
20080303586 | Negative voltage generating circuit - An exemplary negative voltage generating circuit includes a voltage input, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first capacitor, a second capacitor, a switch controller, and a voltage output. The voltage input is connected to ground via the first switch transistor, the first capacitor, and a source electrode and the second switch transistor. The first switch transistor is connected to the second switch transistor via the third switch transistor, the second capacitor, and the fourth switch transistor. The third switch transistor is connected to ground. The fourth switch transistor is connected to the voltage output. The first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are connected to the switch controller. | 2008-12-11 |
20080303587 | Multi-Level Voltage Generator - A multilevel voltage generator includes a first positive voltage generator generating a first output voltage using a first capacitor which receives a reference voltage and is charged to a voltage level corresponding to two times of the reference voltage, a second positive voltage generator generating a second output voltage and a third output voltage using a second capacitor and a third capacitor which receive the first output voltage and are charged to voltage levels corresponding to predetermined multiples of the reference voltage, and a negative voltage generator generating a fourth output voltage having predetermined negative voltage levels using a fourth capacitor which receives the reference voltage, the second output voltage, or the third output voltage and is charged to a voltage level corresponding to a negative voltage of the second or third output voltage. | 2008-12-11 |
20080303588 | REFERENCE VOLTAGE GENERATING CIRCUIT AND CONSTANT VOLTAGE CIRCUIT - A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate, and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate. | 2008-12-11 |
20080303589 | HIGH-ORDER LOW-PASS FILTER CIRCUIT AND METHOD - A low-pass filtering circuit and method are disclosed. The circuit includes a low-pass filter with a capacitor, and a multiplier configured to multiply the capacitance of the capacitor by feeding-back a high-frequency signal apparent in an output signal of the low-pass filter to the capacitor. | 2008-12-11 |
20080303590 | POWER AMPLIFIER WITH NOISE SHAPING FUNCTION - A power amplifier with noise shaping function is provided. The power amplifier includes a differential mode integrator, an integration and adjustment unit and a switch unit. The differential mode integrator is used for receiving a differential mode input signal and a differential mode output signal, and outputting a differential mode first signal. The integration and adjustment unit is coupled to the differential mode integrator for receiving the first signal and an output signal and outputting a single-end mode second signal. The switch unit is used for receiving the second signal and outputting the differential mode output signal to drive the load. The present invention uses a common mode input signal instead of the single-end input signal to eliminate the common mode noise, and uses a 2 | 2008-12-11 |
20080303591 | AMPLIFYING CIRCUIT AND ASSOCIATED LINEARITY IMPROVING METHOD - An amplifying circuit and an associated linearity improving method are provided to correct the AM to PM distortion of an amplifier, thereby improving the amplifier linearity. The amplifying circuit includes an amplifier and a correcting unit. The amplifier has a non-linear input capacitor. The correcting unit generates a correction signal according to an input signal of the amplifier, and performs an AM to PM correction according to the correction signal, thereby making the amplifier have an approximately linear equivalent input capacitor. | 2008-12-11 |
20080303592 | Differential amplifier circuit and A/D converter - PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors. | 2008-12-11 |
20080303593 | MUGFET CIRCUIT FOR INCREASING OUTPUT RESISTANCE - In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a load, a second terminal of the load coupled to a further reference source, the further MuGFET device configured to receive a further input signal at a gate thereof, and wherein the MuGFET device and the further MuGFET device are disposed above a substrate and configured to provide an output signal at the first terminal of the load. | 2008-12-11 |
20080303594 | Amplifier Circuit - There is provided an amplifier circuit including a plurality of unit amplifiers connected in parallel to an input signal terminal, wherein each of the unit amplifiers includes: a first switch switching an input signal inputted from the input signal terminal; a first field effect transistor having a gate connected to the input signal terminal via the first switch and amplifying the input signal of the input signal terminal to output the amplified input signal; a second switch connected in parallel to the first switch and switching the input signal of the input signal terminal at a complementary timing to a switching timing of the first switch; and a capacitor connected to the input signal terminal via the second switch. | 2008-12-11 |
20080303595 | AMPLIFYING CIRCUIT - An amplifier includes: a class AB input stage, receiving an input signal, for generating an inner signal according to the input signal; class AB output stage, includes: a biasing circuit, for providing a first voltage and a second voltage according to the inner signal; and an output stage, for generating an output signal according to the first voltage and the second voltage; wherein a voltage difference between the first voltage and the second voltage generated by the biasing circuit is corresponding to the input signal. | 2008-12-11 |
20080303596 | AMPLIFIER CIRCUIT HAVING AN OUTPUT TRANSISTOR FOR DRIVING A COMPLEX LOAD - An amplifier circuit is disclosed having an output transistor for driving a complex load over a drive frequency range, wherein in the lower part of the range an inductive component of the load dominates and in the upper part the inductive component does not dominate. The amplifier circuit includes a current mirror circuit that is connected upstream of the output transistor and has a shunt path to a second potential, for the purpose of relatively reducing a DC current flowing through the output transistor in comparison with an AC current flowing through the latter. | 2008-12-11 |
20080303597 | SEMICONDUCTOR CIRCUIT - There are included a Wilkinson divider/combiner dividing an input signal, amplifying elements amplifying outputs of the Wilkinson divider/combiner, and a Wilkinson divider/combiner combining outputs of respective amplifying elements. A variable capacitor element is connected to a branch point of a signal transmission path in the Wilkinson divider/combiner. A capacitance value of the variable capacitor element is controlled in correspondence with a frequency of an input signal, whereby a matching frequency is corrected to increase an operating frequency band. | 2008-12-11 |
20080303598 | CIRCUIT AND METHOD FOR REDUCING BIAS NOISE IN AMPLIFIER CIRCUITS - An amplifier circuit and method for reducing bias noise is disclosed. The amplifier circuit includes a passive biasing source for supplying a desired bias signal to the amplifier and an active biasing source for energizing the passive biasing source to supply the desired bias signal. The amplifier circuit also includes a decoupler for selectively decoupling the active biasing source from the passive biasing source when the amplifier is configured for amplifying an input signal so that the amplifier remains isolated from electronic noise produced by the active biasing source while still being supplied the desired bias signal by the passive source. | 2008-12-11 |
20080303599 | SEMICONDUCTOR DEVICE - There is provided a PLL circuit | 2008-12-11 |
20080303600 | Dynamic Ring Oscillators - A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate. | 2008-12-11 |
20080303601 | REFERENCE OSCILLATOR AND ITS USE - A reference clock circuit ( | 2008-12-11 |
20080303602 | Infinite Radio Frequency Spectrum Transceiver - The present invention “Infinite Radio Frequency Spectrum Transceiver” (IRFS for short) relates to a circuit that emits and receives the complete radio frequency spectrum transmission as it exists from 0 hertz to the region where radio frequency ends to j the infrared. Such a circuit causes infinite bandwidth output gain evenly over the entire radio frequency spectrum, can be readily used as a noise source, where such output even gain across the spectrum. Such circuit in its simplest form can be used as a noise source, subsequent use of single circuits organized in series or parallel increase power where they can readily be used as a radio frequency jamming array. Additional insertion into specific points of the circuit can be used to transmit a signal across the bandwidth where such signal takes on the attributes of all frequencies and appears as higher and lower frequency as amplitude gain at such points across the bandwidth. Additional use of various filters can restrict the frequency of transmission. As a receiver signals of all and any kind will show up across the bandwidth viewed on a spectrum analyzer or other analytical instrument to decipher such received signals. As a single component to use in emitting broadband signals for radio frequency beacons. | 2008-12-11 |
20080303603 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a voltage controlled oscillator which controls a bias current or an oscillation frequency to supply an output signal, a phase-locked loop circuit which supplies a frequency control signal based on the output signal supplied from the voltage controlled oscillator, a peak detection circuit which detects a peak of the frequency control signal supplied from the phase-locked loop circuit, and a bias control circuit which produces a bias current based on the peak detected by the peak detection circuit to supply the bias current. The voltage controlled oscillator controls the bias current supplied from the bias control circuit or the oscillation frequency to supply the output signal based on the frequency control signal supplied from the phase-locked loop circuit. | 2008-12-11 |
20080303604 | TRANSMISSION CABLE CAPABLE OF CONTROLLING AND REGULATING ITS CHARACTERISTIC IMPEDANCE AND ELECTROMAGNETIC INTERFERENCE SIMULTANEOUSLY - Disclosed is a transmission cable capable of controlling and regulating its characteristic impedance and electromagnetic interference simultaneously. The transmission cable comprises at least two conduction wires, which are twisted with each other along a longitudinal direction of the transmission cable. In the design of the transmission cable, the electromagnetic interference is controlled through the twisting of the conduction wires (for example, twisted pair cable). In addition, the two conduction wires tightly contact each other without any gap therebetween, thus achieving the control of its characteristic impedance. | 2008-12-11 |
20080303605 | RESISTANCE ADJUSTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A resistance adjusting circuit including a semiconductor integrated circuit includes a reference voltage generating circuit which generates a reference voltage corresponding to a resistance of an external resistor element connected to the semiconductor integrated circuit, a comparison voltage generating circuit which comprises a replica resistor circuit whose resistance is adjusted according to a resistance control signal and generates a comparison voltage corresponding to a resistance of the replica resistor circuit, a main body resistor circuit which has substantially the same configuration as that of the replica resistor circuit and whose resistance is adjusted according to the resistance control signal, and a control signal generating circuit which receives the reference and comparison voltages and converts the voltages to frequency signals corresponding to the voltages, integrates the frequency signals to produce integration data of the frequency signals, and generates the resistance control signal based upon a difference between the integration data. | 2008-12-11 |
20080303606 | Miniaturized Wide-Band Baluns for RF Applications - A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between secondhand third portions of the third coil. | 2008-12-11 |
20080303607 | BALANCED FILTER DEVICE - A balanced filter suitable for a reduction of the filter size. The balanced filter comprises strip-line resonators (SL | 2008-12-11 |
20080303608 | Flexible Microwave Transmission Line - A power amplifier (power amplifier) having multiple solid state sub-amplifiers connected in parallel between the power amplifier input and the power amplifier output are described. The signal input to the power amplifier is provided to an RF splitter connected between the power amplifier input connector and the input of each of the sub-amplifiers. The RF splitter splits the input power from the signal input and provides the power to the sub-amplifier inputs through input electrical paths. The input electrical paths from the power amplifier input to the sub-amplifiers are substantially physically identical. Each of the sub-amplifiers drive an input of an RF combiner connected between the outputs of the sub-amplifiers and the output of the power amplifier. The RF combiner combines the output power from each of the sub-amplifiers through output electrical paths, and provides the combined power to the power amplifier output. The output electrical paths from the sub-amplifiers to the power amplifier output are substantially physically identical. | 2008-12-11 |
20080303609 | POWER LINE COMMUNICATION SYSTEM AND CAPACITIVE SIGNAL COUPLING UNIT - In power line communications using carrier waves of high frequencies in the MHz range such as 2 to 30 MHz, when a coaxial cable for performing transmission of signals and a power line are signal-coupled using a capacitive signal coupling unit, even if an impedance matching circuit is installed in the capacitive signal coupling unit, we have found that leakage current of levels that cannot be neglected from leakage noise considerations flows through the outer sheath of the coaxial cable that transmits the signals, and, accordingly, leaking electromagnetic waves induced by the leakage current flowing through the coaxial cable due to impedance mismatch between the power line and the capacitive signal coupling unit are reduced by an impedance member showing high impedances at high frequencies in the MHz range. | 2008-12-11 |
20080303610 | TUNED FILTERS WITH ENHANCED HIGH FREQUENCY RESPONSE - A tuned filter having enhanced high frequency response includes a circuit board having first and second opposed major surfaces and first and second opposing sides. The opposed major surfaces are substantially parallel to a single plane and are bisected by a longitudinal axis. The first and second opposing sides are substantially parallel to the longitudinal axis. An input terminal and an output terminal are connected to the single circuit board. A filter section is associated with the first major surface. At least two ground paths are associated with the second major surface. One of the ground paths extends along a portion of the first side, and another one of the ground paths extends along a portion of the second opposing side. An isolation region separates the at least two ground paths, and extends along the longitudinal axis. | 2008-12-11 |
20080303611 | Apparatus for Transferring Broadband, High-Frequency Signals - An apparatus for the transfer of broadband, high-frequency signals of a center wavelength (λ | 2008-12-11 |
20080303612 | WAVEGUIDE STRUCTURE - A waveguide structure comprises a first waveguide portion, a second waveguide portion and a third waveguide portion. The first, second and third waveguide portions are connected in a series; signals feed into the first waveguide portion and then propagate through the first, second and third waveguide portions in sequence; and the cross sections of the first to third waveguide portions descend in size. | 2008-12-11 |
20080303613 | Waveguide interface for millimeter wave and sub-millimeter wave applications - A waveguide interface for millimeter wave and sub-millimeter wave applications adapted to couple and uncouple abutting waveguide sections wherein said waveguide interface acts as both a mating surface and a precision alignment mechanism. The waveguide interface comprises a first member having a first waveguide defined therein, a second member having a second waveguide similar in cross-section to said first waveguide defined therein, a means for mating said first member and said second member comprising a centrally located precision mating surface through which propagates electromagnetic energy and additionally comprising at least one pair of diametrically opposed rotational alignment pins and holes located a specified distance from said centrally located precision-mating surface, and wherein said pins and holes are in mating relation of looser fitment than said centrally located precision mating surface. | 2008-12-11 |
20080303614 | Rotary Joint - A high frequency (HF) rotary joint including a rotor and a stator is disclosed. The rotor is connected to the stator by a high frequency connection via a λ/4 line. The rotor, moreover, is mounted in the stator utilizing at least one radial aircushion bearing and at least one axial aircushion bearing. The bearings prevent contact between the rotor and the stator. | 2008-12-11 |
20080303615 | Fault Interrupter and Operating Method - A fault interrupter and a method of operating a fault interrupter to reduce arcing time during fault interruption. Fault interrupter operation is delayed following detecting a peak current such that its operation occurs at a point of the current wave resulting in reduced arcing during fault isolation. | 2008-12-11 |
20080303616 | ELECTRO-MAGNETIC RELAY - The electromagnetic relay comprises a contact block which is structured to uniformly maintain the contact resistance between the terminals of two circuits. Fixed contacts are provided for each of the terminals of the two circuits and each of two sets of a pair of movable contacts in positions corresponding to these is supported by two both-end-supported movable springs. An insulation sheet and a press spring are overlapped over the two movable springs and disposed as a bridge. A pair of tongues ate formed on the press spring by a Z-character shaped cut and by an armature pressing their tips, the insulation sheet and press spring transforms to an upward concave shape, the two movable springs bend and are taken in inside while inclining and the movable contacts touch the fixed contacts while sliding (see FIG. | 2008-12-11 |
20080303617 | Device mounted contactor and method for reducing continuous charge distribution - Provided is a device mounted contactor and a method of reducing continuous charge distribution, especially in a vehicle. The contactor includes a housing, and a plurality of power terminals. The device may further include a conductance shield and support structure extending from the housing. Situated at least partially in the housing is a switch, which is capable of electrically coupling at least two of the plurality of power terminals. One or more electrically insulative covers may be provided. The contactor may also provide a fused accessory terminal, which is electrically coupled to one of the power terminals through a fuse. A method according to the present invention reduces continuous electrical charge distribution in an electrical circuit by mechanically attaching a first contactor power terminal to a battery terminal and electrically coupling a second contactor power terminal to a circuit, which may include a vehicle starter. | 2008-12-11 |
20080303618 | Multi-Position Magnetic Detents - Various embodiments for magnetic detent assemblies provide for detent devices with improved performance and manufacturability. In one embodiment, magnetic detent assemblies provide for custom detent positions and custom force profiles by including a pair of unitary magnetic components each having a special geometry. In an embodiment, the changing area of overlap (and hence magnetic flux) between the magnetic components can give rise to the custom detent positions and custom force profiles. In a specific embodiment, the magnetic components can comprise an N-point star shaped geometry, where the number and distribution of the start wings can be varied to define customized detent positions and the contour of the star wings can be varied to create customized force profiles. In other embodiments, devices such as laptop computers and docking stations for handheld electronic devices can implement multi-position detent hinges with the magnetic detent assemblies. | 2008-12-11 |
20080303619 | PROTECTION OF PERMANENT MAGNENTS IN A DC-INDUCTOR - A DC inductor comprising a core structure ( | 2008-12-11 |
20080303620 | DC Inductor - A DC inductor comprising a core structure ( | 2008-12-11 |
20080303621 | COMMON MODE CHOKE COIL - A common mode choke coil includes two laminated coil conductors, a first magnetic substrate arranged on one of the coil conductors, and a second magnetic substrate arranged on the other coil conductor. When it is assumed that a distance from a conductor center of the one coil conductor to the surface of the first magnetic substrate is designated as A, a distance from a conductor center of the other coil conductor to the surface of the second magnetic substrate is designated as B, and a distance from the conductor center of the one coil conductor to the conductor center of the other coil conductor is designated as C, C<(A+B)/2 is satisfied. Accordingly, because a difference in the distances between the magnetic substrates and the coil conductors becomes relatively small, a leakage inductance due to the difference in the distance decreases, and the cut-off frequency with respect to a differential mode signal can be increased. | 2008-12-11 |
20080303622 | SPIRAL INDUCTOR - There is provided a spiral inductor including an insulation board formed into a flat-plate shape; a conductive pattern having a spiral shape and formed at least one surface of the insulation board, wherein the conductive pattern varies in line width according to a distance from one end of the conductive pattern forming a spiral. | 2008-12-11 |
20080303623 | Inductor structure - An inductor structure comprising a substrate; a plurality of insulation layers on the substrate; a first spiral electric conductive coil positioned in the insulation layers to form an inductor having a first direction of magnetic field; a second spiral electric conductive coil positioned in the insulation layers to form an inductor having a second direction of magnetic field, in which, the two or more inductors are independently positioned in a same 3-D space and have a good integration. | 2008-12-11 |
20080303624 | INDUCTOR - An inductor includes a first magnetic substance core which has a middle leg, a first outer leg, a second outer leg, and a body portion interconnecting the middle leg, the first outer leg and the second outer leg, and a second magnetic substance core which is arranged to be opposed to the first magnetic substance core. A first conductor is arranged in a first space which is formed by the middle leg, the first outer leg, part of the body portion, and the second magnetic substance core. A second conductor is arranged in a second space which is formed by the middle leg, the second outer leg, part of the body portion, and the second magnetic substance core. The middle leg is formed with a region which is lower in height than the first outer leg, in the same direction as the longitudinal direction of the first outer leg. | 2008-12-11 |
20080303625 | PLUG WITH REPLACEABLE FUSE - A plug with a replaceable fuse is provided. The plug includes an outer housing, an inner core, a pair of prongs and a pair of conductive cords. The outer housing includes a fuse uninstall button opening and an inner core install opening. The inner core is installed into the outer housing through the inner core install opening, and the inner core includes a fuse socket and a fuse uninstall button. The fuse socket has an uninstall opening. When it is intended to replace the fuse, the fuse uninstall button is pressed from the fuse uninstall button opening, the fuse is ejected or pushed out of the fuse socket by one end of the fuse uninstall button extending to the uninstall opening. When the fuse uninstall button is not pressed, the fuse uninstall button restores to the original position, such that a new fuse is installed into the fuse socket. | 2008-12-11 |
20080303626 | Fuse For a Chip - In order to produce a cost-effective fuse ( | 2008-12-11 |
20080303627 | RESISTOR FOR MICROWAVE APPLICATIONS - A resistor assembly for use at microwave frequencies, has a substrate with first and second contacts or metalizations at either end of the substrate. A third contact or metallization is provided on one side of the substrate generally in the middle thereof. First and second resistors, as thin film resistors, are provided on the substrate extending between the first and second contacts and the third, central contact. A third resistor is provided on the other side of the substrate, connecting the first and second contacts, so as to form a delta configuration of three resistors. This then provides a resistor configuration that can be used to implement a three port Wilkinson splitter or combiner. | 2008-12-11 |
20080303628 | SCALABLE TWO-STAGE CLOS-NETWORKING SWITCH AND MODULE-FIRST MATCHING - A configuration scheme for IQC switches that hierarchizes the matching process reduces configuration complexity by performing routing first and port matching afterwards in a three-stage Clos-network switch. This scheme applies the reduction concept of Clos networks to the matching process. This, in turn, results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a three-stage switch. The switching performance of the proposed approach using weight-based and weightless selection schemes is high under uniform and non-uniform traffic. The number of stages of a Clos-network switch can be reduced to two. | 2008-12-11 |
20080303629 | VEHICLE-USE KEY, MAINTENANCE SUPPORT/MANAGEMENT SYSTEM OF VEHICLE, AND STOLEN VEHICLE CHECK SYSTEM - A vehicle-use key for storing and for acquisition of information on a vehicle. The vehicle-use key permits an individual to use the vehicle, to prevent the key from being taken away when the vehicle is stolen and for finding the stolen vehicle. A vehicle-use key is used for starting a vehicle, and is configured to include a radio communication part (RFID) which performs communication with an external communication device. By providing the radio communication part to the vehicle-use key which an owner of a vehicle carries with him/her, information (data) can be transmitted or received between the radio communication part and the reader/writer of a PC terminal installed in a dealer or the like by radio. Thus, vehicle history data, maintenance history data and the like on a vehicle associated with the vehicle-use key can be transmitted and received and stored when necessary. | 2008-12-11 |
20080303630 | DigiKey and DigiLock - The present invention discloses an improvement in conventional lock and key mechanical fastening devices. This complete electronic security system utilizes a radio standard and communications protocol such as bluetooth, asymmetric cryptography encryption algorithms for authentication, confidentiality and non-repudiation purposes such as GPG, and a magnetic lock mechanism. | 2008-12-11 |
20080303631 | Mass Storage Device With Locking Mechanism - Embodiments of a mass storage device having a locking mechanism are described. The mass storage device includes a wireless reader to receive identification data from a wireless transponder, and to determine if the identification data matches a pre-stored data. The mass storage device includes a first controller device to enable access to at least a portion of a mass storage unit when the wireless reader determines that the identification data matches the pre-stored data. In one embodiment, a method of locking a mass storage device is described. The method includes receiving first identification data from a first wireless transponder at a mass storage device and unlocking the mass storage device upon determining that the first identification data matches a first pre-stored data. | 2008-12-11 |
20080303632 | Shielding of portable consumer device - A portable consumer device is disclosed. An electromagnetic shield is provided in the portable consumer device that is capable of preventing communication between the portable consumer device and an interrogation device. The shield is movable between a distal position in which communication with the interrogation device is enabled and a proximate position in which the shield prevents the transmitting antenna from communicating with the interrogation device. | 2008-12-11 |
20080303633 | HIGH GAIN RFID TAG ANTENNAS - A non-pervasive modification to radio frequency identification (RFID) tag antennas is provided that can double the tag's reading range distance. Parasitic elements, such as a reflector and one or more directors, are added at appropriate separations to form a Yagi antenna. As a result, the antenna's gain is increased and consequently so is the RFID tag's reading range. The tag antenna's gain can be achieved without directly connecting to or modifying the existing RFID tag. However, since directionality is increased, multiple RFID tags can be attached to an object so that the tagged object can be read from multiple directions. | 2008-12-11 |
20080303634 | TIRE REVOLUTION DETECTING SYSTEM - A tire revolution detecting system includes an electric power generator ( | 2008-12-11 |
20080303635 | Rfid Series and Method for Constructing Location Management System Using Rfid Series - The present invention relates to RFID series and a method for constructing location management system using RFID series. The present invention relates to RFID series constituting an RFID system that can complete work with a little time and workforce without confusion, even when a plurality of RFID tags are required, by concurrently installing a plurality of RFID tags without the need of installing RFID tags one by one and simultaneously computing automatically ID of each RFID, and a method for constructing location management system using RFID series. | 2008-12-11 |
20080303636 | SECURE SYSTEM FOR TRACKING GOODS - A secure system for tracking goods loaded on a delivery vehicle having a driver's cab and at least one container, said driver's cab being provided with a first RFID transponder disposed on any wall of said cab, and each of the containers is provided with at least two RFID transponders, one of which is disposed on any wall of said container and the other of which is disposed on each of the delivery doors of said container, each of said RFID transponders being designed to co-operate with a RFID reader/interrogator integrated into a mobile telephone of the driver of the vehicle, said mobile telephone being in communication with a management server via a mobile communications network. | 2008-12-11 |
20080303637 | Updateable electronic-ink based display label device - An updateable electronic-ink based display label device for attachment to an object to be tracked. The device includes (i) an addressable display assembly including a layer of electronic ink, (ii) an antenna structure, (iii) an interface module, and (iv) a signal transceiver module. The signal transceiver module is responsive to electromagnetic data signals received from a remote communication module, and the addressable display assembly is responsive to output signals generated by the interface module, to display the determined graphical indicia. The antenna structure, the interface module, the signal transceiver module, and the antenna structure are arranged and stacked together to form the updateable electronic-ink based display label device. | 2008-12-11 |
20080303638 | Portable patient devices, systems, and methods for providing patient aid and preventing medical errors, for monitoring patient use of ingestible medications, and for preventing distribution of counterfeit drugs - A portable digital patient assistant includes an RFID reader, a central processing unit for processing signals received from the RFID reader, a memory for storing data, and an output operatively linked to the central processing unit for providing output information regarding use of medicinal drugs. Methods for using the portable digital patient assistant include use at the doctor's office, pharmacy, emergency medical vehicle, hospital, home, and use while taking medications to the verify authenticity thereof and prevent drug overdoses. Related methods and systems for manufacturing, packaging, and shipping medicinal drugs to prevent the distribution of counterfeit drugs are also provided. One of the methods includes the steps of preparing a predetermined amount of a specific type of drug for patient end-users; forming discrete individual doses of the specific type of drug; and associating a respective RFID tag with each of the discrete individual doses of the specific type of drug so that when the specific type of drug is distributed to the patient end-users, at least one RFID reader may be employed to read the RFID tags associated with each of the discrete individual doses to thereby verify the authenticity of the doses as they move through a distribution channel from a manufacture to the patient end-users. | 2008-12-11 |
20080303639 | System and Method Including Partial Pre-Programming of Rfid Data - A system and method for partially pre-programming RFID labels. Common data associated with items to which RFID labels are to be applied is pre-programmed into the labels. Item specific data is programmed by a RFID label programmer in the application process. | 2008-12-11 |
20080303640 | HYBRID SYSTEM OPTION KEY - Embodiments herein place a product and a programmable device within a shipping package, seal the shipping package, and program the programmable device by transmitting wireless signals to the programmable device, without opening the shipping package. Then, after the device is programmed, the shipping package can be shipped to the end user (consumer). The programmable device is adapted to be connected to the product after the product and the programmable device are removed from the shipping package by the end user to enable different features of the product, depending upon the wireless signals that were transmitted to the programmable device. | 2008-12-11 |
20080303641 | RFID DEVICE HAVING NONVOLATILE FERROELECTRIC MEMORY DEVICE - A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal. | 2008-12-11 |
20080303642 | Apparatus and Method for Remotely Obtaining and Evaluating Vehicular and Other Information - An apparatus and method for remotely obtaining and evaluating vehicular and other information is disclosed, where a field device can be used to wirelessly transmit information to a processor. The processor can compare the information against other information in a database. Based upon the results of the comparison, the results are evaluating by the processor using predetermined criteria and one or more of a plurality of different predetermined instructions are wirelessly transmitted to the field device. | 2008-12-11 |
20080303643 | INDIVIDUAL-IDENTIFYING COMMUNICATION SYSTEM AND PROGRAM EXECUTED IN INDIVIDUAL-IDENTIFYING COMMUNICATION SYSTEM - An individual-identifying communication system of the present invention comprises: plural light-emitting devices; an imaging device; a display device capable of displaying an image based on image data obtained by said imaging device; a selection device for selecting a predetermined area within the displayed image; a storage device storing plural identification information data for specifying a mobile terminal to communicate with, each of the identification information data being associated with a unique data indicating a lighting pattern of each light-emitting device; an acquisition device acquiring acquisition lighting pattern data from the image data from the imaging device; a determination device determining the unique data corresponding to the acquisition lighting pattern data, based on the acquisition lighting pattern data acquired from selection area image data and plural unique data; and a communication device communicating with a mobile terminal assigned with identification information data corresponding to the determined unique data. | 2008-12-11 |
20080303644 | Sounder Assembly for a personal alert safety system - A sounder assembly is provided for a personal alert safety system (PASS). The sounder assembly includes a housing and a piezoelectric assembly compressively held in the housing such that a sound chamber is defined by the housing and the piezoelectric assembly. The housing radially expands and contracts relative to the piezoelectric assembly based on temperature changes. | 2008-12-11 |
20080303645 | Braille Support - Methods and apparatuses to provide improved Braille support are described herein. A connection to a Braille device is received, and a Braille caption panel that includes a Braille code is displayed to simulate an output to the Braille device. The Braille caption panel can include a text translated to the Braille code. The Braille caption panel can include a control element. An accessibility service can be automatically launched to provide the output to the Braille device. | 2008-12-11 |
20080303646 | Tactile Feedback Device for Use with a Force-Based Input Device - A tactile device comprising a tactile device and a feedback mechanism operable with a sensing surface to receive a force input from a user and transfer that force input to a force sensing element. The tactile device is configured to allow the user to touch the tactile device and register an input force with the force sensing element. The tactile device is also operable with the feedback mechanism to provide feedback to the user that the force input from the user has been registered with the force sensing element. | 2008-12-11 |
20080303647 | Accessory for a locking assembly - A device for use with an anti-theft locking assembly which comprises an enclosure, a noise emitter mounted within the enclosure, a battery, and a control circuit, an actuator extending externally of the enclosure and being designed to be plugged into a first actuator receptor on a towing vehicle or a second actuator receptor on the locking assembly, the noise emitter being activated when the actuator is unplugged from one of the receptors. The device will strongly remind the user that the anti-theft locking device is to be connected. | 2008-12-11 |