50th week of 2009 patent applcation highlights part 21 |
Patent application number | Title | Published |
20090302814 | SYSTEM AND METHOD FOR CONTROLLING A CONVERTER - A system and method for controlling a converter. One embodiment provides the cyclic actuation of a first switching element, used for applying an input voltage to an inductive storage element. A second switching element is used as a first rectifier element in a rectifier arrangement, in a step-up converter. An actuating circuit is provided for the first and second switching elements. | 2009-12-10 |
20090302815 | VOLTAGE REGULATOR SYSTEM - The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator having an output and a number of stages coupled in parallel to the output of the voltage regulator. Each stage includes a source follower circuit, and a sample and hold circuit coupled in series between the output of the voltage regulator and an input of the source follower circuit. | 2009-12-10 |
20090302816 | SWITCHING POWER SUPPLY AND SEMICONDUCTOR DEVICE USED FOR THE SAME - According to the present invention, it is possible to prevent an overcurrent from passing through a switching element | 2009-12-10 |
20090302817 | DC/DC CONVERTER CONTROL CIRCUIT AND DC/DC CONVERTER CONTROL METHOD - A DC-DC converter has an error amplifier, a first control unit and an oscillator. The error amplifier amplifies an error voltage between an output voltage and a set voltage, the output voltage being outputted from an inductance element by feeding an input voltage to an inductance element in a predetermined cycle. The first control unit: controls the output voltage to a set voltage by causing a switching operation of a switch element in response to an output of the error amplifier, the switch element forming a path for input voltage feed to the inductance. The oscillator generates a periodical signal at the time of switching the switch element. The oscillator handles an oscillation cycle as a short cycle in comparison to any prior cycles, in response to a drop in the output voltage from the set voltage by an amount equivalent to a first voltage value or more. | 2009-12-10 |
20090302818 | Power Supply Device and Control Method of the Same - It is determined that a periodic zero current stagnation state is reached to correct a voltage command of a smoothing capacitor downward by a predetermined voltage when a state where a current (reactor current) flowing through a coil in a dead time when switching elements are both off immediately after the switching element (upper arm) is turned off from on stagnates at a value of 0 occurs at switching periods of the switching elements. This can prevent a voltage of the smoothing capacitor from becoming unexpectedly higher than the voltage command in the current stagnation state, prevent the smoothing capacitor from being damaged by an overvoltage and prevent excessive torque from being output from motors. | 2009-12-10 |
20090302819 | Circuit for Preventing Reverse Current and Method thereof - A circuit for preventing a reverse current is applicable to a voltage converter including a high-side switch, a low-side switch, and an inductor. The high-side and low-side switches are coupled in series between two power lines. The inductor is coupled between an output terminal of the voltage converter and a connection node connecting the high-side and low-side switches. The reverse current flows from the output terminal of the voltage converter to the connection node. The circuit includes a first detection module and a threshold voltage adjusting module. The first detection module detects whether the reverse current occurs within a dead time when both the high-side and low-side switches are off. The voltage adjusting module adjusts a crossing voltage according to whether the reverse current is detected. The low-side switch is turned off when the voltage of the connection node exceeds the crossing voltage. | 2009-12-10 |
20090302820 | SWITCHING REGULATOR - In a switching regulator, a peak current value of an inductor current iL corresponding to a critical current is obtained by {(Vin−Vout)/Vin×Vout/L×Ts}, where Ts is the frequency of clock signals CLK constituting set pulses generated at predetermined timings by an oscillating circuit | 2009-12-10 |
20090302821 | CIRCUIT AND METHOD FOR OPERATING A CIRCUIT - A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section. | 2009-12-10 |
20090302822 | Voltage regulator - A voltage regulator comprises first and second bipolar transistors operating at different current densities; a resistor is connected between their bases across which ΔV | 2009-12-10 |
20090302823 | Voltage regulator circuit - A voltage regulator comprises first and second bipolar transistors operating at different current densities; a resistance is connected between their bases across which ΔV | 2009-12-10 |
20090302824 | REFERENCE VOLTAGE GENERATING APPARATUS AND METHOD - A method and apparatus for generating a low reference voltage having low power consumption characteristics is provided. A reference voltage generating apparatus includes a constant current source circuit which generates a reference current. A load circuit is connected to the constant current source circuit and generates a voltage which is proportional to the reference current. A current branch circuit removes a portion of temperature-invariant current components included in the reference current from a connection terminal of the constant current source circuit and the load circuit to a ground terminal through a current branch which is different from a current branch of the load circuit. | 2009-12-10 |
20090302825 | CURRENT SOURCE - A current source includes a node, a biasing circuit, a loading circuit and a current mirror. The node has a specified voltage. The biasing circuit biases the specified voltage to be a first reference voltage. The loading circuit provides an equivalent resistor across the node and a second reference voltage to generate a reference current. The loading circuit includes a resistor and a metal oxide semiconductor field effect transistor (MOSFET). The resistor has a first temperature coefficient. The transistor operating in a linear region is controlled by a control voltage to turn on and to form a transistor resistor coupled with the resistor in series. The transistor resistor has a second temperature coefficient, wherein a temperature coefficient of the equivalent resistor is relevant to the first and second temperature coefficients. The current mirror receives the reference current and provides a mirrored current of the reference current as the output current. | 2009-12-10 |
20090302826 | POWER SUPPLY INTEGRATED CIRCUIT WITH FEEDBACK CONTROL - A system and method for providing power control in a power management integrated circuit. A power management integrated circuit may comprise a communication interface module that receives power supply information from at least one electrical device external to the power management integrated circuit. The power supply information may, for example, comprise information related to a first electrical power. The power management integrated circuit may also comprise a power regulator module that determines a regulated power signal based, at least in part, on a portion of the power supply information. The regulated power signal may correspond to the first electrical power. For example, the regulated power signal may comprise the first electrical power or cause another circuit to output the first electrical power. The power management integrated circuit may then output the regulated power signal to at least one electrical device external to the power management integrated circuit. | 2009-12-10 |
20090302827 | Sensing circuit and method for a flyback converter - A flyback converter includes a transformer to convert an input voltage into an output voltage, a control circuit senses a primary current of the transformer to generate a current sense signal, and a sensing circuit is configured to sense a variation of the current sense signal between two time points for extracting the input voltage information therefrom. | 2009-12-10 |
20090302828 | OSCILLATING SYSTEM AND ASSISTANT MEASURING CIRCUIT FOR OSCILLATOR - An assistant measuring circuit for an oscillator is provided. The oscillator provides N oscillating signals with different phases. The assistant measuring circuit includes N buffers, N reflection-type modulators, and a controller. An ith buffer among the N buffers receives and further transmits an ith oscillating signal among the N oscillating signals. An ith modulator among the N modulators has an ith signal input end, an ith signal output end, and an ith signal control end. The ith oscillating signal is transmitted to the ith signal input end through the ith buffer. The signal output ends of the N modulators are all electrically connected to a measuring end. The controller is used for providing an ith control signal to the ith signal control end. | 2009-12-10 |
20090302829 | SPECTRUM ANALYZER SYSTEM AND SPECTRUM ANALYZE METHOD - Provided is a spectrum analysis system that measures a signal component at each frequency of an input signal, comprising a sampling section that samples the input signal at prescribed bandwidths to digitize the input signal, and outputs a resulting digital output signal; a converting section that converts the digital output signal from the sampling section into the signal component at each frequency of a unit bandwidth; and an output section that (i) outputs the digital output signal output by the sampling section when a frequency span, which is a frequency range in which the measurement result of the signal component at each frequency of the input signal is output, is greater than or equal to a predetermined reference bandwidth and (ii) outputs the signal component at each frequency converted by the converting section when the frequency span is less than the predetermined reference bandwidth. | 2009-12-10 |
20090302830 | INTEGRATED POWER DETECTOR WITH TEMPERATURE COMPENSATION FOR FULLY-CLOSED LOOP CONTROL - An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal. | 2009-12-10 |
20090302831 | METHOD FOR ENABLING MONITORING OF POWER CONSUMPTION - Power consumption at a site is monitored. An electrical load is connected to a power source by an electrical conductor. A fuel-less energy producing device is electrically connected to a junction along the electrical conductor. A current sensor is electromagnetically coupled to the electrical conductor at a sensing position between the power source and the junction to create a current sensor signal. Sensed current and voltage signals are produced from the current sensor signal. A sensed phase relationship between the sensed signals is determined and compared to a baseline phase relationship to determine the direction of current flow through the conductor. A power source signal, based on the current flowing through the conductor at the sensing position, is created. With some examples a Rogowski type differential current sensor is used. In some examples a single current sensor is used. | 2009-12-10 |
20090302832 | MEASURING SYSTEM FOR DETECTING A ROTARY-LINEAR DISPLACEMENT AND CORRESPONDING ROTARY-LINEAR DRIVE - The invention relates to more accurate rotative and linear positional measurement for a rotary-linear drive. A measuring system comprising a linear sensor ( | 2009-12-10 |
20090302833 | MAGNETIC DETECTION APPARATUS - In a magnetic detection apparatus, a magnetic detection sensor generates a sensor output signal whose high level and low level have different potentials in accordance with the moving direction of a magnetic moving object, and a computer unit includes three comparator circuits and detects the output signal of the magnetic detection sensor with three levels of comparison threshold values, so that the moving direction of the magnetic moving object can be detected accurately without any delay. | 2009-12-10 |
20090302834 | Resonant Linearly Polarized Body Current Sensor - A linearly polarized eddy current sensor including a source antenna and a parasitic antenna coupled to the source antenna, serves as a high sensitivity tool for the measurement of the surface impedance of sheet goods without requiring contact with the sample. Sheet goods can have an anisotropic, frequency-dependent surface impedance that is sensitive to minor changes in configuration of the sample. Because the electric field induced by the sensor is linearly polarized, measurement of directionally dependent sheet impedance can be achieved. The measurement is performed with the resonant device operating in resonance mode whereby the immediate proximity of the material to be measured causes damping and shifting of the coupled loop resonance. The resonant frequency of the sensor can be tuned by making changes to its geometry. | 2009-12-10 |
20090302835 | APPARATUS AND METHOD FOR HOLDING A ROTATABLE EDDY-CURRENT MAGNETIC PROBE, AND FOR ROTATING THE PROBE AROUND A BOUNDARY - An RFEC excitation unit and sensor apparatus and method that facilitate detection of cracks or other anomalies within or under a surface and immediately next to an expected structure (such as a rivet) that would otherwise cause a signal change preventing detection of the cracks. In some embodiments, the apparatus includes actuators and control that move the apparatus and analyze sensed RFEC signals to determine the location of the rivet, and then to rotate (mechanically or electronically) the sensed signal and/or excitation signal to maintain a constant relationship to the edge of the rivet in order that signals from the rivet edge are suppressed and signals from the cracks are detected. In some embodiments, the excitation unit is maintained at the center of the rivet surface, and the sensor is moved around the rivet in a circle centered on the rivet. | 2009-12-10 |
20090302836 | DEVICE FOR NON-DESTRUCTIVE TESTING OF A COMPONENT BY ANALYZING DISTIBUTION OF A LEAKAGE MAGNETIC FIELD - A device for non-destructive control of a component analyzes distribution of a leakage magnetic field emitted by the component when it is subjected to an exciting magnetic field, includes means for generating an exciting magnetic field inside the component to be tested, and means for detecting and measuring the distribution of the magnetic field. The set of means is integrated in a flexible housing to form a device in the form of a flexible coating for being fixed on a region of the surface of the component to be tested. The disclosed embodiments are useful for non-destructive testing of aircraft components, but may also be used in all industrial sectors where testing the integrity of components is important, such as the automotive, railway, marine or nuclear industry. | 2009-12-10 |
20090302837 | NON-LINEAR MAGNETIC FIELD SENSORS AND CURRENT SENSORS - The invention provides a magnetic field sensor or current sensor which can exhibit a substantially linear relationship between the sensor signal and the logarithm of the magnetic field or current. The sensor may be used as a wide dynamic range sensor which can offer a constant relative sensitivity and a uniform SNR over several decades. The design of the sensor device may be implemented in discrete magnetic field sensors or current sensors as well as in integrated current sensors in ICs comprising MRAM modules. | 2009-12-10 |
20090302838 | MR method for selective excitation - A magnetic resonance method for using radio frequency pulses for spatially selective and frequency selective or multidimensionally spatially selective excitation of an ensemble of nuclear spins with an initial distribution of magnetization in a main magnetic field aligned along a z-axis, wherein a spin magnetization with a given target distribution of magnetization is generated, and for refocusing the spin magnetization, is characterized in that the radio frequency pulse is used as a sequence of sub-pulses of independent duration, courses of gradients and spatial and/or spectral resolution, comprising one or more large angle RF pulses with tip angles greater than or approximately equal to 15°, which generate a gross distribution of magnetization approximating the target distribution of magnetization or a desired modification of the distribution of magnetization with a mean deviation less than or approximately equal to 15°, wherein the actual effect of the LAPs on the distribution of spin magnetization before the radio frequency pulse is used is calculated by integration of the Bloch equations without small angle approximation, and one or more small angle RF pulses=SAPs with tip angles less than or approximately equal to 15° reducing the difference between the target distribution of magnetization and the gross distribution of magnetization caused by the LAPs. | 2009-12-10 |
20090302839 | COIL ELEMENT SELECTION DEVICE FOR SELECTING ELEMENTS OF A RECEIVER COIL ARRAY OF A MAGNETIC RESONANCE IMAGING DEVICE - The present invention provides a sensor selection device for selecting sensor elements of a magnetic resonance imaging device, the sensor selection device comprising a provider for providing a first characteristic property ( | 2009-12-10 |
20090302840 | METHOD AND APPARATUS FOR CONTRAST INFLOW DYNAMIC MR ANGIOGRAPHY - A system and method for MR imaging includes a computer programmed to determine first and second view-ordering sequences. The first and second view-ordering sequences comprise values corresponding to respective views of first and second k-space data sets, respectively, wherein the values corresponding to a central view of each the first and second k-space data sets are positioned such that acquisition of k-space data in each central view is acquired from a first and second anatomical region, respectively, as a contrast agent passes therethrough. The positions of the values corresponding to the central views of the first and second k-space data sets within the respective sequences are different. The computer is further programmed to acquire MR data according to the first and second view-ordering sequences over a series of cardiac cycles to fill data in the first and second k-space data sets, respectively. | 2009-12-10 |
20090302841 | Surface Coil Arrays for Simultaneous Reception and Transmission with a Volume Coil and Uses Thereof - This invention provides arrays of counter rotating current surface coils for simultaneous reception and transmission with a volume coil for improved signal-to-noise ratio and radio frequency field homogeneity for in particular high-field (4-8 T) imaging of deep body regions, such as central brain structures. | 2009-12-10 |
20090302842 | BIRADICAL POLARIZING AGENTS FOR DYNAMIC NUCLEAR POLARIZATION - The present invention provides methods for performing dynamic nuclear polarization using biradicals with a structure of formula (I) as described herein. In general, the methods involve (a) providing a frozen sample in a magnetic field, wherein the frozen sample includes a biradical of formula (I) and an analyte with at least one spin half nucleus; (b) polarizing the at least one spin half nucleus of the analyte by irradiating the frozen sample with radiation having a frequency that excites electron spin transitions in the biradical; (c) optionally melting the sample to produce a molten sample; and (d) detecting nuclear spin transitions in the at least one spin half nucleus of the analyte in the frozen or molten sample. The present invention also provides biradicals with a structure of formula (I) with the proviso that Q | 2009-12-10 |
20090302843 | SYSTEM FOR MEASURING A MAGNETIC RESONANCE SIGNAL BASED ON A HYBRID SUPERCONDUCTIVE-MAGNETORESISTIVE SENSOR - The system for measuring a magnetic resonance signal within a sample ( | 2009-12-10 |
20090302844 | Regenerative expansion apparatus, pulse tube cryogenic cooler, magnetic resonance imaging apparatus, nuclear magnetic resonance apparatus, superconducting quantum interference device flux meter, and magnetic shielding method of the regenerative expansion apparatus - A regenerative expansion apparatus includes a regenerative tube configured to regenerate cryogenic cooling at the time of expansion of a coolant gas; a cylinder in communication with a low temperature end of the regenerative tube, the cylinder being configured to generate the cryogenic cooling by repeating compression and expansion of the coolant gas via the regenerative tube; a magnetic cold storage material filling inside the regenerative tube, the magnetic cold storage material being made of a magnetic material, the magnetic cold storage material being configured to come in contact with the coolant gas so that the cryogenic cooling is regenerated; and a magnetic shield member surrounding the magnetic cold storage material; wherein the magnetic shield member has an electric resistivity equal to or less than 50 μΩcm at a normal temperature. | 2009-12-10 |
20090302845 | METHOD AND DEVICE FOR FIELD QUALITY TESTING OF A MAGNETIC RESONANCE ANTENNA - In a method and device for field quality testing of a magnetic resonance antenna arrangement of a magnetic resonance system composed of multiple antenna elements, a test signal is fed into the respective antenna elements by a transmission antenna and the test signal, or a noise signal that occurs with no signal fed to the respective antenna elements, is determined at a receiver unit for each of at least some of the individual antenna elements. The noise received noise signals and/or test signals are analyzed with regard to specific characteristic data and a quality state of the magnetic resonance antenna arrangement is determined based thereon. | 2009-12-10 |
20090302846 | RF-switched superconducting resonators and methods of switching thereof - A multimode resonator resonating at two or more frequencies is operated at cryogenic temperatures and composed of a superconducting material or a normal metal with a superconducting section serving as a RF superconducting switch. The multimode resonator is coupled to a NMR spectrometer and a RF switch power source, wherein its one frequency is selected to correspond to the operating frequency of the NMR spectrometer and at least a second frequency is tuned to a frequency of RF switch power source, unrelated to the spectrometer frequency, therefore power at this frequency does not perturb the operation of the spectrometer. When activated, the RF switch power source induces a current sufficient to approach or exceeds the critical current in one or more sections of the superconducting material of the multimode resonator, thereby increasing its resistance and reducing the Q factor of the multimode resonator. | 2009-12-10 |
20090302847 | MULTI-AXIAL ANTENNA AND METHOD FOR USE IN DOWNHOLE TOOLS - Embodiments of a multi-axial antenna system and system for measuring subsurface formations are generally described herein. Other embodiments may be described and claimed. In some embodiments, the multi-axial antenna system comprising at least two co-located coils wound around a torroidal-shaped bobbin. Each coil generates a magnetic field in a mutually orthogonal direction. Signals provided to the coils may be adjusted to simulate a tilted-coil antenna system. | 2009-12-10 |
20090302848 | Apparatus and method for logging - An apparatus for logging in a borehole comprises a longitudinal body. A pad is coupled to and radially extendable from the longitudinal body toward a wall of the borehole. The radially extendable pad comprises a sensor. The radially extendable pad is rotatable about a longitudinal axis by a predetermined angle. A method for logging a borehole comprises extending a longitudinal body into the borehole; disposing a sensor in a radially extendable pad; coupling the radially extendable pad to the longitudinal body such that the radially extendable pad is rotatable about a longitudinal axis by a predetermined angle; and extending the radially extendable and rotatable pad toward a wall of the borehole. | 2009-12-10 |
20090302849 | ELECTROMAGNETIC EXPLORATION - A system and method include receiving electromagnetic energy emanating from a target using a plurality of receivers, and generating a pseudo-source based at least in part on a location of one or more of the plurality of receivers and the received electromagnetic information. | 2009-12-10 |
20090302850 | Electromagnetic subterranean imaging instrument - The instrument utilizes at least one electromagnetic signal transmitter and at least one electromagnetic signal receiver with the receiver detecting a receiver signal responsive to the transmitter signal and indicative of subterranean details adjacent to the instrument. The instrument is attachable to a tow vehicle for transport and includes a GPS antenna and tags data gathered by the instrument with GPS position information. The instrument is formed- in modular sections which can be removably attached for collapsing into a smaller space and to allow for flexible configuration of the instrument in various different ways. A wheeled carriage is provided to carry the instrument over the ground. Antennas for the transmitter and receiver, as well as circuitry and cooling systems are all provided to supply the instrument with high resolution and a clear signal indicative of the position and characteristics of subterranean details of interest. | 2009-12-10 |
20090302851 | MODULAR GEOSTEERING TOOL ASSEMBLY - A retrievable tool for steering through an earth formation includes a first tool assembly and a tilted antenna attached to the first tool assembly. The tool also includes a second tool assembly attached to the first tool assembly and a tilted antenna attached to the second tool assembly. The first tool assembly attaches to the second tool assembly so that the antennas are tilted in predetermined directions. The tilted antennas are transmitter antennas or receiver antennas. Each tool assembly is a tubular cylinder with a longitudinal axis running the length of the cylinder, wherein the tubular cylinder has two ends, each end including a rotational attachment mechanism. The tool assemblies attach to each other through their rotational attachment mechanisms. The rotational attachment mechanism may be a screw-on mechanism, press-fit mechanism, or welded mechanism. | 2009-12-10 |
20090302852 | MEASURING CASING ATTENUATION COEFFICIENT FOR ELECTRO-MAGNETICS MEASUREMENTS - Methods and related systems are described for making an electromagnetic induction survey of a formation surrounding a cased section of a borehole. An electromagnetic transmitter and/or receiver are deployed into the cased section of the borehole. One or more additional devices are used to measure the properties of a conductive casing relating to conductivity, thickness and magnetic permeability. A casing coefficient is then calculated that can then be used for the processing of the deep-sensing induction measurements. | 2009-12-10 |
20090302853 | HIGH RESOLUTION MAGNETOTELLURIC METHOD FOR REMOVING STATIC FREQUENCY DOMAIN - A high resolution magnetotelluric method for removing a static frequency domain, comprising steps of: (1) installing multiple sampling devices at the surface of the area to be explored in a form of an array, adjacent observation points sharing a same electrode; (2) performing conventional processing on all observation results whereby obtaining conventional observation curves of the observation points; (3) for the time series data of the original observation value of the electric field along the same direction of all observation points, adding electric-filed components of two adjacent observation points, those of three adjacent observation points, . . . , and those of all points whereby obtaining electric fields of different polar distance, i.e. a sequence of electric field components of topology points and encrypted topology points; (4) using the sequence of the electric field components of the topology points sequence and the encrypted topology points sequence obtained above as an observation field value to perform power spectrum analysis and impedance tensor estimate, whereby obtaining a series of topological observation curves of a same record point; (5) drawing a resistance—variation of polar distance curve of a single frequency point of the record point; observing and analyzing a variation rule of resistivity, editing and deleting static interference resistance, whereby obtaining a resistivity value of the point at the frequency; and (6) repeating the previous step to complete edition of all frequency points of all record points, whereby obtaining observation results without the static frequency domain. | 2009-12-10 |
20090302854 | Apparatus for Formation Resistivity Imaging in Wells with Oil-Based Drilling Fluids - Sequential measurements are made using a two terminal resistivity imaging device wherein the measure electrodes are activated sequentially with the remaining electrodes in a floating mode. This eliminates the hardware requirements for focusing electrodes, prevents galvanic leakage between proximal electrodes and the effects of mutual coupling between circuits including proximal electrodes. | 2009-12-10 |
20090302855 | METHOD AND SYSTEM FOR CHARACTERIZING A BATTERY - Methods and systems are provided for characterizing a battery. A property of the battery is measured. A dynamic characteristic of the battery is determined from a second order linear dynamic model. | 2009-12-10 |
20090302856 | Plug-In Module for a Liquid or Gas Sensor - A plug-in module for a liquid- or gas-sensor comprised of a sensor module (SM) and a sensor module head (SMH), which can be releasably connected together, and which, when connected, enable data and energy transfer via a galvanically decoupled transfer section, wherein the sensor module head (SMH) includes an energy supply unit for operating the sensor module head (SMH) and the sensor module (SM), as well as a data memory (MEM), in order to store sensor data received from the sensor module (SM). | 2009-12-10 |
20090302857 | Hydrogen Gas Sensor - The object of the present invention is to provide a hydrogen gas sensor that may suffer less influences from the environmental space as well as exercise less influence to the environmental space. The hydrogen gas sensor | 2009-12-10 |
20090302858 | Trailer signal converter - A signal converter and method of converting a signal are provided. The converter includes a power supply, microcontroller and current sensor. The microcontroller is connected to a power supply and is configured to receive inputs from a vehicle and output signals to loads of a second vehicle. The sensor is connected to the microcontroller to monitor current flow at the loads. The output channels are configured to stagger activity on the output signals. The microcontroller reduces the duty cycle of the output signals if the current flow rises above a first threshold and resumes the output signal to full strength once the current flow falls below a second threshold. The method includes receiving an input signal, sending an output signal, measuring current flow, measuring temperature, reducing the power of the output signal, and restoring the output signal. | 2009-12-10 |
20090302859 | METHOD FOR TESTING A PASSIVE INFRARED SENSOR - The method for testing a passive infrared sensor, the sensor comprising a housing in which an infrared sensor element with two terminal pins and a circuitry connected to the terminal pins of the infrared sensor element are arranged, the method comprises the steps of repeatedly generating and applying individual known electric charges to one of the terminal pins ( | 2009-12-10 |
20090302860 | OPERATING CHARACTERISTIC MEASUREMENT DEVICE AND METHODS THEREOF - A device includes an integrated circuit device having a sensor to measure an operating characteristic of the device. The sensor provides information based on the measured operating characteristic to a trigger module. In response to the information indicating the measured operating characteristic meets a threshold associated with a device failure, the trigger module provides an indication to a storage element, which stores information indicating the threshold has been met. In the event of a failure of the integrated circuit device, the storage element can be accessed by a device analyzer to retrieve the stored information to determine the cause of the device failure. | 2009-12-10 |
20090302861 | CIRCUIT TEST APPARATUS - A circuit testing apparatus for testing a device under test is disclosed. The device under test includes a first terminal end and second terminal end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines whether the device under test has passed the test according to the first and second output signals. | 2009-12-10 |
20090302862 | METHOD AND SYSTEM FOR MONITORING PARTIAL DISCHARGE WITHIN AN ELECTRIC GENERATOR - Electrical generators used for power generation typically operate at high voltage. The High operating voltage results in a severe electrical stress environment for the generator conductor insulation system. The high electrical stress cal lead to a phenomena such as corona, partial discharge and arcing that can cause damage to the insulation and conductors. Disclosed is a novel method and system of detecting partial discharge activity within an electric generator. The method employs at least two Rogowski loops non-contactingly surrounding individual iso-phase bus conductors, where the loops are wired in differential mode to detect fast moving electrical pulses indicative of partial discharge. | 2009-12-10 |
20090302863 | Device for Simulating the Symmetrical and Asymmetrical Impedance of an Asynchronous Motor - The present invention relates to a device for simultaneous simulation of a symmetrical and an asymmetrical impedance of an asynchronous machine. The device has three subcircuits for simulating the three phases of the asynchronous machine. Each subcircuit preferably comprises a series connection of a main inductance, a leakage inductance and a resistor between the input terminal and the output terminal, which are connected in parallel to ground across a capacitor and a resistor in each case. A magnetic coupling is implemented or the effect of a magnetic coupling is simulated for the main inductances of the subcircuits. This device can be used to advantage instead of the asynchronous machine in calibration of EMC filters. | 2009-12-10 |
20090302864 | Method And Device For Indicating An Electric Discharge Inside A Bearing Of An Electric Drive System - The present invention relates to a method for indicating an electric discharge in a non-conducting medium ( | 2009-12-10 |
20090302865 | METHOD AND DEVICE FOR MEASURING THE THICKNESS OF A LAYER OF MATERIAL - Described herein is a method for measuring, via a microwave sensor, the thickness of a layer of first material, said method envisaging: acquiring at least one frequency response of the layer of first material via a microwave sensor; setting the microwave sensor on a plurality of specimens of second materials for different temperature values in such a way as to obtain reference data; calibrating the microwave sensor as a function of the electrical conductivity of the first material using the reference data; measuring the temperature of the layer of first material via a temperature sensor; determining measurement parameters from the frequency response; and processing the reference data with the measurement parameters to obtain a measurement of the thickness of the layer of first material. | 2009-12-10 |
20090302866 | ANALYTICAL SCANNING EVANESCENT MICROWAVE MICROSCOPE AND CONTROL STAGE - A scanning evanescent microwave microscope (SEMM) that uses near-field evanescent electromagnetic waves to probe sample properties is disclosed. The SEMM is capable of high resolution imaging and quantitative measurements of the electrical properties of the sample. The SEMM has the ability to map dielectric constant, loss tangent, conductivity, electrical impedance, and other electrical parameters of materials. Such properties are then used to provide distance control over a wide range, from to microns to nanometers, over dielectric and conductive samples for a scanned evanescent microwave probe, which enable quantitative non-contact and submicron spatial resolution topographic and electrical impedance profiling of dielectric, nonlinear dielectric and conductive materials. The invention also allows quantitative estimation of microwave impedance using signals obtained by the scanned evanescent microwave probe and quasistatic approximation modeling. The SEMM can be used to measure electrical properties of both dielectric and electrically conducting materials. | 2009-12-10 |
20090302867 | Method for Ascertaining and Monitoring Fill Level of a Medium in a Container - A method for ascertaining and monitoring the fill level of a medium in a container the method utilizes a fill-level measuring device, wherein, according to the technique of time-domain reflectometry, high-frequency measuring signals are guided via at least one measuring probe in the direction of the medium, reflected on at least one interface of the medium as wanted echo signals or on disturbance locations as disturbance echo signals, and received. A current echo curve is formed from a produced, reference echo signal, wanted echo signals and disturbance echo signals, wherein, at least from a first disturbance echo signal and the reference echo signal, which are caused in a measurement-inactive region of the fill-level measuring device, a base point is located in the current echo curve, and wherein the fill level is ascertained from the distance between the base point and the wanted echo signal formed in a measurement-active region of the fill-level measuring device. | 2009-12-10 |
20090302868 | Analysis and Compensation Circuit for an Inductive Displacement Sensor - A circuit arrangement for analysis and compensation of the signals for an inductive displacement sensor is provided. The circuit includes a first operating amplifier, a second operating amplifier and a coil for a displacement measurement, in parallel with the second operating amplifier output and the second operating amplifier first input and connected to a capacitance in series with the coil inductance and coil resistance to form an RLC series tuned circuit. In order to improve the accuracy of a measured resonance frequency, the circuit arrangement can be extended with a second coil for a temperature compensation, by connecting a first of the ends of the coil winding to a second end of the coil winding of the first coil and a second of the ends of the coil winding to the second input of the first operating amplifier. | 2009-12-10 |
20090302869 | PROBE WITH ELECTROSTATIC ACTUATION AND CAPACITIVE SENSOR - A supported probe device that has a probe tip and probe body, the probe body having a sample facing surface and an opposing surface. The probe tip and a first electrode are on the sample facing surface. A second electrode is present on the probe body opposing surface. A third electrode is spaced from the second electrode, so that the second electrode is between the third electrode and the probe body. A first DC voltage source is electrically coupled to the first electrode, as is a first sensing circuit. A second DC voltage source is electrically coupled to the second electrode, and an AC voltage source electrically coupled to the third electrode. The probe body may be cantilevered. | 2009-12-10 |
20090302870 | Soil moisture sensor with data transmitter - A sensor and method for sensing moisture content of a medium such as soil is disclosed. In an embodiment, the sensor includes a sensing circuit, a processing module, a register, and a communications interface for communicatively coupling the sensor to an external communications device. In use, the sensing circuit generates a sensed signal having a signal parameter value attributable to the moisture content of the medium. The processing module processes the signal parameter value to provide, at an output, a scaled data value. The register stores a sensor identifier for the sensor and the communications interface is capable of communicating the scaled data value and the sensor identifier to the external device. An irrigation control system is also disclosed. | 2009-12-10 |
20090302871 | METHOD AND APPARATUS FOR DETECTING CAPACITANCE USING A PLURALITY OF TIME DIVISION FREQUENCIES - Disclosed herein is a method for detecting capacitance including: allowing an oscillator to output a plurality of time division oscillation frequencies according to the capacitance detected by a capacitance detection plate; counting the plurality of time division oscillation frequencies during a predetermined time period; and offsetting increasing and decreasing of the oscillation frequencies due to noise such that a count value becomes uniform over the predetermined time period. Even when external noise is applied, distortion of the oscillation frequency due to the external noise is minimized and the oscillation frequency varies depending on only the capacitance of the capacitance detection plate. Accordingly, it is possible to prevent an error due to the noise at the time of the detection of the capacitance. | 2009-12-10 |
20090302872 | Electrochemical strip for use with a multi-input meter - Strips, particularly test strips and adapters for test strips, for use in meters for the electrochemical measurement of analyte in a sample material and in particular the glucose concentration of a sample of blood. The strips comprise a plurality of working connectors, for interfacing with the meter, coupled to one or more working electrodes. The strips are of particular use in adapting multi-input meters for single input use. | 2009-12-10 |
20090302873 | System for electrochemically measuring an analyte in a sample material - Strips, particularly test strips and adapters for test strips, for use in meters for the electrochemical measurement of analyte in a sample material and in particular the glucose concentration of a sample of blood. The strips comprise a plurality of working connectors, for interfacing with the meter, coupled to one or more working electrodes. The strips are of particular use in adapting multi-input meters for single input use. | 2009-12-10 |
20090302874 | METHOD AND APPARATUS FOR SIGNAL PROBE CONTACT WITH CIRCUIT BOARD VIAS - A method and apparatus for probing a circuit board, is provided. One implementation involves a signal probe including a tip having a plurality of strands of flexible conductive material surrounding the tip, the strands extending out from the tip to provide multiple points of contact with the rim of a via or a conductive barrel of the via when the tip is inserted into the via, the probe tip and probe strands being made of same conductive material; such that aligning the signal probe with the via for engaging the probe tip strands with the via, and inserting the tip into the via, causes bending and flexing of the strands for making contact with a conductor on a top rim of the barrel and inside an inner wall of the barrel. | 2009-12-10 |
20090302875 | CHIP TEST METHOD - A chip test method is disclosed and includes: loading chips on a chip tray and fastening a cover plate on the chip tray; loading the chip tray with the cover plate in a chip test device; aligning a probe card of the chip test device with a test unit of the chip tray; testing chips in the chip tray; sorting the passed chips from the failed chips | 2009-12-10 |
20090302876 | COMPONENT FOR TESTING DEVICE FOR ELECTRONIC COMPONENT AND TESTING METHOD OF THE ELECTRONIC COMPONENT - A component for a testing device for an electronic component includes a testing board; a projection electrode provided on a main surface of the testing board; a positioning part provided on the main surface of the testing board, the positioning part being configured to position the electronic component; and a pressing part configured to press the electronic component being positioned by the positioning part and make a lead part of the electronic component come in contact with the projection electrode so that the lead part is elastically deformed and made come in contact with the projection electrode. | 2009-12-10 |
20090302877 | Reduced Ground Spring Probe Array and Method for Controlling Signal Spring Probe Impedance - A reduced ground spring probe array and a method for controlling the impedance of the signal spring probes in the reduced ground spring probe array. Signal spring probes are positioned in a row-column format across the surface of the spring probe tower. Ground spring probes are positioned in a row/alternating-column format across the surface of the spring probe tower such that one ground probe is positioned between two or more signal probes. In doing so, a void space exists for every other ground probe column such that one or more signal lines may be routed within the void space or the array may be compressed to establish a smaller overall spring probe tower footprint. | 2009-12-10 |
20090302878 | Test Contact System For Testing Integrated Circuits With Packages Having An Array Of Signal and Power Contacts - A test fixture ( | 2009-12-10 |
20090302879 | SEMICONDUCTOR DEVICE - When a stop condition is satisfied, a stop condition determination circuit ( | 2009-12-10 |
20090302880 | Wide Area Soft Defect Localization - Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions. | 2009-12-10 |
20090302881 | Internal Memory for Transistor Outline Packages - A transistor outline (TO) package includes a housing having a window and a substrate. Circuitry is coupled to the substrate within the housing. The circuitry comprises a laser diode and memory configured to store information related to the TO package. Electrical connectors are coupled to the substrate at the opposite side to the circuitry. At least one of the electrical connectors is electrically connected to the memory. A disclosed method includes assembling a TO package, testing the TO package, storing results of the testing in memory, and making the information stored in the memory, including the results of the testing, available to a device external to the TO package. The TO package includes a laser diode and memory configured to store information related to the TO package. | 2009-12-10 |
20090302882 | Device forming a logic gate for minimizing the differences in electrical of electro-magnetic behavior in an intergrated circuit manipulating a secret - The invention relates to a logic gate whose consumption is independent from its input data and its logic state. To this end, the device uses logic means forming switches ( | 2009-12-10 |
20090302883 | Device forming a logic gate for detecting a logic error - The invention relates to a device for forming an electric circuit comprising logic means ( | 2009-12-10 |
20090302884 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND COUNTERMEASURE METHOD AGAINST NBTI DEGRADATION - A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit. | 2009-12-10 |
20090302885 | TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING - A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node. | 2009-12-10 |
20090302886 | PROGRAMMABLE DEVICE - A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode. | 2009-12-10 |
20090302887 | APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEVICES AND ASSOCIATED METHODS - A programmable logic device (PLD) includes a driver circuit, a configuration memory, and a control circuit. The configuration memory stores driver strength information for the driver circuit. The control circuit uses the driver strength information stored in the configuration circuit to control the driver strength of the driver. | 2009-12-10 |
20090302888 | INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER - Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuits elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade. | 2009-12-10 |
20090302889 | INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK - Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector. | 2009-12-10 |
20090302890 | TRANSLATOR CIRCUIT HAVING INTERNAL POSITIVE FEEDBACK - An integrated circuit ( | 2009-12-10 |
20090302891 | OUTPUT DRIVER - There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal. | 2009-12-10 |
20090302892 | Method and Apparatus for Selecting an Operating Mode Based on a Determination of the Availability of Internal Clock Signals - A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2009-12-10 |
20090302893 | High Speed "Pseudo" Current Mode Logic (CML) Integrated Circuit Memory Latch - “Negative And” (NAND) logic gate metal oxide semiconductor field effect transistor (MOSFET) switch(es) are incorporated in the first stage of a “pseudo” current mode logic (CML) latch to provide a low-resistance (or high-resistance) circuit path to the output depending on the input voltage. These switch(es) are also used to deactivate (or “switch-off”) the first stage of the circuit during the second half of a timing clock cycle, so as to permit the first stage to be activated (or “switched-on”) only during the first half of a clock cycle. “Cross-coupled” inverter(s) are also used in the second stage of the circuit to provide acceptable “rail-to-rail” output voltage differential “swing” using less current. In addition, the second stage also has MOSFET switch(es) which activate (or “switch-on”) only during the second half of a timing clock cycle and are deactivated (or “switched-off”) during the first half of a clock cycle, which (in combination with operation of the first stage circuit) requires use of less current and thus reduces power consumption. | 2009-12-10 |
20090302894 | DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC - A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation. | 2009-12-10 |
20090302895 | CONSTANT OUTPUT COMMON MODE VOLTAGE OF A PRE-AMPLIFIER CIRCUIT - A method, apparatus and system of constant output common mode voltage of a pre-amplifier circuit are disclosed. In one embodiment, a system includes a first circuit, a comparator circuit coupled with an output of the first circuit, a pre-amplifier circuit of the comparator circuit, a tracking circuit coupled with a common output location of the pre-amplifier circuit to provide (e.g., source/sink) an additional current to the common output location of the pre-amplifier circuit using an alternate current path in the tracking circuit when an input common mode of the pre-amplifier circuit is beyond a saturation range, and a second circuit of the comparator circuit coupled with the pre-amplifier circuit. A scaled version of a pair of input transistors of a pre-amplifier circuit of the tracking circuit may be created using a scaling factor (‘N’). | 2009-12-10 |
20090302896 | SIGNAL CONDITIONING CIRCUIT WITH A SHARED OSCILLATOR - A circuit for signal conditioning including a first stage with a digital/analog converter, a second stage with an I/Q-modulator, and at least one third stage with a mixer. Instead of a multiplicity of independent oscillators, a shared oscillator is provided for the first, second, and third stages, from an output signal of which a respective oscillator signal and clock-pulse signal for each stage of the first, second, and third stages is derived. The oscillator signal and respective clock-pulse signal of the oscillator are supplied via a frequency divider to at least one stage of the first, second, and third stages, or the oscillator signal of the oscillator is supplied via a frequency multiplier to at least one stage. Also, the oscillator signal of the oscillator is supplied as a reference signal to a frequency synthesizer of at least one stage of the first, second, and third stages. | 2009-12-10 |
20090302897 | Driver circuit having high reliability and performance and semiconductor memory device including the same - Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node. | 2009-12-10 |
20090302898 | MULTICHANNEL DRIVE CIRCUIT - The invention provides a multichannel drive circuit by which, even when there occurs a variation between channels in circuit characteristics of each channel including current source due to the semiconductor manufacturing process and the like, loads of each channel constituting a load array can be driven under conditions uniform between all the channels. The invention includes; an interchannel common connection line ( | 2009-12-10 |
20090302899 | DIFFERENTIAL INVERSE ALIASING DIGITAL TO ANALOG CONVERTER - This invention relates to a process for producing a pulsed sampled waveform comprising generating a baseband signal representing the integral of a desired output waveform; sampling and differentiating the baseband signal to produce frequency images of the baseband spectrum at multiples of the sampling rate; employing an analog bandpass filter to pass the spectral image centered at the desired up-conversion frequency band. This invention also relates to an apparatus for creating a high frequency output waveform signal comprising a means for generating a baseband signal representing the integral of a desired output waveform; a means for sampling the baseband signal; a means for generating a time delayed baseband signal by Δt; a means for inverting the delayed baseband signal; a means for summing the inverted the delayed baseband signal with the sampled baseband signal; a means for filtering to pass the high frequency signal. | 2009-12-10 |
20090302900 | FREQUENCY DIVIDING DEVICE - In a frequency dividing device, a 1/P frequency divider subjects an input clock signal to 1/P frequency division. A phase shifter shifts the phase of the 1/P frequency signal and outputs multiple different Q-phase signals. A switch controls phase shifting in accordance with a division ratio control signal, to switch the Q-phase signals from one to another. A 1/R frequency divider subjects the output from the switch to 1/R frequency division and outputs an Rth frequency clock signal. A ½ frequency divider subjects the Rth frequency clock signal to ½ frequency division and outputs a frequency divided clock signal. A division ratio setter receives a division ratio set signal and generates the division ratio control signal. As a division ratio, P×R×2−2×P/Q, P×R×2−P/Q, P×R×2, P×R×2+P/Q, and P×R×2+2×P/Q can be set. | 2009-12-10 |
20090302901 | Command decoder and command signal generating circuit - A command decoder generates a command signal based on first to fourth control signals in response to a second chip select signal generated by delaying a first chip select signal for a predetermined interval. | 2009-12-10 |
20090302902 | POWER UP SIGNAL GENERATION CIRCUIT AND METHOD FOR GENERATING POWER UP SIGNAL - A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal. | 2009-12-10 |
20090302903 | DRIVING APPARATUS, LIQUID CRYSTAL DISPLAY HAVING THE SAME AND DRIVING METHOD THEREOF - A driving apparatus resets driving circuits provided therein after an internal supply voltage reaches a sufficient voltage level. The driving apparatus includes a reset signal generator that resets the driving circuits when the internal supply voltage exceeds the external supply voltage in a rising period of the internal supply voltage. Accordingly, the driving circuits may be prevented from being reset before the internal supply voltage reaches the sufficient voltage level, thereby preventing an abnormal operation of the driving circuits. | 2009-12-10 |
20090302904 | Phase Frequency Detector Circuit for Implementing Low PLL Phase Noise and Low Phase Error - A method and Phase Frequency Detector (PFD) circuit for implementing low phase locked loop (PLL) phase noise and low phase error, and a design structure on which the subject circuit resides are provided. The PFD circuit includes a PFD latch receiving clock and reset signals, and PFD output driver circuit providing PFD output signals. The PFD latch is set by the clock and reset by the reset signal. An AND gate coupled to the PFD latch and the PFD output driver circuit includes differential inputs and outputs and applies the reset signal to the PFD latch. The PFD latch, AND gate and PFD output driver circuit are formed by current mode logic using bipolar transistors. An active loop filter generates a tuning voltage output. | 2009-12-10 |
20090302905 | METHOD AND APPARATUS FOR ON-CHIP PHASE ERROR MEASUREMENT TO DETERMINE JITTER IN PHASE-LOCKED LOOPS - An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change. | 2009-12-10 |
20090302906 | METHOD AND APPARATUS FOR ON-CHIP PHASE ERROR MEASUREMENT TO DETERMINE JITTER IN PHASE-LOCKED LOOPS - An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change. | 2009-12-10 |
20090302907 | CIRCUIT ARRANGEMENT FOR PRODUCING A DEFINED OUTPUT SIGNAL - A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD. | 2009-12-10 |
20090302908 | OSCILLATOR AND A TUNING METHOD OF A LOOP BANDWIDTH OF A PHASE-LOCKED-LOOP - There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal. | 2009-12-10 |
20090302909 | SEMICONDUCTOR DEVICE HAVING DELAY LOCKED LOOP AND METHOD FOR DRIVING THE SAME - A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal. | 2009-12-10 |
20090302910 | DELAY TIME MEASURING METHOD, DELAY TIME ADJUSTING METHOD, AND VARIABLE DELAY CIRCUIT - A variable delay circuit | 2009-12-10 |
20090302911 | FREQUENCY JITTER GENERATOR AND PWM CONTROLLER - A frequency jitter generator and a frequency jitter PWM controller are provided for overcoming the shortcoming that a conventional PWM controller reduces the electromagnetic interference issue by means of varying the operating frequency of the PWM controller based on an input voltage, while resulting in the uncertainty of the range of frequency jitter and the difficulty circuit design due to the effect of the input voltage and the load. The frequency jitter generator and PWM controller adjust the range of frequency jitter by using a signal within a fixed voltage range. The invention not only gets rid of the effect of the input voltage and the loading, but also simplifies the circuit design by fixing the range of frequency jitter no greater than a predetermined percentage regardless of the operating frequency of the PWM controller. | 2009-12-10 |
20090302912 | DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals. | 2009-12-10 |
20090302913 | CIRCUIT AND METHOD FOR INITIALIZING AN INTERNAL LOGIC UNIT IN A SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal. | 2009-12-10 |