49th week of 2016 patent applcation highlights part 52 |
Patent application number | Title | Published |
20160358761 | HIGH THERMAL CONDUCTIVITY WAFER SUPPORT PEDESTAL DEVICE | 2016-12-08 |
20160358762 | SEMICONDUCTOR MANUFACTURING SYSTEM AND SEMICONDUCTOR MANUFACTURING METHOD | 2016-12-08 |
20160358763 | Hermetically Sealed Magnetic Keeper Cathode | 2016-12-08 |
20160358764 | Quasi-Planar Multi-Reflecting Time-of-Flight Mass Spectrometer | 2016-12-08 |
20160358765 | ION SOURCE FILTER | 2016-12-08 |
20160358766 | REDUCING OVERFRAGMENTATION IN ULTRAVIOLET PHOTODISSOCIATION | 2016-12-08 |
20160358767 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM | 2016-12-08 |
20160358768 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | 2016-12-08 |
20160358769 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 2016-12-08 |
20160358770 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE | 2016-12-08 |
20160358771 | METHODS OF FORMING DIFFERENT SIZED PATTERNS | 2016-12-08 |
20160358772 | METHODS FOR SEMICONDUCTOR PASSIVATION BY NITRIDATION | 2016-12-08 |
20160358773 | METHOD FOR MAKING ENHANCED SEMICONDUCTOR STRUCTURES IN SINGLE WAFER PROCESSING CHAMBER WITH DESIRED UNIFORMITY CONTROL | 2016-12-08 |
20160358774 | SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING | 2016-12-08 |
20160358775 | SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL | 2016-12-08 |
20160358776 | 2-DIMENSIONAL PATTERNING EMPLOYING TONE INVERTED GRAPHOEPITAXY | 2016-12-08 |
20160358777 | RESIST UNDER LAYER FILM COMPOSITION AND PATTERNING PROCESS | 2016-12-08 |
20160358778 | METHODS OF FORMING PATTERNS USING PHOTORESISTS | 2016-12-08 |
20160358779 | MECHANISMS FOR SEMICONDUCTOR DEVICE STRUCTURE | 2016-12-08 |
20160358780 | SUBSTRATE TREATMENT APPARATUS AND SUBSTRATE TREATMENT METHOD | 2016-12-08 |
20160358781 | PROCESS CHAMBER | 2016-12-08 |
20160358782 | ATOMIC LAYER ETCHING OF GaN AND OTHER III-V MATERIALS | 2016-12-08 |
20160358783 | METHOD AND DEVICE FOR TEXTURING A SILICON SURFACE | 2016-12-08 |
20160358784 | PLASMA-ENHANCED ETCHING IN AN AUGMENTED PLASMA PROCESSING SYSTEM | 2016-12-08 |
20160358785 | METHOD FOR SELECTIVE UNDER-ETCHING OF POROUS SILICON | 2016-12-08 |
20160358786 | Techniques for Spin-on-Carbon Planarization | 2016-12-08 |
20160358787 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | 2016-12-08 |
20160358788 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED TRENCH DISTORTIONS | 2016-12-08 |
20160358789 | APPARATUS FOR DECREASING SUBSTRATE TEMPERATURE NON-UNIFORMITY | 2016-12-08 |
20160358790 | Barrier Chemical Mechanical Planarization Slurries Using Ceria-Coated Silica Abrasives | 2016-12-08 |
20160358791 | COPPER-CERAMIC BONDED BODY AND POWER MODULE SUBSTRATE | 2016-12-08 |
20160358792 | GAS SYSTEMS AND METHODS FOR CHAMBER PORTS | 2016-12-08 |
20160358793 | PLASMA PROCESSING APPARATUS AND METHOD, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE | 2016-12-08 |
20160358794 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD | 2016-12-08 |
20160358795 | METHODS OF PROTOTYPING AND MANUFACTURING WITH CLEANSPACE FABRICATORS | 2016-12-08 |
20160358796 | Cable drive robot mechanism for exchanging samples | 2016-12-08 |
20160358797 | Semiconductor Processing Boat Design with Pressure Sensor | 2016-12-08 |
20160358798 | FRONT OPENING WAFER CONTAINER WITH ROBOTIC FLANGE | 2016-12-08 |
20160358799 | PURGE DEVICE AND PURGE METHOD | 2016-12-08 |
20160358800 | CHAMBER APPARATUS AND PROCESSING SYSTEM | 2016-12-08 |
20160358801 | JOINED BODY MANUFACTURING METHOD AND JOINED BODY | 2016-12-08 |
20160358802 | BIPOLAR MOBILE ELECTROSTATIC CARRIERS FOR WAFER PROCESSING | 2016-12-08 |
20160358803 | TRANSPARENT ELECTROSTATIC CARRIER | 2016-12-08 |
20160358804 | GRADED IN-SITU CHARGE TRAPPING LAYERS TO ENABLE ELECTROSTATIC CHUCKING AND EXCELLENT PARTICLE PERFORMANCE FOR BORON-DOPED CARBON FILMS | 2016-12-08 |
20160358805 | METHOD OF MECHANICAL SEPARATION FOR A DOUBLE LAYER TRANSFER | 2016-12-08 |
20160358806 | APPARATUS OF SEPARATING FLEXIBLE SUBSTRATE FROM GLASS SUBSTRATE AND MANUFACTURING EQUIPMENT THEREOF | 2016-12-08 |
20160358807 | Method and Apparatus for Preventing the Deformation of a Substrate Supported at its Edge Area | 2016-12-08 |
20160358808 | HYBRID 200 MM/300 MM SEMICONDUCTOR PROCESSING APPARATUSES | 2016-12-08 |
20160358809 | SHUTTER DISK FOR PHYSICAL VAPOR DEPOSITION CHAMBER | 2016-12-08 |
20160358810 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | 2016-12-08 |
20160358811 | INTERCONNECT STRUCTURE | 2016-12-08 |
20160358812 | REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS | 2016-12-08 |
20160358813 | METHOD OF FORMING TRENCHES | 2016-12-08 |
20160358814 | METHOD OF USING A BARRIER-SEED TOOL FOR FORMING FINE PITCHED METAL INTERCONNECTS | 2016-12-08 |
20160358815 | RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS | 2016-12-08 |
20160358816 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE | 2016-12-08 |
20160358817 | Conductive Element Structure and Method | 2016-12-08 |
20160358818 | Dummy Structure for Chip-on-Wafer-on-Substrate | 2016-12-08 |
20160358819 | MECHANISMS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH FEATURE OPENING | 2016-12-08 |
20160358820 | VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION | 2016-12-08 |
20160358821 | THRU-SILICON-VIA STRUCTURES | 2016-12-08 |
20160358822 | Bipolar Junction Transistor Formed on Fin Structures | 2016-12-08 |
20160358823 | GERMANIUM DUAL-FIN FIELD EFFECT TRANSISTOR | 2016-12-08 |
20160358824 | MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS | 2016-12-08 |
20160358825 | N-WELL/P-WELL STRAP STRUCTURES | 2016-12-08 |
20160358826 | INTEGRATION OF HYBRID GERMANIUM AND GROUP III-V CONTACT EPILAYER IN CMOS | 2016-12-08 |
20160358827 | METHOD OF FORMING FIN-SHAPED STRUCTURE | 2016-12-08 |
20160358828 | Handle Substrate of Composite Substrate for Semiconductor, and Composite Substrate for Semiconductor | 2016-12-08 |
20160358829 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD | 2016-12-08 |
20160358830 | Digital Processing Equipment | 2016-12-08 |
20160358831 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES | 2016-12-08 |
20160358832 | CERAMIC PACKAGE AND MANUFACTURING METHOD THEREFOR | 2016-12-08 |
20160358833 | SEMICONDUCTOR APPARATUS, STACKED SEMICONDUCTOR APPARATUS, ENCAPSULATED STACKED-SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING THE SAME | 2016-12-08 |
20160358834 | SEMICONDUCTOR PACKAGE INCLUDING BARRIER MEMBERS AND METHOD OF MANUFACTURING THE SAME | 2016-12-08 |
20160358835 | METHODS FOR SEMICONDUCTOR PASSIVATION BY NITRIDATION AFTER OXIDE REMOVAL | 2016-12-08 |
20160358836 | CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER | 2016-12-08 |
20160358837 | PACKAGE MODULE, STACK STRUCTURE OF PACKAGE MODULE, AND FABRICATING METHODS THEREOF | 2016-12-08 |
20160358838 | Semiconductor Power Package and Method of Manufacturing the Same | 2016-12-08 |
20160358839 | COMPOSITES COMPRISED OF ALIGNED CARBON FIBERS IN CHAIN-ALIGNED POLYMER BINDER | 2016-12-08 |
20160358840 | CERAMIC CIRCUIT BOARD | 2016-12-08 |
20160358841 | PACKAGE INTEGRATED SYNTHETIC JET DEVICE | 2016-12-08 |
20160358842 | MICRO-HOSES FOR INTEGRATED CIRCUIT AND DEVICE LEVEL COOLING | 2016-12-08 |
20160358843 | SEMICONDUCTOR DEVICE INCLUDING A CLIP | 2016-12-08 |
20160358844 | FIELD-EFFECT TRANSISTOR STRUCTURE FOR PREVENTING FROM SHORTING | 2016-12-08 |
20160358845 | DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE | 2016-12-08 |
20160358846 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2016-12-08 |
20160358847 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | 2016-12-08 |
20160358848 | MICROELECTRONIC PACKAGE HAVING A PASSIVE MICROELECTRONIC DEVICE DISPOSED WITHIN A PACKAGE BODY | 2016-12-08 |
20160358849 | Flexible Interconnects, Systems, And Uses Thereof | 2016-12-08 |
20160358850 | SEMICONDUCTOR DEVICE INCLUDING LANDING PAD | 2016-12-08 |
20160358851 | INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS AND METHODS FOR FABRICATING THE SAME | 2016-12-08 |
20160358852 | ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH | 2016-12-08 |
20160358853 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | 2016-12-08 |
20160358854 | Etch Stop Layer in Integrated Circuits | 2016-12-08 |
20160358855 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME | 2016-12-08 |
20160358856 | SEMICONDUCTOR DEVICES | 2016-12-08 |
20160358857 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2016-12-08 |
20160358858 | ELECTRONIC PART EMBEDDED SUBSTRATE AND METHOD OF PRODUCING AN ELECTRONIC PART EMBEDDED SUBSTRATE | 2016-12-08 |
20160358859 | REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS | 2016-12-08 |
20160358860 | CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME | 2016-12-08 |