49th week of 2011 patent applcation highlights part 15 |
Patent application number | Title | Published |
20110297979 | PASSIVATION FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure. | 2011-12-08 |
20110297980 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a light emitting chip and a fluorescent material layer. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The fluorescent material layer is provided on the first major surface and has a larger planer size than the light emitting chip. | 2011-12-08 |
20110297981 | FLUORESCENT STRUCTURE AND METHOD FOR FORMING THE FLUORESCENT STRUCTURE AND LED PACKAGE USING THE SAME - A fluorescent structure for a light-emitting package includes a first fluorescent layer and a second fluorescent layer covering the first fluorescent layer. The first fluorescent layer includes first fluorescent strips, and defines first transparent regions between the first fluorescent strips. The second fluorescent layer includes second fluorescent strips, and defines second transparent regions between the second fluorescent strips. A method for forming the fluorescent structure and a light-emitting diode package using the fluorescent structure are also provided. | 2011-12-08 |
20110297982 | Optoelectronic Semiconductor Chip - A semiconductor chip is specified, comprising an active layer provided for emitting an electromagnetic radiation, and a two-dimensional arrangement of structural units, which is disposed downstream of the active layer in a main emission direction of the semiconductor chip. The structural units are arranged in an arbitrary statistical distribution. Such an arrangement of structural units makes it possible to realize a semiconductor chip having a directional emission characteristic. | 2011-12-08 |
20110297983 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a light emitting unit, first and second conductive members, an insulating layer, a sealing member, and an optical layer. The light emitting unit includes a semiconductor stacked body and first and second electrodes. The semiconductor stacked body includes first and second semiconductor layers and a light emitting layer, and has a major surface on a second semiconductor layer side. The first and second electrodes are connected to the first and second semiconductor layers on the major surface side, respectively. The first conductive member is connected to the first electrode and includes a first columnar portion covering a portion of the second semiconductor. The insulating layer is provided between the first columnar portion and the portion of the second semiconductor. The sealing member covers side surfaces of the conductive members. The optical layer is provided on the other major surface. | 2011-12-08 |
20110297984 | PHOTOELECTRICAL ELEMENT HAVING A THERMAL-ELECTRICAL STRUCTURE - A photoelectrical element having a thermal-electrical structure including: a photoelectrical transforming layer, two semiconductor layers formed on the two opposite sides of the photoelectrical transforming layer respectively, an electrically conductive structure formed on at least one of the semiconductor layer, and a thermal-electrical structure formed in the electrically conductive structure, wherein the thermal-electrical structure performs the thermal-electrical transformation to promote current spreading effect, or proceed electrical-thermal transformation to dissipate the heat from the photoelectrical transforming layer. | 2011-12-08 |
20110297985 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a light emitting section, a light transmitting section, a wavelength conversion section, a first conductive section, a second conductive section and a sealing section. The light emitting section includes a first major surface, a second major surface opposite from the first major surface, and a first electrode section and a second electrode section formed on the second major surface. The light transmitting section is provided on a side of the first major surface. The wavelength conversion section is provided over the light transmitting section. The wavelength conversion section is formed from a resin mixed with a phosphor, and hardness of the cured resin is set to exceed 10 in Shore D hardness. | 2011-12-08 |
20110297986 | LIGHT SOURCE APPARATUS USING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a light source apparatus includes a semiconductor light emitting device, a mounting substrate, first and second connection members. The semiconductor light emitting device includes a light emitting unit, first and second conductive members, a sealing member, and an optical layer. The mounting substrate includes a base body, first and second substrate electrodes. The connection member electrically connects the conductive member to the substrate electrode. The conductive member is electrically connected to the light emitting unit electrode and includes first and second columnar portions provided on the second major surface. The sealing member covers side surfaces of the first and the second conductive members. The optical layer is provided on the first major surface of the semiconductor stacked body and includes a wavelength conversion unit. A surface area of the second substrate electrode is not less than 100 times a cross-sectional area of the second columnar portion. | 2011-12-08 |
20110297987 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, an optical semiconductor device includes a light emitting layer, a transparent layer, a first metal post, a second metal post and a sealing layer. The light emitting layer includes a first and a second major surface, a first and a second electrode. The second major surface is a surface opposite to the first major surface, and the first electrode and second electrodes are formed on the second major surface. The transparent layer is provided on the first major surface. The first metal post is provided on the first electrode. The second metal post is provided on the second electrode. The sealing layer is provided on the second major surface. The sealing layer covers a side surface of the light emitting layer and seals the first and second metal posts while leaving end portions of the first and second metal posts exposed. | 2011-12-08 |
20110297988 | TRANSPARENT SUBSTRATE FOR PHOTONIC DEVICES - Transparent substrate ( | 2011-12-08 |
20110297989 | LIGHT EMITTING DEVICE - The light emitting device comprises a mounting substrate and an LED chip which comprises an n-type nitride semiconductor layer, a nitride light emission layer on the n-type nitride semiconductor layer, p-type nitride semiconductor layer on the nitride light emission layer, an anode electrode opposite of the nitride light emission layer from the p-type nitride semiconductor layer, and a cathode electrode on the n-type nitride semiconductor layer. The mounting substrate has a patterned conductor which is connected to the cathode electrode through a bump and also connected to the anode electrode through a bump. The LED chip further comprises one or more dielectric layer between the p-type nitride semiconductor layer and the anode electrode to have an arrangement which resembles an island. The p-type nitride semiconductor layer has a first region which is overlapped with the bump. The dielectric layer is not formed within the first region. | 2011-12-08 |
20110297990 | LIGHT EMITTING DEVICE AND DISPLAY - A light emitting device comprises: an LED chip having a quantum well structure and a light emitting layer made of a gallium nitride compound semiconductor; a first transparent material covering the LED chip; a second transparent material for protecting the LED chip and the first transparent material; and a phosphor for absorbing a part of the light from the LED chip and emitting a light having a wavelength different from the light from the LED chip; wherein the phosphor is included in second transparent material, and the light from the LED chip and the light from said phosphor are mixed to make a white light. | 2011-12-08 |
20110297991 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A wiring electrode is provided on a mount substrate. A light emitting element is provided on the wiring electrode to connect electrically with the wiring electrode and is configured to emit a blue to ultraviolet light. A reflective film is provided above the light emitting element to cover the light emitting element so that a space is interposed between the reflective film and the light emitting element. The reflective film is capable of transmitting the blue to ultraviolet light. A fluorescent material layer is provided above the light emitting element to cover the light emitting element so that the reflective film is located between the fluorescent material layer and the light emitting element. A light from the fluorescent material layer is reflected by the reflective film. | 2011-12-08 |
20110297992 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device that minimizes reflection or absorption of emitted light, maximizes luminous efficiency with the maximum light emitting area, enables uniform current spreading with a small area electrode, and enables mass production with high reliability and high quality. A semiconductor light emitting device according to an aspect of the invention includes first and second conductivity type semiconductor layers, an active layer formed therebetween, first electrode layer, and a second electrode part electrically connecting the semiconductor layers. The second electrode part includes an electrode pad unit, an electrode extending unit, and an electrode connecting unit connecting the electrode pad unit and electrode extending unit. | 2011-12-08 |
20110297993 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer. | 2011-12-08 |
20110297994 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a plurality of semiconductor layers, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar and a resin layer, and is mounted in a bent state on a curved surface. The plurality of semiconductor layers includes a first main surface, a second main surface opposite to the first main surface, and a light emitting layer, the plurality of semiconductor layers being separated from one another. A material is provided between the plurality of the semiconductor layers separated from one another. The member has a higher flexibility than the semiconductor layers being. | 2011-12-08 |
20110297995 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE MANUFACTURED BY THE SAME - In one embodiment, a method for manufacturing a light-emitting device is disclosed. The method can include removing a substrate from a semiconductor layer. The semiconductor layer is provided on a first main surface of the substrate. The semiconductor layer includes a light-emitting layer. At least a top surface and side surfaces of the semiconductor layer are covered with a first insulating film. A first electrode portion and a second electrode portion electrically continuous to the semiconductor layer are provided. The first insulating film is covered with a second insulating film. The removing is performed by irradiating the semiconductor layer with laser light from a side of a second main surface of the substrate. The second main surface is opposite to the first main surface. Each of band-gap energy of the second insulating film and band-gap energy of the semiconductor layer are smaller than energy of the laser light. | 2011-12-08 |
20110297996 | Electronic device and method of manufacturing the same - An electronic device comprises a functional stack ( | 2011-12-08 |
20110297997 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and a second insulating layer. The semiconductor layer includes a first major surface, a second major surface opposite to the first major surface, and a light emitting layer. The first electrode is provided on a region including the light emitting layer on the second major surface. The second electrode is provided on the second major surface and interposed in the first electrode in a planar view. | 2011-12-08 |
20110297998 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar and a second insulating layer. The semiconductor layer includes a first major surface, a second major surface opposite to the first major surface and a light emitting layer. An edge of a part of the first interconnect layer is exposed laterally from the first insulating layer and the second insulating layer. | 2011-12-08 |
20110297999 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor component is provided, having a connection carrier ( | 2011-12-08 |
20110298000 | CHIP PACKAGE - According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer. | 2011-12-08 |
20110298001 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE MANUFACTURED BY THE SAME - In one embodiment, a method for manufacturing a light-emitting device is disclosed. The method can include removing a substrate from a semiconductor layer. The semiconductor layer is provided on a first main surface of the substrate. The semiconductor layer includes a light-emitting layer. At least a top surface and side surfaces of the semiconductor layer are covered with a first insulating film. A first electrode portion and a second electrode portion electrically continuous to the semiconductor layer are provided. The first insulating film is covered with a second insulating film. The removing is performed by irradiating the semiconductor layer with laser light from a side of a second main surface of the substrate. The second main surface is opposite to the first main surface. The first insulating film is made of silicon nitride. The second insulating film is made of polyimide. | 2011-12-08 |
20110298002 | LIGHT-EMITTING DIODE, LIGHT-EMITTING DIODE LAMP, METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE - The object of the invention is to provide a light-emitting diode that is excellent in terms of thermal radiation properties and is capable of suppressing cracks in the substrate during joining and emitting light with high luminance by applying a high voltage, a light-emitting diode lamp, and a method of manufacturing a light-emitting diode. The above object is achieved by using a light-emitting diode ( | 2011-12-08 |
20110298003 | EPOXY RESIN COMPOSITION FOR OPTICAL USE, OPTICAL COMPONENT USING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE OBTAINED USING THE SAME - The present invention relates to an epoxy resin composition for optical use including the following ingredients (A) to (C): (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler including (c1) an inorganic filler having a refractive index larger than a refractive index of a cured product obtained from the ingredients of the epoxy resin composition excluding the (C) inorganic filler and (c2) an inorganic filler having a refractive index smaller than the refractive index of the cured product obtained from the ingredients of the epoxy resin composition excluding the (C) inorganic filler. | 2011-12-08 |
20110298004 | ENCAPSULATING SHEET FOR OPTICAL SEMICONDUCTOR - The present invention relates to an encapsulating sheet for an optical semiconductor, including: a phosphor-containing layer containing a phosphor; and an encapsulating resin layer containing an encapsulating resin and being laminated on the phosphor-containing layer, in which, on the laminated surface therebetween, an edge of the phosphor-containing layer protrudes from an edge of the encapsulating resin layer, and a protruded length of the phosphor-containing layer is from 1 to 10 times a thickness of the encapsulating resin layer. | 2011-12-08 |
20110298005 | METHOD FOR FABRICATING AN N-TYPE SEMICONDUCTOR MATERIAL USING SILANE AS A PRECURSOR - A method for fabricating a group III-V n-type nitride structure comprises fabricating a growth Si substrate and then depositing a group III-V n-type layer above the Si substrate using silane gas (SiH | 2011-12-08 |
20110298006 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor light emitting device includes a nitride semiconductor layer including a first cladding layer, an active layer, and a second cladding layer, and a current blocking layer configured to selectively inject a current into the active layer. The second cladding layer has a stripe-shaped ridge portion. The current blocking layer is formed in regions on both sides of the ridge portion, and is made of zinc oxide having a crystalline structure. | 2011-12-08 |
20110298007 | SELECT DEVICES INCLUDING AN OPEN VOLUME, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FOR FORMING SAME - Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices. | 2011-12-08 |
20110298008 | SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions. | 2011-12-08 |
20110298009 | EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An object of the present invention is to provide an epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 Ω·cm. | 2011-12-08 |
20110298010 | Cell Library, Integrated Circuit, and Methods of Making Same - A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion. | 2011-12-08 |
20110298011 | Semiconductor Memory Device And System Having Stacked Semiconductor Layers - Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software. | 2011-12-08 |
20110298012 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. | 2011-12-08 |
20110298013 | Vertical Structure Semiconductor Memory Devices And Methods Of Manufacturing The Same - A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. | 2011-12-08 |
20110298014 | Cross-Point Memory Structures - Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction. | 2011-12-08 |
20110298015 | SENSING DEVICE - A sensing device includes: a semiconductor layer of a field effect semiconductor having upper and lower surfaces; a conductive layer formed on the lower surface of the semiconductor layer; and a sensor layer of an insulator formed on the upper surface of the semiconductor layer. The insulator is made from lanthanide-titanium oxide. | 2011-12-08 |
20110298016 | MOSFET having a JFET embedded as a body diode - A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. | 2011-12-08 |
20110298017 | REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT - A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap. | 2011-12-08 |
20110298018 | TRANSISTOR AND MANUFACTURING METHOD OF THE SAME - The invention provides a transistor, including: a substrate having a channel region; a source region and a drain region on two ends of the channel region of the substrate respectively; a gate high-K dielectric layer on a top surface of the substrate above the channel region between the source region and the drain region; an interfacial layer under the gate high-K dielectric layer, including a first portion near the source region and a second portion near the drain region, wherein an equivalent oxide thickness of the first portion is larger than that of the second portion. An asymmetric replacement metal gate forms an asymmetric interfacial layer, which is thin at the drain region side and thick at the source region side. At the thin drain region side, the short channel effect is significant and the asymmetric interfacial layer advantageously suppresses the short channel effect. At the thick source region side, the carrier mobility has a large influence on the device, and the asymmetric interfacial layer prevents the carrier mobility from decreasing. Further, the asymmetric replacement metal gate implements an asymmetric metal work function. | 2011-12-08 |
20110298019 | COMPACT FIELD EFFECT TRANSISTOR WITH COUNTER-ELECTRODE AND FABRICATION METHOD - An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact. | 2011-12-08 |
20110298020 | SEMICONDUCTOR DEVICE - A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal. | 2011-12-08 |
20110298021 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, includes: forming an insulating film containing silicon, oxygen and carbon on at least one of a first substrate and a second substrate; and bonding the first substrate and the second substrate together, with the insulating film interposed therebetween. There can be provided a method capable of manufacturing a semiconductor device having high element density, high performance and high reliability, with high yield. | 2011-12-08 |
20110298022 | MANUFACTURING METHOD FOR SOLID-STATE IMAGE PICKUP DEVICE, SOLID-STATE IMAGE PICKUP DEVICE AND IMAGE PICKUP APPARATUS - A solid-state image pickup device and method for manufacturing the same. The solid-state image pickup device includes a substrate, a first charge accumulation region formed within the substrate, a first impurity region formed within the substrate and located above the charge accumulation region, and a gate electrode disposed on a surface of the substrate which is closer to the first impurity region. Further, a portion of the first impurity region and the charge accumulation region extend underneath a portion of the gate electrode, and edges of the charge accumulation region and first impurity region which lie underneath the gate electrode are in registry with each other. | 2011-12-08 |
20110298023 | SOLID-STATE IMAGING DEVICE - According to the embodiments, a solid-state imaging device is provided, which includes a first electrode film, a first photoelectric conversion film, a first conductive film, a dielectric film, a second photoelectric conversion film, and a second conductive film. The first photoelectric conversion film covers the surface and the side of the first electrode film. The first conductive film covers the light receiving surface and the side of the first photoelectric conversion film. The dielectric film covers a portion corresponding to the side of the first photoelectric conversion film in the first conductive film. The second photoelectric conversion film covers a main portion of a portion corresponding to the light receiving surface of the first photoelectric conversion film in the first conductive film. The second conductive film covers the light receiving surface and the side of the second photoelectric conversion film. | 2011-12-08 |
20110298024 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THEREOF AS WELL AS DRIVING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area is formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area is formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area. | 2011-12-08 |
20110298025 | FINFET-COMPATIBLE METAL-INSULATOR-METAL CAPACITOR - At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer. | 2011-12-08 |
20110298026 | LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS - An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included. | 2011-12-08 |
20110298027 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased. | 2011-12-08 |
20110298028 | HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition. | 2011-12-08 |
20110298029 | SEMICONDUCTOR STORAGE DEVICE | 2011-12-08 |
20110298030 | SEMICONDUCTOR STORAGE DEVICE | 2011-12-08 |
20110298031 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 2011-12-08 |
20110298032 | ARRAY ARCHITECTURE FOR EMBEDDED FLASH MEMORY DEVICES - A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer. | 2011-12-08 |
20110298033 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a charge storage layer, a control gate. The charge storage layer is formed above a semiconductor substrate with first insulating film disposed therebetween. The control gate is formed above the charge storage layer with second insulating film disposed therebetween. The control gate includes a nickel silicide region. The side surface expands outwardly in at least a partial region thereof, and height of the control gate from a portion at which the side surface thereof starts to expand outwardly to a top of the control gate is greater than maximum width of the control gate in a region above the portion at which the side surface starts to expand outwardly. | 2011-12-08 |
20110298034 | MEMORY CELL - A non-volatile memory cell ( | 2011-12-08 |
20110298035 | MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors. | 2011-12-08 |
20110298036 | ISOLATION LAYER STRUCTURE, METHOD OF FORMING THE SAME AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME - An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein. | 2011-12-08 |
20110298037 | VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 2011-12-08 |
20110298038 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE - Provided are a three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include a gate structure on a substrate with the gate structure including a plurality of gate electrodes. Conductive lines are disposed between the gate structure and the substrate. A horizontal semiconductor pattern is disposed between the gate structure and the conductive line. And a vertical semiconductor pattern penetrating the gate structure is connected to the horizontal semiconductor pattern. | 2011-12-08 |
20110298039 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH CHARGE STORAGE LAYER IN MEMORY CELL - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7. | 2011-12-08 |
20110298040 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are disclosed. By forming a boron nitride film as a sealing film of a buried gate of a cell region from being oxidized, it is possible to improve refresh characteristics, to reduce the number of processes, and to reduce parasitic capacitance so as to improve the characteristics of the device. The semiconductor device includes a recess included in a semiconductor substrate, a gate buried over a bottom of the recess, and a boron nitride film included over the semiconductor substrate including the gate and the recess. | 2011-12-08 |
20110298041 | SINGLE-GATE FINFET AND FABRICATION METHOD THEREOF - A single-gate FinFET structure includes an active fin structure having two enlarged head portions and two respective tapered neck portions that connect the enlarged head portions with an underlying ultra-thin body. Two source/drain regions are doped in the two enlarged head portions respectively. An insulation region is interposed between the two source/drain regions. A trench isolation structure is disposed at one side of the tuning fork-shaped fin structure. A single-sided sidewall gate electrode is disposed on a vertical sidewall of the active fin structure opposite to the trench isolation structure. | 2011-12-08 |
20110298042 | POWER SEMICONDUCTOR DEVICE WITH TRENCH BOTTOM POLYSILICON AND FABRICATION METHOD THEREOF - A power semiconductor device comprising a base, a trench, a heavily doped polysilicon structure, a polysilicon gate, a gate dielectric layer, and a heavily doped region is provided. The trench is formed in the base. The heavily doped polysilicon structure is formed in the lower portion of the trench. At least a side surface of the heavily doped polysilicon structure touches the naked base. The polysilicon gate is located in the upper portion of the trench. The gate dielectric layer is interposed between the polysilicon gate and the heavily doped polysilicon structure. The dopants in the heavily doped polysilicon structure are diffused outward to form a heavily doped region. | 2011-12-08 |
20110298043 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 2011-12-08 |
20110298044 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity. | 2011-12-08 |
20110298045 | SELF-ALIGNED CONTACT FOR TRENCH MOSFET - The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased. | 2011-12-08 |
20110298046 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes active regions separated by a trench, a separation layer dividing the trench, and buried bit lines buried in the trench with the separation layer interposed between the buried bit lines. | 2011-12-08 |
20110298047 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS - A three-dimensional semiconductor device includes a first semiconductor device, a second semiconductor device, and a patterned conductive layer disposed between the first and the second semiconductor devices. The first semiconductor device has a first plurality of terminals on a front side of the first semiconductor device and a first metal substrate on its back side, wherein one of the first plurality of terminals in the first semiconductor device is electrically coupled to the first metal substrate. The second semiconductor device has a second plurality of terminals on a front side of the second semiconductor device and a second metal substrate on its back side, wherein the second semiconductor device further includes a second metal substrate on its back side. The patterned conductive layer includes a plurality of conductive regions. Each of the conductive regions is bonded to a conductor coupled to one of the first plurality of terminals and another conductor coupled to one of the second plurality of terminals. | 2011-12-08 |
20110298048 | SEMICONDUCTOR DEVICE - The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material. A Young's modulus of the material of the stress relaxation portion is lower than a Young's modulus of the material of the emitter electrode. | 2011-12-08 |
20110298049 | CMOS Device with Raised Source and Drain Regions - A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate. | 2011-12-08 |
20110298050 | FIN TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures. | 2011-12-08 |
20110298051 | Electrostatic Discharge Management Apparatus, Systems, and Methods - Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed. | 2011-12-08 |
20110298052 | Vertical Stacking of Field Effect Transistor Structures for Logic Gates - A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the semiconductor substrate and three conducting layers, one conducting layer between each vertically adjacent dielectric layer. A first FET (field effect transistor) and a third FET are arranged parallel to the top surface of the semiconductor and a second FET is arranged orthogonal to the top surface of the semiconductor. All three FETs are independently controllable. The first conducting layer is a gate electrode of the first FET; the second conducting layer is a gate electrode of the second FET, and the third conducting layer is the gate electrode of the third FET. | 2011-12-08 |
20110298053 | MANUFACTURING METHOD OF GATE STACK AND SEMICONDUCTOR DEVICE - A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process. | 2011-12-08 |
20110298054 | One-time programmable memory - The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element. | 2011-12-08 |
20110298055 | Semiconductor device and manufacturing method for the same - In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film. | 2011-12-08 |
20110298056 | CONTACT RESISTIVITY REDUCTION IN TRANSISTOR DEVICES BY DEEP LEVEL IMPURITY FORMATION - A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween. | 2011-12-08 |
20110298057 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction. | 2011-12-08 |
20110298058 | FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET - FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds. | 2011-12-08 |
20110298059 | INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME - An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent to a first side edge of the at least one first gate electrode. At least one second dummy gate electrode is disposed adjacent to a second side edge of the at least one first gate electrode. The second side edge is opposite to the first side edge. At least one guard ring is disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode and the at least one second dummy gate electrode. | 2011-12-08 |
20110298060 | INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK - A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface. | 2011-12-08 |
20110298061 | STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC - The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region. | 2011-12-08 |
20110298062 | METAL GATE STRUCTURES AND METHODS FOR FORMING THEREOF - Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode. | 2011-12-08 |
20110298063 | Micromechanical Component - A method is described for manufacturing a micromechanical component. The method includes providing a first substrate, forming a first connecting structure on the first substrate, and forming a microstructure on the first substrate after forming the first connecting structure. The microstructure has at least one movable functional element. The method further includes providing a second substrate having a second connecting structure, and joining the first and second substrates by carrying out a bonding process, the first and second connecting structures being joined to form a common connecting structure, and a sealed cavity being formed in the region of the microstructure. The method provides that the first connecting structure takes the form of a buried connecting structure extending up to an upper surface of the first substrate. Also described is a related micromechanical component. | 2011-12-08 |
20110298064 | SENSOR MODULE AND METHOD FOR PRODUCING SENSOR MODULES - Sensor module, comprising a carrier, at least one sensor chip and at least one evaluation chip which is electrically coupled to the sensor chip. The carrier has a cutout, in which the sensor chip is at least partly situated. The evaluation chip is arranged on the carrier and at least partly covers the cutout. | 2011-12-08 |
20110298065 | ELECTROMECHANICAL SYSTEM HAVING A CONTROLLED ATMOSPHERE, AND METHOD OF FABRICATING SAME - There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of fabricating or manufacturing MEMS having mechanical structures that operate in controlled or predetermined mechanical damping environments. In this regard, the present invention encapsulates the mechanical structures within a chamber, prior to final packaging and/or completion of the MEMS. The environment within the chamber containing and/or housing the mechanical structures provides the predetermined, desired and/or selected mechanical damping. The parameters of the encapsulated fluid (for example, the gas pressure) in which the mechanical structures are to operate are controlled, selected and/or designed to provide a desired and/or predetermined operating environment. | 2011-12-08 |
20110298066 | MICRO STRUCTURE, MICRO ELECTRO MECHANICAL SYSTEM THEREWITH, AND MANUFACTURING METHOD THEREOF - A micro structure includes a base member; a supporting unit disposed on a surface of the base member; a graphene unit which covers at least a portion of the supporting unit and at least a portion of an empty space adjacent to the supporting unit; and a structure unit disposed on at least a portion of the graphene unit over the supporting unit. | 2011-12-08 |
20110298067 | MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY - A magnetoresistive effect element includes: a magnetization free layer; a non-magnetic insertion layer provided adjacent to the magnetization free layer; a magnetic insertion layer provided adjacent to the non-magnetic insertion layer and opposite to the magnetization free layer with respect to the non-magnetic insertion layer; a spacer layer provided adjacent to the magnetic insertion layer and opposite to the non-magnetic insertion layer with respect to the magnetic insertion layer; and a first magnetization fixed layer provided adjacent to the spacer layer and opposite to the magnetic insertion layer with respect to the spacer layer. The magnetization free layer and the first magnetization fixed layer have magnetization components in directions approximately perpendicular to a film surface. The magnetization free layer includes two magnetization fixed portions and a domain wall motion portion arranged between the two magnetization fixed portions. Magnetization of one of the two magnetization fixed portions and magnetization of the other of the two magnetization fixed portions are fixed approximately anti-parallel to each other in a direction approximately perpendicular to a film surface. The domain wall motion portion has a magnetic anisotropy in a direction perpendicular to a film surface. | 2011-12-08 |
20110298068 | MAGNETIC TUNNEL JUNCTION WITH COMPENSATION ELEMENT - A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the reference element. The free magnetic layer includes Co | 2011-12-08 |
20110298069 | MAGNETIC RANDOM ACCESS MEMORY WITH DUAL SPIN TORQUE REFERENCE LAYERS - A magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic cell includes first and second fixed magnetic layers and a free magnetic layer positioned between the fixed magnetic layers. The magnetic cell also includes terminals configured for providing a spin-polarized current through the magnetic layers. The first fixed magnetic layer has a magnetization direction that is substantially parallel to the easy axis of the free magnetic layer, and the second fixed magnetic layer has a magnetization direction that is substantially orthogonal to the easy axis of the free magnetic layer. The dual fixed magnetic layers provide enhanced spin torque in writing to the free magnetic layer, thereby reducing the required current and reducing the feature size of magnetic data storage cells, and increasing the data storage density of magnetic spin torque data storage. | 2011-12-08 |
20110298070 | Semiconductor Device Having Magnetoresistive Element and Manufacturing Method Thereof - A semiconductor device has a magnetoresistive element, a bit line over the magnetoresistive element, and a yoke cover over the bit line. To form the yoke cover, a laminate film is first formed over the bit line, the laminate film having a first barrier metal layer, a magnetic layer, and a second barrier metal layer which are formed successively over the bit line. Then, the laminate film is subjected to: reactive ion etching with a gas mixture of a carbon tetrafluoride (CF | 2011-12-08 |
20110298071 | HIGH POWER DENSITY BETAVOLTAIC BATTERY - To increase total power in a betavoltaic device, it is desirable to have greater radioisotope material and/or semiconductor surface area, rather than greater radioisotope material volume. An example of this invention is a high power density betavoltaic battery. In one example of this invention, tritium is used as a fuel source. In other examples, radioisotopes, such as Nickel-63, Phosphorus-33 or promethium, may be used. The semiconductor used in this invention may include, but is not limited to, Si, GaAs, GaP, GaN, diamond, and SiC. For example (for purposes of illustration/example, only), tritium will be referenced as an exemplary fuel source, and SiC will be referenced as an exemplary semiconductor material. Other variations and examples are also discussed and given. | 2011-12-08 |
20110298072 | RIDGE STRUCTURE FOR BACK SIDE ILLUMINATED IMAGE SENSOR - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value. | 2011-12-08 |
20110298073 | IMAGE SENSOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Disclosed is a method for forming an image sensor device. First, a lens is provided, and a first sacrificial element is then formed on the lens. Subsequently, an electromagnetic interference layer is formed on the lens and the first sacrificial element, and the first sacrificial element and the electromagnetic interference layer thereon are removed to form an electromagnetic interference pattern having an opening exposing a selected portion of the lens. A second sacrificial element is formed in the opening to cover a center region of the selected portion of the lens, while a peripheral region of the selected portion of the lens remains exposed. Next, a light-shielding layer is formed on the electromagnetic interference pattern, the second sacrificial element, and the peripheral region of the selected portion of the lens. Thereafter, the second sacrificial element and the light-shielding pattern thereon are removed to expose the center region of the selected portion of the lens as a light transmitting region. | 2011-12-08 |
20110298074 | SOLID-STATE IMAGING ELEMENT AND ELECTRONIC INFORMATION DEVICE - A solid-state imaging element according to the present invention includes a plurality of light receiving sections formed in a pixel array, each light receiving section constituted of a semiconductor element for performing a photoelectric conversion on and capturing an image of image light from a subject, the solid-state imaging element further including: a light shielding wall or a reflection wall provided therein for pixel separation, in between the light receiving sections adjacent to one another in a plan view on a light entering side from the light receiving sections; and a color filter wherein at least a part of the color filter is embedded between the light shielding walls or the reflection walls, in such a manner to correspond to each of the plurality of light receiving sections, so that the distance between the color filter and a substrate can be shortened. | 2011-12-08 |
20110298075 | Lens Unit, Aligning Method, Image Pickup Device and Method for Manufacturing Image Pickup Device - Provided is a lens unit ( | 2011-12-08 |
20110298076 | PHOTODIODE AND PHOTODIODE ARRAY | 2011-12-08 |
20110298077 | METHODS OF FABRICATION OF PACKAGE ASSEMBLIES FOR OPTICALLY INTERACTIVE ELECTRONIC DEVICES AND PACKAGE ASSEMBLIES THEREFOR - Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier. | 2011-12-08 |
20110298078 | METHOD FOR PRODUCTION OF SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT, AND IMAGING APPARATUS - Disclosed herein is a method for producing a solid-state imaging element which has pixels, each including a sensor section that performs photoelectric conversion and a charge transfer section that transfers charges generated by the sensor section. The method includes: forming an impurity region of the first conduction type and a second impurity region of the second conduction type on the impurity region of the first conduction type by ion implantation by using the same mask; forming on the surface of the semiconductor substrate a transfer gate constituting the charge transfer section which extends over the second impurity region of the second conduction type; forming a charge accumulating region of the first conduction type constituting the sensor section by ion implantation; and forming a first impurity region of the second conduction type, which has a higher impurity concentration than the second impurity region of the second conduction type, by ion implantation. | 2011-12-08 |