49th week of 2013 patent applcation highlights part 18 |
Patent application number | Title | Published |
20130320372 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode, comprising a light emitting diode (LED) cell, a dielectric layer and a metal layer is provided. The LED cell has a top surface, a bottom surface, a first lateral surface and a second lateral surface. The bottom surface is opposite to the top surface. The second lateral surface is opposite to the first lateral surface. An electrode layer is disposed on the top surface. The dielectric layer is disposed on the bottom surface, the first lateral surface and the second lateral surface. The metal layer is disposed on the dielectric layer and electrically insulated from the electrode layer. | 2013-12-05 |
20130320373 | LIGHT EMITTING DEVICE - The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance. | 2013-12-05 |
20130320374 | Double-Layer Circuit Structure with High Heat-Dissipation Efficiency - The present invention relates to a double-layer circuit structure with high heat-dissipation efficiency, comprising: a first thermal-conductive and electric-insulating layer, a plurality of first metal pads, a second thermal-conductive and electric-insulating layer, a circuit layer, and an anti-soldering layer. In the double-layer circuit structure, the second thermal-conductive and electric-insulating layer disposed on the first thermal-conductive and electric-insulating layer has a plurality of openings, and a plurality of second metal pads of the circuit layer on the second thermal-conductive and electric-insulating layer are connected with the openings, respectively. Thus, after each of devices to be welded are soldered on two second metal pads, the solder would flow into the openings through the soldering points between the devices to be welded and the second metal pads, so as to sequentially flow onto the first metal pads. Therefore, the flow path of the solder becomes a heat-dissipating shortcut for heat dissipation. | 2013-12-05 |
20130320375 | OPTOELECTRONIC DEVICE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, an optoelectronic device is provided. The optoelectronic device includes: a lead frame having a reflective structure, wherein the reflective structure has an opening; an optoelectronic element disposed in the opening; at least one electrode disposed in the lead frame and electrically connected to the optoelectronic element; a lens disposed on the lead frame and having an adhesive portion having a holding surface, an alignment surface, and an adhesive surface, wherein the adhesive surface has a convex surface or a concave surface; and a covering adhesive layer filling a region defined by the reflective structure, covering the optoelectronic element, and adhering the lens to the lead frame through the adhesive portion of the lens. | 2013-12-05 |
20130320376 | FRAME HOLDER - A method of assembling an optical element on top of an active component in a substrate, by providing a substrate with active component and an optical element with a base and lateral base walls, fixating a bottom surface of a frame holder with opening and lateral frame walls arranged in a polygonal structure to the substrate so that the opening is positioned over the active component, and mounting the optical element in the opening so the lateral frame walls apply lateral confining mechanical force on the lateral base walls. | 2013-12-05 |
20130320377 | Light-Emitting Element, Light-Emitting Device, Display Device, Electronic Device, and Lighting Device - An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption are provided by using the above light-emitting element. Focus is placed on Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by employing a combination of molecules which makes it possible to obtain an overlap between an emission spectrum band of the molecule which donates energy and the longest-wavelength-side peak of a characteristic curve obtained by multiplying an absorption spectrum of the molecule which receives energy by a wavelength raised to the fourth power. | 2013-12-05 |
20130320378 | LIGHT-EMITTING DEVICE - A light-emitting device includes a face-up type LED chip formed rectangular in a top view, and a rectangular parallelepiped-shaped sealing portion to seal the LED chip. An angle formed between a side surface of the LED chip and a side surface of the sealing portion in the top view is 45±17°, and a portion of light emitted from the LED chip is emitted from the side surface of the sealing portion. | 2013-12-05 |
20130320379 | EPOXY RESIN COMPOSITION AND LIGHT EMITTING APPARATUS - Disclosed are an epoxy resin composition and a light emitting apparatus. The epoxy resin composition includes a triazine derivative epoxy resin and an alicyclic epoxy resin. | 2013-12-05 |
20130320380 | LIGHTING DEVICE AND METHOD OF MANUFACTURING THE SAME - In a first aspect of the present invention, a lighting device includes a light-emitting element, a frame including a phosphor that can be excited by light emitted from the light-emitting element, the frame having an inner side surface surrounding the light-emitting element and an outer side surface being positioned outside the inner side surface that demarcates a quadrilateral area, and a light-transmitting resin arranged in the quadrilateral area demarcated by the inner side surface of the frame and sealing the light-emitting element that is positioned inside the quadrilateral area, and the light-transmitting resin being further provided in contact with an outer side surface of the frame. In some embodiments, it is disclosed that the light-transmitting resin provided in contact with the outer side surface of the frame may include a diffuser. | 2013-12-05 |
20130320381 | LIGHT EMITTING DEVICE, LIGHT EMITTING MODULE, AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer, and a second insulating layer. The portion of the second p-side interconnect layer has the L-shaped cross section being configured to include a p-side external terminal exposed from the first insulating layer and the second insulating layer at a third surface having a plane orientation different from the first surface and the second surface. The portion of the second n-side interconnect layer has the L-shaped cross section being configured to include an n-side external terminal exposed from the first insulating layer and the second insulating layer at the third surface. | 2013-12-05 |
20130320382 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, an inorganic insulating film, a p-side interconnection portion, an n-side interconnection portion, and an organic insulating film. The organic insulating film is provided on the inorganic insulating film, at least on a portion between the p-side interconnection portion and the n-side interconnection portion. An end portion of the p-side interconnection portion on the n-side interconnection portion side and an end portion of the n-side interconnection portion on the p-side interconnection portion side override the organic insulating film. | 2013-12-05 |
20130320383 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side metal pillar, an n-side metal pillar, and an insulator. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side metal pillar includes a p-side external terminal. The n-side metal pillar includes an n-side external terminal. At least one selected from an area and a planar configuration of the p-side external terminal is different from at least one selected from an area and a planar configuration of the n-side external terminal. | 2013-12-05 |
20130320384 | CERAMIC CONVERSION ELEMENT, SEMICONDUCTOR CHIP COMPRISING A CERAMIC CONVERSION ELEMENT AND METHOD FOR PRODUCING A CERAMIC CONVERSION ELEMENT - A ceramic conversion element includes an active ceramic layer that converts electromagnetic radiation in a first wavelength range into electromagnetic radiation in a second wavelength range, which is different from the first wavelength range, and a carrier layer transmissive to radiation in the first wavelength range and/or radiation in the second wavelength range, wherein an inhibitor layer is arranged between the active layer and the carrier layer, the inhibitor layer reducing diffusion of activator ions from the active layer into the carrier layer. | 2013-12-05 |
20130320385 | Method for Producing a Radiation Conversion Element, Radiation Conversion Element and Optoelectronic Component Containing a Radiation Conversion Element - A method for producing a radiation conversion element is provided, in which a solution is applied to a substrate, a gel is formed from the solution and the gel is thermally treated. A radiation conversion element is also provided which is produced according to the method. An optoelectronic component is also provided which contains a radiation conversion element. | 2013-12-05 |
20130320386 | METHODS OF SEPARATING SOLID STATE TRANSDUCERS FROM SUBSTRATES AND ASSOCIATED DEVICES AND SYSTEMS - Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers. | 2013-12-05 |
20130320387 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) and a manufacturing method thereof are provided. The LED comprises a semiconductor composite layer and an electrode. The semiconductor composite layer provides holes and electrons and allows the holes and the electrons to be combined to emit light. The electrode is formed on the semiconductor composite layer, wherein the electrode contains 30%˜98% of aluminum. | 2013-12-05 |
20130320388 | LIGHT-EMITTER AND TRANSISTOR - A light-emitter with a bank having an upper surface located at a height of h0 with reference to the top surface of the base layer and a circumferential surface facing the aperture in the bank. When h denotes a height of a given point on the circumferential surface with reference to the top surface and x denotes a distance, measured in a direction along the top surface, of the given point from a boundary between the upper and circumferential surface, a second-order derivative of h with respect to x is continuous at a point corresponding to the boundary, h being smaller than h0. An inflection point of the second-order derivative is located at a height of 0.9h0 or greater with reference to the top surface, and a top surface of the functional layer is in contact with the circumferential surface at a contact point near the inflection point. | 2013-12-05 |
20130320389 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer; and an insulating layer on an outer peripheral surface of at least two layers of the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer. | 2013-12-05 |
20130320390 | FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE - A flexible polymeric dielectric layer has first and second major surfaces. The first major surface has a conductive layer thereon. The dielectric layer has at least one via extending from the second major surface to the first major surface. The conductive layer includes electrically separated first and second portions configured to support and electrically connect a light emitting semi-conductor device to the conductive layer. | 2013-12-05 |
20130320391 | LIGHT-EMITTING DEVICE - A light-emitting device includes a light-emitting element, and a sealing material for sealing the light-emitting element. The sealing material includes a first layer including a radical polymerizable resin and a second layer including a non-radical polymerizable resin, the first layer being in contact with the light-emitting element and the second layer covering an upper surface of the first layer. | 2013-12-05 |
20130320392 | CURABLE COMPOSITION FOR ENCAPSULATING OPTICAL SEMICONDUCTOR AND OPTICAL SEMICONDUCTOR APPARATUS USING THE SAME - The curable composition for encapsulating an optical semiconductor includes, a linear polyfluoro compound, a cyclic organosiloxane having a SiH group and a fluorine-containing organic group, and/or an organo hydrogen siloxane having a SiH group and a fluorine-containing organic group, a platinum group metal catalyst, a cyclic organosiloxane having a SiH group, a fluorine-containing organic group and an epoxy group, and a cyclic organopolysiloxane having a monovalent unsaturated hydrocarbon group and a fluorine-containing organic group, and a hardness of the cured product obtained by curing is 30 to 80 by Type A durometer regulated by HS K6253-3. The present invention provides a curable composition for encapsulating an optical semiconductor which gives a cured product excellent in impact resistance and adhesiveness, and an optical semiconductor apparatus in which an optical semiconductor device is encapsulated by a cured product obtained by curing the curable composition for encapsulating an optical semiconductor. | 2013-12-05 |
20130320393 | EPOXY RESIN COMPOSITION AND LIGHT EMITTING APPARATUS - Disclosed are an epoxy resin composition and a light emitting apparatus. The epoxy resin composition includes a triazine derivative epoxy resin and a silicon-containing alicyclic epoxy resin | 2013-12-05 |
20130320394 | METHOD FOR PRODUCING GROUP-III NITRIDE SEMICONDUCTOR CRYSTAL, GROUP-III NITRIDE SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR LIGHT EMITTING DEVICE - The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method. | 2013-12-05 |
20130320395 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer. | 2013-12-05 |
20130320396 | MUTUAL BALLASTING MULTI-FINGER BIDIRECTIONAL ESD DEVICE - An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node. | 2013-12-05 |
20130320397 | Fully Isolated LIGBT and Methods for Forming the Same - A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region. | 2013-12-05 |
20130320398 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 2013-12-05 |
20130320399 | EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS - Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins. | 2013-12-05 |
20130320400 | HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed. | 2013-12-05 |
20130320401 | Mixed Orientation Semiconductor Device and Method - A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer. | 2013-12-05 |
20130320402 | pHEMT HBT INTEGRATED EPITAXIAL STRUCTURE AND A FABRICATION METHOD THEREOF - An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure and the fabrication method thereof, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT's structure comprises a buffer layer, a barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. The fabrication method of an HBT and a pHEMT are also included. | 2013-12-05 |
20130320403 | Epitaxial Base Layers For Heterojunction Bipolar Transistors - An exemplary embodiment of the present invention provides a heterojunction bipolar transistor comprising an emitter, a collector, and a base. The base can be disposed substantially between the emitter and collector. The base can comprise a plurality of alternating type-I and type-II layers arranged to form a short period super lattice. The type-I layers can have a band-gap that is narrower than the band-gap of the type-II layers. At least one of the type-I layers and the type-II layers can consist essentially of a quaternary material. | 2013-12-05 |
20130320404 | GALLIUM NITRIDE TO SILICON DIRECT WAFER BONDING - A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs. | 2013-12-05 |
20130320405 | SEMICONDUCTOR DEVICE HAVING DECOUPLING CAPACITORS AND DUMMY TRANSISTORS - A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor. | 2013-12-05 |
20130320406 | IMAGE SENSOR DEVICES HAVING DUAL-GATED CHARGE STORAGE REGIONS THEREIN - An image sensor device may include a dual-gated charge storage region within a substrate. The dual-gated charge storage region includes first and second diodes within a common charge generating region. This charge generating region is configured to receive light incident on a surface of the image sensor device. The first and second diodes include respective first conductivity type regions responsive to first and second gate signals, respectively. These first and second gate signals are active during non-overlapping time intervals. | 2013-12-05 |
20130320407 | IMAGE SENSOR - An image sensor includes a first device isolation layer separating a plurality of pixels from one another, and a second device isolation layer disposed along inner side surfaces of parts of the first device isolation layer that extend around the pixels. The second device isolation layer delimits an active region of the semiconductor substrate. Each pixel includes a photoelectric converter, a floating diffusion region, a ground region, and a gate of a transfer transistor. The gate extends into the active region of the semiconductor substrate. The ground region is electrically connected to a ground voltage terminal. | 2013-12-05 |
20130320408 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device comprises a substrate, a metal-semiconductor compound layer and at least one kind of metal dopant. The substrate has a surface. The metal-semiconductor compound layer extends downwards into the substrate from the surface. The metal dopant which is made by one of a group of metal elements with atomic numbers ranging from 57 to 78 or the arbitrary combinations thereof and doped in the metal-semiconductor compound layer and the substrate with at least one peak concentration formed adjacent to the interface of the metal-semiconductor compound layer and the substrate. | 2013-12-05 |
20130320409 | SOURCE AND DRAIN ARCHITECTURE IN AN ACTIVE REGION OF A P-CHANNEL TRANSISTOR BY TILTED IMPLANTATION - In sophisticated P-channel transistors, which may frequently suffer from a pronounced surface topography of the active regions with respect to the surrounding isolation regions, superior performance may be achieved by using a tilted implantation upon forming the deep drain and source regions, preferably with the tilt angle of 20 degrees or less, thereby substantially avoiding undue lateral dopant penetration into sensitive channel areas. | 2013-12-05 |
20130320410 | METAL GATE ELECTRODE OF A SEMICONDUCTOR DEVICE - The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode. | 2013-12-05 |
20130320411 | BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION - A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region. | 2013-12-05 |
20130320412 | ISOLATED INSULATING GATE STRUCTURE - Systems and methods are presented for forming a gate structure comprising an insulative portion, whereby the insulative portion is utilized to electrically isolate an electrically conductive portion of the gate structure from a conductive element located in the vicinity of the gate structure. The insulative portion is formed by chemically modifying a conductive portion of the gate. Chemical modification is an oxidation process, converting aluminum conductor to aluminum oxide insulator material. Utilizing a chemically modified gate structure enables self aligning contact technique(s) to be utilized with semiconductor devices comprising a replacement metal gate(s). The chemical modification process can be performed prior or after forming a contact opening. | 2013-12-05 |
20130320413 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a trench formed in the semiconductor substrate, in which a rare earth oxide layer is formed in the trench; a channel region partly or entirely formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region, respectively. A relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 02013-12-05 | |
20130320414 | BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION - A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region. | 2013-12-05 |
20130320415 | FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH - Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA. | 2013-12-05 |
20130320416 | SEMICONDUCTOR DEVICE - A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings. | 2013-12-05 |
20130320417 | METHODS TO ENHANCE DOPING CONCENTRATION IN NEAR-SURFACE LAYERS OF SEMICONDUCTORS AND METHODS OF MAKING SAME - A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet- vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence. | 2013-12-05 |
20130320418 | Self-Aligned Implantation Process for Forming Junction Isolation Regions - A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation. | 2013-12-05 |
20130320419 | CIS Image Sensors with Epitaxy Layers and Methods for Forming the Same - A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric. | 2013-12-05 |
20130320420 | CMOS Image Sensors and Methods for Forming the Same - A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region. | 2013-12-05 |
20130320421 | METAL-OXIDE-SEMICONDUCTOR CAPACITOR - A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor. | 2013-12-05 |
20130320422 | FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM - A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin. | 2013-12-05 |
20130320423 | WRAP-AROUND FIN FOR CONTACTING A CAPACITOR STRAP OF A DRAM - A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin. | 2013-12-05 |
20130320424 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer. | 2013-12-05 |
20130320425 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, conductive layers and insulating layers alternately stacked above the semiconductor substrate, a block insulating layer which is formed on an inner surface of a hole formed in the conductive layers and the insulating layers and extending in a stacking direction, a charge storage layer formed on the block insulating layer, a tunnel insulating layer formed on the charge storage layer, and a semiconductor layer formed on the tunnel insulating layer. Letting R | 2013-12-05 |
20130320426 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode. | 2013-12-05 |
20130320427 | GATED CIRCUIT STRUCTURE WITH SELF-ALIGNED TUNNELING REGION - A tunnel field-effect transistor is provided, which includes a fin-shaped, source-drain circuit structure with a source region and a drain region. The circuit structure is angled in cross-sectional elevation, and includes a first portion and a second portion. The first portion extends away from the second portion, and the source region is disposed in the first or second portion, and the drain region is disposed in the other of the first or second portion. The transistor further includes a gate electrode for gating the circuit structure and a self-aligned tunneling region. The tunneling region is self-aligned to at least a portion of the circuit structure and extends between the gate electrode and the first or second portion of the fin-shaped circuit structure, and the self-aligned tunneling region is at least partially disposed in parallel, spaced opposing relation to a control surface of the gate electrode. | 2013-12-05 |
20130320428 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE AND A GATE TAP - An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device. | 2013-12-05 |
20130320429 | PROCESSES AND STRUCTURES FOR DOPANT PROFILE CONTROL IN EPITAXIAL TRENCH FILL - Methods of depositing epitaxial material using a repeated deposition and etch process. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. During the deposition process, a doped silicon film can be deposited. The doped silicon film can be selectively deposited in a trench on a substrate. The trench can have a liner comprising silicon and carbon prior to depositing the doped silicon film. The doped silicon film may also contain germanium. Germanium can promote uniform dopant distribution within the doped silicon film. | 2013-12-05 |
20130320430 | Vertical Power MOSFET and Methods of Forming the Same - A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. | 2013-12-05 |
20130320431 | Vertical Power MOSFET and Methods for Forming the Same - A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via. | 2013-12-05 |
20130320432 | Vertical Power MOSFET and Methods of Forming the Same - A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device. | 2013-12-05 |
20130320433 | VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes. | 2013-12-05 |
20130320434 | SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME - In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm. | 2013-12-05 |
20130320435 | Trench Power MOSFET - A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. | 2013-12-05 |
20130320436 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. Also, because it does not have to consider step coverage based on the aspect ratio of openings, there is no limitation in the method of depositing a metal layer. Therefore, productivity may be improved. | 2013-12-05 |
20130320437 | Power MOSFET and Methods for Forming the Same - A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region. | 2013-12-05 |
20130320438 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a gate electrode buried in a trench within a semiconductor substrate, a first sealing insulating film disposed over the gate electrode and the semiconductor substrate, an ion-implanting region disposed in portions of the semiconductor substrate adjacent to sidewalls of the trench, and a second sealing insulating film formed over the first sealing insulating film to bury the trench. | 2013-12-05 |
20130320439 | DEVICE - A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions. | 2013-12-05 |
20130320440 | Floating Body Transistor Constructions, Semiconductor Constructions, And Methods Of Forming Semiconductor Constructions - The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays. | 2013-12-05 |
20130320441 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics. | 2013-12-05 |
20130320442 | TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively. | 2013-12-05 |
20130320443 | Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Transistor - A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDS | 2013-12-05 |
20130320444 | INTEGRATED CIRCUIT HAVING VERTICAL COMPENSATION COMPONENT - An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed. | 2013-12-05 |
20130320445 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A high voltage metal-oxide-semiconductor (HV MOS) device includes a substrate, a gate positioned on the substrate, a drain region formed in the substrate, a source region formed in the substrate, a first doped region formed in between the drain region and the source region, and a second doped region formed over a top of the first doped region or/and under a bottom of the first doped region. The drain region, the source region, and the second doped region include a first conductivity type, the first doped region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary. | 2013-12-05 |
20130320446 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a rare earth oxide layer formed on the semiconductor substrate; a channel region formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region respectively, in which a relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 02013-12-05 | |
20130320447 | ETSOI WITH REDUCED EXTENSION RESISTANCE - A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance. | 2013-12-05 |
20130320448 | SEMICONDUCTOR DEVICES HAVING THREE-DIMENSIONAL BODIES WITH MODULATED HEIGHTS - Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different. | 2013-12-05 |
20130320449 | LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask. | 2013-12-05 |
20130320450 | MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO | 2013-12-05 |
20130320451 | SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT - The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device. | 2013-12-05 |
20130320452 | Semiconductor Device and Method of Forming the Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact. | 2013-12-05 |
20130320453 | AREA SCALING ON TRIGATE TRANSISTORS - Improving an area scaling on tri-gate transistors is described. An insulating layer is deposited on a fin on a substrate. The insulating layer is recessed to expose the fin. The corner of the fin is rounded off using a noble gas. A gate dielectric layer is deposited on the rounded corner. The radius of curvature of the corner is controllable by adjusting a bias power to the substrate. The radius of curvature of the corner is determined based on the width of the fin to reduce an area scaling of the array. | 2013-12-05 |
20130320454 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area. | 2013-12-05 |
20130320455 | SEMICONDUCTOR DEVICE WITH ISOLATED BODY PORTION - Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body. | 2013-12-05 |
20130320456 | GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME - Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs. | 2013-12-05 |
20130320457 | SEMICONDUCTOR DEVICES INCLUDING SOURCE/DRAIN STRESSORS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer. | 2013-12-05 |
20130320458 | Static Random-Access Memory Cell Array with Deep Well Regions - An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array. | 2013-12-05 |
20130320459 | Semiconductor Isolation Structure with Air Gaps in Deep Trenches - A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate. | 2013-12-05 |
20130320460 | SEMICONDUCTOR DEVICE HAVING FIN STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film. | 2013-12-05 |
20130320461 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region. | 2013-12-05 |
20130320462 | ADAPTIVE CHARGE BALANCED EDGE TERMINATION - In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings. | 2013-12-05 |
20130320463 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure includes: a substrate having a plurality of first conductive pads and a plurality of second conductive pads; an MEMS element disposed on the substrate; a cover member disposed on the MEMS element and having a metal layer formed thereon; a plurality of bonding wires electrically connected to the MEMS element and the second conductive pads of the substrate; a plurality of first wire segments, each having one end electrically connected to a corresponding one of the first conductive pads; and an encapsulant formed on the substrate and encapsulating the MEMS element, the cover member, the first wire segments and the bonding wires, wherein the other end of each of the first wire segments is exposed from the encapsulant. Compared with the prior art, the package structure of the present invention has improved overall yield and functionality. | 2013-12-05 |
20130320464 | INTEGRALLY MOLDED DIE AND BEZEL STRUCTURE FOR FINGERPRINT SENSORS AND THE LIKE - A biometric sensor device, such as a fingerprint sensor, comprises a substrate to which is mounted a die on which is formed a sensor array and at least one conductive bezel. The die and the bezel are encased in a unitary encapsulation structure to protect those elements from mechanical, electrical, and environmental damage, yet with a portion of the sensor array and the bezel exposed or at most thinly covered by the encapsulation or other coating material structure. | 2013-12-05 |
20130320465 | THIN MEMS MICROPHONE MODULE - A MEMS microphone module includes a first circuit board and a second circuit board attached to the first circuit board. A MEMS chip and an ASIC chip are respectively received in one of two concavities of the first circuit board. A first ground layer of the first circuit board and a second ground layer of the second circuit board are electrically coupled to each other to define a ground shielding structure. By this way, an EMI shielding can be applied by the ground shielding structure to the MEMS chip and the ASIC chip. | 2013-12-05 |
20130320466 | Package for Damping Inertial Sensor - A capped micromachined accelerometer with a Q-factor of less than 2.0 is fabricated without encapsulating a high-viscosity gas with the movable mass of the micromachined accelerometer by providing small gaps between the movable mass and the substrate, and between the movable mass and the cap. The cap may be an silicon cap, and may be an ASIC smart cap. | 2013-12-05 |
20130320467 | METHOD FOR ASSEMBLING CONDUCTIVE PARTICLES INTO CONDUCTIVE PATHWAYS AND SENSORS THUS FORMED - A sensor is achieved by applying a layer of a mixture that contains polymer and conductive particles over a substrate or first surface, when the mixture has a first viscosity that allows the conductive particles to rearrange within the material. An electric field is applied over the layer, so that a number of the conductive particles are assembled into one or more chain-like conductive pathways with the field and thereafter the viscosity of the layer is changed to a second, higher viscosity, in order to mechanically stabilise the material. The conductivity of the pathway is highly sensitive to the deformations and it can therefore act as deformation sensor. The pathways can be transparent and is thus suited for conductive and resistive touch screens. Other sensors such as strain gauge and vapour sensor can also be achieved. | 2013-12-05 |
20130320468 | MAGNETIC ELEMENT WITH STORAGE LAYER MATERIALS - According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers. | 2013-12-05 |
20130320469 | Image Sensor with Low Step Height between Back-side Metal and Pixel Array - A CMOS image sensor and a method of forming are provided. The CMOS image sensor may include a device wafer. A conductive feature may be formed on a back-side surface of the device wafer. The device wafer may include a pixel formed therein. A passivation layer may be formed over the back-side surface of the device wafer and the conductive feature. A grid film may be formed over the passivation layer. The grid film may be patterned to accommodate a color filter. The grid film pattern may align the color filter to corresponding pixel in the device wafer. A portion of the grid film formed over the conductive feature may be reduced to be substantially planar with portions of the grid film adjacent to the conductive feature. The patterning and reducing may be performed according to etching processes, chemical mechanical processes, and combinations thereof. | 2013-12-05 |
20130320470 | PHOTODETECTOR - A photodetector | 2013-12-05 |
20130320471 | WAFER LEVEL OPTICAL SENSOR PACKAGE AND LOW PROFILE CAMERA MODULE, AND METHOD OF MANUFACTURE - A wafer-level camera sensor package includes a semiconductor substrate with an optical sensor on a front surface. Through-silicon-vias (TSV) extend through the substrate and provide I/O contact with the sensor from the back side of the substrate. A glass cover is positioned over the front surface, and the cover and substrate are embedded in a molding compound layer (MCL), the front surface of the MCL lying coplanar with the front of the cover, and the back surface lying coplanar with the back of the substrate. Surface-mount devices, electromagnetic shielding, and through-wafer-connectors can be embedded in the MCL. A redistribution layer on the back surface of the MCL includes bottom contact pads for mounting the package, and conductive traces interconnecting the contact pads, TSVs, surface-mount devices, shielding, and through-wafer-connectors. Anisotropic conductive adhesive is positioned on the front of the MCL for physically and electrically attaching a lens array. | 2013-12-05 |