49th week of 2014 patent applcation highlights part 34 |
Patent application number | Title | Published |
20140355325 | Packaging of High Performance System Topology for NAND Memory Systems - A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package. | 2014-12-04 |
20140355326 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes: a plurality of first interconnects, and each of the first interconnects extending in a first direction; a plurality of second interconnects, and each of the second interconnects extending in a second direction intersecting with the first direction; a memory cell connected between each of the plurality of first interconnects and each of the plurality of second interconnects, the memory cell including a memory layer and a diode connected to the memory layer; and a control circuit capable of selecting a selection first interconnect among the first interconnects, selecting a selection second interconnect among the second interconnects, and selecting a selection memory cell connected to both the selection first interconnect and the selection second interconnect. | 2014-12-04 |
20140355327 | MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME - A memory system includes a controller, a first memory module, and a second memory module. The first memory module includes a first number of memory packages and a second number of memory packages. The second memory module includes a third number of memory packages and a fourth number of memory packages. The first and third numbers of memory packages are selected to correspond to a same rank based on control signals from the controller. The control signals are transmitted from the controller to the first and second memory modules through respective ones of a plurality of optical channels. | 2014-12-04 |
20140355328 | FERROELECTRIC MEMORY CELL FOR AN INTEGRATED CIRCUIT - An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a ferroelectric material that is at least partially in a ferroelectric state and further includes, as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr). | 2014-12-04 |
20140355329 | METHOD AND APPARATUS FOR COMMON SOURCE LINE CHARGE TRANSFER - A method and apparatus for charge transfer comprising a resistive random access memory (ReRAM) cell, coupled to a common source voltage line (CSL) for controlling state of the ReRAM cell, and a charge transfer circuit, coupled to the memory cell through the CSL and a charge consumption circuit, for transferring charge from the CSL to the charge consumption circuit when the state of the memory cell is modified. | 2014-12-04 |
20140355330 | INTEGRATED CIRCUIT - An integrated circuit that does not involve increase in power consumption or decrease in switching probability that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit | 2014-12-04 |
20140355331 | MULTI-LEVEL MEMORY CELL WITH CONTINUOUSLY TUNABLE SWITCHING - The present disclosure provides a data storage device that includes multi-level memory cells. The data storage device may include circuitry configured to write data to the multi-level memory cell. The write circuitry may include compliance circuitry configured to implement continuously tunable switching. The write circuitry may be configured to select a compliance mode for the switching, the compliance mode being selected from the group comprising current compliance and voltage compliance. | 2014-12-04 |
20140355332 | VOLATILE MEMORY DEVICE AND REFRESH METHOD THEREOF - Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal. | 2014-12-04 |
20140355333 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column. | 2014-12-04 |
20140355334 | HANDSHAKING SENSE AMPLIFIER - Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation responsive to the completion. A completion of evaluation may not be aligned with a clock edge. | 2014-12-04 |
20140355335 | STATIC RANDOM ACCESS MEMORY SYSTEM AND OPERATION METHOD THEREOF - A static random access memory system includes a static random access memory, a multiplexer, an input buffer, an output buffer, and a shifter. The input buffer writes write data stored in the input buffer to addresses of the static random access memory corresponding to a write address signal according to a write command. The output buffer reads read data of addresses of the static random access memory corresponding to a read address signal according to a read command. The multiplexer transmits the write address signal and the read address signal to the static random access memory, and generates the write command and the read command. The shifter shifts the write command to an operation clock behind the read command when the write command and the read command exist simultaneously. | 2014-12-04 |
20140355336 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, the semiconductor memory device includes a first memory cell, first, second, third and fourth interconnect lines and first, second and third write circuits. The first memory cell includes a first magnetic tunnel junction (MTJ) element. The first interconnect line is connected to one end of the first memory cell. The first write circuit drives the first interconnect line. The second interconnect line is connected to the other end of the first memory cell. The second write circuit drives the second interconnect line. The third and fourth interconnect lines are adjacent to the first memory cell. The third write circuit drives the third and fourth interconnect lines. | 2014-12-04 |
20140355337 | METHOD OF PINNING DOMAIN WALLS IN A NANOWIRE MAGNETIC MEMORY DEVICE - There is provided a method of pinning domain walls in a magnetic memory device ( | 2014-12-04 |
20140355338 | NON-VOLATILE PHASE-CHANGE RESISTIVE MEMORY - A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the memory cells, including the formation of a layer of a phase-change material having an original amorphous state at the end of the steps of manufacturing the memory cells. The method for implementing the embedded system includes, after the steps of manufacturing the memory cells, at least the following steps: (i) pre-programming the memory device consisting of an electrical recrystallization of a selection of memory cells from their original amorphous state; and (ii) assembling the pre-programmed memory device in the system during which the device is subjected to a temperature of between 240° C. and 300° C. | 2014-12-04 |
20140355339 | DRIVING METHOD OF SEMICONDUCTOR DEVICE - In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD−α, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that α is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ΔV in the standby period. That is, Vth+ΔV<α is satisfied where Vth is the threshold value of the second transistor. | 2014-12-04 |
20140355340 | UPDATING READ VOLTAGES - A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage elements of the memory are sensed using a set of candidate read voltages to generate sensing data that is transferred to a memory accessible to the controller. The multiple representations of data may be generated based on the sensing data to emulate results of reading the storage elements using a different combination of candidate reading voltages. | 2014-12-04 |
20140355341 | READ THRESHOLD ESTIMATION IN ANALOG MEMORY CELLS USING SIMULTANEOUS MULTI-VOLTAGE SENSE - A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds. | 2014-12-04 |
20140355342 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. | 2014-12-04 |
20140355343 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted. | 2014-12-04 |
20140355344 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 2014-12-04 |
20140355345 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 2014-12-04 |
20140355346 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes first to N-th memory blocks, wherein N is an integer and N≧3. Each memory block, of the first to N-th memory blocks comprises first to (M−1)-th strings, wherein each string, of the first to (M−1)-th strings, includes drain-side memory cells, source-side memory cells, and a pipe transistor connecting the drain-side memory cells and the source-side memory cells, where M is an integer and M≧2, and an M-th string, including drain-side memory cells formed adjacent to the first string, of a first to (M−1)-th strings, and including source-side memory cells formed adjacent to an (M−1)-th string of the first to (M−1)-th strings. | 2014-12-04 |
20140355347 | MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION - A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells. | 2014-12-04 |
20140355348 | FLASH MEMORY SYSTEM AND WORD LINE INTERLEAVING METHOD THEREOF - Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array. | 2014-12-04 |
20140355349 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block. | 2014-12-04 |
20140355350 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 2014-12-04 |
20140355351 | CONTROLLER - A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out on the strings, the first value for a first string being updated when a read or write operation is carried out on a memory cell transistor of the first string and the second value being updated when a read or write operation is carried out on a memory cell transistor of a second string that is different from the first string. | 2014-12-04 |
20140355352 | MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE - Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described. | 2014-12-04 |
20140355353 | CURRENT SENSING AMPLIFIER AND SENSING METHOD THEREOF - A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage. | 2014-12-04 |
20140355354 | INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF - An integrated circuit includes a mirroring/amplifying unit suitable for mirroring and amplifying a sensing current that flows on a signal transmission line coupled to an internal circuit, and outputting an amplified current; a reference current generating unit suitable for generating a reference current; and a state determination unit suitable for comparing the reference current with the amplified current and determining a state of the internal circuit based on a comparison result. | 2014-12-04 |
20140355355 | METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES - The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells. | 2014-12-04 |
20140355356 | DATA TRANSFER CIRCUIT AND MEMORY INCLUDING THE SAME - A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for driving the second line based on the data from the corresponding first line in a first operation, and a plurality of connection units, each suitable for coupling the third line to the corresponding first line when the corresponding first line is selected in a second operation. | 2014-12-04 |
20140355357 | METHOD FOR WRITING IN AN EEPROM-TYPE MEMORY INCLUDING A MEMORY CELL REFRESH - The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL, in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes. | 2014-12-04 |
20140355358 | Circuits and Methods for Efficient Execution of A Read or A Write Operation - A system for efficient execution of a read or a write is described. The system includes a memory array including a way. The system further includes a read and compare circuit. The read and compare circuit compares data stored within lower address memory cells of the way with information received from a storage device to generate a result of comparison. Moreover, the read and compare circuit compares data stored within higher address memory cells of the way with the information to generate a result of comparison. The system further includes a merge and multiplex circuit coupled to the read and compare circuit. The merge and multiplex circuit merges the result of comparison generated based on the comparison with the lower address memory cells and the result of comparison generated based on the comparison with the higher address memory cells to create a merged outcome of comparison. | 2014-12-04 |
20140355359 | CONTINUOUS TUNING OF PREAMBLE RELEASE TIMING IN A DOUBLE DATA-RATE MEMORY DEVICE INTERFACE - Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison. | 2014-12-04 |
20140355360 | HIGH SPEED AND LOW OFFSET SENSE AMPLIFIER - A sense amplifier includes a sensing circuit and an equalizing circuit. The sensing circuit is configured to supply one or more output signals according to one or more input signals. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to an inverting state in response to a potential of the one or more input signals. Each transistor in the sensing circuit may switch to logic 0 or logic 1 faster and die-to-die PVT variations may be compensated, thereby providing high speed and low offset read operation. | 2014-12-04 |
20140355361 | CIRCUIT IN DYNAMIC RANDOM ACCESS MEMORY DEVICES - A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry. | 2014-12-04 |
20140355362 | PIPELINED ONE CYCLE THROUGHPUT FOR SINGLE-PORT 6T RAM - Pipelined one cycle throughput for single-port 6T RAM. In accordance with a first embodiment, an electronic circuit is configured to perform consecutive read accesses using one sense amplifier. The electronic circuit includes circuitry configured to precharge the sense amplifier, circuitry configured to precharge a sense node coupled to the sense amplifier, and circuitry configured to develop the sense node. The electronic circuit also includes circuitry configured to evaluate the sense node to read a first bit, and circuitry configured to detect a completion of an evaluate operation on the sense nodes. The consecutive read accesses may be conducted with single cycle throughput of a synchronizing clock signal. The circuitry configured to detect a completion of an evaluate operation on the sense nodes may include a three state latch. | 2014-12-04 |
20140355363 | MEMORY CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel. | 2014-12-04 |
20140355364 | MEMORY AND MEMORY SYSTEM - A memory may include first to N | 2014-12-04 |
20140355365 | PULSE GENERATOR - Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method may include resetting a latch using feedback from a pulse generator by setting a latch using an input signal, triggering a pulse generator using an output from the latch, and resetting the latch using feedback from the pulse generator. | 2014-12-04 |
20140355366 | MULTIPLE DATA RATE MEMORY WITH READ TIMING INFORMATION - A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees. | 2014-12-04 |
20140355367 | MULTIPLE DATA RATE MEMORY WITH READ TIMING INFORMATION - A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees. | 2014-12-04 |
20140355368 | SEMICONDUCTOR DEVICE - An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation. | 2014-12-04 |
20140355369 | MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES - A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices. | 2014-12-04 |
20140355370 | SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR PACKAGE - A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification. | 2014-12-04 |
20140355371 | ADDRESS DETECTION CIRCUIT, MEMORY SYSTEM INCLUDING THE SAME - An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at least a threshold number of times in each period that the active command is activated M (1≦M≦N) number of times, based on the N number of addresses stored in the address storage unit. | 2014-12-04 |
20140355372 | Feedback Controlled Concrete Production - Techniques or processes for efficiently producing concrete using dynamic feedback are disclosed. A concrete plant can use a control system to manage concrete production based on the dynamic feedback. The dynamic feedback can control mixing of concrete ingredients so as to yield uniform particle distribution for the concrete ingredients. The dynamic feedback can also avoid overflow situations as well as yield improved loading of the resulting concrete into a concrete transport vehicle (e.g., concrete truck). | 2014-12-04 |
20140355373 | MIXER FOR CONTINUOUS FLOW REACTOR - A mixer for a continuous flow reactor and methods for forming the mixer and the operation thereof. The mixer allows for segmentation of a primary reactant flow through a plurality of ports into many smaller flows that are injected as jets into a secondary reactant flow in channels of the mixer. The channel has a constant width dimension to enhance even flow distribution and local turbulence of the primary and secondary reactant flows. The constant width dimension of the channel and the size and number of the ports of the mixer can be configured to ensure the primary reactant flow injected into the channel directly impinges on a surface of the channel that is opposite the injection point at normal operating conditions. | 2014-12-04 |
20140355374 | PORTABLE ULTRASOUND IMAGING DEVICES - A portal ultrasound imaging apparatus having an adjustable hinge assembly, which includes a key having a narrower end and an end wider in the circumferential direction of the hinge assembly. The key is movable in a slot in an axial direction of the hinge assembly to a locked position, where the side surfaces of the key presses against the walls of the slot to eliminate circumferential gaps between the key and the slot. When at the locked position in the slot, the key can be pushed towards the opposite of the axial direction to an unlocked position where an angular lock of the hinge assembly is released, allowing the hinge assembly to be adjusted to a desired angular coupling. The key can then be pushed in the axial direction back to the locked position in the slot to prevent change in the coupling angle of the hinge assembly. | 2014-12-04 |
20140355375 | GENERALIZED INTERNAL MULTIPLE IMAGING - Various examples are provided for generalized internal multiple imaging (GIMI). In one example, among others, a method includes generating a higher order internal multiple image using a background Green's function and rendering the higher order internal multiple image for presentation. In another example, a system includes a computing device and a generalized internal multiple imaging (GIMI) application executable in the computing device. The GIMI application includes logic that generates a higher order internal multiple image using a background Green's function and logic that renders the higher order internal multiple image for display on a display device. In another example, a non-transitory computer readable medium has a program executable by processing circuitry that generates a higher order internal multiple image using a background Green's function and renders the higher order internal multiple image for display on a display device. | 2014-12-04 |
20140355376 | Display With Backside Ultrasonic Sensor Array - A display device has a visual display capable of providing an image and an ultrasonic sensor array attached to a backside component of the visual display. The ultrasonic sensor array may be an ultrasonic area array sensor. For example, the backside component may be a backlight, an optical waveguide, or a display TFT. | 2014-12-04 |
20140355377 | ULTRASOUND IMAGE ENHANCEMENT AND SUPER-RESOLUTION - Techniques to improve resolution in an ultrasound system are disclosed. An exemplary apparatus is a portable ultrasound probe having transducer elements and supporting electronics within the probe. The beam is shaped to split the resolution to sub-pixel accuracy. Super resolution sample technique based on interpolation can be used to further increase resolution. In one embodiment the ultrasound system supports ½ crystal physical resolution and ¼ crystal digital resolution. | 2014-12-04 |
20140355378 | Ultrasonic Observation Equipment, Ultrasonic Observation System, and Ultrasonic Observation Method - A single-element ultrasonic sensor includes a single transducer element and transmits an ultrasonic wave on the basis of a pulse wave. An ultrasonic array sensor includes a plurality of transducer elements and receives an ultrasonic reflected wave. A pulsar supplies the pulse wave to the single element ultrasonic sensor. A receiver receives electric signals from the transducer elements included in the ultrasonic array sensor. An amplification and conversion unit amplifies the electric signals received from the transducer elements included in the ultrasonic array sensor, converts the electric signals into digital signals, and arranges the digital signals in a serial order so as to generate a serial digital signal. An image generator generates an image on the basis of the serial digital signal. | 2014-12-04 |
20140355379 | METHODS AND SYSTEMS FOR MARINE SURVEY ACQUISITION - Methods and systems for marine survey acquisition are disclosed. In one embodiment, a method is provided that may deploy a marine seismic spread that includes a first seismic source, a second seismic source and a streamer with a receiver. The second source may be disposed at a distance from the first seismic source in an inline direction. The distance may be selected to produce one or more pairs of shot points during a seismic survey. The shot points within a pair may be disposed within a range that is used to calculate a pressure source gradient between the shot points within the pair. The method may shoot the first seismic source and the second seismic source substantially simultaneously. The method may record seismic data associated with shooting the first seismic source and the second seismic source. The method may calculate the pressure source gradient for respective pairs of shot points. | 2014-12-04 |
20140355380 | SYSTEM AND METHOD FOR SEISMIC STREAMER CONTROL - A control system for use in a marine seismic survey is provided. The system may include one or more processors configured to receive a desired position for one or more seismic streamers during the marine seismic survey. The one or more processors may be further configured to determine a current position for the one or more seismic streamers and to adjust a position of a steering device on each streamer, based upon, at least in part, a comparison between the current position of the one or more seismic streamers and the desired position of the one or more seismic streamers. | 2014-12-04 |
20140355381 | COMPUTATION DEVICES AND ARTIFICIAL NEURONS BASED ON NANOELECTROMECHANICAL SYSTEMS - Techniques, systems, and devices are described for implementing for implementing computation devices and artificial neurons based on nanoelectromechanical (NEMS) systems. In one aspect, a nanoelectromechanical system (NEMS) based computing element includes: a substrate; two electrodes configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force. The first beam structure is kept at a constant voltage while the other voltage varies based on an input signal applied to the NEMS based computing element. | 2014-12-04 |
20140355382 | ULTRASONIC SENSOR - An ultrasonic sensor is provided with a mount that is fixed to an inside-face of the bumper, and a sensor body that is coupled to the mount so as to be exposed outside the bumper through an exposure hole that is provided in the bumper. Compared with a case where an ultrasonic sensor is fixed to a bumper by sandwiching the bumper from inside and outside of the bumper, appearance can be improved, since protrusion outward from the bumper is eliminated. | 2014-12-04 |
20140355383 | Location and Monitoring of Undersea Cables - The present application described methods an apparatus for locating and/or monitoring subsea cables ( | 2014-12-04 |
20140355384 | SYSTEM AND METHOD TO DETECT HIDDEN MATERIALS USING AN ANDROID MOBILE TELEPHONE - A system and method using an Android cellular telephone to detect hidden materials, or contraband, in an automobile by measuring vibration. The mathematical formula frequency of vibration uses the mass M which affects the vibration. As mass of solid surface changes, so does the vibration. If difference in the vibration is detected between the inspected vehicle and empty vehicle that is the baseline, it may indicate hidden materials or contraband. The Android mobile cellular telephone contains components needed to implement this system and method. An accelerometer. A vibrator. A touch screen display. A computer operating system, Android, that runs Android Java software. SQLite, a computer database. A computer network connection to the internet using a wireless network. A GPS sensor to provide the latitude and longitude location of the phone during testing The phone also provides an electrical power source using the phone battery, or wall outlet electricity. | 2014-12-04 |
20140355385 | OBJECT DETECTING APPARATUS - An object detecting apparatus includes a first transmission and reception unit having a first transmitter and a first receiver, a second transmission and reception unit having a second transmitter and a second receiver, and a failure judging section. The first receiver produces a first output signal corresponding to a transmission wave, which is transmitted directly from the second transmitter to the first receiver. The second receiver produces a second output signal corresponding to a transmission wave, which is transmitted directly from the first transmitter to the second receiver. Using at least one of the first output signal and the second output signal, the failure judging section judges whether a failure of the first transmitter or the second receiver has occurred, or judges whether a failure of the first transmission and reception unit or the second transmission and reception unit has occurred. | 2014-12-04 |
20140355386 | SONIC COMMUNICATION SYSTEM AND METHOD - Implementations are provided for wirelessly transmitting and receiving data through sonic communication. A transmit device having a sonic transducer transmits a sonic carrier signal through the air with a digital representation of the data with a modulation protocol using sonic transmission frequencies in accordance with present invention. The sonic transducer operates to transmit the one or more sonic carrier signals carrying the modulated data over the air with sufficient gain to carry the signal to a receiver device where the data is demodulated using at least one sonic transducer of a receive device. The receive device may be configured to perform the demodulation of the data at one or more sonic transmission frequencies and in accordance with a sonic modulation protocol to provide a binary representation of the data. Ambient noise captured by the receiver device is processed along with the data transmitted over the sonic carrier signals. | 2014-12-04 |
20140355387 | ULTRASONIC RECEIVER WITH COATED PIEZOELECTRIC LAYER - This disclosure provides systems, methods and apparatus related to an ultrasonic receiver for detecting ultrasonic energy received at a first surface of the ultrasonic receiver. The ultrasonic receiver includes an array of pixel circuits disposed on a substrate, each pixel circuit in the array including at least one thin film transistor (TFT) element and having a pixel input electrode electrically coupled to the pixel circuit. The ultrasonic receiver is fabricated by forming a piezoelectric layer so as to be in electrical contact with the pixel input electrodes. Forming the piezoelectric layer includes coating a solution containing a polymer onto the array of pixel circuits, crystallizing the polymer to form a crystallized polymer layer and poling the crystallized polymer layer. | 2014-12-04 |
20140355388 | TRANSDUCER ARRANGEMENT - There is disclosed a transducer apparatus for acoustic communications through a substrate at a predetermined centre frequency, the apparatus comprising: —an active piezoelectric element for generating an acoustic signal; an intermediate layer, having a surface for accommodating the piezoelectric element, and having a first array of protrusions on a surface opposite the surface for accommodating the piezoelectric element; and a second array of protrusions at the substrate, wherein the active piezoelectric element is mounted onto the intermediate layer, and the intermediate layer is secured in position relative to the substrate such that the first array of protrusions faces the second array of protrusions such that the acoustic signal may propagate through the first and second arrays. There are further disclosed a method of mounting such an apparatus and a plate suitable for use in the transducer apparatus. | 2014-12-04 |
20140355389 | METHOD AND APPARATUS FOR ESTABLISHING DEVICE COMMUNICATION - A method, apparatus and computer program product are provided to provide for the control of a remote device. The method may include determining, with a processor, a control radius for a remote device, determining a first proximity of a user device to the remote device, in response to determining that the first proximity is within the control radius, enabling the user device to control the remote device, determining at least one command input from the user device to the remote device based on a second proximity of the user device to the remote device, and causing transmission of the command input to the remote device. | 2014-12-04 |
20140355390 | TIMEPIECE CAPABLE OF INTEGRALLY INDICATING TIME AND PHYSICAL QUANTITIES - With conventional timepieces, information about target physical quantities, target achievement, and time has been indicated using separate displays, thereby making it difficult for users to instantly understand whether or not a target has been achieved. Therefore, a timepiece comprising a dual-purpose scale for integrally indicating time and physical quantities, a physical quantity information acquisition unit for obtaining the information about the physical quantities described above, a physical saving quantity information acquisition unit for obtaining physical saving quantity information indicating the physical quantity to be obtained by the current time within a time segment, a time display unit for displaying the time on the dual-purpose scale, an achieved value information acquisition unit for obtaining information on a quantity achieved up to the current time for the physical quantity, and a quantity variance display unit for indicating the variance in quantity obtained from achieved value and physical saving quantity is proposed. | 2014-12-04 |
20140355391 | Electronic Device and Method Providing Improved World Clock Feature - An improved electronic device and method provide an improved clock feature that includes an improved world clock function. | 2014-12-04 |
20140355392 | RADIO-CONTROLLED TIMEPIECE - Disclosed is a radio-controlled timepiece. The radio-controlled timepiece includes an oscillating unit, a display unit, a display driving unit, an error storage unit, a radio wave receiving unit, and a frequency setting unit. The display driving unit drives the display unit with a driving signal of a predetermined driving waveform frequency generated by the clock signal output by the oscillating unit. The error storage unit stores error data of an oscillating frequency. The radio wave receiving unit tunes to a receiving frequency of a radio wave including time information, and receives the radio wave. The frequency setting unit sets the driving waveform frequency based on the error data so that the receiving frequency does not overlap with a higher order harmonic wave of the driving waveform frequency during a period that the radio wave is received. | 2014-12-04 |
20140355393 | CLOCK MECHANISM FOR STORING AND DISPLAYING TIME INFORMATION - Mechanism ( | 2014-12-04 |
20140355394 | CLOCK MECHANISM FOR STORING AND DISPLAYING TIME INFORMATION - Clock movement ( | 2014-12-04 |
20140355395 | ANTIFRICTION COATING FOR MAINSPRING MADE OF COMPOSITE MATERIAL - Mainspring for driving a clock movement, said mainspring being made of a material comprising a polymer matrix containing fibres, said mainspring having a coating containing a thermoset or thermoplastic polymer. The mainspring proposed reduces the friction of the turns of the mainspring. | 2014-12-04 |
20140355396 | SPRING FOR CLOCK MOVEMENT | 2014-12-04 |
20140355397 | METHOD OF IMPROVING THE PIVOTING OF A WHEEL SET - A method of improving pivoting of a wheel set for a scientific instrument, including an arbor pivoting or oscillating about an axis, in which: static balancing of the wheel set is performed to bring the center of gravity onto the axis; a desired value is determined for resulting unbalance moment of the wheel set about the axis, corresponding to a predetermined divergence between a first principal longitudinal axis of inertia of the wheel set, and the axis; at a predetermined speed about the axis, the resulting unbalance moment is measured with regard to the axis; and an adjustment of the resulting unbalance moment is made within a given determined tolerance with regard to the desired value, and performed by machining both sides of a median plane including the two secondary axes of inertia of the wheel set. | 2014-12-04 |
20140355398 | STRIKING MECHANISM PROVIDED WITH A MEANS OF SELECTING THE MODE OF VIBRATION OF A GONG - The striking mechanism ( | 2014-12-04 |
20140355399 | HEAT ASSISTED MAGNETIC RECORDING HEAD HAVING WIDER HEAT SINK AND POLE - In one embodiment, a system includes a magnetic head having a write portion having a main pole, a near field transducer comprising a conductive metal film having outer regions extending from an active region, and an optical waveguide for illumination of the near field transducer, wherein the conductive metal film extends in a cross track direction for a width at least 200% greater than a width of the active region of the conductive metal film, wherein a portion of the main pole extends along the conductive metal film in a cross track direction for a width at least 200% greater than the width of the active region of the conductive metal film. | 2014-12-04 |
20140355400 | NOBLE METAL SURROUNDED MAGNETIC LIP AND HEAT SINK FOR HEAT ASSISTED MAGNETIC RECORDING HEAD - The embodiments of the present invention generally relate to a magnetic head having a magnetic lip. The vertical sides and the bottom of the magnetic lip are covered by one or more conductive layers. In one embodiment, the bottom of the magnetic lip is covered by a first conductive layer and the vertical sides of the magnetic hp are covered by a second conductive layer. The conductive layers are made of a material that would not react with oxygen, thus no oxide films are formed on the vertical sides and the bottom of the magnetic lip during the manufacturing of the magnetic head. | 2014-12-04 |
20140355401 | POLARIZATION ROTATOR - Implementations disclosed herein allow a magneto-optical polarization rotator to couple light from a light source of a HAMR recording device to waveguide attached to a slider. According to one implementation, the magneto-optical polarization rotator has a magnetophotonic crystal structure with a number of thin film layers configured to rotate the light by 90 degrees. | 2014-12-04 |
20140355402 | SOLID IMMERSION MIRROR WITH FILL MATERIAL BETWEEN INNER AND OUTER SIDEWALLS - An apparatus includes a solid immersion mirror with opposing, reflective, inner sidewalls having inner surfaces facing a focal region and outer surfaces opposite the inner surfaces. The solid immersion mirror also include opposing outer sidewalls spaced apart from and facing the outer surfaces of the inner sidewalls, and a fill material between the inner sidewalls and outer sidewalls. The apparatus also includes a near-field transducer located in the focal region proximate a media-facing surface. | 2014-12-04 |
20140355403 | OPTICAL INFORMATION PROCESSING APPARATUS AND OPTICAL INFORMATION PROCESSING METHOD, AND ADJUSTMENT DEVICE, ADJUSTMENT METHOD, AND ADJUSTMENT PROGRAM FOR OPTICAL INFORMATION PROCESSING APPARATUS - An optical information processing apparatus includes: a unit that radiates light onto an optical disc and detects the reflected light to output a reproduced signal; a unit that corrects spherical aberration of the light; a unit that adjusts a focus position of the light based on a focus adjustment value; and an adjustment unit that measures a characteristic of the reproduced signal at each of at least three positions on each of at least three straight lines on a plane with coordinate axes representing an amount of spherical aberration correction and focus adjustment value, obtains, from the measurements, as estimated positions, at least five positions on the plane at which the characteristic has substantially the same value, performs an ellipse approximation on the estimated positions, obtains a center of the ellipse, and determines the amount of spherical aberration correction and focus adjustment value based on the center of the ellipse. | 2014-12-04 |
20140355404 | OPTICAL MEDIUM REPRODUCING APPARATUS AND OPTICAL MEDIUM REPRODUCING METHOD - An optical medium reproducing apparatus that optically reproduces an optical medium on which a plurality of tracks is formed in which a beam returning from the optical medium is divided into a first region of an outside portion and a second region of an inside region, according to the shape of the pupil of an object lens, and crosstalk between the tracks is reduced by using a first detection signal of the first region and a second detection signal of the second region. | 2014-12-04 |
20140355405 | DISC DRIVE TESTING SIGNAL GENERATION DEVICE AND RELATED METHOD - A testing signal generation device for testing performance of a disc drive includes a signal generating unit, a signal converting unit, and a signal transmitting unit. The signal generating unit generates at least one pulse signal for controlling the disc drive to work at predetermined working modes. The signal converting unit converts the at least one pulse signal into at least one test signal. The signal transmitting unit transmits the at least one test signal to the disc drive, to control the disc drive to read data from an optical disc in the disc drive. A testing signal generation method for testing performance of the disc drive is also provided. | 2014-12-04 |
20140355406 | DUAL-SIDED OPTICAL DISCS WITH NORMALLY ORIENTED AND INVERTED TEXT PATTERNS - Disclosed is an optical disc with a first area to store data for playback and that is reflective or opaque to visible light, and a second area that is transparent to visible light and includes first and second concentric rings. In one embodiment, a method of printing information on the optical disc includes: printing an inverse first text pattern in the first ring during a first printing on a first side, where the first text pattern is formed in reverse as viewed from the first side; printing a second text pattern in the second ring during a second printing on the first side, where the second text pattern is correctly visible from the first side; and printing, during the second printing, a first solid pattern to overlay at least a portion of the first text pattern, where the first text pattern is correctly visible as viewed from a second side. | 2014-12-04 |
20140355407 | METHODS AND SYSTEMS FOR EFFICIENT MULTI-WIRE COMMUNICATIONS AND CROSSTALK CANCELLATION - Methods and systems are disclosed for efficient cancellation of crosstalk between signals transmitted over multiple signal paths. Symmetry is induced on the signals transmitted over the signal paths such that the crosstalk matrix becomes a matrix with structure. Such structured matrix may be a circulant matrix of which the inverse may be applied efficiently to transmitted symbols or received symbols. Application of such inverse may comprise the fast Fourier transform. Applications of the methods and systems disclosed include chip-to-chip communications, on-chip communications, communication over cables and storage of information. | 2014-12-04 |
20140355408 | METHOD OF SCRAMBLING REFERENCE SIGNALS, DEVICE AND USER EQUIPMENT USING THE METHOD - A Method of scrambling reference signals, device and user equipment using the method are provided. In the method, a plurality of layers of reference signals assigned on predetermined radio resource of a plurality of layers of resource blocks with the same time and frequency resources are scrambled, the method comprising: an orthogonalizing step of multiplying each layer of reference signal selectively by one of a plurality of orthogonal cover codes (OCCs) with the same length wherein the OCC multiplied to a first layer of reference signal can be configured as different from those multiplied to other layers of reference signals; and a scrambling step of multiplying all of symbols obtained from the OCC multiplied to each of the other layers of reference signals by a symbol-common scrambling sequence wherein the symbol-common scrambling sequences can be different from each other for reference signals multiplied by the same OCC. | 2014-12-04 |
20140355409 | Method For Debugging Private VLAN - A method, apparatus and computer program product for debugging private Virtual Local Area Networks (VLANs) is provided. In a Connectivity Fault Management (CFM) domain wherein a primary Virtual Local Area Network (VLAN) includes promiscuous ports and wherein a secondary VLAN includes isolated ports, a determination is made at a first network device whether a CFM packet is received on a primary VLAN or a secondary VLAN. When the CFM packet is received on a secondary VLAN, then the CFM packet is responses to on the primary VLAN. | 2014-12-04 |
20140355410 | Systems and Methods for Data Transmission - Systems and methods are provided for data transmission. For example, first data to be sent is obtained; the first data is sent to a reception terminal; second data related to a packet-loss rate returned by the reception terminal is received; and in response to the packet-loss rate exceeding a pre-determined threshold, at least a portion of the first data is sent multiple times. | 2014-12-04 |
20140355411 | CELL DEPENDENT MULTI-GROUP HYBRID AUTOMATIC REPEAT METHOD FOR MULTICAST IN WIRELESS NETWORKS - A method and apparatus are described including determining address using an access point address and a multicast group address, transmitting a recovery request message to a recovery server to request recovery data using the address and receiving the recovery data from the recovery server. Also described are a method and apparatus including receiving a registration message, transmitting a reply to the registration message, receiving a recovery request message, transmitting recovery data responsive to the recovery request message and transmitting a message to a recovery multicast group to determine status of the recovery multicast group. | 2014-12-04 |
20140355412 | COMPUTER IMPLEMENTED METHOD FOR TRACKING AND CHECKING MEASURES AND COMPUTER PROGRAMS THEREOF - A computer implemented method for tracking and checking measures and computer programs thereof. A master node receiving from a plurality of slaves nodes messages related with measures generated by the slaves nodes, the method including: capturing, a traffic driver unit, the messages sent by the slaves nodes and further sending them to a monitor unit; analyzing, the monitor unit, the received messages so as to detect, by a behavioral learning technique, anomalies in the messages; when an anomaly is detected, sending, the monitor unit, the detected anomaly to a regenerator unit for regenerating at least the detected anomaly by a prediction technique; and injecting, said traffic drive unit, measures regenerated by the regenerator unit to the transport network. | 2014-12-04 |
20140355413 | Peer, Application and Method for Detecting Faulty Peer in Peer-To-Peer Network - An application, peer and method for determining a faulty peer in a structured Peer-to-Peer overlay network. The overlay network includes plural peers besides the faulty peer. The method includes determining that a message sent from a given peer to a target peer along a first path did not reach the target peer; determining an intermediate peer at which the message had arrived; using a second path to send the message from the given peer to the target peer; determining that the message had arrived at the target peer on the second path; adjusting a node identifier (nodeID) of at least one of the target peer and the intermediate peer to obtain a new target peer or a new intermediate peer; and reusing the first and second paths to send the message to the new target peer or the new intermediate peer until the faulty peer is detected. | 2014-12-04 |
20140355414 | Label Switched Path Network Failure Detection And Traffic Control - A method for providing ingress fault protection in a label switched network, comprising sending data traffic from a source node to a first label switched path (LSP) via a first ingress node, detecting a first fault using a first fault detection link between the source node and the first ingress node, sending the data traffic from the source node to a second LSP via a second ingress node in response to detecting the first fault, detecting a second fault using a second fault detection link between the first ingress node and the second ingress node, and merging the data traffic from the second LSP into the first LSP at a next-hop node of the first ingress node, wherein the data traffic is no longer sent to the first LSP via the first ingress node after the first fault. | 2014-12-04 |
20140355415 | SEMI-CENTRALIZED ROUTING - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for semi-centralized routing. In one aspect, a computer-implemented method receives a network protocol packet at a router adapted for routing data packets to one or more additional routers. The network protocol packet conforms to a routing protocol that provides distributed routing computation. The method also sends the network protocol packet, through a controller, to a selected one of a plurality of route control servers. The method also processes the network control packet at the selected route control server to generate a routing computation result that conforms to the routing protocol. The method also generates routing information based on the routing computation. The routing information conforms to a control protocol that provides centralized routing computation. The method also sends the routing information to the router for routing of data packets based on the control protocol. | 2014-12-04 |
20140355416 | Layer 3 (L3) Best Route Selection Rule For Shortest Path Bridging Multicast (SPBM) Networks - A method, apparatus and computer program product for providing a best route selection rule is presented. A determination is made at a first edge router, whether a second edge router in a network advertises a first BMAC address and at least one other BMAC address When the second edge router advertises only a first BMAC address, then the first BMAC address is used in a routing table for a Layer 3 (L3) next hop for a route. When the second edge router advertises more than one BMAC address, at least one other BMAC address is used in the routing table for said L3 next hop for the route. | 2014-12-04 |
20140355417 | METHOD AND APPARATUS FOR PROCESSING NAS SIGNALING REQUEST IN WIRELESS COMMUNICATION SYSTEM - The present invention relates to a wireless communication system, and more particularly, to a method and an apparatus for processing a NAS signaling request. A method for performing a non-access stratum (NAS) signaling process by means of a terminal in a wireless communication system according to one embodiment of the present invention comprises: a step of receiving a first message that includes information indicating a network failure from a network node of a first network; a step of starting a timer relating to a network selection; and a step of selecting a second network from among network candidates excluding the first network during the operation of the timer relating to a network selection. | 2014-12-04 |
20140355418 | METHODS AND DEVICES FOR OPTIMIZED CELL ACQUISITIONS - Access terminals are adapted to blacklist one or more neighboring cells from acquisition attempts. For instance, an access terminal may receive a transmission including a list of neighboring cells to be monitored while connected to a particular serving cell. The access terminal may determine that a predefined number of consecutive acquisition attempts with a particular neighboring cell have failed. In response to failure of the predefined number of consecutive acquisition attempts, the access terminal can blacklist the neighboring cell from subsequent acquisition attempts for a predefined blacklisting period. Following the duration of the blacklisting period, the access terminal may conduct a subsequent acquisition attempt with the neighboring cell. Other aspects, embodiments, and features are also claimed and described. | 2014-12-04 |
20140355419 | PSEUDO WIRE END-TO-END REDUNDANCY SETUP OVER DISJOINT MPLS TRANSPORT PATHS - According to one embodiment, a method for establishing a primary and redundant PW over disjoint bidirectional RSVP-TE LSPs include establishing a first bidirectional RSVP-TE LSP that includes a first upstream path and a first downstream path. The method includes transmitting a first label distribution protocol (LDP) label mapping message that includes a first transport path include field that causes the second PE router to use the first downstream path for the primary PW. The method includes establishing a second bidirectional RSVP-TE LSP that includes a second upstream path and a second downstream path. The method includes transmitting a second LDP label mapping message that includes a second transport path include field that causes the second PE router to use the second downstream path for the redundant PW. | 2014-12-04 |
20140355420 | Method of Establishing Smart Architecture Cell Mesh (SACM) Network - The present disclosure provides a method of establishing a SACM network is disclosed. The method comprises deploying a plurality of mesh nodes, wherein each of mesh nodes having a mesh node capability to communicate with the other mesh nodes as well as a gateway capability to provide an access to a service network, wherein the service network provides a wireless communication service; establishing a plurality of links between the mesh nodes, each of the links connecting two of the mesh nodes; searching and selecting a plurality of dynamic gateway nodes from the plurality of the mesh nodes and establishing a plurality of connections between the dynamic gateway nodes and the service network and performing routing and path optimizing to find optimal route paths for all the mesh nodes to access the service network. | 2014-12-04 |
20140355421 | Link Aggregation Control Protocol (LACP) Loop Detection - Link Aggregation Control Protocol (LACP) loop detection in a network that includes a Software Defined Networking (SDN) controller, a server and an edge switch is provided. The server virtualizes a virtual switch and virtual machines. The virtual switch includes uplink ports that are aggregated with downlink ports of the edge switch to form an aggregation group, and the SDN controller controls operation of the virtual switch. The virtual switch periodically sends a LACP data unit (LACPDU) message to the edge switch via each of the uplink ports in the aggregation group. The virtual switch receives a LACPDU message from the edge switch via one of the uplink ports in the aggregation group. When it is determined that the received LACPDU message originates from the virtual switch itself, the virtual switch keeping one of the uplink ports running and shutting down the rest of the uplink ports. | 2014-12-04 |
20140355422 | INCREASING FAILURE COVERAGE OF MOFRR WITH DATAPLANE NOTIFICATIONS - An enhanced fast re-route mechanism provides increased failure coverage to a multicast communication network. If a network node detects a failure and determines that it cannot re-route multicast data, the network node sends a downstream fast notification packet (DFNP) in the network. The DFNP causes a downstream merge node to switch reception of the multicast data to its secondary path. The network node then receives an upstream fast notification packet (UFNP) from the merge node. The network node modifies its forwarding information upon receipt of the UFNP such that the multicast data is to be received by the network node from its downstream via which the UFNP was received. The DFNP and the UFNP cause the multicast data to reverse its flow direction between the network node and the merge node. | 2014-12-04 |
20140355423 | SYSTEM AND METHOD FOR RAPID PROTECTION OF RSVP BASED LSP - Various exemplary embodiments relate to a method performed by a network node in a resource reservation protocol (RSVP) based label switch path (LSP) network, the method including: receiving a message to establish a LSP; receiving a resv message; initiating the establishment of a backup path; determining that the establishment of the backup path failed; setting a backup timer; and initiating the establishment of a backup path upon the expiration of the backup timer. | 2014-12-04 |
20140355424 | Contention Handling in SMP Based Networks - Nodes and methods are disclosed for protection and restoration in the event of multiple failures for multiple paths involved for the same service in shared mesh networks, including, a method comprising the steps of storing, in non-transitory memory of a first node in a shared mesh network having a plurality of connections through the shared mesh network, records of global contention handling priority values of the plurality of connections; detecting a first signal from a second node requesting activation of a first connection of the plurality of connections, and a second signal from a third node requesting activation of a second connection of the plurality of connections, the first and second connections having overlapping requirements; determining that the second connection has a higher global contention handling priority value than the first connection based at least in part on the records; and activating the second connection. | 2014-12-04 |