49th week of 2008 patent applcation highlights part 30 |
Patent application number | Title | Published |
20080298112 | Memory array including programmable poly fuses - According to one exemplary embodiment, a memory array includes a memory cell having a programmable poly fuse coupled between a designated program node and a ground node, where the programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. In the programmable poly fuse, the P type resistive poly segment is coupled to the ground node and the N type resistive poly segment is coupled to the designated program node. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to the ground node. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to the designated program node. | 2008-12-04 |
20080298113 | Resistive memory architectures with multiple memory cells per access device - A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. | 2008-12-04 |
20080298114 | Phase change memory structure with multiple resistance states and methods of programming an sensing same - A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states. | 2008-12-04 |
20080298115 | Memory cell array with low resistance common source and high current drivability - In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body. | 2008-12-04 |
20080298116 | DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE - A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits. | 2008-12-04 |
20080298117 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal operation mode or a read mode is input externally, wherein said power supply is turned off and then turned on again in said normal operation mode, and in this state, data corresponding to the relationship between the magnitudes of the resistances of said first variable resistor element and said second variable resistor element is read in said read mode. | 2008-12-04 |
20080298118 | Asymmetrical SRAM cell with 4 double-gate transistors - The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor. The first load transistor and the driver transistor, in series, form an inverter at the supply voltage terminals. At least the transistors not comprised in the inverter comprise two electrically independent gate electrodes. The second gate electrode of the access transistor is connected to the first gate electrode of the second load transistor and the second gate electrode of the latter is connected to the supply voltage. | 2008-12-04 |
20080298119 | MAGNETIC MEMORY CELL WITH MULTIPLE-BIT IN STACKED STRUCRUTE AND MAGNETIC MEMORY DEVICE - A multi-bit magnetic memory cell in a stacked structure controlled by at least one read bit line and one read word line is provided. The multi-bit magnetic memory cell includes at least two magnetic memory units and a switching device. Each magnetic memory unit has a magneto-resistance value and at least the two magnetic memory units are stacked to form a circuit of serial connection or parallel connection. The circuit and the read bit line are connected. The switching device is connected to the circuit, wherein the switching device is controlled by the read word line to be conducting or non-conducting so as to connect the circuit with a ground voltage. Furthermore, a plurality of the multi-bit magnetic cells is used to form a magnetic memory device. | 2008-12-04 |
20080298120 | Peripheral Devices Using Phase-Change Memory - Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage. | 2008-12-04 |
20080298121 | METHOD OF OPERATING PHASE-CHANGE MEMORY - A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction. | 2008-12-04 |
20080298122 | Biasing a phase change memory device - A phase change memory device includes a plurality of cells connected to bitlines and including respective phase change memory elements and cell select devices and an addressing circuit for selectively addressing at least one bitline and one cell connected thereto. A reading column bias circuit supplies a bitline voltage to the addressed bitline and cell. The bitline voltage includes the sum of a safe voltage and a reference select device voltage, wherein the reference voltage is equal to a select device voltage on the select device when a cell current flowing through the phase change memory element and the cell select device is equal to a safe current. The safe voltage and the safe current are such that phase transition of the phase change memory element is prevented in any bias condition including a cell voltage lower than the safe voltage and in any bias condition including the cell current lower than the safe current. | 2008-12-04 |
20080298123 | Non-volatile memory cell healing - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 2008-12-04 |
20080298124 | PARALLEL PROGRAMMING OF MULTIPLE-BIT-PER-CELL MEMORY CELLS BY CONTROLLING PROGRAM PULSEWIDTH AND PROGRAMMING VOLTAGE - Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly. | 2008-12-04 |
20080298125 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including an element region which is surrounded by an element isolation insulation layer, a transistor including a gate electrode which is provided on the element region, and a source region and a drain region which are provided in the first element region, a first auxiliary wiring layer and a second auxiliary wiring layer which extend in a channel length direction and are provided on the element isolation insulation layer such that the first transistor is interposed between the first auxiliary wiring layer and the second auxiliary wiring layer, and a control circuit which sets, while the first transistor is in an ON state, the first auxiliary wiring layer and the second auxiliary wiring layer at a first voltage of the same polarity as a gate voltage of the first transistor that is in the ON state. | 2008-12-04 |
20080298126 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR REPLACING DEFECTIVE BLOCKS THEREOF - A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence. | 2008-12-04 |
20080298127 | Method of Reading Flash Memory Device for Depressing Read Disturb - Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage. | 2008-12-04 |
20080298128 | METHOD OF STORING E-FUSE DATA IN FLASH MEMORY DEVICE - Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit. | 2008-12-04 |
20080298129 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ADAPTED TO STORE A MULTI-VALUED DATA IN A SINGLE MEMORY CELL - A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell. | 2008-12-04 |
20080298130 | MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM - A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command. | 2008-12-04 |
20080298131 | INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISCHARGE RAMP RATE CONTROL AND METHOD THEREFOR - An integrated circuit ( | 2008-12-04 |
20080298132 | Sense transistor protection for memory programming - A method and apparatus for protecting a sense transistor in a sense amplifier during memory programming and erase operations, and for increasing the coupling efficiency of the memory device during the programming and erase operations. | 2008-12-04 |
20080298133 | PROGRAM VERIFYING METHOD AND PROGRAMMING METHOD OF FLASH MEMORY DEVICE - A duel program verify operation is performed using first and second verify voltages. In order to reduce the width of a threshold voltage distribution during an incremental step pulse program implementation, data of a corresponding memory cell are verified twice using the first verify voltage and the second verify voltage. During a second verify operation using the second verify voltage, a sensing current is adjusted by controlling voltages applied as a bit line select signal and an evaluation time period. Therefore, the threshold voltage of the memory cell can be measured higher or lower than its actual value and the width of a threshold voltage distribution is reduced. | 2008-12-04 |
20080298134 | METHOD OF READING CONFIGURATION DATA IN FLASH MEMORY DEVICE - Provided is a method of reading configuration data in a flash memory device, including a memory cell array which stores configuration data about an operating environment of the flash memory device. The method includes setting a read time of the configuration data to differ from a read time of normal data, and reading the configuration data. | 2008-12-04 |
20080298135 | METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING AN ARRAY STRUCTURE COMPRISING THE SAME DEVICES - The present invention discloses a metal oxide semiconductor (MOS) device and a method for operating an array structure comprising the same devices. The MOS device of the present invention comprises a device layer; an ion-implanted layer formed on the device layer and providing the source, the drain and the channel; and a gate structure formed on the ion-implanted layer. Via applying a bias voltage to the gate, the carrier density in the channel region is different from that in the source region or the drain region; thereby, the MOS device of the present invention can undertake programming, erasing and reading activities. The present invention can simplify the MOS device fabrication process, reduce the operating voltage, and promote the integration density of a 2-dimensional or 3-dimensional MOS device array. | 2008-12-04 |
20080298136 | ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY - Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage. | 2008-12-04 |
20080298137 | METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH - A domino read bit line structure ( | 2008-12-04 |
20080298138 | Semiconductor device - Disclosed is a semiconductor device comprising: a signal selecting circuit for receiving, at first and second inputs thereof, respectively, a first signal output from a first initial-stage circuit that receives a data strobe signal from a first terminal, which is an input/output terminal, and a second signal output from a second initial-stage circuit that receives a data mask signal from a second terminal, which is an input terminal, and based upon a control signal that is supplied thereto, outputting the first and second signals from first and second outputs or interchanging the first and second signals and outputting the interchanged first and second signals from the second and first outputs; a buffer circuit for receiving an output signal from a third initial-stage circuit that receives a data signal from a data terminal; and a data latch circuit for latching a signal from the buffer circuit. The signal from the first output of the signal selecting circuit is supplied to the data latch circuit as a latch timing signal. | 2008-12-04 |
20080298139 | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and /or controlling same - A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry. | 2008-12-04 |
20080298140 | MEMORY STRUCTURE WITH WORD LINE BUFFERS - A memory comprises a plurality of memory cells. A row decoder module selectively drives word lines using a voltage level to access selected ones of the memory cells. A first regeneration module selectively pulls the voltage level on one of the word lines to one of first and second predetermined voltage levels. At least one of the memory cells of the one of the word lines is located between the first regeneration module and the row decoder module. | 2008-12-04 |
20080298141 | BIT LINE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for generating an overdriving signal defining an overdriving period in response to an active command; an overdriving control signal generator for receiving the overdriving signal to generate an overdriving control signal for selectively performing an overdriving operation according to a voltage level of an overdriving voltage; and a second driver for driving the normal driving voltage terminal to the overdriving voltage in response to the overdriving control signal. | 2008-12-04 |
20080298142 | CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES - Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal. | 2008-12-04 |
20080298143 | MEMORY DEVICE WITH DELAY TRACKING FOR IMPROVED TIMING MARGIN - A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells. | 2008-12-04 |
20080298144 | Semiconductor Memory Device Capable of Confirming a Failed Address and a Method Therefor - A semiconductor memory device includes an address buffer, a row decoder, a column decoder, a fuse circuit, a memory cell array including regular and redundant memory cells, a regulator, a regular sense amplifier, a redundant sense amplifier, a selection circuit, an input/output buffer, and a test control circuit for a test mode. The test control circuit controls the regular and redundant sense amplifiers so as to output the signal upon accessing a regular memory cell different in level from that output upon accessing a redundant memory cell, whereby a failed address can be electrically confirmed with ease. | 2008-12-04 |
20080298145 | ANTIFUSE REPLACEMENT DETERMINATION CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY DEVICE - An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed; a comparison and determination circuit for comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and a determination part for deter g, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination circuit, whether or not replacement of the bad memory cell has been performed normally by using the antifuse element. | 2008-12-04 |
20080298146 | MEMORY REDUNDANCE CIRCUIT TECHNIQUES - In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof. | 2008-12-04 |
20080298147 | Semiconductor memory - To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output circuits of the signal terminals; test-purpose signal terminals fewer than the signal terminals; a selection portion which, as data to be written to the memory cells, selects data input from the signal terminals or data input from the test-purpose signal terminals, and repetitively allocates inputs of the test-purpose signal terminals to inputs of the signal terminals based on an arrangement of the signal terminals; and a test-purpose power source terminal connected to the power source terminal, and arrangement intervals of the test-purpose signal terminals and the test-purpose power source terminal are larger than an arrangement interval of the signal terminals. | 2008-12-04 |
20080298148 | Semiconductor memory device and test method therefor - There is disclosed a semiconductor memory device in which, activation timing control of a plurality of word lines of a plurality of ports is managed based on a plurality of clock signals, test signals are provided in association with the plurality of clock signals respectively controlling the activation timings of the word lines of the plurality of ports. If, with the cell, with the plurality of ports selected, the one test signal is in an activated state and the other test signal is in a non-activated state, activation of word lines of the plurality of ports is controlled in response to one clock signal, with the other clock signal being then masked. The timing difference, inclusive of the zero timing difference, between the activation timing of the plurality of word lines of the plurality of port may be finely adjusted by a delay control signal. | 2008-12-04 |
20080298149 | CURRENT REDUCTION WITH WORDLINE BIT LINE SHORT-CIRCUITS IN DRAMS AND DRAM DERIVATIVES - An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line. | 2008-12-04 |
20080298150 | Semiconductor device - A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the DRAM cell. A power supply circuit supplies the power supply voltages to the sense amplifier. A sense amplifier dummy circuit provides a replica of a state of the sense amplifier immediately after the activation of the sense amplifier; and a power supply control circuit controls the power supply circuit based on the replica such that the power supply voltages are varied with time. | 2008-12-04 |
20080298151 | Sense Amplifier Overdriving Circuit and Semiconductor Device Using the Same - A sense amplifier overdriving circuit includes a first voltage driver which supplies an internal voltage from an internal voltage terminal to a sense amplifier in response to a first enabling signal, a logic unit which logically operates a block select signal for selection of a cell block and a second enabling signal enabled for a predetermined time after enabling of the first enabling signal, and outputs the resultant signal, and a second voltage driver which supplies an external voltage to the internal voltage terminal in response to the signal output from the logic unit. A semiconductor device using the sense amplifier overdriving circuit is also disclosed. | 2008-12-04 |
20080298152 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed. | 2008-12-04 |
20080298153 | Semiconductor memory device - The present invention provides a semiconductor memory device with an open bit line structure in which sense amplifiers are arranged in a zigzag pattern and a plurality of banks, each having a plurality of mats, are provided. The semiconductor memory device includes: a refresh counter that counts the number of refresh commands and generates word line addresses; pre-decoders, each of which is provided for a corresponding bank, and which pre-decodes the word line address and outputs a pre-decode signal for selecting a mat row; bit arrangement changing circuits each of which changes the arrangement of bits of the pre-decode signal when a refresh signal indicating a refresh operation is input; and X decoders each of which outputs signals for driving a mat row and a word line according to the pre-decode signal and the word line address. | 2008-12-04 |
20080298154 | Semiconductor memory device - A semiconductor memory device includes: a plurality of banks each of which includes a plurality of mats each having normal word lines and redundant word lines; a first refresh generating circuit that generates a first refresh start signal for performing a first refresh operation in response to input of a refresh command; and a second refresh generating circuit that generates a second refresh start signal for performing a second refresh operation in response to a refresh operation end signal indicating that the first refresh operation ends. | 2008-12-04 |
20080298155 | SEMICONDUCTOR MEMORY DEVICE COMPENSATING LEAKAGE CURRENT - A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off. | 2008-12-04 |
20080298156 | SEMICONDUCTOR DEVICE UNDERGOING DEFECT DETECTION TEST - A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode. | 2008-12-04 |
20080298157 | MULTI-DIE PACKAGED DEVICE - A packaged multi die device includes at least one memory die. The one or more of the memory dice includes a memory function circuit configured to program or read data, a logic circuit configured to control the program operation and the read operation of the memory function circuit in accordance with an inputted operation command, and a power supplying circuit configured to provide a power corresponding to an operation mode to the memory function circuit, and apply an extra power to the logic circuit. | 2008-12-04 |
20080298158 | TWO TRANSISTOR WORDLINE DECODER OUTPUT DRIVER - A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal. | 2008-12-04 |
20080298159 | SEMICONDUCTOR INTEGRATED CIRCUIT - An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced. | 2008-12-04 |
20080298160 | Asphalt Reactor and Blending System - A modified asphalt Contactor reactor for blending and reacting asphalt cement and modifiers is described; for example, a vertically oriented vessel having an outer shell having an internal surface and an external surface, a lower end and a flat flanged top; an internal circulation tube having a base, a top and an outside surface, wherein the outside surface of the internal circulation tube and the internal surface of the outer shell forms an annulus; a heating jacket having heating oil inlet and a heating oil outlet coupled to the external surface of the outer shell for circulation of heating oil; and a hydraulic head assembly having an impeller coupled to the lower end the vertically oriented vessel wherein the impeller is located near the base of the internal circulation tube, wherein the impeller and the annulus are of sufficient size to facilitate the flow of high viscosity fluids. | 2008-12-04 |
20080298161 | MIXING HEAD WITH CREEP BARRIER ON THE CLEANING PISTON - A mixing head includes a mixing device which is secured to a housing and has a mixing chamber for mixing at least two plastic components to form a material mixture. Received in a recess of the housing is a cleaning device which has a cleaning piston for back-and-forth movement in relation to the mixing chamber between a first position in which the cleaning piston is retracted from the mixing chamber and a second position in which the cleaning piston extends into the mixing chamber. The cleaning device has a barrier which interacts with a housing wall for pushing the material mixture radially outside. The barrier has a flank which has an incline which is steeper than an incline of the housing wall. | 2008-12-04 |
20080298162 | Test-Tube Agitation Device, Comprising Means for the Optical Detection of a Test-Tube - A powered test-tube agitation device ( | 2008-12-04 |
20080298163 | Vibration Assisted Mixer - An embodiment of a mixer for mixing a powder with a liquid comprises a mix housing to accommodate a mixture of the powder and the liquid, a liquid delivery housing coupled to the mix housing to provide the liquid thereto, and a powder delivery housing coupled to the mix housing to provide the powder thereto, wherein the mixer is configured to induce a vibration therein for substantially avoid an occluding cake build-up of the mixture thereat. | 2008-12-04 |
20080298164 | Cordless Mixer - A cordless kitchen appliance ( | 2008-12-04 |
20080298165 | Method for Preparing a Silicate-Based Foam, Device for Using this Method, Aerosol Can and Foam Product Obtained by the Method - Method for preparing a silicate-based foam by mixing the silicate anti a pressurized carrier gas, characterized in that an accelerator, which causes the silicate to harden by chemical reaction, is added to the silicate. The accelerator can be selected from acids and acid-forming substances. While retaining the good properties and possible applications of the foam prepared in accordance with the prior art, this foam is improved by preparing a solid foam, i.e. a foam which remains foam after drying. This solid foam, inherently, i.e. without any reinforcing agent or filler, has a good dimensional stability. Devices for applying the method, an aerosol can in which the method is applied, and a prepared foam product. | 2008-12-04 |
20080298166 | Method and Apparatus for Preparation of Granulated Material - An apparatus for preparing samples of granulated material comprises an upper vessel having a floor including a plurality of planks, slots between each plank, and an open ceiling to allow passing of homogenized material, a lower vessel under the upper vessel and having a plurality of division plates that fit in the slots and form a plurality of compartments which hold samples, a feeder which oscillates over the upper surface of the upper vessel to render a homogenised and representative sample. The method comprises positioning the lower vessel under the upper vessel, feeding material to be sampled through the feeder by an oscillating movement, raising the lower vessel such that the division plates partition the heap of material to form a plurality of samples, removing planks from the upper vessel, thus forcing the plurality of samples to fall toward the compartments, and separating both the vessels to remove the samples. | 2008-12-04 |
20080298167 | Device for manufacturing ready-to-use knifing filler by mixing a binder and hardener component | 2008-12-04 |
20080298168 | Mixing vessels system and related methods - A system and methods for maintaining separation between substances such that the substances can be mixed as needed. The substances may be a liquid or a solid and may be edible or non-edible. More specifically, the present invention is directed to a system and methods that include an apparatus including at least two vessels, an additive vessel and a receiving vessel, for maintaining the separation of the substances and facilitating the mixing of the substances as needed. | 2008-12-04 |
20080298169 | ENCLOSURE FOR A BLENDING TOOL OF A MIXING DEVICE - A mixing device configured for shipment and/or storage includes a base housing at least one motor, a jar removably mountable to the base in an operating configuration for containing foodstuff, and a blade assembly loosely positioned in the jar. The blade assembly has a first surface and an opposing second surface. The second surface of the blade assembly operatively engages that at least one motor in the operating configuration. The device further includes a blending tool operatively connected to the first surface of the blade assembly and an enclosure removably mountable to the first surface of the blade assembly to enclose the blending tool. | 2008-12-04 |
20080298170 | STIRRER AND APPARATUS FOR SMALL VOLUME MIXING - This invention is a stirrer, impeller or stirrer paddle used for mixing small volumes of liquid in a vessel having a small capacity for liquid, said impeller being characterized by an impeller blade connected to the bottom portion of a support, where the blade has an opening extending through the blade from the front to the back surface of the blade said opening extending across the rotational axis of the impeller. The invention is also an apparatus comprising that blade, a method of mixing components using the apparatus and an array of two or more of the apparatuses. | 2008-12-04 |
20080298171 | Process for Mixing and Screening Liquid Compositions - A process for mixing one or more liquid compositions comprising the steps of:
| 2008-12-04 |
20080298172 | BLENDER APPARATUS WITH ALTERNATE BLADE MECHANISMS - A blender apparatus ( | 2008-12-04 |
20080298173 | Wide area seabed analysis - A seabed region ( | 2008-12-04 |
20080298174 | Method for determining seismic anisotropy - The method disclosed is useful for estimating anisotropic properties of an earth formation. The method includes extracting travel time values of components of the acoustic wave induced from a downhole tool and reflected from a boundary bed formation. The method further includes obtaining a travel time ratio of the wave components and using the travel time ratio to estimate the anisotropic properties of the formation. | 2008-12-04 |
20080298175 | Waterproof Membrane Cover for Acoustic Arrays in Sodar Systems - A waterproof or water-resistant membrane cover for the acoustic transducer array of a sodar system. The membrane is placed over each transducer of the array. The membrane may be spaced from the array, with a structure such as a frame used to hold the membrane in place relative to the array. | 2008-12-04 |
20080298176 | Systems and methods of identifying/locating weapon fire using envelope detection - A system and method for detecting, identifying, and fixing the location of the source of an acoustic event. The inventive system includes: a plurality of sensors dispersed at somewhat regular intervals throughout a monitored area; a communication network adapted to deliver information from the sensors to a host processor; and a process within the host processor for determining, from the absolute times of arrival of an event at two or more sensors, a position of the source of the event. Acoustic events are detected and analyzed at each sensor so that the sensor transmits over the network: an identifier for the sensor; an identifier for the type of event; and a precise absolute time of arrival of the event at the sensor. In a preferred embodiment, the system also identifies the type of weapon firing a gunshot. | 2008-12-04 |
20080298177 | SUBMERSIBLE LOUDSPEAKER ASSEMBLY - A submersible loudspeaker assembly is provided. The loudspeaker assembly includes: a housing; a loudspeaker enclosed within the housing; an external diaphragm disposed adjacent to the loudspeaker. The external diaphragm is acoustically transparent when subject to ambient air pressure, but configured to flex towards the loudspeaker when submerged in water. | 2008-12-04 |
20080298178 | Clockwork Movement - A clockwork movement includes a control member actuatable by a control lever in response to a user's action and having the form of a column wheel. The control member is rotatably mounted on the clockwork movement frame around an axis X, perpendicular thereto, for controlling first and second mechanisms exhibiting at least one movement function such as chronograph or alarm function. The control member includes rotationally fixable first, second and third parts which are mounted on a shaft at first, second and third levels, respectively, in a direction of the axis X for interacting with the control lever and for controlling the mechanisms. The shaft which is pivotally mounted with respect to the frame is arranged in at least two bearings, which are positioned remotely to each other for ensuring the shaft good stability, whereas the second and third parts are located on the both parts of the frame. | 2008-12-04 |
20080298179 | High-Performance Lever Escapement - The invention concerns an escapement ( | 2008-12-04 |
20080298180 | LEVER ESCAPEMENT FOR A TIMEPIECE - The escapement includes an escape wheel set ( | 2008-12-04 |
20080298181 | OPTICAL DISC APPARATUS AND OPTICAL DISC APPARATUS CONTROL METHOD - According to one embodiment, a control method, includes moving a pickup head to an adjustment position adjusting the quantity of adjustment of focus balance measuring the amplitude of an RF signal in the adjustment position adjusting the focus balance adjustment quantity and measuring the RG signal amplitude a plurality of times estimating the focus balance adjustment quantity at which the RF signal amplitude is maximized from the measured focus balance adjustment quantities and RF signal amplitude moving the pickup head to a different adjustment position estimating the focus balance adjustment quantity at which the RF signal amplitude is maximized in the different adjustment position by adjusting the focus balance adjustment quantity and measuring the RF signal amplitude a plurality of times and adjusting the focus balance adjustment quantity to the focus balance adjustment quantity estimated in the different adjustment position. | 2008-12-04 |
20080298182 | METHOD AND APPARATUS TO DETECT LAND/GROOVE SWITCH POSITION IN SEEK MODE, AND OPTICAL DISK DRIVE USING THE SAME - A land/groove switch position detecting method includes measuring information about a land/groove switch generation timing of a disc, using a first signal having a frequency that varies in proportion to a rotation speed of the disk in a normal playback mode, and a second signal having a predetermined frequency higher than the frequency of the first signal, and calculating a predicted land/groove switch generation position in the seek mode, using the information about the land/groove switch generation timing. | 2008-12-04 |
20080298183 | Method and Device for Tilt Compensation In an Optical Storage System - The invention relates to a tilt controller for controlling the tilt (radial and/or tangential) of an actuator relative to a recording surface of an optical storage medium, compensation for the radial to tilt crosstalk being effected by feeding a filtered version of the radial control signal (r) into the tilt branch, and/or compensation for the focus to tilt crosstalk being effected by feeding a filtered version of the focus control signal (f) into the tilt branch. | 2008-12-04 |
20080298184 | OPTICAL DISC RECORDING SYSTEM - An optical disc recording system includes a host apparatus configured to issue commands; and an optical disc recording apparatus configured to carry out a process corresponding to each of the commands, and to reply a response data to the command to the host apparatus. The host apparatus issues a record command as one of the commands to record a record data in an optical disc medium, and an optical disc recording apparatus records the record data in a data area in a predetermined format in response to the record command, wherein the optical disc comprises the data area and a first control data recording area. The optical disc recording apparatus additionally sets each of second control data recording areas in the data area in association with a command from the host apparatus as one of the commands, and a record status control data is recorded in the first or second control data recording area to indicate record status of the record data. At least a part of a second control data recording area associated data with at least one of the second control data recording areas is shared by the host apparatus and the optical disc recording apparatus. | 2008-12-04 |
20080298185 | Information Recording Device, Information Recording Method, and Information Recording Program - Accurate calibration of recording power is performed without exceeding a rated output value of a laser diode even if recording speed is increased and high recording power is required. An information recording apparatus records information on an information recording medium such as a DVD-R/RW or a DVD+R/RW by applying a laser light onto the information recording medium. A pickup has a laser light source. A light receiving unit for detecting the amount of light by receiving the laser light emitted from the laser light source is provided, and the power of the laser light is controlled based on the power of the detected laser light. Before the actual information recording, a test emission is performed during calibration to determine an adequate recording power, and the emission duty of the laser light is controlled within the range not exceeding the rated output value of the laser light source. | 2008-12-04 |
20080298186 | Disk Drive With Multiple Level Power Reduction During Write - A disk drive data storage system comprising at least one data storage disk and a sensor assembly proximate the data storage disk. The sensor assembly further comprises circuitry for writing data to the data storage disk and circuitry for reading data from the data storage disk. The system also comprises circuitry for controlling the circuitry for reading data during different time periods so that the circuitry for reading data consumes different levels of power while the circuitry for writing data is writing data to the data storage disk. | 2008-12-04 |
20080298187 | OPTICAL DISC DEVICE AND RECORDING POWER CONTROL METHOD - An optical disc device and recording power control method that can ensure the recording quality of data recorded on an optical disc are suggested. When recording data on an optical disc, data recorded on the optical disc is reproduced periodically; a β value, an index of recording quality of the data on the optical disc, is obtained based on a waveform of the reproduced data; a correction factor of recording power is calculated based on the obtained β value, and the recording power is corrected according to the correction factor; at the same time, a recording area of the optical disc is divided into a plurality of zones and the correction factor for each zone is managed; and the recording power is corrected according to the correction factor of the zone where data is to be recorded next on the optical disc. | 2008-12-04 |
20080298188 | Device for and Method of Recording Information on a Record Carrier - A recording device for recording information at addressable locations on a removable record carrier for storing data. The device comprises monitoring means ( | 2008-12-04 |
20080298189 | METHOD AND AN APPARATUS FOR RECORDING INFORMATION, AND AN INFORMATION RECORDING MEDIUM - In a method for recording information on an information recording medium having a data recording area for storing user data and a test area used for test recording by a recording apparatus, it is detected whether the test area is unusable when executing the test recording. The test recording is executed in the test area when the test area is detected not to be unusable, or executed in the data recording area when detected to be unusable. Management information relating to the test recording executed in the data recording area is recorded in a predetermined area. Hence, it is possible to eliminate a limit of number of times of test recording which depends on the size of the test recording area. | 2008-12-04 |
20080298190 | OPTICAL DISK APPARATUS AND OPTICAL DISK PROCESSING METHOD - According to one embodiment, an optical disk apparatus is provided with a read section which reads data from an optical disk to output read information, a determination section which determines presence/absence of an error of the read information to output an error presence/absence signal, a transfer processing section which receives the error presence/absence signal and receives a hash request signal and transfers the hash request signal when the error presence/absence signal indicates the absence of an error, and does not transfer the hash request signal when the error presence/absence signal indicates the presence of an error, and a processing section which performs hash processing to the read information upon reception of the hash request signal. | 2008-12-04 |
20080298191 | Method and System for Thermal Management in an Optical Storage System - The invention relates to a control method and system ( | 2008-12-04 |
20080298192 | Method and System for Adjusting the Pitch of Light Spots Used to Read an Information Carrier - The invention relates to a method and system for adjusting the pitch of an array of light spots ( | 2008-12-04 |
20080298193 | OPTICAL DISC, OPTICAL DISC UNIT AND METHOD OF CONTROLLING THE OPTICAL DISC UNIT - When a laser light focal point, driven by an objective lens, passes through each of a plurality of recording layers of an optical disc, data recorded on the recording layers through which the focal point passes may be deteriorated due to a difference in optical sensitivity for each recording layer or the like. In a focal point position movement in which switching of recording layers is made by a focus error signal, when the focal point position moves from a recording layer on which a laser light is focused to another recording layer which is not adjacent, light intensity or light density at the focal point is reduced in accordance with the recording layer to be passed through, thus deterioration of the data on the optical disc being prevented. | 2008-12-04 |
20080298194 | Optical disc apparatus and data recording method thereof - In order to ensure recording quality while suppressing the adverse effects due to performance variations among apparatuses and disc radial positions on an optical disc, an optical disc apparatus according to the present invention performs, at the time of data recording, the steps of: acquiring a jitter value and β value from a reproduced signal based on laser light reflected from the optical disc in relation to a disc radial position; learning a β value when the acquired jitter value is a minimum as a target β value; and, if a jitter value acquired thereafter is larger than the minimum jitter value by a preset reference value or above, correcting recording power based on the magnitude relation and the difference between the β value associated with the acquired jitter value and the target β value or performing trial record processing. | 2008-12-04 |
20080298195 | Optical recording method and optical recording device - To adjust the parameters of a write strategy for recording data on an optical recording medium, the jitter value of a reproduced signal obtained from recorded data is detected. If the jitter value exceeds a prescribed threshold, a write strategy parameter having a comparatively small effect on the jitter value is adjusted, and subsequent data are written on the recording medium using the adjusted parameter. Parameters are selected for adjustment in ascending order of their effect on the jitter value. Stable data recording can thereby be carried out without significant jitter degradation. | 2008-12-04 |
20080298196 | Mapping Defects on a Data Wedge Basis - A method to map defects is provided. A select data track of a storage medium is scanned for a defect. At least one data wedge affected by the defect on the select data track is identified. Each data wedge includes available area for writing user data defined between two servo wedges that include position information. The at least one affected data wedge is identified as unusuable. | 2008-12-04 |
20080298197 | CONTROLLING A HEAT RESISTIVE ELEMENT WITH A PULSE MODULATED SIGNAL - The disclosure is related to pulse width modulating a power signal to a heat resistive element of a transducer. The power signal may be a power output signal of preamplifier. The power signal may be provided to a heat resistive element in a transducer that is operable to read data from or write data to a data storage medium. The pulse width modulated power signal can allow for controlling the heating of the heat resistive element based on a thermal time constant of the heat resistive element and based on adjustable components of the pulse width modulated power signal. | 2008-12-04 |
20080298198 | OPTICAL RECORDING APPARATUS AND METHOD FOR OPTIMIZING RECORDING SIGNAL - An exemplary method for optimizing a recording signal of an optical recording apparatus to record data onto a disc, the recording signal having a first pulse-width parameter, the method includes selecting an initial value of the first pulse-width parameter; generating adjusted values based on the initial value to record test data onto the disc respectively; measuring mark lengths of lands; determining average lengths of the mark lengths of lands; determining differences between the average lengths and a predetermined standard length; linear curve fitting the adjusted values and the differences employing the following linear curve fitting equation: Y=AX+B to obtain the constants A and B, wherein X represents the adjusted values, Y represents the differences; determining and storing an optimum value of the first pulse-width parameter to be used for recording the data onto the disc, this optimum value equals to −B/A. An optical recording apparatus is also provided. | 2008-12-04 |
20080298199 | WRITING STRATEGY PARAMETERS INDEXING METHOD AND RECORDING APPARATUS THEREFOR - A writing strategy parameters indexing method and a recording apparatus therefor. The writing strategy parameters indexing method includes operations of receiving an NRZ sequence; moving the NRZ sequence by as much as a bit with respect to a channel block using a slide-window having a length of N bits; determining whether a bit pattern of the NRZ sequence in the window-slide has a predetermined bit pattern; extracting writing strategy parameters corresponding to the predetermined bit pattern when the bit pattern of the NRZ sequence in the window-slide has the predetermined pattern; and generating recording pulses using the writing strategy parameters. | 2008-12-04 |
20080298200 | RECORDING METHOD AND APPARATUS USING WRITE PULSE WAVEFORMS - A data recording method according to the present invention is a method for recording data as edge position information, including marks and spaces of multiple different lengths, on a storage medium by irradiating the storage medium with a pulsed energy beam. The method includes the steps of: (A) generating a write code sequence based on the data to be recorded; (B) determining a write pulse waveform, defining the power modulation of the energy beam, according to the code lengths of respective codes included in the write code sequence; and (C) modulating the power of the energy beam based on the write pulse waveform. If the shortest code length of the write code sequence is n (which is an integer equal to or greater than one), a write pulse waveform that has only one write pulse is assigned to recording mark making periods corresponding to codes with code lengths x of n, n+1 and n+2, and a write pulse waveform that has multiple write pulses Pw is assigned to recording mark making periods corresponding to codes with code lengths x of n+3 or more. | 2008-12-04 |
20080298201 | METHOD AND PROGRAM FOR OBTAINING AND SETTING OF RECORDING SETTING INFORMATION, AND DATA RECORDING/PLAYBACK DEVICE - A method for obtaining and setting recording setting information, including: obtaining device identification information of an optical disc recording/playback device; transmitting a recording setting information request signal including at least the device identification information to a server connected through a network; receiving recording setting information corresponding to at least the device identification information transmitted from the server based on the recording setting information request signal; and storing the received recording setting information in memory within the optical disc recording/playback device. Thus, for example, recording setting information as to all of optical discs may be obtained and set as much as possible in a case wherein access to the server can be performed, whereby even a case can be handled wherein data recording is carried out as to various types of optical discs later. | 2008-12-04 |
20080298202 | RECORDING APPARATUS AND RECORDING METHOD - According to one embodiment, there is provided a recording apparatus including a recording unit which copies first contents with a first number of producible copies and records second contents with a second number of producible copies in a recording region, and a management unit which arbitrarily distributes the second number of producible copies from the first number of producible copies when the recording unit copies the first contents to record the second contents in the recording region and, thereby rewrites the first number of producible copies with a new first number of producible copies subtracted by the distributing process and the copy process of the contents. | 2008-12-04 |
20080298203 | OPTICAL INFORMATION RECORDING MEDIUM AND METHOD OF FABRICATING THE SAME - Proposed are a method of fabricating an optical information recording medium that can prevent the degradation of the appearance caused by a hardening resin entering between a center cap and a substrate due to capillary action, and an optical information recording medium using a substrate for implementing the method. | 2008-12-04 |
20080298204 | Optical disc drive apparatus - An optical disc drive apparatus, for recording/reproducing upon/from an optical disc medium having a plural number of recording layers, comprises a recording/reproducing element, which is configured to irradiate a laser upon the optical disc medium, to as to conduct recording/reproducing thereon/from, wherein recording is conducted within a region of an arbitrary range on the optical disc medium by means of the recording/reproducing element, and the region is used for moving an optical spot of the laser irradiated from the recording/reproducing element when recording/reproducing data thereon/from. | 2008-12-04 |
20080298205 | OPTICAL DISC APPARATUS AND OPTICAL DISC DISTINGUISHING METHOD - According to one embodiment, an optical disc distinguishing method includes irradiating the loaded optical disc with a light beam having one of a first to third wavelengths, determining whether the loaded optical disc belongs to a first group consisting of a first to third optical discs or a second group consisting of two kinds of optical discs which do not correspond to the wavelength of the irradiated light beam, identifying the loaded optical disc as one of the first to third optical discs, irradiating the loaded optical disc with one of the two kinds of the light beams except for the light beam with which the loaded optical disc is irradiated in making the determination of the group when the loaded optical disc belongs to the second group, and identifying the loaded optical disc as one of the two kinds of the optical discs belonging to the second group. | 2008-12-04 |
20080298206 | WRITE-ONCE READ-MANY INFORMATION RECORDING MEDIUM, INFORMATION RECORDING METHOD, INFORMATION REPRODUCTION METHOD, INFORMATION RECORDING APPARATUS, AND INFORMATION REPRODUCTION APPARATUS - A write-once read-many information recording medium is provided, which is capable of easily searching for a latest DDS and a latest defect list. At least one disc management working area is sequentially allocated in a predetermined direction on the write-once read-many information recording medium of the present invention. The latest defect list and the latest DDS are provided in a recorded disc management working area neighboring a border between the recorded disc management working area and an unrecorded disc management working area, where the latest defect list precedes the latest DDS in the predetermined direction. | 2008-12-04 |
20080298207 | Reproduction Device and Reproduction Method - Reproduction reference light is irradiated on a hologram recording medium on which imaged digital data are recorded as a plurality of element holograms in the form of interference fringes obtained by interference between object light of the digital data and recording reference light. Then, a reproduction image obtained from the hologram recording medium by the irradiation of the reproduction reference light is detected. Then, readout data are produced based on the detected reproduction image. Thereafter, it is discriminated whether or not the readout data should be stored into a memory, and the readout data are stored into the memory in response to a result of the discrimination. Where a predetermined amount or more of the data is accumulated in the memory, reproduction data are produced from the readout data accumulated in the memory and then reproduced. | 2008-12-04 |
20080298208 | OPTICAL HEAD AND OPTICAL DISC APPARATUS - An optical head includes semiconductor lasers for 455 nm, 655 nm, and 785 nm bands; a polarization change element and a polarizing beam splitter for luminous flux with a wavelength of 455 nm band, a first collimation lens for converting luminous flux having passed through the polarizing beam splitter into parallel flux, a first quarter-wave plate, a BD objective for focusing the flux onto a signal recording surface of BD, a first photo-detector for receiving light reflected by BD, a composite prism for reflecting flux reflected by the splitter and transmitting most of flux from the lasers for 655 nm and 785 nm bands, a second collimation lens for converting flux emitted from the composite lens into parallel flux, a second quarter-wave plate, an objective compatible with HD DVD, DVD, and CD; and a second photo-detector for receiving light reflected by HD DVD, DVD, and CD. | 2008-12-04 |
20080298209 | FOCUSING CONTROL METHOD FOR READING/WRITING OPTICAL DISC - An optical reading/writing apparatus has an optical head that includes a collimator and a lens. For efficient and reliable focusing control for writing an empty optical disk, calibration of focus offset and spherical aberration is executed by setting a boundary and performing data-reading in an OPC area only with combinations of focus offset and spherical aberration within the boundary. Accordingly, an optimum combination of focus offset and spherical aberration is determined for focusing compensation in subsequent writing operation of the empty disk. | 2008-12-04 |
20080298210 | OPTICAL PICKUP AND OPTICAL DISC APPARATUS - An optical pickup free from tracking error signal variation when playing back a double-layered disc, and coping with incompatible optical discs, such as BDs and HD DVDs, includes a laser light source, a first polarization rotation element for rotating a polarization direction of an optical beam from the source, an optical branching element disposed in a position after the polarization rotation element to reflect or transmit an optical beam according to polarization of the beam, first and second object lenses for focusing the reflected and transmitted optical beams onto first and second optical discs, respectively, a photodetector for sensing reflected light from the first and second optical discs, and a second polarization rotation element disposed after reflection or transmission of the reflected light from the first and second optical discs conducted by the branching element, to rotate a polarization direction of the reflected light. | 2008-12-04 |
20080298211 | Disc Device - A disc device includes a lens that focuses a laser light on an optical disc surface, a focus drive unit that drives the lens in a focusing direction, a focus control unit that controls to focus the laser light on the optical disc surface, a focus displacement detecting unit that detects a displaced amount in the focusing direction, a differentiation unit that differentiates a focus displacement detected signal, and a unit that inverts a sign of a differentiated signal, thereby, the disc device is driven intermittently to restrain a motion of an objective lens in a focusing direction and avoid colliding the objective lens with the optical disc surface. | 2008-12-04 |