49th week of 2020 patent applcation highlights part 65 |
Patent application number | Title | Published |
20200381501 | DOUBLE-SIDED DISPLAY PANEL, FABRICATING METHOD OF SAME, AND DISPLAY DEVICE - A double-sided display panel and a method of fabricating the same are provided. The double-sided display panel is an organic light emitting diode (OLED) device with two structures of bottom emission and top emission on a single thin film transistor (TFT) substrate. An OLED display mode combines two different driving structures of active matrix organic light emitting diodes and passive matrix organic light emitting diodes, such that an OLED display realizes double-sided display performance, and has a high-resolution performance on one side and a basic display performance on another side. | 2020-12-03 |
20200381502 | DISPLAY DEVICE - A display device includes a window, a display panel arranged below the window and including a display area and a peripheral area outside the display area; and a component arranged below the display panel and at least partially overlapping the peripheral area, wherein a black matrix is arranged on a bottom surface of the window in correspondence with an area in the peripheral area other than an area where the component is located. | 2020-12-03 |
20200381503 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display (OLED) device includes an organic light emitting diode having an anode and a cathode. The organic light emitting diode is configured to receive a reference voltage. A control transistor includes a first control electrode and a first semiconductor active layer. The control transistor is configured to receive a control signal. A driving transistor includes a second control electrode that is electrically connected to the control transistor, an input electrode that is configured to receive a power voltage, an output electrode that is electrically connected to the anode of the organic light emitting diode, and a second semiconductor active layer that includes a different material from that of the first semiconductor active layer. A shielding electrode is disposed on the second semiconductor active layer, overlapping the driving transistor, and configured to receive the power voltage. | 2020-12-03 |
20200381504 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device including: a substrate; an active layer, and including channel and conductive regions and; a first conductive layer including a driving gate electrode and a scan line in a first direction; a second conductive layer including a storage line; a third conductive layer including a first connecting member above the storage line; an insulating layer between the storage line and the first connecting member; and a data line and a driving voltage line crossing the scan line in a second direction, wherein the first connecting member electrically connects the driving gate electrode and a conductive region, the driving voltage line overlaps the first connecting member, the insulating layer includes first and second sub-insulating layers, and an edge of the second sub-insulating layer substantially overlaps an edge of the first connecting member in a thickness direction of the display device. | 2020-12-03 |
20200381505 | DISPLAY DEVICE - A display device may include a substrate, a pixel, a transistor, a data line, a connection line, a pad, and an electrostatic discharge protection circuit. The substrate may include a display area and a pad area. The pad area may overlap the display area. The pixel may be supported by the display area and may include a pixel electrode. The data line may be electrically connected through the transistor to the pixel electrode. The connection line may be supported by the display area and may be electrically connected through the data line to the transistor. The pad may be supported by the pad area and may be electrically connected through the connection line to the data line. The display area and the pad area may be positioned between the connection line and the pad. The electrostatic discharge protection circuit may be electrically connected to the connection line. | 2020-12-03 |
20200381506 | DISPLAY DEVICE - A display device includes: a substrate comprising a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area and in the first column, a third portion extending along a second column of the display area and in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area and connected to the third portion of the first connection line and a data line in a third column of the display area. | 2020-12-03 |
20200381507 | DISPLAY DEVICE - The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view. | 2020-12-03 |
20200381508 | DISPLAY DEVICE - A display device includes a first substrate having a display area and a non-display area. The first substrate includes a conductive line in the non-display area. A second substrate faces the first substrate and is spaced apart from the first substrate. A conductive layer is disposed between the first substrate and the second substrate. The conductive layer is spaced apart from the first substrate in a direction perpendicular to a top surface of the first substrate. The conductive layer at least partially overlaps the conductive line and is electrically floated. | 2020-12-03 |
20200381509 | SEMI-INSULATING GALLIUM ARSENIDE CRYSTAL SUBSTRATE - A semi-insulating gallium arsenide crystal substrate has a main surface with a plane orientation of (100) and a diameter of 2R mm, the main surface having a specific resistance with an average value of 5×10 | 2020-12-03 |
20200381510 | MOSFET AND POWER CONVERSION CIRCUIT - A MOSFET according to the present invention includes a semiconductor base substrate having a super junction structure. A gate electrode is on a first main surface side of the semiconductor base substrate byway of a gate insulation film, wherein in a state where a total amount of dopant in an n-type column region differs from a total amount of dopant in a p-type column region, assuming a depth position where an average positive charge density ρ(x) becomes 0 as X | 2020-12-03 |
20200381511 | Semiconductor Device with Drain Structure and Metal Drain Electrode - A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer. | 2020-12-03 |
20200381512 | SHIELD STRUCTURE FOR BACKSIDE THROUGH SUBSTRATE VIAS (TSVS) - Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV. | 2020-12-03 |
20200381513 | SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES - The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below. | 2020-12-03 |
20200381514 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided. | 2020-12-03 |
20200381515 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region. | 2020-12-03 |
20200381516 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region. The first doped region and the second doped region surround a contact hole plug in the source-drain doped region, such that the contact hole plug is not easily in direct contact with the source-drain doped region, contact resistance between the contact hole plug and the source-drain doped region is reduced, and the electrical performance of the semiconductor structure is improved. | 2020-12-03 |
20200381517 | MULTI-SUPER LATTICE FOR SWITCHABLE ARRAYS - A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure. | 2020-12-03 |
20200381518 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device includes: a first nitride semiconductor layer constituting an electron transit layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and constituting an electron supply layer; a ridge-shaped gate portion formed on the second nitride semiconductor layer; and a source electrode and a drain electrode disposed on the second nitride semiconductor layer so as to face each other with the ridge-shaped gate portion interposed therebetween, wherein the ridge-shaped gate portion includes: a nitride semiconductor gate layer containing acceptor-type impurities and disposed on the second nitride semiconductor layer; a gate metal film disposed on the nitride semiconductor gate layer; a gate insulating film formed on the gate metal film; and a gate electrode capacitively-coupled to the gate metal film by the gate insulating film. | 2020-12-03 |
20200381519 | SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting substrate, a first GaN layer of a first conductivity type provided on the side of a first main surface of the supporting substrate, a second GaN layer of the first conductivity type provided on the first GaN layer, an AlxGa1−xN layer provided on the second GaN layer, a third GaN layer of a second conductivity type provided on the AlxGa1−xN layer, a fourth GaN layer of the first conductivity type provided on the third GaN layer, an insulating film covering a top of the fourth GaN layer, a trench gate reaching the inside of the second GaN layer, a gate electrode, a first main electrode connected to the third GaN layer, and a second main electrode, and the donor concentration of the third GaN layer is lower than that of the fourth GaN layer. | 2020-12-03 |
20200381520 | ASYMMETRIC THRESHOLD VOLTAGES IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being in contact with the inner spacer and with the other outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. The inner spacer is etched away. A gate stack is formed on the semiconductor fin, between the outer spacers. | 2020-12-03 |
20200381521 | DEVICES WITH LOWER RESISTANCE AND IMPROVED BREAKDOWN AND METHOD FOR PRODUCING THE SAME - Methods of forming a ferroelectric material layer below a field plate for achieving increased V | 2020-12-03 |
20200381522 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate electrode groove formed in contact with a drift region, a well region, and a source region; a gate electrode formed on a surface of the gate electrode groove via an insulating film; a source electrode groove in contact with the gate electrode groove; a source electrode electrically connected to a source region; and a gate wiring electrically insulated from the source electrode and formed inside the source electrode groove in contact with the gate electrode. | 2020-12-03 |
20200381523 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE - Embodiments of the present disclosure disclose a thin film transistor, a method for manufacturing a thin film transistor, an array substrate, and a display device. The thin film transistor includes a source electrode and a drain electrode, each of the source electrode and the drain electrode including a metal substrate and a conductive layer covering the metal substrate. An adhesion between the conductive layer and a photoresist material is larger than an adhesion between the metal substrate and the photoresist material. The metal substrate and the conductive layer are both formed on a base substrate, an orthographic projection of the conductive layer on the base substrate covers an orthographic projection of the metal substrate on the base substrate, and. an area of the orthographic projection of the conductive layer on the base substrate is larger than an area of the orthographic projection of the metal substrate on the base substrate. | 2020-12-03 |
20200381524 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE - Embodiments of the present disclosure provide a thin film transistor, a method of manufacturing the same, and a display device. The thin film transistor includes a metal conductive pattern layer, an interlayer insulating layer, and a metal oxide layer; and the metal conductive pattern layer includes: a light shielding pattern, a source signal line, and/or a drain signal line; the metal oxide layer includes: a source electrode, a drain electrode, and an active layer. An orthographic projection of the active layer on the base substrate has an overlapping region with that of the light shielding pattern; the source electrode extends through the interlayer insulating layer to connect to the source signal line, and/or the drain electrode extends through the interlayer insulating layer to connect to the drain signal line. | 2020-12-03 |
20200381525 | BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES OF DEVICES - An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device. | 2020-12-03 |
20200381526 | SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE AND SEPARATION STRUCTURE - A semiconductor device including a gate structure and a separation structure is provided. The semiconductor device includes: first and second active regions; an insulating layer between the first and second active regions; a first gate structure on the first active region and the insulating layer, the first gate structure having a first end portion on the insulating layer; a second gate structure on the second active region and the insulating layer, the second gate structure having a second end portion facing the first end portion in a first direction, the second gate structure on the insulating layer; and a separation structure between the first end portion and the second end portion and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction. | 2020-12-03 |
20200381527 | DRAIN AND/OR GATE INTERCONNECT AND FINGER STRUCTURE - Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect. | 2020-12-03 |
20200381528 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts. | 2020-12-03 |
20200381529 | Gate Structure, Semiconductor Device and the Method of Forming Semiconductor Device - A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack. | 2020-12-03 |
20200381530 | MULTI-GATE DEVICE AND RELATED METHODS - Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers. | 2020-12-03 |
20200381531 | MULTI-GATE DEVICE AND RELATED METHODS - Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers. | 2020-12-03 |
20200381532 | Method and Structure for FinFET Comprising Patterned Oxide and Dielectric Layer Under Spacer Features - A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer. | 2020-12-03 |
20200381533 | INTEGRATED ENHANCEMENT/DEPLETION MODE HEMT AND METHOD FOR MANUFACTURING THE SAME - An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer. | 2020-12-03 |
20200381534 | FINFET STRUCTURE WITH DOPED REGION - Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer. | 2020-12-03 |
20200381535 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACK - A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack. | 2020-12-03 |
20200381536 | FIN FIELD EFFECT TRANSISTOR DEVICES WITH ROBUST GATE ISOLATION - A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of vertical fins on a substrate, and forming at least two dummy gates across the plurality of vertical fins. The method further includes forming a masking block on one of the at least two dummy gates, and removing the portions of the at least two dummy gates not covered by the masking block, wherein the portion of the one dummy gate covered by the masking block forms a dummy gate plug. The method further includes forming a gate dielectric layer on the exposed surfaces of the plurality of vertical fins and dummy gate plug, and forming a conductive gate layer on the gate dielectric layer, wherein the dummy gate plug physically separates two active gate structures. | 2020-12-03 |
20200381537 | Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof - Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material. | 2020-12-03 |
20200381538 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench. | 2020-12-03 |
20200381539 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method includes etching a semiconductor substrate to form a plurality of semiconductor fins. The semiconductor fins are etched to form a recess. An epitaxy structure is grown in the recess. The epitaxy structure has a W-shape cross section. A capping layer is formed over the epitaxy structure. The capping layer is at least conformal to a sidewall of the epitaxy structure. The capping layer is etched to expose a top surface of the epitaxy structure. A first portion of the capping layer remains over the sidewall of the epitaxy structure after etching the capping layer. A contact is formed in contact with the exposed top surface of the epitaxy structure and the first portion of the capping layer. | 2020-12-03 |
20200381540 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE DEVICE - The disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. The semiconductor device includes: a substrate, the substrate being a silicon substrate or an SOI substrate; a SiGe Fin formed on the substrate, wherein the SiGe Fin is a sandwich-like Si | 2020-12-03 |
20200381541 | SPLIT GATE MEMORY CELL FABRICATION AND SYSTEM - A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface. | 2020-12-03 |
20200381542 | SEMICONDUCTOR DEVICE INCLUDING EMITTER REGIONS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region. | 2020-12-03 |
20200381543 | INTEGRATED ENHANCEMENT/DEPLETION MODE HEMT AND METHOD FOR MANUFACTURING THE SAME - An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer. | 2020-12-03 |
20200381544 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME - A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer. | 2020-12-03 |
20200381545 | Inner Spacers for Gate-All-Around Transistors - A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members. | 2020-12-03 |
20200381546 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability. | 2020-12-03 |
20200381547 | INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME - Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction. | 2020-12-03 |
20200381548 | TRANSISTOR WITH LOW LEAKAGE CURRENTS AND MANUFACTURING METHOD THEREOF - A transistor with low leakage currents includes a substrate, a gate, spacers, pad dielectric layers, a source, and a drain. The gate is formed above a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The spacers have a second dielectric constant. The pad dielectric layers are formed under the spacers and having a third dielectric constant. The source and the drain are adjacent to the spacers and in two opposite directions of the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other. | 2020-12-03 |
20200381549 | HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS - Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain. | 2020-12-03 |
20200381550 | TRANSISTOR STRUCTURE - A transistor is disclosed. In an embodiment a transistor includes a first semiconductor region of a substrate, a first trench delimiting the first semiconductor region on a first side, a first electrically-conductive element located in the first trench, a channel area in contact with the first semiconductor region and a first area of contact with the first semiconductor region, wherein the channel area and the first area of contact are on the same surface side of the substrate. | 2020-12-03 |
20200381551 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film. | 2020-12-03 |
20200381552 | TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions. | 2020-12-03 |
20200381553 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT (LDMOS) TRANSISTOR AND DEVICE HAVING LDMOS TRANSISTORS - A LDMOS transistor that may include (i) a first region that is a reduced surface field (RESURF) implant region of a first type; (ii) a second region that is a RESURF implant region of a second type, wherein the first type differs from the second type; (iii) a gate; (iv) a stepped oxide region and a gate oxide region that are positioned above the first region and below the gate. Each one of the first region and the second region has a substantially uniform thickness | 2020-12-03 |
20200381554 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first III-V compound layer, a gate electrode, drain trenches, and at least one drain electrode. The drain trenches are disposed and arranged with high integrity. The substrate has a first side and a second side opposite to the first side. The first III-V compound layer is disposed at the first side of the substrate. The gate electrode is disposed on the first III-V compound layer. Each of the drain trenches extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trenches are arranged regularly. The drain electrode is disposed in at least one of the drain trenches. | 2020-12-03 |
20200381555 | SEMICONDUCTOR DEVICES - Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si). | 2020-12-03 |
20200381556 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device having a high on-state current is provided. | 2020-12-03 |
20200381557 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor device includes an oxide semiconductor layer including indium (In), aluminum (Al), and zinc (Zn), the oxide semiconductor layer having an atomic ratio of the aluminum to a sum of indium, aluminum, and zinc of equal to or more than 8% and equal to or less than 23%, a gate electrode, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. | 2020-12-03 |
20200381558 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask. | 2020-12-03 |
20200381559 | SEMICONDUCTOR DEVICE WITH NEGATIVE CAPACITANCE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a negative capacitance (NC) material. The semiconductor device structure also includes a gate electrode layer, a gate dielectric structure, a source feature, and a drain feature. The gate dielectric structure covers the top surface and the opposing sidewall surfaces of the fin structure. The gate electrode layer is formed over the gate dielectric structure. The source feature and the drain feature are formed in and protrude from the fin structure, and separated from each other by the gate electrode layer. | 2020-12-03 |
20200381560 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides a thin film transistor, a fabricating method thereof, an array substrate, and a display device. The thin film transistor includes: a substrate; a channel region; a heavily doped first semiconductor pattern located on both sides of the channel region; a second semiconductor pattern disposed on the heavily doped first semiconductor pattern; a gate insulating layer covering the channel region and the second semiconductor pattern; a gate pattern disposed on the gate insulating layer, an orthographic projection of the gate pattern on the substrate being within an orthographic projection of the channel region on the substrate; and a source pattern and a drain pattern in contact with the heavily doped first semiconductor pattern through the first via and the second via, respectively. | 2020-12-03 |
20200381561 | THIN FILM TRANSISTOR COMPRISTING LIGHT SHIELDING LAYER AND LIGHT BLOCKING PORTION AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE - Embodiments of the present disclosure relate to a thin film transistor, a method for manufacturing the same, a display panel, and a display device. The thin film transistor includes a substrate, an active layer located on the substrate, and a light shielding layer, a first dielectric layer, and a second dielectric layer located between the substrate and the active layer, wherein the first dielectric layer is located between the second dielectric layer and the substrate, and wherein a refractive index of the first dielectric layer is greater than a refractive index of the second dielectric layer. | 2020-12-03 |
20200381562 | SEMICONDUCTOR DEVICES - A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels. | 2020-12-03 |
20200381563 | SEMICONDUCTOR DEVICES - A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer. | 2020-12-03 |
20200381564 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness. | 2020-12-03 |
20200381565 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer. | 2020-12-03 |
20200381566 | NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME - Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars. | 2020-12-03 |
20200381567 | PHOTOVOLTAIC DEVICES AND SEMICONDUCTOR LAYERS WITH GROUP V DOPANTS AND METHODS FOR FORMING THE SAME - A photovoltaic device ( | 2020-12-03 |
20200381568 | PHOTO-VOLTAIC ELEMENT AND METHOD OF MANUFACTURING THE SAME - A photo-voltaic element ( | 2020-12-03 |
20200381569 | WIRING MATERIAL, SOLAR CELL USING SAME, AND SOLAR CELL MODULE - A wiring member for transporting a carrier generated in a solar cell includes: an assembled wire that is an assembly of wires; and an insulating resin body that encapsulates the assembled wire and exhibits adhesion upon application of energy. | 2020-12-03 |
20200381570 | Eco-Friendly CuGaS2/ZnS Nanocrystals working as Efficient UV-Harvesting Down-Converter for Photovoltaics - Provided here nontoxic CuGaS | 2020-12-03 |
20200381571 | BIFACIAL P-TYPE PERC SOLAR CELL BENEFICIAL TO SUNLIGHT ABSORPTION AND PREPARATION METHOD THEREFOR - A bifacial P-type PERC solar cell beneficial to sunlight absorption and a preparation method therefor are provided. The solar cell includes consecutively, from the bottom up, a rear electrode ( | 2020-12-03 |
20200381572 | BIFACIAL PUNCHED PERC SOLAR CELL AND MODULE, SYSTEM, AND PREPARATION METHOD THEREOF - A bifacial punched PERC solar cell comprises a rear silver busbar ( | 2020-12-03 |
20200381573 | HIGH RADIATION DETECTION PERFORMANCE FROM PHOTOACTIVE SEMICONDUCTOR SINGLE CRYSTALS - Methods and devices for detecting incident radiation are provided. The methods and devices use high quality single-crystals of photoactive semiconductor compounds in combination with metal anodes and metal cathodes that provide for enhanced photodetector performance. | 2020-12-03 |
20200381574 | OPTICAL SENSING CHIP PACKAGING STRUCTURE - An optical sensing chip packaging structure includes a substrate, an optical sensing member, a light emitting member, a transparent glue layer and a transparent cover plate, wherein the optical sensing member is positioned on the substrate; the light emitting member is positioned on the optical sensing member, and the light emitting member includes a light emitting surface; the transparent glue layer is positioned on the light emitting member, and contacts and covers the light emitting surface; the transparent cover plate is positioned on the transparent glue layer. | 2020-12-03 |
20200381575 | INTERCONNECTION OF NEIGHBORING SOLAR CELLS ON A FLEXIBLE SUPPORTING FILM - A solar cell assembly comprising a plurality of solar cells and a flexible support, the support comprising a conductive layer on the top surface thereof divided into two electrically isolated portions—a first conductive portion and a second conductive portion. Each solar cell comprises a front surface, a rear surface, and a first contact on the rear surface and a second contact on the front surface. Each one of the plurality of solar cells is placed on the first conductive portion with the first contact electrically connected to the first conductive portion so that the solar cells are connected through the first conductive portion. A second contact of each solar cell can be connected to the second conductive portion. The two conductive portions serve as bus bars of two different polarities of the solar cell assembly. | 2020-12-03 |
20200381576 | MANUFACTURING SYSTEMS AND METHODS INCLUDING INLINE CUTTING - An automated photovoltaic (PV) subassembly manufacturing method involves in-line cutting of material strips. A tape is cut longitudinally into multiple strips. The strips are separated and guided into spaced apart positions relative to a surface of the PV cell subassembly comprising one or more PV cells. The multiple strips remain attached to the tape while the strips are guided to the spaced apart positions. The multiple strips are positioned at attachment locations on the surface of a PV cell subassembly. | 2020-12-03 |
20200381577 | METHOD OF MANUFACTURING SHINGLED SOLAR MODULES - A method including singulating a solar cell to form a plurality of strips, the singulation exposes unpassivated portions of the solar cell. The method further includes sorting the strips to ensure that similar shaped strips are grouped together, and re-passivating the plurality of strips, wherein the re-passivation eliminates active recombination centers. The method further includes aligning the re-passivated strips in an overlapping pattern, depositing electrically conductive adhesive (ECA) between the overlapped portions of the re-passivated strips, wherein the ECA adheres adjacent re-passivated strips to one another and electrically connects the re-passivated strips to form a string, electrically connecting a plurality of strings in parallel to form a string set, electrically connecting at least two string sets in series, and encapsulating the electrically connected string sets. | 2020-12-03 |
20200381578 | MANUFACTURING METHOD OF THIN FILM SOLAR CELL AND THIN FILM SOLAR CELL - The present disclosure provides a thin film solar cell and a manufacturing method thereof. The thin film solar cell includes a transparent substrate and a photovoltaic unit disposed on the transparent substrate and facing a display module. The photovoltaic unit includes a front electrode disposed on the transparent substrate, a light absorption layer disposed on the front electrode, and a back electrode disposed on the light absorption layer. The thin film solar cell further includes a metal auxiliary electrode and an insulating layer. The insulating layer covers the back electrode and the light absorption layer, and extends to be in contact connection with the front electrode. The metal auxiliary electrode is in contact connection with the front electrode, and extends onto the insulating layer. A taper angle is formed between a periphery of the insulating layer and the front electrode, and the taper angle ranges from 35° to 75°. | 2020-12-03 |
20200381579 | Semiconductor Body and Method for Producing a Semiconductor Body - A semiconductor body and a method for producing a semiconductor body are disclosed. In an embodiment a semiconductor body includes a p-conducting region, wherein the p-conducting region has at least one barrier zone and a contact zone, wherein the barrier zone has a first magnesium concentration and a first aluminum concentration, wherein the contact zone has a second magnesium concentration and a second aluminum concentration, wherein the first aluminum concentration is greater than the second aluminum concentration, wherein the first magnesium concentration is at least ten times less than the second magnesium concentration, wherein the contact zone forms an outwardly exposed surface of the semiconductor body, and wherein the barrier zone adjoins the contact zone, and wherein the semiconductor body is based on a nitride compound semiconductor material. | 2020-12-03 |
20200381580 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - A method of manufacturing a nitride semiconductor light emitting element includes: growing an n-side nitride semiconductor layer; growing an active layer on the n-side nitride semiconductor layer; and growing a p-side nitride semiconductor layer on the active layer, which includes: growing a first p-side nitride semiconductor layer, growing a second p-side nitride semiconductor layer, growing a third p-side nitride semiconductor layer, and growing a fourth p-side nitride semiconductor layer, while varying flow rates of an Al source gas, a Ga source gas, an N source gas, and a Mg source gas. | 2020-12-03 |
20200381581 | GROUP III NITRIDE BASED LED STRUCTURES INCLUDING MULTIPLE QUANTUM WELLS WITH BARRIER-WELL UNIT INTERFACE LAYERS - Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include Ill nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region. | 2020-12-03 |
20200381582 | VERTICAL SOLID STATE DEVICES - A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure. | 2020-12-03 |
20200381583 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: providing a first member comprising: a first substrate, a semiconductor layer disposed on the first substrate and defining a first recess, and a first metal layer disposed above at least a portion other than the first recess, the first member defining a second recess in a region of a surface of the first member including a region directly above the first recess; providing a second member comprising: a second substrate, a second metal layer on or above the second substrate, a third metal layer on the second metal layer, and a fourth metal layer on the third metal layer; and bonding the first member and the second member together by heating the first metal layer and the fourth metal layer while facing each other. The third metal layer impedes interdiffusion between the second metal layer and the fourth metal layer. | 2020-12-03 |
20200381584 | ENHANCED EFFICIENCY OF LED STRUCTURE WITH N-DOPED QUANTUM BARRIERS - The present invention provides light-emitting devices with improved quantum efficiency. The light emitting diode structure comprising: a p-doped layer an n-doped layer; and a multiple quantum well structure sandwiched between the p-doped layer and n-doped layer, wherein the multiple quantum well structure comprising a quantum well disposed between n-doped barrier layers. | 2020-12-03 |
20200381585 | LIGHT-EMITTING DEVICE - To provide a light-emitting device for achieving fluorescence emission with higher efficiency and longer life, a light-emitting device includes an exciton generation layer in which quantum dots are dispersed, a light-emitting layer in which light emitters, which are phosphors or phosphorescent members, are dispersed, the light-emitting layer adjoining the exciton generation layer in a vertical direction, a first electrode located on a lower side of the exciton generation layer and the light-emitting layer, and a second electrode located on an upper side of the exciton generation layer and the light-emitting layer, and the light emission spectrum of the quantum dots and the absorption spectrum of the light emitters at least partially overlap. | 2020-12-03 |
20200381586 | LIGHT EMITTING DIODE PANEL AND TILING DISPLAY APPARATUS - An LED panel including a substrate, multiple first pixels, multiple second pixels, multiple first protrusion structures and second protrusion structures is provided. The first pixels and second pixels each disposed in a display area of the substrate has at least one light emitting element. The second pixels are positioned on at least one display edge of the display area and positioned between the first pixels and a substrate edge. Each first protrusion structure is positioned on the periphery of the at least one light emitting element of one corresponding first pixel. Each second protrusion structure is positioned on the periphery of the at least one light emitting element of one corresponding second pixel. The orthogonal projection contour of each first protrusion structure on the substrate is different from that of each second protrusion structure on the substrate. A tiling display apparatus adopting the light emitting diode panel is also provided. | 2020-12-03 |
20200381587 | GLASS WIRING SUBSTRATE, METHOD OF PRODUCING THE SAME, PART-MOUNTED GLASS WIRING SUBSTRATE, METHOD OF PRODUCING THE SAME, AND DISPLAY APPARATUS SUBSTRATE - A glass wiring substrate includes a glass substrate, a first wiring portion being formed on a first surface of the glass substrate, a second wiring portion being formed on a second surface opposite to the first surface, a through-hole formed in a region of the glass substrate in which the first wiring portion and the second wiring portion are not formed, the through-hole having a diameter on a second surface side larger than a diameter on a first surface side, and a through-hole portion formed in the through-hole, one end portion of the through-hole portion extending to the first wiring portion, the other end portion of the through-hole portion extending to the second wiring portion, in which a wiring pitch P | 2020-12-03 |
20200381588 | LED ARRAYS HAVING A REDUCED PITCH - Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a device includes an array having a plurality of LEDs and a reflector that is in Ohmic contact with at least two adjacent LEDs of the plurality of LEDs. Each LED of the plurality of LEDs includes a p contact, and the reflector is physically separated from the p contact of each LED of the plurality of LEDs. | 2020-12-03 |
20200381589 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a bonding-type semiconductor light-emitting device which has excellent reliabilities with smaller time deviations of the light output power and the forward voltage. A semiconductor light-emitting device | 2020-12-03 |
20200381590 | DISPLAY APPARATUS, SOURCE SUBSTRATE STRUCTURE, DRIVING SUBSTRATE STRUCTURE, AND METHOD OF MANUFACTURING DISPLAY APPARATUS - A display apparatus, including a light-emitting device including a device-side electrode; a driving substrate configured to drive the light-emitting device; a driver-side electrode provided on the driving substrate; and a metal layer configured to connect the device-side electrode to the driver-side electrode, and including a first interface between the metal layer and the device-side electrode, and a second interface between the metal layer and the driver-side electrode, wherein at least one of the first interface and the second interface includes an intermetallic compound. | 2020-12-03 |
20200381591 | LIGHT EMITTING DIODE - Provided is a light emitting diode. The light emitting diode includes a substrate, a first semiconductor layer on the substrate, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a conductor passing through the second semiconductor layer and the active layer to contact the first semiconductor layer. | 2020-12-03 |
20200381592 | ELECTRONIC COMPONENT MOUNTING PACKAGE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE - An electronic component mounting package includes: an insulating base body including a principal face and a recess which opens in the principal face; and a metallic pattern including a plurality of metallic layers lying across a side face of the recess and the principal face. The metallic pattern includes, as an inner layer, at least one metallic layer selected from a tungsten layer, a nickel layer, and a gold layer, and an aluminum layer as an outermost layer. The metallic pattern includes an exposed portion corresponding to a part of the metallic layer constituting the inner layer which part is exposed at the principal face. | 2020-12-03 |
20200381593 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device includes preparing a light emitting device including: a package defining a recess; a first light source placed within the recess, and including a first light emitting element and a first wavelength conversion member; a second light source placed within the recess; and a second wavelength conversion member in contact with and covering the first light source and the second light source, the first light source and the second light source being configured to emit light independently of each other. The method further includes: emitting light simultaneously from the first light source and the second light source to obtain mixed light for which light from the first light source, light from the second light source, and light from the second wavelength conversion member are mixed; determining a chromaticity of the mixed light; and binning the mixed light based on the chromaticity. | 2020-12-03 |
20200381594 | SPIN-SENSITIVE ULTRAVIOLET LIGHT-BASED DEVICE AND METHOD - A spin-sensitive ultraviolet light-based device includes a p-type GaN layer; an n-type Gd doped ZnO nanostructure grown on the GaN layer; a first electrode formed on the GaN layer; and a second electrode formed on the Gd doped ZnO nanostructure. Electrons supplied through the first and second electrodes are spin-polarized by the Gd doped ZnO nanostructure. Polarized ultraviolet light emitted or received by the Gd doped ZnO nanostructure is correlated with the spin-polarized electrons. | 2020-12-03 |
20200381595 | White Light Emitting Device Comprising Multiple Photoluminescence Materials - There is provided a white light emitting device comprising: first and second LEDs operable to generate excitation light having a dominant wavelength in a range from 440 nm to 480 nm and mounted on a substrate; a first photoluminescence material which generates light having a peak emission wavelength in a range from 500 nm to 590 nm; and a second photoluminescence material which generates light having a peak emission wavelength in a range from 600 nm to 650 nm, wherein the first LED is covered by the first photoluminescence material, and the second LED is covered by the first and second photoluminescence materials. | 2020-12-03 |
20200381596 | LIGHT EMITTING DEVICE, BACKLIGHT UNIT AND DISPLAY APPARATUS - A light emitting device includes a first LED chip to emit a light having a peak wavelength in a range of 410 to 430 nm, a second LED chip to emit a light having a peak wavelength in a range of 440 to 460 nm, a first quantum dot to convert light emitted by the first and second LED chips into light having a peak wavelength in a range of 510 to 550 nm, and a second quantum dot to convert light emitted by the first and second LED chips into light having a peak wavelength in a range of 610 to 660 nm, wherein, in an emission spectrum of final light, intensity of a peak wavelength of the first LED chip is 15% or less of intensity of a peak wavelength of the second LED chip. | 2020-12-03 |
20200381597 | WAVELENGTH CONVERSION MEMBER AND LIGHT-EMITTING DEVICE USING SAME - Provided are: a wavelength conversion member capable of reducing the decrease in luminescence intensity with time and the melting of component materials when irradiated with high-power excitation light; a method for producing the same; and a light-emitting device using the wavelength conversion member. A wavelength conversion member | 2020-12-03 |
20200381598 | LIGHT-EMITTING DEVICE WITH LIGHT SCATTER TUNING TO CONTROL COLOR SHIFT - A system and methods for light-emitting diode (LED) devices with a dimming feature that can tailor a color point shift in the light color temperature of a scattering/transparent layer to enlarge a dim to warm range are disclosed herein. A light-emitting device may include a wavelength converting structure configured to receive light from a light emitting semiconductor structure and an adjacent light scattering structure. The light scattering structure may comprise a plurality of scattering particles with a lower refractive index (RI) than the RI of the matrix material in which the scattering particles are disposed. The wavelength converting structure may include a red phosphor and a green phosphor such that to adjust overlap between green emission and absorption by the red phosphor to correspondingly adjust scattering and magnitude of color shift. In an embodiment, the light scattering structure may be integrated in the wavelength converting structure. | 2020-12-03 |
20200381599 | OPTICAL DEVICE - An optical device includes two substrates disposed opposite to each other. Each of the substrates has a surrounding edge and a side surface at the surrounding edge. A wavelength conversion layer is disposed between the two substrates. A light emitting unit corresponding to the wavelength conversion layer is disposed between the corresponding wavelength conversion layer and one of the two substrates. A sealing element is disposed along the edges and in contact with the side surfaces of the two substrates, and seals the wavelength conversion layer and the light emitting unit located between the two substrates. | 2020-12-03 |
20200381600 | SELF-EMISSIVE ELEMENT AND MANUFACTURING METHOD OF LIGHT EMITTING APPARATUS - A self-emissive element includes a light-emitting diode (LED) and an auxiliary structure. The LED includes a first type semiconductor, a second type semiconductor, a first pad, and a second pad. The second type semiconductor is overlapped with the first type semiconductor in a vertical direction perpendicular. The auxiliary structure includes a cover portion, a protection portion and a first anchor portion. The cover portion is overlapped with the LED in the vertical direction. The protection portion is not overlapped with the LED in the vertical direction. An orthographic projection area of the protection portion in the vertical direction is greater than or equal to an orthographic projection area of the LED in the vertical direction. The first anchor portion and the protection portion are respectively located at different sides of the LED. | 2020-12-03 |