49th week of 2020 patent applcation highlights part 60 |
Patent application number | Title | Published |
20200381001 | CONCEPT FOR SWITCHING OF SAMPLING RATES AT AUDIO PROCESSING DEVICES - Audio decoder device for decoding a bitstream, the audio decoder device including: a predictive decoder for producing a decoded audio frame from the bitstream, wherein the predictive decoder includes a parameter decoder for producing one or more audio parameters for the decoded audio frame from the bitstream and wherein the predictive decoder includes a synthesis filter device for producing the decoded audio frame by synthesizing the one or more audio parameters for the decoded audio frame; a memory device including one or more memories, wherein each of the memories is configured to store a memory state for the decoded audio frame, wherein the memory state for the decoded audio frame of the one or more memories is used by the synthesis filter device for synthesizing the one or more audio parameters for the decoded audio frame; and a memory state resampling device configured to determine the memory state for synthesizing the one or more audio parameters for the decoded audio frame, which has a sampling rate, for one or more of the memories by resampling a preceding memory state for synthesizing one or more audio parameters for a preceding decoded audio frame, which has a preceding sampling rate being different from the sampling rate of the decoded audio frame, for one or more of the memories and to store the memory state for synthesizing of the one or more audio parameters for the decoded audio frame for one or more of the memories into the respective memory. | 2020-12-03 |
20200381002 | DIRECTIONAL SPEECH SEPARATION - A system configured to perform directional speech separation. The system may dynamically associate direction-of-arrivals with one or more audio sources in order to generate output audio data that separates each of the audio sources. The system identifies a target direction for each audio source, dynamically determines directions that are correlated with the target direction, and generates output signals for each audio source. The system may associate individual frequency bands with specific directions based on a time delay detected by two or more microphones. The system may determine a cross-correlation between each direction and the target direction and select directions with strong correlation. The system may generate time-frequency mask data indicating frequency bands corresponding to the directions associated with a particular audio source. Using the mask data, the system generates output audio data specific to the audio source, resulting in directional speech separation between different audio sources. | 2020-12-03 |
20200381003 | AUDIO OBJECT CLASSIFICATION BASED ON LOCATION METADATA | 2020-12-03 |
20200381004 | METHODS AND SYSTEMS FOR PROVIDING IMAGES FOR FACILITATING COMMUNICATION - Aspects of the disclosure include a computer-implemented method for interacting with a user. Identity information for a user can be received. The identity information can be analyzed to identify the user. User information for an identified user can be retrieved, the user information indicating that a voice interacting with the identified user is to be translated into image data to help the identified user communicate with the voice. Translated image data translating voice instructions by the voice can be retrieved. The translated image data can be displayed to the identified user. | 2020-12-03 |
20200381005 | Music Selections for Personal Media Compositions - In some implementations, a computing device can generate personalized music selections to associate with any collections of visual media (e.g., photos and videos) stored on the computing device. A user may prefer particular genres of music and listen to some genres more frequently than others. The computing device can create measures of the user's genre preferences and use these measures to select music that is preferred by the user and music that may be significant or relevant to the particular collection of visual media. The computing device may also determine music that was being played when and where the visual media were being created. The computing device may store the visual media and music items in association with each other. The computing device may generate composite media items that combine the visual media and music items. When the visual media are viewed, the selected music item is also played. | 2020-12-03 |
20200381006 | Minimizing Gunshot Detection False Positives - This invention is a gunshot detection device that provides very reliable inside and outside real-time situational awareness of gunshot events, while reducing Gunshot Detection False Positives and Negatives. | 2020-12-03 |
20200381007 | ELECTRONIC DEVICE AND CONTROL METHOD THEREFOR - An electronic device is disclosed. The electronic device comprises a communication unit, a speaker, and a processor for: outputting a test sound through the speaker when a preset signal is received from an external terminal device through the communication unit; acquiring, on the basis of sound data, reverberation time information for each frequency of the test sound and size information on a space in which the electronic device is positioned when sound data acquired by recording a test sound in a terminal device is received through the communication unit; acquiring, on the basis of the reverberation time information for each frequency and the size information on a space, a sound absorption rate of an object arranged in the space; and identifying information on the object on the basis of the sound absorption rate. | 2020-12-03 |
20200381008 | STORAGE MEDIUM, SPEAKER DIRECTION DETERMINATION METHOD, AND SPEAKER DIRECTION DETERMINATION DEVICE - A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes setting a plurality of speaker regions in different directions; calculating a phase difference in each of a plurality of different frequency bands on the basis of a plurality of sound signals acquired by the plurality of microphones; calculating a representative value of the number of phase differences belonging to each of a plurality of phase difference regions corresponding to each of the plurality of speaker regions on the basis of the calculated phase differences and the set plurality of speaker regions; comparing magnitudes of the calculated representative values; and determining, as a direction in which a speaker exists, a direction of a speaker region corresponding to a phase difference region where the compared representative value is large. | 2020-12-03 |
20200381009 | LOW LATENCY AUTOMIXER INTEGRATED WITH VOICE AND NOISE ACTIVITY DETECTION - Systems and methods are disclosed for providing voice and noise activity detection with audio automixers that can reject errant non-voice or non-human noises while maximizing signal-to-noise ratio and minimizing audio latency. | 2020-12-03 |
20200381010 | CARD READER AND CONTROL METHOD FOR CARD READER - A card reader includes a writing coil that is provided to a magnetic head for recording magnetic data in a magnetic card, and a drive circuit that supplies a write current to the writing coil. The drive circuit is a chopping circuit that supplies a chopping current, on/off of which is switched in a specified cycle, as the write current to the writing coil. An on/off cycle of the chopping current is a cycle in which a length of a magnetized pattern in a recording direction is shorter than a reading gap formed in a core around which the writing coil is wound or a core around which a reading coil being separately provided from the writing coil is wound, the magnetized pattern in the recording direction being formed in the magnetic card by the chopping current in a period including one each of the on and the off. | 2020-12-03 |
20200381011 | WRITE HEADS CONFIGURED TO REDIRECT CURRENT - Embodiments of the present disclosure generally relate to data storage devices, and more specifically, to storage devices employing an energy-assisted magnetic recording write head. The write head may comprise a main pole, a trailing shield, a conducting gap disposed between the main pole and the trailing shield, and one or more current blockers. The conducting gap may be conformal with the main pole. The one or more current blockers may be configured to direct the current from the main pole to the trailing shield through the conducting gap. The one or more current blockers may be further configured to recess the conducting gap away from the media facing surface. The one or more current blockers may be configured to direct the current away from a media facing surface of the write head. | 2020-12-03 |
20200381012 | MAGNETIC HEAD WITH ASSISTED MAGNETIC RECORDING AND METHOD OF MAKING THEREOF - A magnetic head includes a main pole configured to serve as a first electrode, an upper pole containing a trailing magnetic shield configured to a serve as a second electrode, and a record element located in a trailing gap between the main pole and the trailing magnetic shield. The record element includes an electrically conductive, non-magnetic material portion which is not part of a spin torque oscillator stack. The main pole and the trailing magnetic shield are electrically shorted by the record element across the trailing gap between the main pole and the trailing magnetic shield such that an electrically conductive path is present between the main pole and the trailing magnetic shield through the record element. | 2020-12-03 |
20200381013 | HEAD SUSPENSION ASSEMBLY AND DISK APPARATUS - A head suspension assembly includes a support plate, an interconnection member including a metal plate on the support plate, a first insulating layer on the metal plate, a conductive layer on the first insulating layer and forming a pair of connection pads, and a second insulating layer on the conductive layer, a head mounted in the interconnection member, and a piezoelectric element electrically connected to the connection pads and configured to displace the head when a predetermined voltage is applied across the connection pads. At least one opening is formed in each of the connection pads. The piezoelectric element is electrically connected to each of the connection pads by a conductive adhesive that is between the piezoelectric element and each of the connection pads and filled in the opening. | 2020-12-03 |
20200381014 | ELECTROSTRICTIVE CONTROL FOR THE WIDTH OF A TAPE-HEAD-ARRAY - The present disclosure generally relates to tape heads for use in a tape drive system. The tape head includes a plurality of servo elements and a plurality of data elements disposed between the servo elements. An electrostrictive material is present in the tape head. Electrodes are coupled to the electrostrictive material to permit a voltage to be distributed across the electrostrictive material. The voltage causes the electrostrictive material to expand, and thus expand the tape head. By expanding the tape head by adding voltage, or contracting the tape head by lowering voltage, the spacing between adjacent data elements can be adjusted to match the spacing between adjacent data tracks on a tape. | 2020-12-03 |
20200381015 | ALUMINUM-ALLOY SUBSTRATE FOR MAGNETIC DISK, METHOD FOR MANUFACTURING SAME AND MAGNETIC DISK EMPLOYING SAID ALUMINUM-ALLOY SUBSTRATE FOR MAGNETIC DISK - Provided is an aluminum alloy substrate for a magnetic disk that includes an aluminum alloy containing 0.4 to 3.0 mass % (hereinafter abbreviated as “%”) of Fe, 0.005% to 1.000% of Cu, and 0.005% to 1.000% of Zn, with a balance of Al and unavoidable impurities. This substrate has a ratio A/B of 0.70 or more, where A indicates a distribution density of Al—Fe intermetallic compound particles having maximum diameters of 10 μm or more and less than 16 μm, and B indicates a distribution density of Al—Fe intermetallic compound particles having maximum diameters of 10 μm or more. The distribution density of Al—Fe intermetallic compound particles having maximum diameters of 40 μm or more is at most one per square millimeter. Also provided are a method of fabricating this aluminum alloy substrate for a magnetic disk and a magnetic disk composed of the aluminum alloy substrate for a magnetic disk. | 2020-12-03 |
20200381016 | CALIBRATING ELEVATOR ACTUATOR FOR DISK DRIVE - A data storage device is disclosed wherein an elevator actuator is controlled to move a head along an axial dimension toward a first disk surface of a first disk while processing a proximity signal generated by a proximity sensor. A first actuator position is detected when the actuator arm is proximate the first disk surface of the first disk based on the proximity signal. | 2020-12-03 |
20200381017 | FLEXIBLE CONTENT RECORDING SLIDER - A recording slider interface is provided for interactively creating content recordings, the recording slider interface including a flexible recording slider object for controlling capture of the content recordings. A first manipulation of the flexible recording slider object is detected. A first content recording is captured in accordance with the first manipulation of the flexible recording slider object, a duration of the first content recording being set based on a characteristic of the first manipulation of the flexible recording slider object. A second manipulation of the flexible recording slider object is detected. A second content recording is captured in accordance with the second manipulation of the flexible recording slider object, a second duration of the second content recording being set based on a second characteristic of the second manipulation of the flexible recording slider object. A composite recording comprising the first content recording and the second content recording is stored. | 2020-12-03 |
20200381018 | TAGGING TRACKED OBJECTS IN A VIDEO WITH METADATA - Embodiments herein describe a video editor that can identify and track objects (e.g., products) in a video. The video editor identifies a particular object in one frame of the video and tracks the location of the object in the video. The video editor can update a position of an indicator that tracks the location of the object in the video. In addition, the video editor can identify an identification (ID) of the object which the editor can use to suggest annotations that provide additional information about the object. Once modified, the video is displayed on a user device, and when the viewer sees an object she can is interested in, she can pause the video which causes the indicator to appear. The user can select the indicator which prompts the user device to display the annotations corresponding to the object. | 2020-12-03 |
20200381019 | SYSTEM FOR CREATING AN INTERACTIVE VIDEO USING A MARKUP LANGUAGE - A system creating an interactive video using a markup language is disclosed. The disclosed system receives a video request including a set of source scene IDs arranged in a predetermined ordering. The system retrieves a set of source scenes associated with the set of source scene IDs and generates video scenes in the form of a Hypertext Markup Language (HTML) page for the set of source scenes. Each of the generated video scenes includes one or more interactive HTML elements and one or more animations. The system then generates a scene collection to include the video scenes arranged based on the predetermined ordering and renders the video scenes in the scene collection. | 2020-12-03 |
20200381020 | INTERACTIVE PRESENTATION OF VIDEO CONTENT AND ASSOCIATED INFORMATION - A system is provided that presents video content on an electronic device such that, when a user swipes to dismiss the video content, non-video summary information or contextual material about the video content is automatically displayed in place of the video content. The non-video summary information is presented on a summary card dragged on-screen responsive to user swipe input. If, for example, the user swipes to dismiss a video advertisement before an informational payload of the video advertisement has been delivered, the informational payload can automatically be displayed in text format on a summary card dragged by the user in replacement of the dismissed video advertisement. | 2020-12-03 |
20200381021 | System and Method for Improving User Performance in a Sporting Activity - A method is provided for identifying and displaying video data of a user, either alone or together (in synchronization) with other data, such as biometric data acquired during a time that the video data was captured/received. The method includes storing biometric data separately from the video data, allowing the biometric data to be search quickly to identify at least one value (e.g., a value corresponding to at least one biometric event). At least one biometric time-stamp (e.g., a time, a sample rate, a position within a plurality of values, etc.) linked to the identified value can then be used to identify a corresponding video time-frame, which can then be used to play the video data, either alone or together with biometric data, starting at a particular time (e.g., at a time that the event occurred, shortly before the event occurred, etc.). | 2020-12-03 |
20200381022 | METHOD AND APPARATUS FOR STORAGE AND SIGNALING OF COMPRESSED POINT CLOUDS - A method, apparatus and computer program product are provided to signal and store compressed point clouds in video encoding. The method, apparatus and computer program product may be utilized in conjunction with a variety of video formats. Relative to encoding of compressed point clouds, the method, apparatus and computer program product access a point cloud compression coded bitstream and cause storage of the point cloud compression coded bitstream. The point cloud compression coded bitstream comprises a texture information bitstream, a geometry information bitstream, and an auxiliary metadata bitstream. Relative to the decoding of compressed point clouds, the method, apparatus and computer program product receive a point cloud compression coded bitstream and decode the point cloud compression coded bitstream. | 2020-12-03 |
20200381023 | MEMORY CORE POWER-UP WITH REDUCED PEAK CURRENT - A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the power-up of a succeeding core in the power-up order responsive to the core power supply voltage exceeding the threshold voltage of a control transistor in the succeeding core. | 2020-12-03 |
20200381024 | PAGE BUFFER AND MEMORY DEVICE INCLUDING THE SAME - A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit. | 2020-12-03 |
20200381025 | APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS - Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space. | 2020-12-03 |
20200381026 | IN-MEMORY COMPUTING DEVICE FOR 8T-SRAM MEMORY CELLS - An in-memory computing device includes a memory array, a multiple row decoder and a sensing circuit. The memory includes non-destructive memory cells, each of which includes an 8T-SRAM to store a bit of data. Each cell is connected to a read word line and a write word line, both connecting a row of said memory cells, a write bit line and a complementary write bit line, and a read bit line connecting a single column of said memory cells. The multiple row decoder activates at least two read word lines at a same time. The sensing circuit detects a signal on each of the selected read bit lines of multiple selected columns for reading. Each signal is a Boolean function of the stored data in the memory cells in its column activated by the activated read word lines. | 2020-12-03 |
20200381027 | DAC/ADC ARCHITECTURE FOR AI IN MEMORY - A computing device in some examples includes multiple digital-to-analog converters (DACs) having outputs connected to respective operational amplifiers, with outputs connected to the gates of respective transistors, each forming a serial combination with a respective memory element. The serial combinations are connected between a voltage reference point and a conductive line. An analog-to-digital converter is connected to the conductive line at the input. The DACs generate analog signals having ON-periods of lengths corresponding to the respective numbers at the DACs' inputs. The transistors generate currents indicative of the level of output signals of the respective DACs and memory states of the respective memory elements for the ON-periods. The combined currents charges or discharges the conductive line, which has a parasitic capacitance, to a voltage, which is indicative of the sum of the numbers weighted by the memory states. The voltage is converted to a digital representation of the weighted sum. | 2020-12-03 |
20200381028 | CLOCK GENERATING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A memory device includes a clock generating circuit suitable for generating a plurality of internal clock signals based on an external clock signal during an output period of read data, in response to a read command, and a data strobe output circuit suitable for outputting a first data strobe signal to a data strobe pad in response to the internal clock signals, wherein the internal clock signals toggle regardless of the output period of the read data, in response to a test mode signal. | 2020-12-03 |
20200381029 | Apparatuses And Methods For Setting A Duty Cycle Adjuster For Improving Clock Duty Cycle - Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset. | 2020-12-03 |
20200381030 | VERTICAL DECODERS - Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases. | 2020-12-03 |
20200381031 | MAGNETIC RANDOM ACCESS MEMORY STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present disclosure provides a method for manufacturing a magnetic random access memory (MRAM) structure, including forming a magnetic tunneling junction (MTJ) structure in a first region, forming a dielectric stack over the first region and a second region different from the first region, etching an upper portion of the dielectric stack in the first region and the second region, and performing a planarization operation over the remaining portion of the dielectric stack in the first region and the second region. | 2020-12-03 |
20200381032 | STORAGE CIRCUIT PROVIDED WITH VARIABLE RESISTANCE TYPE ELEMENT, AND SENSE AMPLIFIER - A storage circuit ( | 2020-12-03 |
20200381033 | MAGNETIC STORAGE ELEMENT AND ELECTRONIC APPARATUS - [Overview] [Problem to be Solved] Provided are a magnetic storage element and an electronic apparatus having a reduced writing current while retaining a magnetism retention property of a storage layer. [Solution] The magnetic storage element includes: a spin orbit layer extending in one direction; a writing line that is electrically coupled to the spin orbit layer, and allows a current to flow in an extending direction of the spin orbit layer; a tunnel junction element including a storage layer, an insulator layer, and a magnetization fixed layer that are stacked in order on the spin orbit layer; and a non-magnetic layer having a film thickness of 2 nm or less, and disposed at any stack position between the spin orbit layer and the insulator layer. | 2020-12-03 |
20200381034 | SEMICONDUCTOR STORAGE ELEMENT, SEMICONDUCTOR STORAGE DEVICE, SEMICONDUCTOR SYSTEM, AND CONTROL METHOD - [Object] To provide a semiconductor storage element, a semiconductor storage device, a semiconductor system, and a control method that make it possible to perform stable writing of information. [Solution] Provided is a semiconductor storage element including: a first transistor having a gate insulation film that includes a ferroelectric material at least partially and being a transistor to which information is written, and a second transistor that is coupled to, at one of a source and a drain, a source or drain of the first transistor. The first transistor has a threshold voltage smaller than | 2020-12-03 |
20200381035 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME - A nonvolatile memory device includes a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory cell region includes a first memory stack comprising first memory cells vertically stacked on each other, and a second memory stack comprising second memory cells vertically stacked on each other. The peripheral circuit region includes a control logic for setting a voltage level of a second voltage applied for a second memory operation to a second memory cell of the second memory cells based on a first voltage applied to a first memory cell of the first memory cells in a first memory operation. Cell characteristics of the first memory cell are determined using the first voltage. | 2020-12-03 |
20200381036 | CONTROLLER AND OPERATING METHOD THEREOF - A controller controlling a memory device includes an elapsed time calculator suitable for receiving an absolute time from a host whenever a state is changed between an active state and an inactive state, calculating an average hibernation elapsed time for elapsed times between first and second absolute times, and calculating a system time based on a third absolute time and the average hibernation elapsed time, and a flash translation layer suitable for controlling a program operation for the memory device in response to a program command for a memory region, calculating a program operation time for the memory region based on the system time, and controlling a read operation for the memory device using a read voltage, which is determined based on an elapsed time since the program operation time, in response to a read command for the memory region. | 2020-12-03 |
20200381037 | 3-DIMENSIONAL MEMORY DEVICE - A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions. | 2020-12-03 |
20200381038 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line. | 2020-12-03 |
20200381039 | APPROXIMATE MEMORY ARCHITECTURE AND DATA PROCESSING APPARATUS HAVING THE SAME - The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period. | 2020-12-03 |
20200381040 | APPARATUSES AND METHODS FOR TRACKING VICTIM ROWS - The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows. | 2020-12-03 |
20200381041 | PSEUDO STATIC RANDOM ACCESS MEMORY AND METHOD FOR WRITING DATA THEREOF - A pseudo static random access memory and a method for writing data thereof are provided. In the method, a basic clock signal having a basic cycle is provided. A chip enable signal is enabled to perform a write operation and write data is received during an enabled time interval of the chip enable signal. A plurality of internal clock signals is generated sequentially at intervals of the basic cycle according to a write command enable signal. A refresh conflict signal is received and it is determined whether the refresh conflict signal is enabled. When the refresh conflict signal is enabled, the internal clock signals are delayed, and the write data is written to a selected sensing amplifier according to the delayed internal clock signals. | 2020-12-03 |
20200381042 | Method and Apparatus for Memory Noise-Free Wake-Up Protocol from Power-Down - A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells. | 2020-12-03 |
20200381043 | SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS - A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit. | 2020-12-03 |
20200381044 | CROSS-POINT MEMORY COMPENSATION - The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop. | 2020-12-03 |
20200381045 | SEMICONDUCTOR DEVICE AND ERROR DETECTION METHOD - A semiconductor device which includes: a switch array in which a switch cell including a variable resistance switch is arranged at each location where a plurality of wires constituting a crossbar switch intersect; a first selection circuit that selects all of the variable resistance switches included in the switch array; a second selection circuit that selects any of the variable resistance switches included in the switch array; a reading circuit that reads a state of the variable resistance switch selected by any of the first selection circuit and the second selection circuit; and an error detection circuit that detects, based on a state of the variable resistance switch read by the reading circuit, an error in at least any of the variable resistance switches included in the switch array. | 2020-12-03 |
20200381046 | MIXED CROSS POINT MEMORY - Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines. | 2020-12-03 |
20200381047 | NON-VOLATILE MEMORY BANK WITH EMBEDDED INLINE COMPUTING LOGIC - A non-volatile memory device having processing logic embedded within a memory bank of the non-volatile memory device is disclosed herein. By way of example, commands for controlling the processing logic can be exposed to a host device, enabling the host device to activate processing capacity of the memory bank in conjunction with a memory operation. The processing capacity can be directed by a data command, transmitted by the host device, at read or write data identified by the memory operation. Read data can be processed by the memory bank before being output onto a data interface connected to the memory bank. Likewise, write data received at the memory bank can be processed in conjunction with storing the write data in the non-volatile memory device. A disclose memory device can therefore implement internal processing in conjunction with reading or writing data to a memory device comprising respective banks of two-terminal non-volatile memory. | 2020-12-03 |
20200381048 | HYPER-DIMENSIONAL COMPUTING DEVICE - A device for hyper-dimensional computing may be provided. The device comprises a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors, of the resistive memory device, wherein the resistive memory device comprises a first crossbar array of the components, wherein the components are memristive 2D components addressable by word-lines and bit-lines, and a peripheral circuit connected to the word-lines and bit-lines and adapted for encoding operations by activating the word-lines and bit-lines sequentially in a predefined manner. | 2020-12-03 |
20200381049 | Memory Systems and Memory Programming Methods - Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline. | 2020-12-03 |
20200381050 | 3D FLASH MEMORY MODULE AND HEALING AND OPERATING METHODS OF 3D FLASH MEMORY - A three-dimensional (3D) flash memory module, a healing method of 3D flash memory, and an operating method of 3D flash memory are provided. The 3D flash memory module includes a 3D flash memory structure and a conductive layer. The 3D flash memory structure is disposed on a substrate. The conductive layer is disposed on the substrate and is adjacent to at least one side wall of the 3D flash memory structure. The conductive layer extends along the at least one side wall of the 3D flash memory structure, and each of two opposite end portions of the conductive layer has an electrical connection point in an extending direction of the conductive layer. | 2020-12-03 |
20200381051 | MEMORY DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE INCLUDING MEMORY DEVICE AND MEMORY CONTROLLER - The memory controller controls a memory device. The controller is configured to determine to perform a target operation on a first memory block and determine an activation voltage level transferred to a block word line based on block state information of a second memory block. | 2020-12-03 |
20200381052 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage. | 2020-12-03 |
20200381053 | NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF - An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period. | 2020-12-03 |
20200381054 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY SYSTEM - A memory device includes: a memory block including a plurality of main pages and a dummy page; a peripheral circuit for performing a normal program operation on the plurality of main pages and a dummy program operation on the dummy page in a program operation, and reading data stored in the dummy page and the plurality of main pages in a read operation; and control logic for controlling the peripheral circuit to program, to the dummy page, the same data as first logical page data of a first main page among the plurality of main pages in the program operation. | 2020-12-03 |
20200381055 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THEREOF - Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers. | 2020-12-03 |
20200381056 | SEMICONDUCTOR DEVICE AND HEALTHCARE SYSTEM - Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit | 2020-12-03 |
20200381057 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device having an improved threshold voltage distribution includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform an erase operation on the memory block; and control logic configured to: control the peripheral circuit to suspend the erase operation in response to a suspend command received from an external source, determine an erase state of the plurality of memory cells by using a plurality of erase state verify voltages in response to a resume command received subsequently to the suspend command, and determine a level of an erase voltage to be applied to the memory block and an erase voltage applying time for which the erase voltage is to be applied based on the determination result. | 2020-12-03 |
20200381058 | NON-VOLATILE MEMORY DEVICE AND METHOD OF ERASING THE SAME - A non-volatile memory device includes a memory cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad; a substrate in the memory cell region; a memory cell array in the memory cell region comprising a plurality of gate conductive layers stacked on the substrate and a plurality of pillars penetrating through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the substrate, wherein at least one of the plurality of gate conductive layers is a ground select line; a control logic circuit in the peripheral circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit in the peripheral circuit configured to, in response to the erase enable signal, output a substrate bias voltage at a first target level to the substrate from a first time to a second time after the first time during a first delay period and, after the first delay period gradually increase a level of the substrate bias voltage to an erase voltage having a higher level than the first target level; and a row decoder in the peripheral circuit configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay period. | 2020-12-03 |
20200381059 | NON-VOLATILE MEMORY DEVICE AND INITIALIZATION INFORMATION READING METHOD THEREOF - In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells. | 2020-12-03 |
20200381060 | RAPID RESTART PROTECTION FOR A NON-VOLATILE MEMORY SYSTEM - Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts. | 2020-12-03 |
20200381061 | MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY DEVICE - A memory system, a memory controller and a memory device. In a set operation, by applying different pass voltages to at least one first word line and at least one second word line among the plurality of word lines excluding a selected target word line, an operation error of the memory device may be prevented. | 2020-12-03 |
20200381062 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section. | 2020-12-03 |
20200381063 | SYSTEMS AND METHODS PROVIDING IMPROVED CALIBRATION OF MEMORY CONTROL VOLTAGE - Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlry may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming. | 2020-12-03 |
20200381064 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING CONTROLLER, AND METHOD OF OPERATING CONTROLLER - A method of operating a controller that controls an operation of a semiconductor memory device includes controlling the semiconductor memory device to perform an operation for a selected memory block, determining whether or not the operation is successful, and compensating for a change in a threshold voltage distribution of select transistors by changing an operation voltage applied to the select transistors included in the selected memory block, based on whether or not the operation is successful. | 2020-12-03 |
20200381065 | MEMORY DEVICE WITH IMPROVED PROGRAM PERFORMANCE AND METHOD OF OPERATING THE SAME - A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic. | 2020-12-03 |
20200381066 | MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE - Provided herein may be a memory device and a method of operating the memory device. The memory device may include memory cells configured to store data, a peripheral circuit configured to perform program and read operation on memory cells selected from among the memory cells, and a refresh controller configured to include a counter and a refresh manager, wherein the counter is configured to count a number of memory cells which are in an erased state or a programmed state by performing a read operation on the selected memory cells using a reference read voltage, and the refresh manager is configured to compare a read count indicating the counted number of memory cells, with a preset reference count, to determine whether to shift the reference read voltage and to control the peripheral circuit so that the program operation is performed using a voltage different than a program voltage by a step voltage. | 2020-12-03 |
20200381067 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first memory cell and a second memory cell capable of storing data and coupled in parallel to a bit line; a first word line coupled to the first memory cell; a second word line coupled to the second memory cell and being different from the first word line; and a control circuit. The first memory cell and the second memory cell share a first well region and are opposed to each other, with the first well region interposed. The control circuit is configured, in a first operation, to repeat application of a first voltage to the first word line and the second word line a plurality of times while increasing the first voltage. | 2020-12-03 |
20200381068 | MEMORY CONTROLLER, MEMORY DEVICE AND MEMORY SYSTEM HAVING IMPROVED THRESHOLD VOLTAGE DISTRIBUTION CHARACTERISTICS AND RELATED OPERATING METHODS - Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions. | 2020-12-03 |
20200381069 | STRIPE BASED SELF-GATING FOR RETIMING PIPELINES - Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry. | 2020-12-03 |
20200381070 | MEMORY DEVICE AND TEST OPERATION METHOD THEREOF - The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed. | 2020-12-03 |
20200381071 | SYSTEMS AND METHODS FOR SIMULATED DEVICE TESTING USING A MEMORY-BASED COMMUNICATION PROTOCOL - Embodiments of the present invention provide a method of simulating a memory-based communication protocol for testing a simulated device. The method includes storing data in known locations of a host data buffer, where the host data buffer is implemented in a shared memory space, executing instructions of a first program to store a command in the shared memory space using a data structure including an index, an ID, and a memory location, executing instructions of a second program to read the command from the host data buffer, access the data in the shared memory space to perform an operation defined by the ID using the data, where a location of the data is indicated by the index, and send a completion indicator to the first program after the operation is complete. | 2020-12-03 |
20200381072 | CYCLIC REDUNDANCY CHECK CIRCUIT, CORRESPONDING DEVICE AND METHOD - A device includes serial cyclic redundancy check (CRC) processing circuitry and parallel CRC processing circuitry. The serial CRS processing circuitry, in operation, generates a set of intermediate CRC bits based on a first set of seed bits and input data. The parallel CRC processing circuitry is coupled to the serial CRC processing circuitry, and, in operation, generates, using the set of intermediate CRC bits as a set of parallel seed bits and using null input bits, a set of output CRC bits corresponding to the input data. | 2020-12-03 |
20200381073 | METHOD FOR DRIVING AN ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY IN A TEST MODE - A method drives an electronic device including a semiconductor memory in a test mode. The method includes applying a stress pulse simultaneously to a plurality of memory cells to turn on the plurality of memory cells, determining whether the memory cells are turned on or turned off, and applying a second maximum voltage to a selected memory cell of the plurality of memory cells only when the selected memory cell is determined to be in a turned-off state. | 2020-12-03 |
20200381074 | NON-VOLATILE MEMORY DEVICE AND ERASING OPERATION METHOD THEREOF - A non-volatile memory device and an erasing operation method thereof are provided. The non-volatile memory device includes a main memory cell region and a control circuit electrically connected to the main memory cell region. The main memory cell region has a plurality of memory cells. The control circuit is configured to perform an erasing operation on the memory cells, wherein the control circuit is configured to: obtain a current threshold voltage of the memory cell to be erased; calculate a difference between the current threshold voltage and an original threshold voltage to obtain a voltage shift value, wherein the original threshold voltage represents the pre-delivery threshold voltage of the memory cells; adjust an erase verify voltage level according to the voltage shift value; and determine whether the erasing operation is completed according to the adjusted erase verify voltage level. | 2020-12-03 |
20200381075 | NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICES, AND METHOD OF TRAINING DATA INPUT AND OUTPUT LINES BETWEEN CONTROLLER AND NONVOLATILE MEMORY DEVICES - A storage device includes a plurality of nonvolatile memory devices; and a controller connected in common to the plurality of nonvolatile memory devices through data lines, the controller being configured to detect first offset information by performing a first training operation with respect to a first nonvolatile memory device from among the plurality of nonvolatile memory devices, the controller being further configured to, based on the first offset information, perform a second training operation with respect to a second nonvolatile memory device from among the plurality of nonvolatile memory devices. | 2020-12-03 |
20200381076 | SYSTEM AND METHOD FOR PRIORITIZATION OF BIT ERROR CORRECTION ATTEMPTS - System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit. | 2020-12-03 |
20200381077 | APPARATUSES AND METHODS FOR FUSE LATCH REDUNDANCY - Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits. | 2020-12-03 |
20200381078 | STRUCTURE SEARCH APPARATUS, METHOD, AND RECORDING MEDIUM - A structure formed with a plurality of molecules that have interactions is searched by a computer. The computer performs a process including: preparing position bits of a number calculated based on the number of constituent units included in the plurality of molecules and the number of molecules included in the plurality of molecules for each constituent unit in each molecule included in the plurality of molecules, and searching the structure formed with the plurality of molecules that have the interactions based on a cost function that includes (A-1) a negative interaction, (A-2) an original interaction, (B-1) a constraint that each of the constituent units in the one molecule exists in one of the position bits, and (B-2) a constraint that one or no constituent unit exists in any one of the plurality of molecules in the position bits. | 2020-12-03 |
20200381079 | METHODS FOR DETERMINING SUB-GENIC COPY NUMBERS OF A TARGET GENE WITH CLOSE HOMOLOGS USING BEADARRAY - Presented herein are methods and compositions for copy number estimation of a target gene with close homologs, comprising determining sub-genic copy numbers. The methods are useful for estimating copy numbers of clinically important genes with high sequence similarity between gene of interest and their homologs, including non-functional pseudogenes. | 2020-12-03 |
20200381080 | DISCOVERY OF ENGINEERED SEQUENCES - Techniques for determining whether a nucleic acid sequence is genetically engineered are provided. In some embodiments, a ratio is calculated based on a number of input reads that align with reference data, and the ratio is inputted into a classifier to determine whether the input reads represent an engineered sequence. In some embodiments, first output data is generated based on unassembled read-based comparison of nucleic acid data, while second output data is generated based on assembly-based comparison of the nucleic acid data; the first and second output data are inputted into a classifier to determine whether the input data represents an engineered sequence. In some embodiments, nucleic acid data is compared to three reference datasets representing (i) engineered sequences, (ii) evolutionary variations of an organism, and (iii) evolutionary variations of other organisms; a determination as to whether the input data represents an engineered sequence is based on the three comparisons. | 2020-12-03 |
20200381081 | Microbial Quantitation - In various embodiments of an analytics system, a spike-in including synthetic constructs of nucleic acid is added to soil samples for processing. The analytics system determines sequence reads classified to a microbe in the soil sample. The analytics system determines one or more measures of soil texture of the soil sample, for example, indicating percentages of sand, silt, and clay. The analytics system determines a measure of the microbe as a function of at least the classified sequence reads, the one or more measures of soil texture, and a mass of the spike-in. The analytics system can transmit the measure of the microbe to a client device for display on a user interface. A field where the soil sample was obtained can be treated according to the measure of the microbe. | 2020-12-03 |
20200381082 | ALIGNMENT METHODS, DEVICES AND SYSTEMS - The disclosure discloses an alignment method, device, and system. The alignment method includes: converting each read into a set of short fragments corresponding to the read to obtain a plurality of sets of short fragments; determining a corresponding position of the short fragment in a reference library to obtain a first positioning result, wherein the reference library is a hash table constructed based on a reference sequence, the reference library includes a plurality of entries, one entry of the reference library corresponds to one seed sequence, and the seed sequence is capable of matching at least one sequence on the reference sequence, a distance between two seed sequences corresponding to two adjacent entries of the reference library on the reference sequence is less than a length of the short fragment; removing a short fragment positioned on any one of the adjacent entries of the reference library in the first positioning result to obtain a second positioning result; and extending based on short fragments from the same read in the second positioning result to obtain an alignment result of the read. The alignment method can efficiently and accurately process and position sequencing data. | 2020-12-03 |
20200381083 | ESTIMATING PREDISPOSITION FOR DISEASE BASED ON CLASSIFICATION OF ARTIFICIAL IMAGE OBJECTS CREATED FROM OMICS DATA - Methods and systems are provided for classifying genetic variant and gene function and/or expression data, as well as DNA methylation, epigenomics, proteomics, metabolomics, microbiomics, and other biological/omics data into one or more uni- or multi-dimensional artificial image objects (AIOs) for image analyses. AIOs are composed of a plurality of cells, each being assigned a specific variant. Each variant is assigned a specific value. The graphic pixel signals from AIOs generated from a population of subjects each possessing a particular trait (or not) are analyzed and/or trained collectively with Machine Learning (ML) or other Artificial Intelligence (AI) algorithms. The trained algorithm then detects characteristic signatures of the trait from the AIO to determine whether a subject possesses the trait or not, thereby affording rapid and accurate detection and better treatment. Traits include, but are not limited to, diseases such as mental illness, cancer, heart disease, and other biological conditions. | 2020-12-03 |
20200381084 | IDENTIFYING SALIENT FEATURES FOR INSTANCES OF DATA - A computer-implemented method according to one embodiment includes identifying principal components for a dataset defined by data instances and features corresponding to the data instances, identifying, for at least one of the data instances, at least some of the principal components, wherein the identified principal components are determined to be salient for said at least one data instance, and determining, for said at least one of the data instances, one or more salient features corresponding to the identified salient principal components. | 2020-12-03 |
20200381085 | MATERIAL CHARACTERISTIC PREDICTION APPARATUS AND MATERIAL CHARACTERISTIC PREDICTION METHOD - An apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine a degree of similarity between a target material and a first material based on a structure and characteristic of each of the target material and the first material; predict a characteristic value of the target material based on a first value representing the characteristic of the first material; and output the predicted characteristic value. | 2020-12-03 |
20200381086 | SYTEMS AND METHODS FOR MONITORING SUBJECTS HAVING CHRONIC GASTROINTESTINAL INCICATIONS - Systems and methods are provided for monitoring a user having a chronic gastrointestinal indication. A questionnaire regarding a plurality of conditions is provided on a repeating basis. Each such condition at least partly arises from the gastrointestinal indication. Questionnaire questions are each associated with a corresponding condition and provide an affordance that allows the user to select between low and high values in accordance with user association with the condition. Responses are stored in a data store associated with the user. A user requested report comprising a graphical quality of life measure of the user is provided based upon temporal questionnaire answers. Questionnaire information is communicated to a remote device for medical practitioner evaluation and computation of a temporal overall quality of life score based on a plurality of component quality of life scores, each of which is associated with a condition in the plurality of conditions. | 2020-12-03 |
20200381087 | SYSTEMS AND METHODS OF CLINICAL TRIAL EVALUATION - Systems and methods are configured to match a patient to a clinical trial. A method includes receiving text-based criteria for the clinical trial, including a molecular marker. Additionally, the method includes associating at least a portion of the text-based criteria to one or more pre-defined data fields containing molecular marker information. The method further includes comparing a molecular marker of the patient to the one or more pre-defined data fields, and generating a report for a provider. The report is based on the comparison and includes a match indication of the patient to the clinical trial. | 2020-12-03 |
20200381088 | METHOD AND SYSTEM FOR CLINICAL TRIAL RESOURCE MANAGEMENT USING BLOCK CHAIN - A method is disclosed including: allowing a contract research organization device to generate clinical trial information and transmit the information to a blockchain server; allowing the server to register the information, and assign a first private key and a first public key to a set site device and transmit the assigned keys to the site device in response to a request from the organization device; allowing the server to complete applicant authentication using a second private key assigned to an applicant for a clinical trial; allowing the site device to confirm previous participation information of the applicant; and allowing the site device to perform the clinical trial based on the previous participation information, encrypt a performance result of the clinical trial using the first public key, a second public key corresponding to the second private key, and the second private key, and transmit the encrypted performance result to the server. | 2020-12-03 |
20200381089 | SYSTEM AND METHOD OF DATA INTERPRETATION AND PROVIDING RECOMMENDATIONS TO THE USER ON THE BASIS OF HIS GENETIC DATA AND DATA ON THE COMPOSITION OF GUT MICROBIOTA - This technical decision relates to the field of computer technology in genetics and microbiology, and more specifically, to a new system and method for studying and interpreting genetic data and data on the composition of the human gut microbiota in the field of microbiology. A system for providing recommendations to the user based on genetic data and/or data on the composition of the gut microbiota comprises a primary data acquisition unit configured to obtain the user's genetic data and/or user's gut microbiota data; a quality control unit configured to monitor the quality of the user's genetic data and the user's gut microbiota data obtained by the primary data acquisition unit, wherein the genetic data includes single nucleotide polymorphisms, and the microbiota data includes reads; a user origin determination unit configured to determine the paternal and maternal haplogroup, the population composition of the user based on his genetic data; a block of taxonomic analysis of microbiota data, performed with the ability to classify metagenomic risks; a disease risk determination unit configured to determine the protection against diseases, as well as mutation testing for the presence of pathogenic alleles and disease status evaluation, a symptom detection unit configured to determine the states of the user features by reducing the dependency graph of the characteristics; a unit for generating recommendations to the user, configured to form a recommendation to the user based on the data of the disease risk determination unit and the user attribute determination unit. | 2020-12-03 |
20200381090 | Patient Context Vectors: Low Dimensional Representation of Patient Context Towards Enhanced Rule Engine Semantics and Machine Learning - A PCV generation process using deep learning networks and multi-task learning wherein what knowledge is already known can be used to learn new knowledge such as the addition of CPT and medication information to augment patient PCVs based on ICD codes and expressions of history in free text notes. | 2020-12-03 |
20200381091 | GENERATION OF CUSTOMIZED PERSONAL HEALTH ONTOLOGIES - A user device may use a curated health sub-ontology to index a user's health record data sourced from multiple electronic health record (EHR) systems. As part of indexing the health record data, the user device may create a personal health ontology that is specific to the user's health record data. | 2020-12-03 |
20200381092 | CUSTOMIZED PRESENTATION OF HEALTH RECORD DATA - A user device may use a curated health sub-ontology to index a user's health record data sourced from multiple electronic health record (EHR) systems. As part of indexing the health record data, the user device may create a personal health ontology that is specific to the user's health record data. | 2020-12-03 |
20200381093 | CLINICAL TRIAL RE-EVALUATION SYSTEM - A clinical trial re-evaluation system is operable to perform at least one assessment function on a set of medical scans for each of a first subset of a set of patients of a failed clinical trial to generate automated assessment data for each of the first subset of the set of patients. The first subset of the set of patients corresponds to a subset of human assessment data determined to have failed to meet criteria of the clinical trial. Patient re-evaluation data is generated for each of the first subset of the set of patients by comparing the automated assessment data to the criteria. The patient re-evaluation data for a second subset of the first subset of the set of patients indicates the automated assessment data passes the criteria. Trial re-evaluation data is generated based on the patient re-evaluation data for transmission to a computing device for display. | 2020-12-03 |
20200381094 | SYSTEM AND METHOD TO ELECTRONICALLY COORDINATE AND DOCUMENT PATIENT CARE REGARDLESS OF PHYSICAL SETTING - A system to electronically coordinate and document patient care regardless of physical setting. The system includes a wearable subsystem attached to a patient at the point of injury and configured to remain attached to the patient at the point of injury and during one or more encounters with medical personnel or to a time the patient reaches a clinical health care facility. The wearable subsystem is configured to store patient identification information and critical health care information received via wireless communication from an end user computing device at the point of injury and is configured to store added health care information provided by medical personnel from or at the point of injury and during the one or more encounters with the medical personnel or to a time the patient reaches a clinical care facility. | 2020-12-03 |
20200381095 | PERSONALIZED MEDICATION NON-ADHERENCE EVALUATION - A method, a computer program product, and a computer system predict medication adherence of a patient. The method includes identifying risk factors associated with medication adherence of the patient. The method includes determining a likely behaviour for medication adherence of the patient based on the identified risk factors and a temporal causal model. The temporal causal model is based on features of a patient cluster to which the patient belongs. The features are nodes in the temporal causal model. The likely behaviour is based on causality measures for each identified risk factor to the nodes. The method includes determining a current medication adherence value of the patient. The current medication adherence value is indicative of a ratio between an actual medication regiment and an expected medication regiment. The method includes determining a future medication adherence value of the patient based on the current medication adherence value and the causality measures. | 2020-12-03 |
20200381096 | Methods of Predicting Disorder Progression for Control Arms Within an Experimental Trial - Methods of performing experimental treatments on a cohort of subjects are provided. A predictive model can be utilized to predict progression of a medical disorder or relevant imaging biomarker. The predicted medical disorder progression can be utilized as a control to determine whether an experimental treatment has an effect on the progression of the medical disorder. In some instances, the enrollment of subjects within a control group for clinical experiment is eliminated or reduced. | 2020-12-03 |
20200381097 | METHODS OF TREATING EOSINOPHILIC ESOPHAGITIS - Described herein are methods of managing eosinophilic esophagitis (EoE) in a patient, wherein the patient records the number of episodes of dysphagia on a patient report outcome (PRO) questionnaire prior to and during the course of treatment. While on treatment, the number of episodes of dysphagia are reduced, as reported on the PRO questionnaire. In some embodiments, the esophageal eosinophils are counted before or after treatment, or both. In some embodiments, esophageal eosinophils counts are not correlated with a reduction in the episodes of dysphagia. | 2020-12-03 |
20200381098 | UTILIZING A MACHINE LEARNING MODEL TO IDENTIFY UNHEALTHY ONLINE USER BEHAVIOR AND TO CAUSE HEALTHY PHYSICAL USER BEHAVIOR - A device receives, from a client device, behavior data indicating an action of a user of the client device, and processes the behavior data, with a model, to determine whether the action satisfies a behavior threshold. The device determines preventative actions to perform to prevent the action of the user, when the action is determined to satisfy the behavior threshold, and performs the preventative actions to prevent the action of the user. The device provides, to the client device, a request indicating that the user perform a physical activity before the one or more preventative actions are disabled, and monitors a performance of the physical activity by the user. The device determines whether the user satisfies the performance of the physical activity based on the monitoring, and disables the one or more preventative actions when it is determined that the user satisfies the performance of the physical activity. | 2020-12-03 |
20200381099 | HEALTH APPLICATION USER INTERFACES - The present disclosure generally relates to health-related user interfaces. In some embodiments, user interfaces for managing health-related data are described. In some embodiments, user interfaces for viewing health data are described. In some embodiments, user interfaces related to sharing health data are described. | 2020-12-03 |
20200381100 | ACTIVITY TRENDS AND WORKOUTS - The present disclosure generally relates to computer user interfaces, and more specifically to techniques for presenting activity trends and managing workouts. | 2020-12-03 |