49th week of 2015 patent applcation highlights part 77 |
Patent application number | Title | Published |
20150349716 | Differential Output Stage of an Amplification Device, for Driving a Load - Differential output stage ( | 2015-12-03 |
20150349717 | AMPLIFIER CIRCUIT WITH IMPROVED ACCURACY - An amplifier circuit with improved accuracy is provided that comprises a cascade of amplifier stages, a control line for controlling the amplifier stages, a feedback circuit having an input port for receiving a reference signal, and a feedback loop connecting the feedback circuit to the control line. Via the feedback circuit and the feedback loop, the large signal behavior of the amplifier stage is accurately fixed. As a result, the small signal gain of the amplifier stages has an improved accuracy as well. | 2015-12-03 |
20150349718 | SYSTEMS AND METHODS FOR DELAY CALIBRATION IN POWER AMPLIFIER SYSTEMS - A power amplifier system is provided. The power amplifier system includes a power supply to generate a supply voltage based on an input signal, a power amplifier powered by the supply voltage to amplify the input signal and generate an output signal, a delay determiner to determine a delay mismatch between the input signal and the supply voltage, and a programmable delay block coupled to the delay determiner to compensate for the determined delay mismatch between the input signal and the supply voltage. The delay determiner determines the delay mismatch based on a first delay between the input and output signals when the input signal is below a threshold and a second delay between the input and output signals when the input signal is above the threshold. | 2015-12-03 |
20150349719 | DOHERTY POWER AMPLIFIER APPARATUS - Disclosed is a Doherty power amplifier apparatus, including: a drive amplifier circuit, a power splitter circuit and a power combiner circuit, wherein the power splittercircuit is connected to the drive amplifier circuit, the apparatus further comprising: a carrier amplifier circuit and a peak amplifier circuit connected in parallel between the power splitter circuit and the power combiner circuit, wherein the carrier amplifier circuit comprises one or more parallel carrier amplification branches, wherein each carrier amplification branch comprises a multi-stage carrier amplifier apparatus, the multi-stage carrier amplifier apparatus is used for achieving multi-stage carrier amplification; and the peak amplifier circuit comprises one or more parallel peak amplification branches, wherein each peak amplification branch comprises a multi-stage peak amplifier apparatus, the multi-stage peak amplifier apparatus is used for achieving multi-stage peak amplification. | 2015-12-03 |
20150349720 | POWER AMPLIFIERS WITH SIGNAL CONDITIONING - A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value. | 2015-12-03 |
20150349721 | NEUTRALIZATION OF PARASITIC CAPACITANCE USING MOS DEVICE - An apparatus comprises an amplifier comprising at least one metal oxide semiconductor (MOS) transistor having a parasitic gate-to-drain capacitance, and at least one MOS neutralization device having a neutralization capacitance configured to compensate for the parasitic gate-to-drain capacitance of the at least one MOS transistor. | 2015-12-03 |
20150349722 | Dual Stage Carrier-Aggregation (CA) Low Noise Amplifier (LNA) Having Harmonic Rejection and High Linearity - A device includes a load circuit configured to receive an amplified communication signal, the load circuit having a center tapped inductor structure configured to divide the amplified communication signal into a first portion and a second portion, the load circuit configured to resonate at a harmonic of the amplified communication signal. | 2015-12-03 |
20150349723 | HYBRID POWER AMPLIFIER HAVING ELECTRICAL AND THERMAL CONDUCTION PATH - A heterojunction bipolar transistor (HBT) hybrid type RF (radio frequency) power amplifier includes a first device including an input terminal for receiving an RF signal, a pre-driver stage for amplifying the received RF signal, and an output terminal, the input terminal, the pre-driver stage and the output terminal being disposed in or over a first substrate; and a second device having a main stage having an HBT amplifier circuit disposed in or over a second substrate to further amplify the RF signal amplified by the pre-driver stage. The RF signal further amplified by the main stage is output through the output terminal of the first device. | 2015-12-03 |
20150349724 | DISTORTION CANCELLATION FOR DUAL STAGE CARRIER-AGGREGATION (CA) LOW NOISE AMPLIFIER (LNA) NON-LINEAR SECOND ORDER PRODUCTS - A device includes a main two-stage low noise amplifier (LNA) configured to amplify a carrier aggregation (CA) communication signal, the main two-stage LNA comprising a first LNA stage and a second LNA stage, an output of the first LNA stage having a first stage second order intermodulation product, the second LNA stage comprising a phase-inverter configured to phase-invert the output of the first LNA stage to generate a second stage phase-inverted output, and an auxiliary LNA stage coupled to the main two-stage LNA, the auxiliary LNA stage configured to cancel the first stage second order intermodulation product. | 2015-12-03 |
20150349725 | DISTORTION-COMPENSATION DEVICE AND DISTORTION-COMPENSATION METHOD - Disclosed is a distortion-compensation apparatus that can reduce the storage space for storing coefficients required for distortion-compensation calculation, and can accurately execute distortion compensation. Distortion-compensation apparatus ( | 2015-12-03 |
20150349726 | Mutual Coupling Inductor Based Ultra-Wideband Power Amplifier And Design Method Thereof - A transformer based power amplifier introducing leakage inductance to extend a working bandwidth thereof and corresponding design methodology are provided. An ultra-wideband transformer comprises a primary coil, a secondary coil mutual coupling with the primary coil, a primary tuning capacitor coupled with the primary coil in parallel and a secondary tuning capacitor coupled with the secondary coil in parallel. By means of setting a self-inductance of the primary coil, a self-inductance of the secondary coil, a mutual coupling factor between the primary coil and the secondary coil, a capacitance value of the primary tuning capacitor, and a capacitance value of the secondary tuning capacitor, a 3 dB bandwidth of the transformer covers a first mutual resonated frequency and a second mutual resonated frequency formed by the transformer. This is also applicable to single-stage or transformer coupled multi-stage amplifier design, and to multi-coil coupled implementations, such as transformer-based power combiner power amplifiers. | 2015-12-03 |
20150349727 | BANDWIDTH LIMITING METHODS FOR GAN POWER TRANSISTORS - A transistor package includes a transistor and one or more bandwidth limiting matching networks. The one or more bandwidth limiting matching networks are coupled to one of a control contact and an output contact of the transistor in order to limit the gain response of the transistor outside of a predetermined frequency band. Specifically, the transistor package has a gain roll-off greater than 0.5 dB within 200 MHz of the predetermined frequency band, while providing signal losses less than 1.0 dB inside the predetermined frequency band at a power level greater than 240 W. By providing the bandwidth limiting matching networks in the transistor package, the gain response of the transistor may be appropriately limited in order to comply with the spectral masking requirements of one or more wireless communications standards, for example, Long Term Evolution (LTE) standards. | 2015-12-03 |
20150349728 | CURRENT-VOLTAGE CONVERSION AMPLIFIER CIRCUIT INCLUDING MULTIPLIER AND MULTI INPUT AMPLIFIER - Provided is a current-voltage conversion amplifier circuit including: a plurality of light receiving devices generating a current signal proportional to an amount of light by receiving the light; multipliers amplifying the current signal, converting the amplified current signal into a first voltage signal, outputting the amplified current signal, or outputting the converted first voltage signal; multi input amplifiers outputting first and second output voltage pairs through a process for receiving output values of multipliers and an offset voltage and amplifying the received output values and offset voltage; a multiplexing unit selecting and outputting one first and second output voltage pair among the first and second output voltage pairs outputted from multi input amplifiers; and a signal conversion unit converting a difference value between first and second output voltages outputted from the multiplexing unit and outputting the converted digital signal. | 2015-12-03 |
20150349729 | AMPLIFIER CIRCUIT, BI-STAGE AMPLIFIER CIRCUIT, MULTI-STAGE AMPLIFIER CIRCUIT, RF-AMPLIFIER CIRCUIT, RECEIVER SECTION, RF-TRANSCEIVER, AND INTEGRATED CIRCUIT - The present invention relates to an amplifier circuit, comprising: first to fourth semiconductor amplifiers for controlling first to fourth currents between supply and output terminals, a first input terminal connected to provide a first input signal to a first control terminal of the first semiconductor amplifier and to a fourth control terminal of the fourth semiconductor amplifier, and a second input terminal connected to provide a second input signal to a second control terminal of the second semiconductor amplifier and to a third control terminal of the third semiconductor amplifier. | 2015-12-03 |
20150349730 | APPARATUS AND METHODS POWER AMPLIFIER BIASING - Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled. | 2015-12-03 |
20150349731 | HYBRID POWER AMPLIFIER COMPRISING HETEROJUNCTION BIPOLAR TRANSISTORS (HBTs) AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES - A heterojunction bipolar transistor (HBT) hybrid type RF (radio frequency) power amplifier includes a first device including an input terminal for receiving an RF signal, a pre-driver stage for amplifying the received RF signal, and an output terminal, the input terminal, the pre-driver stage and the output terminal being disposed in or over a first substrate; and a second device having a main stage having an HBT amplifier circuit disposed in or over a second substrate to further amplify the RF signal amplified by the pre-driver stage. The RF signal further amplified by the main stage is output through the output terminal of the first device. | 2015-12-03 |
20150349732 | COMMON-SOURCE POWER AMPLIFIERS - A system includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to amplify an input signal and generate first output signals. The first amplifier stage includes a common-source differential amplifier. The common-source differential amplifier includes a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) having source terminals connected to a common potential. The second amplifier stage includes a first differential amplifier and a second differential amplifier configured to respectively generate first and second differential outputs based on the first output signals. Each of the first and second differential amplifiers includes a plurality of MOSFETs having source terminals connected to the common potential via a respective balun. | 2015-12-03 |
20150349733 | TRANSMITTER DIGITAL-TO-ANALOG CONVERTER (DAC)- BASEBAND FILTER (BBF) COMMON MODE INTERFACE - Removing common-mode current from a pair of complementary current signals, including: generating a common-mode voltage of the pair of complementary current signals including at least a first current signal and a second current signal; measuring and outputting a difference voltage between the generated common-mode voltage and a common-mode reference voltage; and removing at least a portion of the common-mode current from the first current signal and the second current signal based on the difference voltage. | 2015-12-03 |
20150349734 | DIFFERENTIAL AMPLIFIER WITH HIGH-SPEED COMMON MODE FEEDBACK - The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage. | 2015-12-03 |
20150349735 | DIRECTIONAL COUPLERS HAVING VARIABLE POWER RATIOS AND RELATED DEVICES, SYSTEMS, AND METHODS - Variable power ratio (VPR) directional couplers that permit an amount of power directed to different outputs to be varied and managed. In some embodiments, the power ratio of the VPR coupler is represented by an equivalent coupling factor C′ corresponding to a conventional coupling factor C. The VPR coupler may include one or more variable reactive network (VRN) circuits, each configured to reflect a portion of power received from an input back toward the input, and to transmit a remainder of the power toward an output. An amount of power reflected and transmitted by the VRN circuit may be varied based on a control voltage applied to the VRN circuit. In one example, a plurality of VPR couplers can be arranged in series to create a versatile and simplified network for distributing signals to a plurality of end units. | 2015-12-03 |
20150349736 | FEEDBACK AMPLIFIER - Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal. | 2015-12-03 |
20150349737 | INPUT CURRENT LIMITED POWER SUPPLY AND AUDIO POWER AMPLIFIER FOR HIGH POWER REPRODUCTION OF NONDETERMINISTIC SIGNALS - A method and apparatus for amplifying audio signals without exceeding an input current limit budgeted for the audio power amplifier circuit includes an intermediate energy storage between a battery and the audio power amplifier which provides an energy reserve to support amplifying peaks where the peaks have a peak power that is greater than the power that can be drawn from the battery due to the input current limit. Speech signals, which include substantial periodic content having short peaks relative to a pitch period, can be amplified without depleting the intermediate energy storage, allowing the intermediate energy storage to recover after a peak and before occurrence of a next peak. When an audio signal is amplified that results in depletion of the intermediate energy storage, a depletion recovery circuit reduces the overall audio gain to reduce the power demand of the audio power amplifier so as to substantially avoid distortion. | 2015-12-03 |
20150349738 | APPARATUS AND METHOD FOR DYNAMICALLY ADAPTING A USER VOLUME INPUT RANGE ON AN ELECTRONIC DEVICE - Method of dynamically adapting user volume input range on mobile device having global volume range starts by receiving a volume input selection from a user that is level included in user volume input range. User volume input range is a portion of global volume range. Device's processor then detects ambient noise level surrounding device and adjusts user volume input range from current portion of global volume range to different portion of global volume range based on detected ambient noise level. Volume input selection remains at the same level included in user volume input range after user volume input range is adjusted. Processor may identify sound profile that corresponds to ambient noise level being detected and adjusts user volume input range to a different portion of the global volume range based on identified sound profile. Other embodiments are also described. | 2015-12-03 |
20150349739 | COMMON MODE NOISE SUPPRESSING DEVICE - An all-pass filtering module of a common mode noise suppressing device includes first and second differential transmission circuits coupled to a reference node. Each of the first and second differential transmission circuits has an input terminal and an output terminal, and includes: first and second capacitive elements coupled in series between the input terminal and the output terminal; a first inductor coupled between the input terminal and the output terminal; and a third capacitive element and a second inductor coupled in series between the reference node and a common node between the first and second capacitive elements. | 2015-12-03 |
20150349740 | IMPEDANCE MATCHING DEVICE, LINEAR MOTION MODULE, AND RADIO FREQUENCY POWER SUPPLY DEVICE - An impedance matching device includes a first variable capacitor connected to an RF power source and including a first shaft moving linearly, a first linear motion unit axially coupled to the first shaft of the first variable capacitor to provide linear motion, a first insulating joint connecting the first shaft to a first driving shaft of the first linear motion unit, and a first displacement sensor adapted to measure a movement distance of the first driving shaft of the first linear motion unit. | 2015-12-03 |
20150349741 | TEMPERATURE COMPENSATED CIRCUITS FOR RADIO-FREQUENCY DEVICES - Temperature compensated circuits for radio-frequency (RF) devices. In some embodiments, an RF circuit can include an input node and a plurality of components interconnected to the input node and configured to yield an impedance for an RF signal at the input node. At least one of the plurality of components can be configured to have temperature-dependence within a temperature range so that the impedance varies to compensate for an effect of temperature change. Such an RF circuit can be, for example, an impedance matching circuit implemented at an output of a power amplifier. The component having temperature-dependence can include a temperature-dependent capacitor such as a ceramic capacitor. | 2015-12-03 |
20150349742 | ADAPTIVE LOAD FOR COUPLER IN BROADBAND MULTIMODE MULTI-BAND FRONT END MODULE - Directional couplers for front end modules (FEMs) are disclosed that include a first port configured to receive a radio-frequency (RF) signal, a second port connected to the first port via a first transmission line and configured to provide an RF output signal, and a third port connected to a second transmission line, the second transmission line coupled to the first transmission line. A directional coupler in accordance with the present disclosure may further include a termination circuit connected to the second transmission line and configured to provide a first impedance when the RF signal is within a first frequency band and provide a second impedance when the RF signal is within a second frequency band. | 2015-12-03 |
20150349743 | ACOUSTIC RESONATOR COMPRISING VERTICALLY EXTENDED ACOUSTIC CAVITY - A bulk acoustic wave (BAW) resonator having a vertically extended acoustic cavity is provided. The BAW resonator includes a bottom electrode disposed on a substrate over a cavity formed in the substrate; a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer. The piezoelectric layer has a thickness of approximately λ/2, wherein λ is a wavelength corresponding to a thickness extensional resonance frequency of the BAW resonator. At least one of the bottom electrode and the top electrode comprises a composite electrode having a thickness of approximately λ/2. | 2015-12-03 |
20150349744 | CRYSTAL DEVICE AND PRODUCING METHOD OF CRYSTAL DEVICE - A crystal device has a crystal blank, a first excitation electrode part which is provided on an upper surface of the crystal blank, a first wiring part which extends from the first excitation electrode part to an edge part of the upper surface, a first lead-out terminal which is provided at the edge part of the upper surface of the crystal blank, a first mounting terminal which is provided at a position facing the first lead-out terminal, a first connection part which is provided so that one end is superimposed on the first lead-out terminal and the other end is superimposed on the first mounting terminal, a substrate having a mounting pad which is provided on its upper surface, a conductive adhesive which is provided between the mounting pad and the first mounting terminal, and a lid which is bonded to the upper surface of the substrate. | 2015-12-03 |
20150349745 | ACOUSTIC RESONATOR WITH ELECTRICAL INTERCONNECT DISPOSED IN UNDERLYING DIELECTRIC - An apparatus comprises a substrate, a dielectric disposed on the semiconductor substrate, an acoustic resonator disposed on the dielectric, and an electrical interconnect disposed in the dielectric and configured to transmit an electrical signal to or from at least one electrode of the acoustic resonator through a signal path disposed at least partially below a level of the acoustic resonator. | 2015-12-03 |
20150349746 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT - A vibrator (electronic device) includes: a vibrator element including vibrating arms; a base portion supporting the vibrator element and having a rectangular shape in a plan view; and a lid provided on the side of the vibrator element opposite to the base portion | 2015-12-03 |
20150349747 | CAPACITIVE COUPLED RESONATOR DEVICE WITH AIR-GAP SEPARATING ELECTRODE AND PIEZOELECTRIC LAYER - A bulk acoustic wave (BAW) resonator includes a bottom electrode disposed on a substrate, a piezoelectric layer disposed over the bottom electrode, and a top electrode disposed over the piezoelectric layer. The BAW resonator further includes at least one air-gap and corresponding support structure, where the at least one air-gap separates at least one of the bottom electrode and the top electrode from the piezoelectric layer, respectively. | 2015-12-03 |
20150349748 | Broad-band Filter in Branching Technology - A reactance filter can be use branching technology. A series circuit contains a first filter element, a second filter element and a third filter element. Each filter element includes a first impedance element that is connected in series with an impedance element of an adjacent element. Each filter element also includes a second element connected to the first impedance element of that filter. The first and/or second impedance element of each filter element comprises a includes a resonator. Each impedance element has a bandwidth that is expressed by its pole zero distance and each filter element comprises a means for setting the bandwidths of the impedance elements. | 2015-12-03 |
20150349749 | PROGRAMMABLE TRANSMIT CONTINUOUS-TIME FILTER - A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provided to an upconversion mixer for conversion to RF for transmission. The TX-CTF includes amplifier circuitry and passive circuitry that together define the filter parameters. The TX-CTF further includes programmable current circuitry that provides a programmable bias current to the amplifier circuitry. The TX-CTF system also includes control logic that receives one or more transmitter control signals and, in response, generates signals that control the bias current provided to the TX-CTF. | 2015-12-03 |
20150349750 | Impedance-Matching Network Using BJT Switches in Variable-Reactance Circuits - This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology. | 2015-12-03 |
20150349751 | IMPEDANCE TUNERS WITH POSITION FEEDBACK - An impedance tuner includes a controller, an RF transmission line, and a movable capacitive object configured for movement commanded by the controller relative to the transmission line to alter impedance. A position sensor is configured to provide feedback position data to the controller indicative of the actual position of the capacitive object after it is moved. The controller is configured to utilize the feedback position data in a closed loop to position the capacitive object at a desired position within a tolerance. | 2015-12-03 |
20150349752 | ADAPTIVE STABILITY CONTROL FOR A DRIVER CIRCUIT - A circuit for driving a load may include a control loop having a response characteristic. A headroom signal indicative of the headroom voltage of the circuit may set one or more parameters of the response characteristic. A load sign indicative of electrical loading on the circuit may further set the response characteristic. | 2015-12-03 |
20150349753 | INTEGRATION CIRCUIT - An integration circuit according to one embodiment includes a first capacitance element, a capacitance circuit, a comparison circuit, a memory circuit and an operation circuit. The first capacitance element receives a current signal. The capacitance circuit includes a first switch and a second capacitance element, and is connected in parallel to the first capacitance element. The second capacitance element receives a current signal via the first switch. The comparison circuit compares a voltage of the first capacitance element with a reference voltage to obtain a comparison result. The memory circuit stores the comparison result, and opens or closes the first switch based on the comparison result. The operation circuit outputs a residual signal based on a difference between the integrated value obtained by the first capacitance element and the second capacitance element and a value based on the comparison result. | 2015-12-03 |
20150349754 | PULSE STRETCHING CIRCUIT AND METHOD - A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal. | 2015-12-03 |
20150349755 | FREQUENCY CONVERTER - A frequency converter, comprising a multi-phase local oscillator and a multi-phase mixer. The mixer comprises a plurality of mixer switches, each connected to a respective amplifier. The local oscillator is configured to provide a switching signal to each mixer switch, and comprises a plurality of inverters configured as a ring oscillator. | 2015-12-03 |
20150349756 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock. | 2015-12-03 |
20150349757 | Hysteresis Circuit - A hysteresis circuit includes a current comparator arranged to receive an input current signal. A reference current source is coupled to the current comparator and arranged to provide a reference current. A hysteresis current source is arranged to provide a hysteresis current. A switch is coupled between the reference current source and the hysteresis current source. At least one buffer is coupled to the current comparator and arranged to provide an output voltage signal. The output voltage signal has a first voltage if the input current signal is greater than a sum of the reference current and the hysteresis current and the output voltage signal has a second voltage if the input current signal is less than the reference current. | 2015-12-03 |
20150349758 | COMPARATOR WITH CONTROLLED CURRENT SUPPLY CAPACITY - A comparator includes an input-stage circuit that sets, in a first operating state, two voltage signals in a first voltage state, and changes, in a second operating state, the two voltage signals from the first voltage state to a second voltage state at different speeds, a latch-stage circuit that includes two field effect transistors and two inverters, the two field effect transistors receiving the two voltage signals at control nodes and disposed between two output nodes and a predetermined potential, the two inverters cross-coupled between the two output nodes and placed in an inactive state in the first operating state and in an active state in the second operating state, and a control circuit that controls current capacities in two paths through which drive voltages are applied to the two inverters, causing the current capacities to be different during at least part of a period of the second operating state. | 2015-12-03 |
20150349759 | LEVEL SHIFT CIRCUIT - A level shift circuit includes a first pair of transistors of the first conductive type (M | 2015-12-03 |
20150349760 | DATA AND CLOCK SIGNAL VOLTAGES WITHIN AN INTEGRATED CIRCUIT - An integrated circuit | 2015-12-03 |
20150349761 | POWER MODULE - A power module includes: a base plane; at least one switch chip assembled on the base plane; and a voltage clamping circuit for clamping a voltage of the at least one switch chip and comprising components of a charging loop, wherein a projection of at least one of the components of the charging loop on the base plane is located within at least one first circle, defined with a center point of the at least one switch chip as a center of the first circle, and with a product of a maximum of a length and a width of the at least one switch chip and a first coefficient, as a radius of the first circle. | 2015-12-03 |
20150349762 | DELAY CONTROLLING CIRCUIT FOR DRIVING CIRCUIT, DRIVING CIRCUIT HAVING DELAY CONTROLLING CIRCUIT, AND METHOD OF OPERATING DRIVING CIRCUIT - A driving circuit includes first and second switches coupled in series, a delay generating circuit and a delay controlling circuit. The delay generating circuit and the delay controlling circuit are coupled to first and second control terminals of the first and second switches. The delay generating circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The delay controlling circuit is configured to store a setting of the delay, and control the delay generating circuit to generate the delay in accordance with the stored setting, a first voltage on the first control terminal and a second voltage on the second control terminal. | 2015-12-03 |
20150349763 | METHOD FOR PERFORMING PHASE SHIFT CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals. | 2015-12-03 |
20150349764 | Flip-Flop Having Integrated Selectable Hold Delay - A circuit includes a flip-flop and a delay circuit integrated with the flip-flop, the delay circuit including at least one delay element, the flip-flop and delay circuit having a predefined architecture such that a delay provided by the delay circuit may have a selectable value while the flip-flop remains within the predefined architecture. | 2015-12-03 |
20150349765 | DELAY LINE CIRCUITS AND SEMICONDUCTOR INTEGRATED CIRCUITS - A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors. | 2015-12-03 |
20150349766 | DELAY LINE CIRCUITS AND SEMICONDUCTOR INTEGRATED CIRCUITS - A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors. | 2015-12-03 |
20150349767 | PULSE WIDTH MODULATION CONTROL UNIT, VOLTAGE REGULATOR AND CONTROL METHOD THEREOF - A PWM control unit is provided. A comparison unit compares an output voltage with a reference voltage to generate a first compared result, and controls a voltage of a first node. A constant current source is coupled to the first node. A storage module is coupled to the first node and receives a ground voltage. A first comparator compares the output voltage with the voltage of the first node to generate a turn-on signal. A second comparator compares the voltage of the first node with the input voltage to generate an output signal. A logic gate generates a turn-off signal according to the turn-on and output signals. When each of the turn-on and output signals is at a first level, a logic gate asserts the turn-off signal at a second level. The PWM generator combines the turn-on and turn-off signals to generate a PWM signal. | 2015-12-03 |
20150349768 | PROGRAMMABLE SWITCHED CAPACITOR BLOCK - A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal | 2015-12-03 |
20150349769 | Current-controlled CMOS logic family - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 2015-12-03 |
20150349770 | System and Method for a Radio Frequency Switch - In accordance with an embodiment, a circuit includes a plurality of switching networks coupled between a corresponding plurality of RF ports and a common RF port, and a control circuit. Each of the plurality of switching networks includes a first switch coupled between its corresponding RF port and the common RF port, and at least one of the plurality of switching networks includes a selectable network coupled between the first switch and the common RF port, such that the selectable network provides a DC path in a first state and a series capacitance in a second state. | 2015-12-03 |
20150349771 | SEMICONDUCTOR DEVICE AND CASCODE CIRCUIT - A semiconductor device and a cascode circuit are disclosed herein. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first electrode, a second electrode, a control electrode, and a control pad. The second transistor includes a first electrode, a second electrode, a control electrode, and a control pad. The second electrode of the first transistor is configured to receive a first predetermined voltage. The control electrode of the first transistor is configured to receive an input signal. The first electrode of the second transistor configured to receive a second predetermined voltage. The second electrode of the second transistor is electrically coupled to the first electrode of the first transistor. The control pad is disposed between the first electrode of the second transistor and the control electrode of the second transistor, and is configured to receive a first adjust signal. | 2015-12-03 |
20150349772 | Method and Device for Switching an Electronic Component on or off - An electronic component is switched under the control of a pulse-width modulation signal. The electronic component outputs an output signal that is controlled by a control signal. The switching on or off is initiated within a pulse-width modulation cycle period at a level change time by a change of the pulse-width modulation signal. The control signal is set within each PWM cycle period to a first control value between the level change time and a first switching time, to a second control value between the first switching time and a second switching time, and to a third control value from the second switching time until a final gate-voltage value is reached on the gate of the electronic component. Each switching time of a PWM period is determined in dependence on an amplitude value determined during a preceding PWM cycle period, to limit amplitudes of the oscillation of the output signal. | 2015-12-03 |
20150349773 | Single Layer Touchscreen with Ground Insertion - A sensor array that has first electrodes, second electrodes and third electrodes formed from a single layer of conductive material and interleaved without intersecting one another, in which each first electrode is coupled with at least one of the second electrodes via a mutual capacitance. Some of the third electrodes are disposed between the first electrodes and the second electrodes. All electrodes are interleaved without intersecting one another. | 2015-12-03 |
20150349774 | RESISTIVE INPUT SYSTEM WITH RESISTOR MATRIX - A resistive input system is disclosed, which includes a resistor matrix. The resistor matrix includes M first traces, N second traces, and M*N resistors. First ends of the resistors of a same column are coupled to one of the M first traces, second ends of the resistors of a same row are coupled to one of the N second traces, M is integers greater than 1, and N is integers greater than and equal to 1. The M*N resistors include variable resistors. A measurement circuit measures variations of a first voltage level of each of the second traces while a power control circuit provides the first voltage to the one of the M first traces and the second voltage to the rest of the M first traces. At least one input point is determined according to the variation of the first voltage level of each of the second traces. | 2015-12-03 |
20150349775 | Radiation Hardened By Design Digital Input/Output Circuits And Related Methods - Embodiments of radiation hardened by design digital input/output circuits are described herein. Other examples and related methods are also disclosed herein. | 2015-12-03 |
20150349776 | HIGH SIDE DRIVER COMPONENT AND METHOD THEREFOR - A high side driver component for generating a drive signal at an output thereof for driving a high side switching device within a high voltage driver circuit. The high side driver component is arranged to operate in at least one reduced slew rate mode in which at least one drive stages is arranged to be in a non-drive state, and the high side driver component further comprises at least one discharge protection component arranged to, when the high side driver component is operating in the at least one reduced slew rate mode, receive an indication of the high voltage driver circuit being in an idle state, and cause the second switching device within the at least one drive stage in a non-drive state to be turned on, in response to the indication of the high voltage driver circuit being in an idle state. | 2015-12-03 |
20150349777 | SWITCHING CIRCUIT AND ELECTRONIC DEVICE - The present invention provides a switching circuit and an electronic device, which relate to the field of electronic technologies, so as to improve reliability of image processing. The switching circuit includes a comparator circuit, a first switch circuit, a second switch circuit, a first drive voltage source, and a second drive voltage source. Two input ends of the comparator circuit respectively receive an input voltage and a reference voltage, an output end is separately connected to an input end of the first switch circuit and an input end of the second switch circuit; The comparator circuit determines whether the input voltage is greater than the reference voltage, outputs a high level when determining that the input voltage is greater than the reference voltage, and outputs a low level when determining that the input voltage is not greater than the reference voltage. | 2015-12-03 |
20150349778 | LEVEL SHIFTER FOR A TIME-VARYING INPUT - A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit. | 2015-12-03 |
20150349779 | LEVEL SHIFTER FOR A TIME-VARYING INPUT - A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an input node to receive an input signal and an output node to output to a level-shifted output signal corresponding with the input signal. An idle state on the input node corresponds with a particular binary logic value that is maintained for a first time period, and which is detected by a detection sub-circuit. Further, the level shifter circuit includes a first inverter that uses the second supply voltage, and has a feedback path between the input and output of the first inverter. The feedback path includes a first resistive element and a first transmission gate. The first transmission gate is configurable to open the feedback path when the detection sub-circuit detects an idle state on the input node of the level shifter circuit. | 2015-12-03 |
20150349780 | HYBRID QUANTUM CIRCUIT ASSEMBLY - Systems and methods are provided for a hybrid qubit circuit assembly is provided. A first plural set of Josephson junctions is arranged in series on a first path between two nodes of a circuit. A second plural set of Josephson junctions is arranged in parallel with one another to form a direct current superconducting quantum interference device (DC SQUID). The DC SQUID is in parallel with the first plural set of Josephson junctions. A capacitor is in parallel with each of the first plural set of Josephson junctions and the DC SQUID. | 2015-12-03 |
20150349781 | MULTI-MODULUS FREQUENCY DIVIDER - A frequency divider circuit can achieve multi-modulus operation. The frequency divider includes clocking transistor devices, memory transistor circuits, write transistor devices, and a current source bias. The clocking transistor devices receive a differential input signal having a first frequency at an input of the frequency divider. The memory transistor circuits store signals based on the differential input signal from the clocking transistor devices. The write transistor devices make a divided frequency signal available at an output terminal. The current source bias is coupled to the clocking transistor devices. The current source bias applies a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider. | 2015-12-03 |
20150349782 | RECONFIGURABLE FRACTIONAL DIVIDER - Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal. | 2015-12-03 |
20150349783 | RECEIVING CIRCUIT - A receiving circuit includes: clock-and-data-recovery-circuits arranged in parallel, each of the clock-and-data-recovery-circuits including an LC-voltage-controlled-oscillator configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, each clock-and-data-recovery-circuit being configured to sample a piece of input data with an output clock of the LC-voltage-controlled-oscillator and adjust the oscillation frequency of the LC-voltage-controlled-oscillator in accordance with a phase difference and a frequency difference between the piece of input data and the output clock of the LC-voltage-controlled-oscillator, thereby recovering data and a clock based on the piece of input data; and a gain-adjustment-circuit configured to adjust ratios of gains of up and down of the oscillation frequency of the LC-voltage-controlled-oscillator in a loop in each of the clock-and-data-recovery-circuits arranged adjacent to each other, in accordance with a phase difference between the pieces of input data and a phase difference between the output clocks of the respective clock-and-data-recovery-circuits. | 2015-12-03 |
20150349784 | Clock Recovery Techniques - Clock recovery techniques (CRT) useful in a wide variety of communication systems based on wireless, optical and wireline links, include: a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing clocks, waveforms or messages, receiver synchronization techniques (RST) contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock. | 2015-12-03 |
20150349785 | FAST ACQUISITION FREQUENCY DETECTOR - A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison. | 2015-12-03 |
20150349786 | HIGH SPEED CURRENT MODE LATCH - A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal. | 2015-12-03 |
20150349787 | SLOW TO FAST CLOCK SYNCHRONIZATION - A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal. | 2015-12-03 |
20150349788 | CIRCUITS AND METHODS FOR ELIMINATING REFERENCE SPURS IN FRACTIONAL-N FREQUENCY SYNTHESIS - Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL. | 2015-12-03 |
20150349789 | OSCILLATOR CIRCUIT AND CONFIGURATION METHOD THEREOF - The present disclosure provides an oscillator circuit. The oscillator circuit includes a signal selecting unit, a control voltage generating unit, a reference voltage generating unit, an output adjusting unit, and a frequency-dividing unit. The signal selecting unit is configured to select a reference signal or a frequency-divided signal as an input signal. The control voltage generating unit is configured to generate a control voltage based on the input signal. The reference voltage generating unit is configured to generate a reference voltage. The output adjusting unit is configured to generate an output signal based on the control voltage and the reference voltage. The frequency-dividing unit is configured to divide the frequency of the output signal and generate the frequency-divided signal. | 2015-12-03 |
20150349790 | ATOMIC RESONANCE TRANSITION DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - An atomic resonance transition device includes a gas cell having an internal space that seals an alkali metal, a light emitter that emits excitation light containing a resonance light pair that causes the alkali metal to resonate toward the alkali metal, and a magnetic field generator that applies a magnetic field to the alkali metal. The excitation light diverges in a width direction in the internal space as the light travels from a side where the excitation light is incident toward a side where the excitation light exits, and the magnetic field from the magnetic field generator has a portion where the intensity of the magnetic field increases in the internal space with distance from the side where the excitation light is incident toward the side where the excitation light exits. | 2015-12-03 |
20150349791 | ATOM CELL, QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - A gas cell includes an alkali metal, a pair of window parts, a body part provided between the pair of window parts and forming an internal space in which the alkali metal in a gaseous state is enclosed with the pair of window parts, and a space within a recessed part forming a part of the internal space or communicating with the internal space, in which a liquid-state or solid-state alkali metal is placed, and a bottom part as a wall part between the space within the recessed part and an outside has a smaller thickness than the window parts. | 2015-12-03 |
20150349792 | LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS) - Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In particular, a plurality of DAC elements in a digital-to-analog converter (DAC) may be controlled during digital-to-analog conversions, with the controlling comprising use of a switching arrangement that comprises one or more switching elements configured for controlling switching of each of the plurality of DAC elements. The controlling may comprise forcing one or more of the plurality of DAC elements in the DAC to not switch during the digital-to-analog conversions. Further, the remaining DAC elements may be scrambled. The controlling of the plurality of DAC elements in the DAC may be based on analysis of an input to the DAC that is being converted. The analysis may comprise determining when the input is backed off from full-scale. A switching sequence may be applied, via each of the one or more switching elements. | 2015-12-03 |
20150349793 | DIGITAL CALIBRATION OF TRANSMIT DIGITAL TO ANALOG CONVERTER FULL SCALE CURRENT - A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current. | 2015-12-03 |
20150349794 | SELF-CALIBRATING VCO-BASED ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF - A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal. | 2015-12-03 |
20150349795 | COMMON MODE SAMPLING MECHANISM FOR RESIDUE AMPLIFIER IN SWITCHED CURRENT PIPELINE ANALOG-TO-DIGITAL CONVERTERS - A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal. | 2015-12-03 |
20150349796 | DEDICATED ARITHMETIC ENCODING INSTRUCTION - A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction. | 2015-12-03 |
20150349797 | System and Method for Improved Data Transmission - A system, method, and apparatus for compressing binary code comprising at least a processor, memory, storage, and an encoding device or decoding device or both. The methods include comparing a given binary code string having a certain size to be compressed or decompressed with a table comprising all possible combinations of zeroes and ones for any binary data of size x. The given binary code string and all possible combinations are partitioned in packets of size y and each packet assigned a value. A second value representing an assembly of all the values into a second value is performed. The assembly may be performed n times to obtain an nth value. The second or nth value is transmitted or received or both by the encoding and decoding devices, respectively, in place of the given binary code. Table comparison may be performed using pattern recognition. | 2015-12-03 |
20150349798 | CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICE - A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. | 2015-12-03 |
20150349799 | PARALLEL BIT INTERLEAVER - A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word. | 2015-12-03 |
20150349800 | METHOD FOR DETERMINING LAYER STOPPAGE IN LDPC DECODING - A method for determining a layer stoppage in LDPC decoding is provided. The method may include determining the occurrence of the layer stoppage to detect and record a convergence of a layer arithmetic unit after the performance of a layer decoding operation using LDPC decoding, and in a subsequent iteration operation stopping an operation of the layer arithmetic unit that has converged and repeating determining the layer stoppage for the layer arithmetic unit that has not yet converged. An output of the non-convergent layer may be diverted to the next non-convergent layer while bypassing the convergent layer without interrupting the subsequent iteration operation while maintaining the overall error correction capability. | 2015-12-03 |
20150349801 | METHOD AND APPARATUS FOR DECODING NON-BINARY LOW DENSITY PARITY CHECK CODE IN COMMUNICATION SYSTEM - A method for decoding a non-binary Low Density Parity Check (LDPC) code by a decoding apparatus in a communication system is provided. The method includes selecting a predetermined number of symbol messages from among received symbol messages, performing a variable node update process on the selected symbol messages to generate variable node updated symbol messages, performing a check node update process on the variable node updated symbol messages, and performing a decoding operation based on the result of the variable node update process and the check node update process, wherein the performing of the check node update process includes generating an intermediate message for the variable node updated symbol messages using symbol messages which are selected based on reliability, and generating an output message of each edge between a variable node and a check node. | 2015-12-03 |
20150349802 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device including an encoding unit configured to encode an information bit into an LDPC code with a code length of 64800 bits and an encoding rate of 12/30, based on a parity check matrix of an LDPC (Low Density Parity Check) code. The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit. The information matrix part is shown by a parity check matrix initial value table. The parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part every 360 columns. | 2015-12-03 |
20150349803 | ENCODING METHOD, DECODING METHOD - An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. | 2015-12-03 |
20150349804 | METHOD FOR ENCODING MULTI-MODE OF BCH CODES AND ENCODER THEREOF - A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix. | 2015-12-03 |
20150349805 | Method of Handling Error Correcting Code in Non-volatile Memory and Non-volatile Storage Device Using the Same - A method of handling an error correcting code (ECC) in a non-volatile memory includes performing a first ECC operation on data codes to generate first parity codes; compressing the first parity codes to generate compressed parity codes; performing a second ECC operation on the compressed parity codes to generate additional parity codes; and writing the data codes, the compressed parity codes and the additional parity codes into a memory unit of the non-volatile memory. | 2015-12-03 |
20150349806 | TECHNIQUE FOR ADAPTIVELY STRENGTHING ECC FOR FLASH CACHE - In an aspect of the subject matter, a “full” amount of the flash cache (e.g., storage cells) is initially utilized to store data i.e., substantially all of the storage space of the flash cache may be designated to store user data, with the remaining storage space designated to store ECC information (e.g., parity bits) associated with a predefined ECC algorithm utilized to encode the user data. When a bit errors associated with the user data reaches a predefined threshold value, the storage space of the flash cache may transition to store less user data so as to accommodate the space needed to store ECC information associated with a stronger ECC algorithm. The storage space of the flash cache designated to store user data is reduced, while the storage space designated to store ECC information is increased to accommodate the stronger ECC algorithm. | 2015-12-03 |
20150349807 | ERROR CORRECTING CODE DECODER - Apparatuses, systems, methods, and computer program products are disclosed for error correcting code (ECC) decoding. A soft information module may be configured to determine whether to obtain an indication of the accuracy of a data value for a variable node of an ECC decoder such as a low density parity check (LDPC) code decoder. A score module may be configured to assign and update a score for the variable node. The score may be based on the accuracy indication and on a count of unsatisfied check nodes of the ECC decoder that are associated with the variable node. A precision for the score may be based on an estimated number of errors for the received code word. A check node update module may be configured to update check nodes associated with the variable node based on the score. | 2015-12-03 |
20150349808 | Multi-Band Multi-Path Receiving and Transmitting Device and Method, and Base Station System - A multi-band multi-path receiving and transmitting device and method, and a base station system are provided. The multi-band multi-path receiving and transmitting device includes a broadband antenna, at least two multi-frequency couplers, a multi-band transceiver, and a signal processing module. The multi-band transceiver is adopted to decrease the number of the transceivers, thereby reducing the material cost and the mounting cost of the base station system. | 2015-12-03 |
20150349809 | RADIO FREQUENCY SWITCH CONTROLLER - Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution. | 2015-12-03 |
20150349810 | CROSS-MODALITY ELECTROMAGNETIC SIGNATURE ANALYSIS FOR RADIO FREQUENCY PERSONA IDENTIFICATION - Systems and methods can support identifying multiple radio transmitters as being integrated within a single communications device. Radio frequency signals may be collected using one or more sensors incorporating radio receivers. A first radio frequency signature and a second radio frequency signature may be identified within one or more of the radio frequency signals as originating respectively from a first radio transmitter and a second radio transmitter. Characteristics of the first and second radio frequency signatures may be analyzed to evaluate a relationship between the first and second radio frequency signatures. It may be determined whether or not the first and second radio transmitters are integrated within a common wireless electronic device based upon the evaluated relationship between the first radio frequency signature and the second radio frequency signature. Characteristics and behaviors associated with the wireless electronic device may be determined therefrom. | 2015-12-03 |
20150349811 | SCALABLE MAPPING WITH INTEGRATED SUMMING OF SAMPLES FOR MULTIPLE STREAMS IN A RADIO INTERFACE FRAME - An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to buffer a plurality of antenna carrier sample streams. The second circuit is coupled to the first circuit and may be configured to generate message data through pipelined processing and mapping of the antenna carrier samples. The third circuit is coupled to the second circuit and may be configured to generate a master frame in response to the processed and mapped message data. | 2015-12-03 |
20150349812 | CIRCUITS AND METHODS RELATED TO POWER DETECTORS FOR RADIO-FREQUENCY APPLICATIONS - Circuits and methods related to power detectors for radio-frequency (RF) applications. In some embodiments, a power amplifier (PA) system can include a PA circuit having a driver stage and an output stage. The PA system can further include a detector configured to receive a portion of an RF signal from a path between the driver stage and the output stage. The detector can be further configured to generate an output signal representative of power associated with the RF signal and compensated for variation in at least one operating condition associated with the PA circuit. | 2015-12-03 |
20150349813 | APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS - A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data. | 2015-12-03 |
20150349814 | DISTORTION-COMPENSATION DEVICE AND DISTORTION-COMPENSATION METHOD - Disclosed is a distortion compensation apparatus that, by appropriately generating a distortion-compensation coefficient, makes it possible to obtain a desired transmission output, and substantially reduce the amount of power leakage to an adjacent channel. Reception section ( | 2015-12-03 |
20150349815 | RADIO DEVICE - A radio device is configured to be capable of performing upsampling on a forward wave containing a first signal and a second signal to broaden a processing band to a transmission band, then amplifying the forward wave using an amplifier, and transmitting the amplified forward wave. In the radio device, an FW power calculator calculates the power of a first component corresponding to a part of the transmission band from among the forward wave. An Rev power calculator calculates the power of a second component corresponding to a part of the transmission band from among a reflected wave. A VSWR calculator calculates a VSWR using the power of the forward wave calculated by the FW power calculator and the power of the reflected wave calculated by the Rev power calculator. | 2015-12-03 |