49th week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090294869 | Negative Differential Resistance Device and Memory Using the Same - A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory. | 2009-12-03 |
20090294870 | Semiconductor device with trench gate and method of manufacturing the same - A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously. | 2009-12-03 |
20090294871 | SEMICONDUCTOR DEVICES HAVING RARE EARTH METAL SILICIDE CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME - MOS transistors and methods for fabricating MOS transistors are provided. One exemplary method comprises providing a substrate having a silicon-comprising surface region. A first metal silicide layer is formed overlying the silicon-comprising surface region. Ion implantation is used to implant rare earth metal ions at an interface between the first metal silicide layer and the silicon-comprising surface region. The substrate is heated to form a second rare earth metal silicide layer disposed below the first metal silicide layer. | 2009-12-03 |
20090294872 | Ge/Xe IMPLANTS TO REDUCE JUNCTION CAPACITANCE AND LEAKAGE - A method of reducing junction capacitance and leakage and a structure having reduced junction capacitance and leakage wherein germanium or xenon is implanted in the source and drain regions to at least partially deactivate the dopants in the source and drain regions. | 2009-12-03 |
20090294873 | FIELD EFFECT STRUCTURE AND METHOD INCLUDING SPACER SHAPED METAL GATE WITH ASYMMETRIC SOURCE AND DRAIN REGIONS - A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device, such as a field effect transistor, that includes a spacer shaped metal gate located over a channel within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. Within the semiconductor structure, the plurality of source and drain regions is asymmetric with respect to the spacer shaped metal gate. The particular semiconductor structure may be fabricated using a self aligned dummy gate method that uses a portion of a spacer as a self alignment feature when forming the spacer shaped metal gate, which may have a sub-lithographic linewidth. | 2009-12-03 |
20090294874 | Method of Fabricating Semiconductor Apparatus Having Saddle-Fin Transistor and Semiconductor Apparatus Fabricated Thereby - A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench. | 2009-12-03 |
20090294875 | Metal Oxide Semiconductor Device and Method for Manufacturing the Same - A Metal Oxide Semiconductor device includes a semiconductor substrate; a gate electrode formed on the surface of the substrate, having an offset spacer on each side; source/drain electrodes in the substrate having lightly doped regions respectively; metal silicide located on the gate electrode and the source/drain electrodes; and first impurity ions and second impurity ions in the lightly doped regions. A method for manufacturing a Metal Oxide Semiconductor device includes forming a gate electrode on a semiconductor substrate; implanting first impurity ions and second impurity ions to form lightly doped regions; depositing a dielectric layer and etching the dielectric layer to form offset spacers; implanting the first impurity ions to form the source/drain electrodes; forming metal silicide on the surfaces of the gate electrode and the source/drain regions. This invention can effectively prevent metal nickel diffusion into the lightly doped regions. | 2009-12-03 |
20090294876 | METHOD FOR DEPOSITION OF AN ULTRA-THIN ELECTROPOSITIVE METAL-CONTAINING CAP LAYER - A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer. | 2009-12-03 |
20090294877 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, a gate insulating film is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating film. Thick regions of the gate insulating film which are located under both ends of the gate electrode, respectively, have a larger thickness than that of a middle region of the gate insulating film which is located under a middle region of the gate electrode. | 2009-12-03 |
20090294878 | CIRCUITRY AND GATE STACKS - The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack. | 2009-12-03 |
20090294879 | Method for Capping a MEMS Wafer - A method for capping a MEMS wafer to form a hermetically sealed device. The method includes applying a glass bonding agent to the cap wafer and burning off organic material in the glass bonding agent. The cap wafer/glass bonding agent combination is then cleaned to reduce lead in the combination. The cleaning is preferably accomplished using an oxygen plasma. The MEMS device is coated with a WASA agent. The cap wafer is then bonded to the MEMS wafer by heating this combination in a capping gas atmosphere of hydrogen molecules in a gas such as nitrogen, argon or neon. This method of capping the MEMS wafer can reduce stiction in the MEMS device. | 2009-12-03 |
20090294880 | Method for manufacturing a sensor element, and sensor element - A method for manufacturing a capped sensor element by providing a substrate with a sensor structure, the sensor structure being produced in the substrate using a sacrificial material, applying a cap made of zeolite to the sensor structure and the sacrificial material, and removing the sacrificial material, the sacrificial material being removed through the cap made of zeolite. A sensor element having capping is also provided. | 2009-12-03 |
20090294881 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH | 2009-12-03 |
20090294882 | METHODS AND SYSTEMS FOR MAGNETIC SENSING - One embodiment relates to a method of manufacturing a magnetic sensor. In the method, an engagement surface is provided. A magnet body is formed over the engagement surface by gradually building thickness of a magnetic material. The magnet body has a magnetic flux guiding surface that substantially corresponds to the engagement surface. Other apparatuses and methods are also set forth. | 2009-12-03 |
20090294883 | METHOD FOR ELECTRONICALLY PINNING A BACK SURFACE OF A BACK-ILLUMINATED IMAGER FABRICATED ON A UTSOI WAFER - A method for fabricating a back-illuminated imager which has a pinned back surface is disclosed. A first insulator layer is formed overlying a mechanical substrate. A conductive layer is deposited overlying the first insulator layer. A second insulator layer is formed overlying the conductive layer to form a first structure, an interface being formed between the conductive layer and the second insulator layer, the conductive layer causing band bending proximal to the interface such that the interface is electrically pinned. Hydrogen is implanted in a separate device wafer to form a bubble layer. A final insulator layer is formed overlying the device wafer to form a second structure. The first structure and the second structure are bonded to form a combined wafer. A portion of the combined wafer is removed underlying the bubble layer to expose a seed layer comprising the semiconductor material substantially overlying the second insulator layer. | 2009-12-03 |
20090294884 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate. | 2009-12-03 |
20090294885 | Silicon Nanoparticle Embedded Insulating Film Photodetector - A photodetector is provided with a method for fabricating a semiconductor nanoparticle embedded Si insulating film for photo-detection applications. The method provides a bottom electrode and introduces a semiconductor precursor and hydrogen. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a semiconductor nanoparticle embedded Si insulating film is formed, where the Si insulating film includes either N or C elements. For example, the Si insulating film may be a non-stoichiometric SiO | 2009-12-03 |
20090294886 | METHOD OF MAKING WAFER STRUCTURE FOR BACKSIDE ILLUMINATED COLOR IMAGE SENSOR - An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic. | 2009-12-03 |
20090294887 | Semiconductor device - A semiconductor device comprises a semiconductor substrate comprised of an interposer having one surface and a semiconductor element provided on the one surface of the interposer, the semiconductor element including a light receiving portion for receiving light thereon; a transparent substrate having light-transmitting property and one surface facing the light receiving portion, the transparent substrate arranged in a spaced-apart relationship with the one surface of the interposer through a gap formed between the one surface of the interposer and the one surface of the transparent substrate; and a spacer formed in a shape of a frame, the spacer positioned between the one surface of the interposer and the one surface of the transparent substrate for regulating the gap, and the spacer having an inner surface and an outer surface, wherein the one surface of the interposer, the one surface of the transparent substrate and the inner surface of the spacer form a space which is hermetically sealed, and wherein the spacer has a wall including at least one thin wall portion and a thick wall portion other than the at least one thin wall portion, and a vapor permeability of the at least one thin wall portion is greater than a vapor permeability of the thick wall portion, wherein a vapor allowed to flow into the space through the wall of the spacer from an outside preferentially permeates from the space to the outside through the thin wall portion. The semiconductor device is capable of reliably preventing dust from infiltrating into the semiconductor device and capable of reliably preventing occurrence of dew condensation in an inner wall of the semiconductor device, particularly on an inner surface of a transparent substrate. | 2009-12-03 |
20090294888 | METHOD FOR FABRICATING AN IMAGE SENSOR - A method for fabricating an image sensor is disclosed. First, a semiconductor substrate is provided, in which a photosensitive region is defined on the semiconductor substrate. At least one photosensitive material is then formed on the semiconductor substrate, and a first exposure process is performed to form a tapered pattern in the photosensitive material. A second exposure process is performed to form a straight foot pattern in the photosensitive material, and a developing process is performed to remove the tapered pattern and straight foot pattern to form the photosensitive material into a plurality of photosensitive blocks. A reflow process is conducted thereafter to form the photosensitive blocks into a plurality of microlenses. | 2009-12-03 |
20090294889 | Semiconductor device - A semiconductor device according to the present invention includes a semiconductor substrate: a photodiode responsive to a light, which is formed in the semiconductor substrate; at least an interlayer insulating layer formed over the semiconductor substrate, the at least an interlayer insulating layer comprising an upper most insulating layer; at least a conductive wiring layer, comprising an upper most conductive wiring layer formed on the upper most insulating layer; and a first passivation layer formed over the upper-most conductive wiring layer. The upper-most wiring layer is not formed directly above the photodiode. The first passivation layer is made of a permeability-resist material and is not formed directly above the photodiode. | 2009-12-03 |
20090294890 | MULTI-COLOUR SENSITIVE DEVICE FOR COLOR IMAGE SENSING - A sensor element ( | 2009-12-03 |
20090294891 | SEMICONDUCTOR DEVICE - A semiconductor layer of a vertical diode is divided into a center region and a surrounding region. An anode electrode contacts a surface of the center region in the semiconductor layer. An insulation layer contacts a surface of the surrounding region in the semiconductor layer. Ring-shaped FLR regions are formed in the surface of the surrounding region in the semiconductor layer. The innermost FLR region extends from an inside to an outside of a boundary between the anode electrode and the insulation layer and extends along the boundary. A shoulder portion is formed in the surface of the semiconductor layer in a manner such that a portion that contacts the insulation layer is higher than a portion that contacts the anode electrode. Flows of holes directed toward the anode electrode pass through a plurality of positions in the shoulder portion. | 2009-12-03 |
20090294892 | Edge Termination for Semiconductor Devices - A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion. | 2009-12-03 |
20090294893 | ISOLATION TRENCH INTERSECTION STRUCTURE WITH REDUCED GAP WIDTH - The invention relates to isolation trenches having a high aspect ratio for trench-insulated smart power technologies in Silicon On Insulator (SOI) silicon wafers. The specific geometric layout of the intersections and junctions of the isolation trenches allows error rate reduction and simplification of manufacture. | 2009-12-03 |
20090294894 | INTEGRATED CIRCUIT HAVING LOCALIZED EMBEDDED SiGe AND METHOD OF MANUFACTURING - An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate. | 2009-12-03 |
20090294895 | INTEGRATED CIRCUIT WITH CONDUCTIVE STRUCTURES - An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors. | 2009-12-03 |
20090294896 | SHALLOW TRENCH ISOLATION PROCESS UTILIZING DIFFERENTIAL LINERS - A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate. | 2009-12-03 |
20090294897 | SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS - A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion. | 2009-12-03 |
20090294898 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES - Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material. | 2009-12-03 |
20090294899 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS - A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via. | 2009-12-03 |
20090294900 | Fuse Device - Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device. | 2009-12-03 |
20090294901 | STRUCTURE AND METHOD OF FORMING ELECTRICALLY BLOWN METAL FUSES FOR INTEGRATED CIRCUITS - A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer. | 2009-12-03 |
20090294902 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively. | 2009-12-03 |
20090294903 | ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME - An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer. | 2009-12-03 |
20090294904 | INTEGRATED CIRCUIT SYSTEM EMPLOYING BACK END OF LINE VIA TECHNIQUES - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group. | 2009-12-03 |
20090294905 | Semiconductor device - A substrate is provided with a first wiring layer | 2009-12-03 |
20090294906 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME, AND LIGHT MODULATION DEVICE AND FABRICATION METHOD FOR THE SAME - A light modulation device, which uses the ITO used as a transparent electrode as an etching mask of the PLZT, performing the self-aligned formation, and a fabrication method for the light modulation device is provided. A light modulation device includes a substrate; and a ferroelectric capacitor placed on the substrate and includes a lower electrode, a ferroelectric film placed on the lower electrode, and an upper electrode placed on the ferroelectric film, and the upper electrode includes a conducting film by which self-alignment patterning is performed to the ferroelectric film as an etching mask of the ferroelectric film, and the ferroelectric capacitor is provided so as to laminate on the substrate, and the ferroelectric capacitor is functioned as a Fabry-Perot type resonator from which a refractive index of the ferroelectric film changes according to an electric field applied between the lower electrode and the upper electrode. | 2009-12-03 |
20090294907 | SEMICONDUCTOR COMPONENT WITH MIM CAPACITOR - A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode. | 2009-12-03 |
20090294908 | Diluted magnetic semiconductor nanowires exhibiting magnetoresistance - A method for is disclosed for fabricating diluted magnetic semiconductor (DMS) nanowires by providing a catalyst-coated substrate and subjecting at least a portion of the substrate to a semiconductor, and dopant via chloride-based vapor transport to synthesize the nanowires. Using this novel chloride-based chemical vapor transport process, single crystalline diluted magnetic semiconductor nanowires Ga | 2009-12-03 |
20090294909 | N-type group III nitride-based compound semiconductor and production method therefor - An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. | 2009-12-03 |
20090294910 | SILICON WAFER - A reinforcement member made with silicon carbide different from silicon is installed on the back face of a silicon wafer, thereby the silicon wafer is increased in Young's modulus and the wafer is less likely to deflect. | 2009-12-03 |
20090294911 | Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets - A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die. | 2009-12-03 |
20090294912 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region. | 2009-12-03 |
20090294913 | Method for manufacturing semiconductor chip and semiconductor device - An improved yield of chips is realized by reducing the width of dicing streets on the front surface side of a semiconductor wafer. A method for semiconductor chip, divided a semiconductor wafer | 2009-12-03 |
20090294914 | Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material - A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die. | 2009-12-03 |
20090294915 | TSV-Enabled Twisted Pair - A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace. | 2009-12-03 |
20090294916 | BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING - There is described a hybrid bonding method for through-silicon-via based wafer stacking. Patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bondng is used to electrically connect the vias. The adhesive layers are patterned to enable outgassing and to provide stress relief. | 2009-12-03 |
20090294917 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process. | 2009-12-03 |
20090294918 | SEMICONDUCTOR WAFER - In a state where a semiconductor wafer is not acted upon by its own weight, a shear stress on a rear surface side portion of the semiconductor wafer is higher than that on a front surface side portion of the semiconductor wafer, in a compression direction. Thereby, sag of the semiconductor wafer is reduced when the semiconductor wafer is simple-supported in a horizontal state. | 2009-12-03 |
20090294919 | METHOD OF FORMING A FINFET AND STRUCTURE - A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer. | 2009-12-03 |
20090294920 | METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N | 2009-12-03 |
20090294921 | SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORMED DIELECTRIC CAP LAYER - A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity. | 2009-12-03 |
20090294922 | ORGANIC SILICON OXIDE FINE PARTICLE AND PREPARATION METHOD THEREOF, POROUS FILM-FORMING COMPOSITION, POROUS FILM AND FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - Provided is an organic silicon oxide fine particle capable of satisfying an expected dielectric constant and mechanical strength and having excellent chemical stability for obtaining a high-performance porous insulating film. More specifically, provided is an organic silicon oxide fine particle comprising a core comprising an inorganic silicon oxide or a first organic silicon oxide containing an organic group having a carbon atom directly attached to a silicon atom and, and a shell on or above an outer circumference of the core, the shell comprising a second organic silicon oxide different from the first organic silicon oxide which the second organic silicon has been formed by hydrolysis and condensation, in the presence of a basic catalyst, of a shell-forming component comprising an organic-group-containing hydrolyzable silane containing an organic group having a carbon atom directly attached to a silicon atom or a mixture of the organic-group-containing hydrolyzable silane and an organic-group-free hydrolyzable silane not having the organic group, wherein a ratio [C]/[Si] is 0 or greater but less than 1 in the core and 1 or greater 1 in the shell wherein [C] represents the number of all the carbon atoms and [Si] represents the number of all the silicon atoms. | 2009-12-03 |
20090294923 | Structure and Method for Reducing Threshold Voltage Variation - A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage. | 2009-12-03 |
20090294924 | HAFNIUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film. | 2009-12-03 |
20090294925 | MECHANICALLY ROBUST METAL/LOW-k INTERCONNECTS - A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material. | 2009-12-03 |
20090294926 | DEEP TRENCH IN A SEMICONDUCTOR STRUCTURE - A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening. | 2009-12-03 |
20090294927 | SEMICONDUCTOR-DEVICE ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREBY - A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, forming a cap film covering the substrate and filling the recess, performing an etching process to remove the cap film outside the recess, and forming a contact etch stop layer covering the substrate and filling the recess. Due to the filling recess with the cap film first, the contact etch stop layer covering the substrate and filling the recess does not have seams or voids. | 2009-12-03 |
20090294928 | Semiconductor Device and Method of Forming Holes In Substrate to Interconnect Top Shield and Ground Shield - A shielded semiconductor device is made by embedding a ground shield between layers of a substrate. Semiconductor die are mounted to the substrate over the ground shields. An encapsulant is formed over the semiconductor die and substrate. The encapsulant is diced to form dicing channels between the semiconductor die. A plurality of openings is drilled into the substrate along the dicing channels down through the ground shield on each side of the semiconductor die. A top shield is formed over the semiconductor die. The openings in the substrate are filled with a shielding material to electrically and mechanically connect the top shield to the ground shield. The substrate is singulated to separate the semiconductor die with top shield and ground shield into individual semiconductor devices. IPDs in the semiconductor die generate electromagnetic interference which is blocked by the respective top shield and ground shield. | 2009-12-03 |
20090294929 | SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS - A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling. | 2009-12-03 |
20090294930 | Semiconductor packages having electromagnetic interference-shielding function, manufacturing method thereof and jig - The present invention relates to relates to a semiconductor package having a function of shielding electromagnetic interference (EMI), a manufacturing method thereof and a jig, and more particularly, to such a semiconductor package having an electromagnetic interference (EMI)-shielding function, a manufacturing method thereof and a jig for use in a plasma sputtering, in which a nickel alloy is coated on the surface of a semiconductor package by a sputtering method so as to shield electromagnetic interference (EMI) generated from the semiconductor package. | 2009-12-03 |
20090294931 | Methods of Making an Electronic Component Package and Semiconductor Chip Packages - An electronic component package having an EMI shielded space is disclosed. The package comprises a substrate having an electronic component located on its surface and a conductive enclosure having a top and downwardly extending sides enclosing the component and defining a shielded space. A vent opening is provided through the substrate and is located in the shielded space for venting the shielded space. A second vent opening may be provided in the top of the conductive enclosure. | 2009-12-03 |
20090294932 | LEADFRAME HAVING DELAMINATION RESISTANT DIE PAD - A lead frame ( | 2009-12-03 |
20090294933 | Lead Frame and Chip Package Structure and Method for Fabricating the Same - The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted. | 2009-12-03 |
20090294934 | CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE - A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers. | 2009-12-03 |
20090294935 | SEMICONDUCTOR PACKAGE SYSTEM WITH CUT MULTIPLE LEAD PADS - A semiconductor package system includes: providing a leadframe having inner frame bars, outer frame bars, a die pad, tiebars, and rows of leads, the inner frame bars being coplanar with outer frame bars; attaching a semiconductor chip to the die pad; attaching bond wires between the semiconductor chip and the rows of leads; encapsulating the semiconductor chip, the bond wires, the inner frame bars, the outer frame bars, the die pad, the tiebars, and the rows of leads in an encapsulant; cutting a groove to remove the inner frame bars; and singulating the leadframe and the encapsulant to remove the outer frame bars. | 2009-12-03 |
20090294936 | FOUR MOSFET FULL BRIDGE MODULE - A molded, leadless packaged semiconductor multichip module includes | 2009-12-03 |
20090294937 | TWO-WAY HEAT EXTRACTION FROM PACKAGED SEMICONDUCTOR CHIPS - One embodiment of the invention is a semiconductor device ( | 2009-12-03 |
20090294938 | FLIP-CHIP PACKAGE WITH FAN-OUT WLCSP - A flip-chip package includes a package carrier; a semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, and contact pads are situated on the die face; a rewiring laminate structure between the semiconductor die and the package carrier, the rewiring laminate structure including a re-routed metal layer, and at least a portion of the re-routed metal layer projects beyond the die edge; and bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier. | 2009-12-03 |
20090294939 | LEAD FRAME AND SEMICONDUCTOR DEVICE UTILIZING THE SAME - A lead frame and semiconductor device providing improved bond strength from wave bonding such as of wires in lead frames manufactured with depressed inner leads. The lead frame comprises an outer lead, an inner lead, a step difference section formed between the outer lead and inner lead, and an extended section extending from the inner lead towards the outer lead side. The extended section is provided to be adjacent to the step difference section. An acceptor clamp jig set on the lead frame includes a body, an inner lead support section and extended section support section respectively corresponding to the outer lead, the inner lead and the extended section. The outer lead is pressed from above by a retainer clamp jig. The extended section of the inner lead and the extension support section of the acceptor clamp jig prevent the tip of the inner lead from floating upward by acting together to accept and resist the tensile stress applied on the step difference section of the lead. Ultrasonic waves are in this way applied more efficiently and ultrasonic wave loss in the bond part between the inner lead and the wire is reduced. | 2009-12-03 |
20090294940 | SEMICONDUCTOR LIGHT EMITTING DEVICE - The semiconductor device includes a support substrate | 2009-12-03 |
20090294941 | PACKAGE-ON-PACKAGE SYSTEM WITH HEAT SPREADER - A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base. | 2009-12-03 |
20090294942 | PACKAGE ON PACKAGE USING A BUMP-LESS BUILD UP LAYER (BBUL) PACKAGE - In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented. In this regard, an apparatus is introduced comprising a microelectronic die having an active surface, an inactive surface parallel to said active surface, and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes a bottom surface substantially planar to said microelectronic die active surface and a top surface substantially planar to said microelectronic die inactive surface, a through via connection in said encapsulation material extending from said top surface to said bottom surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface. Other embodiments are also disclosed and claimed. | 2009-12-03 |
20090294943 | Stacked structure of integrated circuits having space elements - A stacked structure of integrated circuits having spacer elements includes a substrate, a spacer element, a lower-layer integrated circuit, an upper-layer integrated circuit, and a molding layer. The substrate includes an upper surface on which the spacer element and the lower-layer integrated circuit are arrayed with each other. The lower-layer integrated circuit includes a solder-pad region and a non-solder-pad region adjacent to the spacer element. The upper-layer integrated circuit is disposed on the spacer element, and covers partly over the non-solder-pad region of the lower-layer integrated circuit. Therefore, the overall height of the stacked structure of integrated circuits can be lowered, making the packaging process simplified, the manufacturing process more stable, and the yield rate of production will be raised. Since the inlet end of the wire is electrically connected to the solder pad of the upper-layer integrated circuit, the height of the packaging can be reduced, and so the whole height of the stacked structure of integrated circuits. | 2009-12-03 |
20090294944 | SEMICONDUCTOR DEVICE ASSEMBLY AND METHOD THEREOF - A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements. | 2009-12-03 |
20090294945 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between. The uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers. | 2009-12-03 |
20090294946 | Package-Borne Selective Enablement Stacking - The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs. | 2009-12-03 |
20090294947 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip. | 2009-12-03 |
20090294948 | Contrast Interposer Stacking System And Method - The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices. | 2009-12-03 |
20090294949 | MOLDED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip and at least one metal line over a first side of the semiconductor chip. The semiconductor device includes a molded body covering at least a second side of the semiconductor chip. The molded body includes at least one recess. | 2009-12-03 |
20090294950 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized. | 2009-12-03 |
20090294951 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light. | 2009-12-03 |
20090294952 | CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF - The present invention discloses a chip package carrier and a fabrication method, which have the advantages of high reliability, thickness reduction and the scale reduction. The carrier and the method uses blind holes., which penetrates the substrate but external traces and external bonding pads, which cover the external traces. A chip can be installed and encapsulated directly on a first surface. | 2009-12-03 |
20090294953 | INTEGRATED CIRCUIT PACKAGE MODULE AND METHOD OF THE SAME - The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening. The outer contacting portion is provided for electronically connecting an electronic device to the patterned conductive layer selectively at the front side through the second opening and at the back side through the first opening. | 2009-12-03 |
20090294954 | 3-D ICs WITH MICROFLUIDIC INTERCONNECTS AND METHODS OF CONSTRUCTING SAME - Three dimensional integrated circuits with microfluidic interconnects and methods of constructing same are provided. According to some embodiments, and microfluidic integrated circuit system can comprise a plurality of semiconductor die wafers each having a top and bottom exterior surface. The semiconductor die wafers can form a stack of die wafers. The die wafers can comprise one or more channels formed through the die wafers. The channels can extend generally between top and bottom exterior surfaces of the semiconductor die wafers. A plurality of micro-pipes can be disposed between adjacent semiconductor die wafers in the stack. The micro-pipes can enable the channels to be in fluid communication with each other. A barrier layer can be disposed within at least one of the channels and the micro-pipes. The barrier layer can be adapted to prevent a coolant flowing through the at least one of the channels and the micro-pipes from leeching into the channels and micro-pipes. Other embodiments are also claimed and described. | 2009-12-03 |
20090294955 | COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE - An integrated circuit package includes: a substrate; an electronic circuit located on the substrate, the electronic circuit comprising a topography of at least one level; a cooling device located over the electronic circuit; a compliant interface disposed between the electronic circuit and the cooling device, wherein the compliant interface comprises a first surface and a second surface and wherein the first surface is in thermal contact with the electronic circuit, and wherein the compliant interface is preformed from a compliant material such that the first surface substantially conforms to the topography of the electronic circuit. | 2009-12-03 |
20090294956 | Cooling fin and package substrate comprising the cooling fin and manufacturing method thereof - Disclosed herein is a cooling fin, which is excellent in cooling performance and is simply manufactured, a package substrate comprising the cooling fin, and a manufacturing method thereof. Fireable paste containing a carbon component is applied into grooves of a mold, thus forming a cooling fin having a pattern corresponding to the grooves. Thus, it enables the production of cooling fins having various configurations, thus improving a cooling performance of a package substrate incorporating the cooling fin. | 2009-12-03 |
20090294957 | APPARATUS AND METHOD FOR INCREASING THE QUANTITY OF DISCRETE ELECTRONIC COMPONENTS IN AN INTEGRATED CIRCUIT PACKAGE - An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package. | 2009-12-03 |
20090294958 | WAFER LEVEL REDISTRIBUTION USING CIRCUIT PRINTING TECHNOLOGY - Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. A wafer has a surface defined by a plurality of integrated circuit regions Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. An ink jet printer is configured to print a plurality of routing interconnects on the surface of a wafer in the form of an ink. The ink jet printer is configured to print the plurality of routing interconnects such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer. Bump interconnects are attached to the routing interconnects. The wafer may be singulated to create a plurality of wafer-level integrated circuits. | 2009-12-03 |
20090294959 | Semiconductor package device, semiconductor package structure, and fabrication methods thereof - A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer. | 2009-12-03 |
20090294960 | SEMICONDUCTOR DEVICE - A semiconductor device, including: a substrate having an upper face on which a first ground pad, a first power supply pad, a first signal pad, and a second signal pad are formed; a first substrate formed on the substrate and having an upper face on which a third signal pad connected to the first signal pad and a first circuit are formed; and a semiconductor element including a second substrate having a reverse face on which a bump electrode connected to the first circuit and a second circuit are formed and an upper face on which a fourth signal pad connected to the second signal pad is formed, with a signal through via connected to the second circuit and the fourth signal pad being buried in the second substrate. | 2009-12-03 |
20090294961 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip and a metal layer electrically coupled to the semiconductor chip. The semiconductor device includes an array of solder balls coupled to the metal layer and a front side protect material directly contacting the metal layer and laterally surrounding a portion of at least a plurality of solder balls. The front side protect material is configured to become fluid during solder reflow. | 2009-12-03 |
20090294962 | PACKAGING SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications. | 2009-12-03 |
20090294963 | MODULE INCLUDING A SINTERED JOINT - A method comprises applying a paste comprising metal grains, a solvent, and a sintering inhibitor to one of a die and a metal layer. The method comprises evaporating the solvent in the paste and placing the one of the die and the metal layer on the other of the die and the metal layer such that the paste contacts the die and the metal layer. The method comprises applying a force to the one of the die and the metal layer and decomposing the sintering inhibitors to form a sintered joint joining the die to the metal layer. | 2009-12-03 |
20090294964 | ELECTRICALLY-CONDUCTIVE INORGANIC COATING, METHOD FOR PRODUCING THE COATING, CIRCUIT BOARD, AND SEMICONDUCTOR APPARATUS - A method for producing an electrically-conductive inorganic coating includes depositing, on a substrate, a coating-precursor containing a plurality of inorganic particles and at least one kind of organic component by a liquid-phase method by using a material-liquid containing the inorganic particles and an organic solvent. The inorganic particles are coated with a dispersant binding to the surfaces of the inorganic particles by chemical bonds that can be broken by oxidation. Further, the method includes oxidizing the coating-precursor at a temperature exceeding 100° C., and that is less than or equal to the pyrolysis initiation temperature of an organic component that has the highest pyrolysis initiation temperature among the at least one kind of organic component and less than or equal to the heat-resistance temperature of the substrate, thereby breaking the chemical bonds to eliminate the dispersant from the surfaces, and decomposing the at least one kind of organic component. | 2009-12-03 |
20090294965 | Method of Manufacturing A Semiconductor Device - Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping. | 2009-12-03 |
20090294966 | CARBON NANOTUBES AS INTERCONNECTS IN INTEGRATED CIRCUITS AND METHOD OF FABRICATION - A method of making an electrode, such as an interconnect for a semiconductor device, includes forming aligned carbon nanotubes using dielectrophoresis. | 2009-12-03 |
20090294967 | Diodes, And Methods Of Forming Diodes - Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes. | 2009-12-03 |
20090294968 | SUPPRESSION OF LOCALIZED METAL PRECIPITATE FORMATION AND CORRESPONDING METALLIZATION DEPLETION IN SEMICONDUCTOR PROCESSING - A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire. | 2009-12-03 |