48th week of 2021 patent applcation highlights part 75 |
Patent application number | Title | Published |
20210376070 | NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION - This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate. | 2021-12-02 |
20210376071 | DIELECTRIC FINS WITH AIR GAP AND BACKSIDE SELF-ALIGNED CONTACT - A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins. | 2021-12-02 |
20210376072 | Reducing Parasitic Capacitance in Semiconductor Devices - A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap. | 2021-12-02 |
20210376073 | CONFINED SOURCE/DRAIN EPITAXY REGIONS AND METHOD FORMING SAME - A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin. | 2021-12-02 |
20210376074 | ISOLATION STRUCTURE OF SEMICONDUCTOR AND METHOD OF FORMING THE SAME - Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench ; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure. | 2021-12-02 |
20210376075 | RFSOI SEMICONDUCTOR STRUCTURES INCLUDING A NITROGEN-DOPED CHARGE-TRAPPING LAYER AND METHODS OF MANUFACTURING THE SAME - A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range. | 2021-12-02 |
20210376076 | Semiconductor Device and Method - In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact. | 2021-12-02 |
20210376077 | Integrated Circuit Device with Source/Drain Barrier - Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin. | 2021-12-02 |
20210376078 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure. | 2021-12-02 |
20210376079 | METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR USING CARBON NANOTUBES AND A FIELD EFFECT TRANSISTOR - In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT. | 2021-12-02 |
20210376080 | MEMORY DEVICE AND METHOD OF FABRICATING THE MEMORY DEVICE - The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group. | 2021-12-02 |
20210376081 | Gate-All-Around Field-Effect Transistor Device - A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires. | 2021-12-02 |
20210376082 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device in which the contact resistance of the body electrode is reduced without reducing the channel mobility. The p-type layer is a Mg-doped p-GaN layer deposited on the first re-type layer. The p-type layer has a two-layer structure in which a first p-type layer and a second p-type layer are sequentially deposited. The second p-type layer has a Mg concentration higher than the Mg concentration of the first p-type layer. The recess is formed in a predetermined position on the surface of the second n-type layer, and has a depth passing through the second n-type layer and reaching the second p-type layer. The body electrode is formed on the bottom surface of the recess in contact with the p-type layer exposed thereon. | 2021-12-02 |
20210376083 | Integrated Assemblies, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies. | 2021-12-02 |
20210376084 | PROTRUSION FIELD-EFFECT TRANSISTOR AND METHODS OF MAKING THE SAME - A transistor, integrated semiconductor device and methods of making. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer. | 2021-12-02 |
20210376085 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE HAVING POSITION-DEPENDENT HEAT GENERATION - A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height. | 2021-12-02 |
20210376086 | PASSIVATION LAYER FOR EPITAXIAL SEMICONDUCTOR PROCESS - The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. | 2021-12-02 |
20210376087 | SEMICONDUCTOR STRUCTURE OF TRENCH TRANSISTORS AND MANUFACTURING METHOD THEREOF - A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches. | 2021-12-02 |
20210376088 | SEMICONDUCTOR WAFER HAVING EPITAXIAL LAYER - A semiconductor wafer of monocrystalline silicon. The semiconductor wafer having: a substrate wafer of monocrystalline silicon; and a layer of monocrystalline silicon that lies on a front side of the substrate wafer. The substrate wafer has a crystal orientation. An averaged front side-based ZDD of the semiconductor wafer, with a division of a surface of an epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than −30 nm/mm | 2021-12-02 |
20210376089 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals. | 2021-12-02 |
20210376090 | ELECTRODE STRUCTURE FOR VERTICAL GROUP III-V DEVICE - Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer. | 2021-12-02 |
20210376091 | SILICIDE-SANDWICHED SOURCE/DRAIN REGION AND METHOD OF FABRICATING SAME - A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure. | 2021-12-02 |
20210376092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening. | 2021-12-02 |
20210376093 | Self-Aligned Backside Source Contact Structure - A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer. | 2021-12-02 |
20210376094 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor. | 2021-12-02 |
20210376095 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer. | 2021-12-02 |
20210376096 | Multigate Device Having Reduced Contact Resistivity - An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10 | 2021-12-02 |
20210376097 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film. | 2021-12-02 |
20210376098 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a plurality of isolation regions in the substrate and an active region surrounded by the isolation regions. A p-type doped region is interposed between two n-type doped regions in the substrate. A buried gate structure is formed in the substrate and disposed between the p-type doped region and the n-type doped region. The buried gate structure comprises a gate conductive material, a gate insulating layer disposed over the gate conductive material and a gate liner surrounding the gate conductive material and the gate insulating layer. A plurality of contact plugs are formed on the p-type doped region and the plurality of n-type doped regions. | 2021-12-02 |
20210376099 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor. | 2021-12-02 |
20210376100 | PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES - A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall. | 2021-12-02 |
20210376101 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region. | 2021-12-02 |
20210376102 | QUANTUM DOT DEVICES WITH TRENCHED SUBSTRATES - Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material. | 2021-12-02 |
20210376103 | LINER-FREE CONDUCTIVE STRUCTURES - The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure. | 2021-12-02 |
20210376104 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer. | 2021-12-02 |
20210376105 | Semiconductor Devices and Methods of Manufacture - Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material. | 2021-12-02 |
20210376106 | GATE STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure. | 2021-12-02 |
20210376107 | FERROELECTRIC FIELD EFFECT TRANSISTOR - Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer. | 2021-12-02 |
20210376108 | FERROELECTRIC CHANNEL FIELD EFFECT TRANSISTOR - Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant. | 2021-12-02 |
20210376109 | METHOD OF FORMING MULTIPLE-VT FETS FOR CMOS CIRCUIT APPLICATIONS - A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction. | 2021-12-02 |
20210376110 | METHOD OF FABRICATING DIODE STRUCTURE - A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method. | 2021-12-02 |
20210376111 | Semiconductor Devices with Air Gate Spacer and Air Gate Cap - A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids. | 2021-12-02 |
20210376112 | TRANSISTOR SPACER STRUCTURES - The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material. | 2021-12-02 |
20210376113 | Post-Formation Mends of Dielectric Features - The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride. | 2021-12-02 |
20210376114 | FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region. | 2021-12-02 |
20210376115 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate. The bottom part is trimmed so that a width of an uppermost portion of the bottom part is smaller than a width of the upper part. Bottom end corners of the upper part are trimmed to reduce a width of the upper part at a bottom of the upper part. An isolation insulating layer is formed so that the upper part protrudes from the isolation insulating layer. A dummy gate structure is formed. A source/drain structure is formed. An interlayer dielectric layer is formed over the dummy gate structure and the source/drain structure. The dummy gate structure is replaced with a metal gate structure. | 2021-12-02 |
20210376116 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns. | 2021-12-02 |
20210376117 | METHOD FOR MANUFACTURING AN IGBT DEVICE - A method for manufacturing an IGBT device includes: forming a cell structure of the IGBT device in a substrate; forming front metal layers on the substrate; thinning the substrate; forming a collector region on the back of the substrate; forming back metal layers on the back of the substrate; and forming target metal on the front and back of the substrate via electroless plating processes. | 2021-12-02 |
20210376118 | STRUCTURES AND METHODS FOR CONTROLLING DOPANT DIFFUSION AND ACTIVATION - Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer. | 2021-12-02 |
20210376119 | Multi-Gate Devices With Multi-Layer Inner Spacers And Fabrication Methods Thereof - A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer. | 2021-12-02 |
20210376120 | THIRD GENERATION FLASH MEMORY STRUCTURE WITH SELF-ALIGNED CONTACT AND METHODS FOR FORMING THE SAME - A memory device and method of making the same are disclosed. The memory device includes a first split gate memory cell including a first memory stack located over a substrate. The first memory stack includes a first floating gate and a first control gate located above the first floating gate. The split gate memory cell also includes a first select gate located adjacent to the first floating gate and the first control gate and a contact etch stop located over a portion of a top surface of the first select gate. The contact etch stop enables a narrowing of the drain contact via during an etch process. By narrowing the drain contact via, the density of split gate memory cells may be increased. | 2021-12-02 |
20210376121 | METHOD OF FABRICATING METAL GATE TRANSISTOR - A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench. | 2021-12-02 |
20210376122 | Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier. The conducting material less-than-fills the void-space in the lowest first tier. The conducting material is etched from the lowest first tier. After the etching of the conducting material, conductive material is deposited into the void-space of the lowest first tier and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Additional embodiments, including structure independent of method, are disclosed. | 2021-12-02 |
20210376123 | SUBSTRATE PROCESSING METHOD FOR FORMING INNER SPACERS IN A NANO-SHEET DEVICE - A method including depositing a dielectric film on a substrate including stacked structures with recessed portions formed on side surfaces of each of the stacked structures, wherein the dielectric film is deposited so that the stacked structures are covered at a thickness which is equal to or less than half a width of the recessed portions; filling a trench or trenches that are located between the stacked structures with a sacrificial film; etching the sacrificial film along the stacked structures; etching the dielectric film so that the dielectric film is etched more than the sacrificial film; removing the sacrificial film; after the removing of the sacrificial film, depositing a dielectric film to a thickness equal to or less than half the width of the recessed portions; and etching the deposited dielectric film, on a condition that the deposited dielectric film remains in the recessed portions. | 2021-12-02 |
20210376124 | Radical Etching in Gate Formation - A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height. | 2021-12-02 |
20210376125 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees. | 2021-12-02 |
20210376126 | INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME - Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region. | 2021-12-02 |
20210376127 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides a method for producing a semiconductor device in which the on-resistance can be reduced while increasing the threshold voltage. A first n-type layer, a first p-type layer, a second p-type layer, and a second n-type layer are sequentially deposited through MOCVD on a substrate. The second p-type layer has a Mg concentration higher than the Mg concentration of the first p-type layer and not less than 6×10 | 2021-12-02 |
20210376128 | FIN SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - A manufacturing method of a fin semiconductor device comprises: providing a substrate, wherein a fin channel base is patterned on and in contact with the substrate; epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core; oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer at the top part of the fin channel base and an intermediate part of the fin channel base under the top part; and removing the oxide layer to expose the fin channel core, wherein the fin channel core suspends over the substrate. | 2021-12-02 |
20210376129 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices and methods of forming semiconductor devices are described herein. A method includes forming a first fin and a second fin in a substrate. A low concentration source/drain region is epitaxially grown over the first fin and over the second fin. The material of the low concentration region has less than 50% by volume of germanium. A high concentration contact landing region is formed over the low concentration regions. The material of the high concentration contact landing region has at least 50% by volume germanium. The high concentration contact landing region has a thickness of at least 1 nm over a top surface of the low concentration source/drain region. | 2021-12-02 |
20210376130 | Semiconductor Device with Varying Numbers of Channel Layers and Method of Fabrication Thereof - A method includes providing a structure having a frontside and a backside, the structure including a substrate, two or more semiconductor channel layers over the substrate and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure; recessing the first S/D feature, thereby exposing a terminal end of one of the semiconductor channel layers; and depositing a dielectric layer on the first S/D feature and covering the exposed terminal end of the one of the semiconductor channel layers. | 2021-12-02 |
20210376131 | FIN SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - A manufacturing method of a fin semiconductor device comprises: providing a substrate; etching the substrate form a fin channel structure protruding from the substrate for a first time to; forming a protective layer made of an oxide on two sidewalls and the top surface of the fin channel structure; etching the substrate for a second time to extend the fin channel structure deeper into the substrate to form the base part of the fin channel structure, wherein the base part is not covered by the protective layer; oxidizing the base part of the fin channel, wherein the upper part of the fin channel is blocked from oxidation by the protective layer; and removing the protective layer and the oxidized base part of the fin channel structure, so that the upper part of the fin channel structure is suspended over the substrate. | 2021-12-02 |
20210376132 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions. | 2021-12-02 |
20210376133 | FIN FIELD-EFFECT TRANSISTOR DEVICE WITH LOW-DIMENSIONAL MATERIAL AND METHOD - A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer. | 2021-12-02 |
20210376134 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts. | 2021-12-02 |
20210376135 | INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE - Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region. | 2021-12-02 |
20210376136 | NITRIDE SEMICONDUCTOR DEVICE - The present disclosure provides a nitride semiconductor device capable of reducing the ohmic contact resistance of a source electrode and a drain electrode with respect to a two-dimensional electron gas. The nitride semiconductor device includes: a first nitride semiconductor layer configured as an electron transportation layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and configured as an electron supply layer, an etch stop layer formed on the second nitride semiconductor layer and formed by a nitride semiconductor material having a bandgap greater than that of the second nitride semiconductor layer, a gate formed on the etch stop layer; and a source electrode and a drain electrode, disposed above the etch stop layer on opposite sides, wherein the gate is between the source electrode and the drain electrode. Lower portions of the source electrode and the drain electrode penetrate the etch stop layer into a middle portion of the second semiconductor layer along a vertical direction. | 2021-12-02 |
20210376137 | STACKED SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer. | 2021-12-02 |
20210376138 | WORK FUNCTION CONTROL IN GATE STRUCTURES - A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials. | 2021-12-02 |
20210376139 | Semiconductor Device and Method - In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide. | 2021-12-02 |
20210376140 | VERTICAL TRANSISTOR WITH SELF-ALIGNED GATE - A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, S | 2021-12-02 |
20210376141 | FinFET Device - A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile. | 2021-12-02 |
20210376142 | WIDE-GAP SEMICONDUCTOR DEVICE - A wide gap semiconductor device has: a drift layer using wide gap semiconductor material being a first conductivity type; a well region being a second conductivity type and provided in the drift layer; a source region provided in the well region; a gate contact region provided in the well region and electrically connected to a gate pad; and a Zener diode region provided in the well region and provided between the source region and the gate contact region. | 2021-12-02 |
20210376143 | POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region. | 2021-12-02 |
20210376144 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors. | 2021-12-02 |
20210376145 | LDMOS DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides an LDMOS device and a manufacturing method thereof. The LDMOS device includes: a substrate, a drift region formed in the substrate; a gate structure, located on the substrate on one side of the drift region, and covering part of the drift region; a drain region, located in the drift region on one side of the gate structure, an isolation structure located on the substrate, the isolation structure located between the drain region and the gate structure; a gate electrode, located on the gate structure and electrically connected with the gate structure; a drain electrode, located on the drain region and electrically connected with the drain region; a block layer, covering the drift region and the isolation structure between the gate electrode and the drain electrode in a shape-preserving manner; and a groove electrode located on the block layer, the groove electrode located between the isolation structure and the gate structure, and at least covering part of the top of the isolation structure. The LDMOS device improves a device breakdown voltage, and cannot increase Rdson. | 2021-12-02 |
20210376146 | LOW LOSS POWER DEVICE AND METHOD FOR FABRICATING THEREOF - Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to optimize device channel resistance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thin dielectric layer may be formed under an extension gate to reduce channel resistance. A thick dielectric layer may be formed under an extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor). | 2021-12-02 |
20210376147 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF HIGH VOLTAGE SEMICONDUCTOR DEVICE - A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer. | 2021-12-02 |
20210376148 | RADIO FREQUENCY (RF) SWITCH DEVICE ON SILICON-ON-INSULATOR (SOI) AND METHOD FOR FABRICATING THEREOF - Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune RF switch FET device performance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor). | 2021-12-02 |
20210376149 | Transistor Structure and Method With Strain Effect - A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack. | 2021-12-02 |
20210376150 | FINFET DEVICE AND METHOD OF FORMING SAME - A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions. | 2021-12-02 |
20210376151 | TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD - A transistor includes a first gate electrode, a composite channel layer, a first gate dielectric layer, and source/drain contacts. The composite channel layer is over the first gate electrode and includes a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer stacked in sequential order. The first gate dielectric layer is located between the first gate electrode and the composite channel layer. The source/drain contacts are disposed on the composite channel layer. | 2021-12-02 |
20210376152 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized. | 2021-12-02 |
20210376153 | Memory Array Gate Structures - A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. | 2021-12-02 |
20210376154 | MULTI-BIT MEMORY STORAGE DEVICE AND METHOD OF OPERATING SAME - A ferroelectric field-effect transistor (FeFET) configured as a multi-bit storage device, the FeFET including: a semiconductor substrate that has a source region in the semiconductor substrate, and a drain region in the semiconductor substrate; a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack, the gate stack including a ferroelectric layer over the semiconductor substrate, and a gate region over the ferroelectric layer. The transistor also includes first and second ends of the ferroelectric layer which are proximal correspondingly to the source and drain regions. The ferroelectric layer includes dipoles. A first set of dipoles at the first end of the ferroelectric layer has a first polarization. A second set of dipoles at the second end of the ferroelectric layer has a second polarization, the second polarization being substantially opposite of the first polarization. | 2021-12-02 |
20210376155 | Semiconductor Devices Including Backside Vias and Methods of Forming the Same - Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure. | 2021-12-02 |
20210376156 | RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME - A transistor, integrated semiconductor device and methods of making. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer. | 2021-12-02 |
20210376157 | HETEROSTRUCTURE OXIDE SEMICONDUCTOR VERTICAL GATE-ALL-AROUND (VGAA) TRANSISTOR AND METHODS FOR MAKING THE SAME - A semiconductor transistor comprises a channel structure comprising a channel region and two source/drain regions located on respective sides of the channel region, wherein the channel region and the two source/drain regions are stacked up along a first direction. A gate structure surrounds the channel region. | 2021-12-02 |
20210376158 | CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES - Contact structures for semiconductor devices are disclosed. Contact structures that include a metal layer and a substrate of a semiconductor device may be annealed to provide suitable contact resistance. Localized annealed regions may be formed in a pattern within the contact structure to provide a desired contact resistance while reducing exposure of other portions of the semiconductor device to anneal conditions. The annealed regions may be formed in patterns that reduce intersections between annealed regions and fracture planes of the substrate, thereby improving mechanical robustness of the semiconductor device. The patterns may include annealed regions formed in lines that are nonparallel with fracture planes of the substrate. The patterns may also include annealed regions formed in lines that are nonparallel with peripheral edges of the substrate. | 2021-12-02 |
20210376159 | FIELD-EFFECT TRANSISTORS WITH A POLYCRYSTALLINE BODY IN A SHALLOW TRENCH ISOLATION REGION - Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material. | 2021-12-02 |
20210376160 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - A thin film transistor is provided. The thin film transistor includes an active layer, and the active layer includes a plurality of stacked structures, and each of the stacked structures includes: a N-layer indium oxidation layer; a gallium oxidation layer, the gallium oxidation layer is provided on the indium oxidation layer of the N-layer indium oxidation layer; and a zinc oxidation layer is provided on the gallium oxidation layer. These stacked structures improve the performance of the thin film transistor. A preparation method of the thin film transistor and a display panel containing the thin film transistor is also provided. | 2021-12-02 |
20210376161 | INVERTER EMPOLYING THIN-FILM TRASISTOR FABRICATED BY ADJUSTING SILICON CONTENT AND METHOD FOR MANUFACTURING SAME - The present invention relates to an inverter employing a thin film transistor fabricated by adjusting a silicon content and a method for manufacturing the same, and the inverter employing a thin film transistor fabricated by adjusting a silicon content includes a depletion mode transistor including a first gate electrode formed on a substrate, a first insulating layer formed on the first gate electrode, and a first source electrode, a first drain electrode, and a first channel layer formed on the first insulating layer, an enhancement mode transistor including a second gate electrode formed on the substrate, a second insulating layer formed on the second gate electrode, and a second source electrode, a second drain electrode, and a second channel layer formed on the second insulating layer; and a wiring unit electrically connecting the electrodes, and the first channel layer and the second channel layer are formed of amorphous silicon oxide layers having different silicon contents. According to the present invention, an inverter may be configured by adjusting a silicon content of a channel layer with the same electrode layer, only using an oxide thin film transistor of an n channel layer in a CMOS including both a p channel layer and an n channel layer to cause a difference in a threshold voltage. | 2021-12-02 |
20210376162 | TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTOR - A transistor includes a first gate structure, a channel layer, and source/drain contacts. The first gate structure includes nanosheets. The channel layer is over the first gate structure. A portion of the channel layer wraps around the nanosheets of the first gate structure. The source/drain contacts are aside the nanosheets. The source/drain contacts are electrically connected to the channel layer. | 2021-12-02 |
20210376163 | CHANNEL CONFIGURATION FOR IMPROVING MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATION THEREOF - Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets. | 2021-12-02 |
20210376164 | SEMICONDUCTING METAL OXIDE TRANSISTORS HAVING A PATTERNED GATE AND METHODS FOR FORMING THE SAME - A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized. | 2021-12-02 |
20210376165 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion. | 2021-12-02 |
20210376166 | SEMICONDUCTOR DEVICE WITH PASSIVE MAGNETO-ELECTRIC TRANSDUCER - A semiconductor device includes a first diffusion region of a first type with embedded therein, a second and a third diffusion region of a second type different from the first type. The second and third diffusion regions are more doped than the first region. The second and third diffusion regions are each connected to a respective contact. A dielectric layer covers at least an edge of the second and third diffusion regions, and the region in between the second and third diffusion regions. A piezoelectric layer is disposed on, over, adjacent to or in contact with the dielectric layer. A first structure is in a first soft ferromagnetic material and is arranged to perform mechanical stress on the piezoelectric layer in response to a magnetic field. | 2021-12-02 |
20210376167 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor and a diode formed at a common semiconductor substrate. The diode region includes: a fifth semiconductor layer of a second conductivity type; a second semiconductor layer of the second conductivity type provided on the fifth semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to a first main surface of the semiconductor substrate; a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer; and a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from a second main surface. | 2021-12-02 |
20210376168 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a first semiconductor region connected to the first electrode and being of a first conductivity type, a second semiconductor region provided on the first semiconductor region, contacting the first semiconductor region and being of a second conductivity type, first metal layers and second metal layers provided on the second semiconductor region and contacting the second semiconductor region, a third semiconductor region provided between the first semiconductor region and the first metal layer, and a second electrode. The third semiconductor region contacts the first and second semiconductor regions and being of the first conductivity type. An impurity concentration of the third semiconductor region is greater than an impurity concentration of the first semiconductor region. The second electrode contacts the first semiconductor region, the second semiconductor region, the first metal layers, and the second metal layers. | 2021-12-02 |
20210376169 | MULTI-TRENCH SCHOTTKY DIODE - A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area. | 2021-12-02 |