48th week of 2021 patent applcation highlights part 72 |
Patent application number | Title | Published |
20210375770 | SEMICONDUCTOR PACKAGE STRUCTURE COMPRISING RIGID-FLEXIBLE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame. | 2021-12-02 |
20210375771 | ELECTRONIC DEVICE - An electronic device includes a bus bar that includes a first terminal and a second terminal and extends between the first terminal and the second terminal on a side of a first surface of a substrate; first solder configured to pass through the substrate in a thickness direction and connect a first through terminal connected to a first electronic component that is disposed on a second surface side of the substrate and the first terminal; and second solder configured to pass through the substrate in the thickness direction and connect a second through terminal connected to a second electronic component disposed on the second surface side of the substrate and the second terminal. | 2021-12-02 |
20210375772 | METHOD FOR FORMING PACKAGE STRUCTURE - A method for forming a package structure is provided. The method includes forming a first molding compound layer surrounding a first interposer. The method also includes forming a first redistribution structure over a first side of the first interposer and the first molding compound layer. The method also includes bonding a first semiconductor die and a second semiconductor die to the first redistribution structure through a plurality of first connectors. The method also includes bonding a surface-mount device (SMD) to the first redistribution structure through a second connector. The method also includes forming a second redistribution structure over a second side of the first interposer opposite the first side of the first interposer. A top surface of the surface-mount device (SMD) is lower than top surfaces of the first semiconductor die and the second semiconductor die. | 2021-12-02 |
20210375773 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate. | 2021-12-02 |
20210375774 | PACKAGE STRUCTURE - A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film. | 2021-12-02 |
20210375775 | Fan-Out Package Having a Main Die and a Dummy Die - A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. | 2021-12-02 |
20210375776 | Electro-Migration Reduction - The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%. | 2021-12-02 |
20210375777 | Graphene Layer for Reduced Contact Resistance - A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material. | 2021-12-02 |
20210375778 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film. | 2021-12-02 |
20210375779 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer. | 2021-12-02 |
20210375780 | PATTERNING A TRANSPARENT WAFER TO FORM AN ALIGNMENT MARK IN THE TRANSPARENT WAFER - In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark. | 2021-12-02 |
20210375781 | PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS - Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift. | 2021-12-02 |
20210375782 | METHOD OF PRODUCING LASER-MARKED SILICON WAFER AND LASER-MARKED SILICON WAFER - A method of producing a silicon wafer includes: a laser mark printing step of printing a laser mark having a plurality of dots on a silicon wafer; an etching step of performing etching on at least a laser-mark printed region in a surface of the silicon wafer; and a polishing step of performing polishing on both surfaces of the silicon wafer having been subjected to the etching step. In the laser mark printing step, each of the plurality of dots is formed by a first step of irradiating a predetermined position on a periphery of the silicon wafer with laser light of a first beam diameter thereby forming a first portion of the dot and a second step of irradiating the predetermined position with laser light of a second beam diameter that is smaller than the first beam diameter thereby forming a second portion of the dot. | 2021-12-02 |
20210375783 | ELECTRONIC PACKAGE - An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors. | 2021-12-02 |
20210375784 | MOTHER SUBSTRATE FOR DISPLAY SUBSTRATES, MANUFACTURE METHOD THEREOF, DISPLAY SUBSTRATE AND DISPLAY DEVICE - A mother substrate for display substrates, a manufacture method thereof, a display substrate and a display device are provided. The mother substrate for display substrates includes multiple display element formation regions and a dividing line surrounding each display element formation region. A recess-protrusion structure is provided between the dividing line and the display element formation region, the recess-protrusion structure includes multiple recesses and protrusions which are arranged alternately, and extension directions of the recess and the protrusion are identical to an extension direction of the dividing line. | 2021-12-02 |
20210375785 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure. | 2021-12-02 |
20210375786 | SEMICONDUCTOR MODULE - A semiconductor module includes semiconductor elements, a case that houses the semiconductor elements, an external terminal electrically connecting the semiconductor elements and an external conductor, and a nut into which a bolt that secures the external conductor and the external terminal is threaded. The nut includes a cylindrical main body having a threaded hole, and a flange projecting in a direction radially outward of a center axis of the threaded nut hole and being disposed on one face of the main body. The case includes a wall surrounding the nut, the wall having a first recess that houses the main body, a second recess above the first recess and housing the flange, and a notch cut in a portion of the wall surrounding the main body. The first recess extends deeper than the main body, and the fillet is formed on a floor surface of the first recess. | 2021-12-02 |
20210375787 | LEAD FRAME SURFACE FINISHING - The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame. | 2021-12-02 |
20210375788 | CORNER STRUCTURES FOR AN OPTICAL FIBER GROOVE - Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip. | 2021-12-02 |
20210375789 | Methods of Manufacturing An Integrated Circuit Having Stress Tuning Layer - Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component. | 2021-12-02 |
20210375790 | SEMICONDUCTOR DIE INCLUDING DIFFUSION BARRIER LAYERS EMBEDDING BONDING PADS AND METHODS OF FORMING THE SAME - Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures. | 2021-12-02 |
20210375791 | SEMICONDUCTOR DIE INCLUDING DIFFUSION BARRIER LAYERS EMBEDDING BONDING PADS AND METHODS OF FORMING THE SAME - Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures. | 2021-12-02 |
20210375792 | CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE - A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure. | 2021-12-02 |
20210375793 | INTEGRATED CIRCUIT DEVICE AND FABRICATION METHOD THEREOF - A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer. | 2021-12-02 |
20210375794 | PROCESS OF REALIZATION OF AN AREA OF INDIVIDUALIZATION OF AN INTEGRATED CIRCUIT - A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections. | 2021-12-02 |
20210375795 | MICRO-COMPONENT ANTI-STICTION STRUCTURES - A micro-component comprises a component substrate having a first side and an opposing second side. Fenders project from the first and second sides of the component substrate and include first-side fenders extending from the first side and a second-side fender extending from the second side of the component substrate. At least two of the first-side fenders have a non-conductive surface and are disposed closer to a corner of the component substrate than to a center of the component substrate. | 2021-12-02 |
20210375796 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING - A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring. | 2021-12-02 |
20210375797 | MICROELECTRONIC PACKAGE FABRICATION UTILIZING INTERCONNECTED SUBSTRATE ARRAYS CONTAINING ELECTROSTATIC DISCHARGE PROTECTION GRIDS - Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps. Afterwards, the interconnected package array is singulated to yield a plurality of singulated microelectronic packages. | 2021-12-02 |
20210375798 | Package Interface with Improved Impedance Continuity - An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance. | 2021-12-02 |
20210375799 | LOW-LOSS MILLIMETER WAVE TRANSMISSION LINES ON SILICON SUBSTRATE - A semiconductor die and a transmission line structure has a first doped semiconductor substrate and a radio frequency transmission line disposed above the first doped semiconductor substrate. A second doped semiconductor segment is defined in the first doped semiconductor substrate and is arranged in a transverse relationship to a transmission line axis, with a depletion region being defined in areas of the first doped semiconductor substrate adjacent thereto that reduces power loss in signals through the transmission line. | 2021-12-02 |
20210375800 | METHOD FOR FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack. | 2021-12-02 |
20210375801 | ELECTRICAL COMPONENT WITH COMPONENT INTERCONNECTION ELEMENT - An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad. | 2021-12-02 |
20210375802 | POST PASSIVATION INTERCONNECT - An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer. | 2021-12-02 |
20210375803 | SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME - The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate. The first and the second passivation layers surround the second conductive structure, and a first air gap is enclosed by the first and the second passivation layers. | 2021-12-02 |
20210375804 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention relates to display device and method of manufacturing the same. The display device includes: a substrate; a driving pad disposed on the substrate; an insulating layer exposing the driving pad and disposed on the substrate; a circuit board including a circuit pad overlapping the driving pad; and a connector disposed between the circuit board and the insulating layer and including a plurality of conductive particles electrically connecting the driving pad and the circuit pad, the driving pad including: a first pad disposed on the substrate; and a second pad disposed on the first pad and having an opening exposing the first pad. | 2021-12-02 |
20210375805 | SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip. | 2021-12-02 |
20210375806 | VERTICAL MEMORY DEVICES - Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of layers. The stack of layers includes a common source layer, gate layers and insulating layers disposed on a substrate. The gate layers and insulating layers are stacked alternatingly. Then, the semiconductor device includes an array of channel structures formed in an array region. The channel structure extends through the stack of layers and forms a stack of transistors in a series configuration. The channel structure includes a channel layer that is in contact with the common source layer. The common source layer extends over the array region and a staircase region. The semiconductor device includes a contact structure disposed in the staircase region. The contact structure forms a conductive connection with the common source layer. | 2021-12-02 |
20210375807 | PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES - Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. | 2021-12-02 |
20210375808 | PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS - In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer. | 2021-12-02 |
20210375809 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer. A first portion of the UBM pattern physically contacts a via portion of the patterned conductive layer which is tapered toward the UBM pattern, and a second portion of the UBM pattern is connected to the first portion and protruded from the patterned dielectric layer. | 2021-12-02 |
20210375810 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer. | 2021-12-02 |
20210375811 | PIN-GRID-ARRAY-TYPE SEMICONDUCTOR PACKAGE - A semiconductor package of a pin-grid-array type includes a bump pad on a first substrate, a metal socket on a second substrate, a core material for reverse reflow on the bump pad, and solder paste or a solder bump forming a solder layer on the core material for reverse reflow. The solder paste or the solder bump is in contact with the bump pad. The core material for reverse reflow and the solder paste or the solder bump bonded to the core material for reverse reflow are used as a pin and detachably attached to the metal socket. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer. | 2021-12-02 |
20210375812 | MICROELECTRONIC DEVICE WITH PILLARS HAVING FLARED ENDS - A microelectronic device has a die with a die conductor at a connection surface. The microelectronic device includes a pillar electrically coupled to the die conductor, and a head electrically coupled to the pillar. The pillar has a die-side flared end at a die end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by more than a lesser of half a thickness of the die conductor and half a lateral width of the pillar midway between a die end and a head end. The pillar has a head-side flared end at a head end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by a distance that is greater than a lesser of half a thickness of the head and half the lateral width of the pillar. Methods of forming the microelectronic device are disclosed. | 2021-12-02 |
20210375813 | MECHANICAL PUNCHED VIA FORMATION IN ELECTRONICS PACKAGE AND ELECTRONICS PACKAGE FORMED THEREBY - An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall. | 2021-12-02 |
20210375814 | INTEGRATED CIRCUIT MODULE STRUCTURE AND METHOD FOR MANUFACTURING SAME - Disclosed are an integrated circuit module structure and a method for manufacturing the same. The integrated circuit module structure includes an integrated device, a molding layer, at least one redistribution layer and at least one insulating layer. At least one interface that is connected to a first functional circuit is disposed in a first face of the integrated device. The molding layer exposes the at least one interface of the integrated device. Each redistribution layer includes at least one metal pattern, and at least one metal pattern is correspondingly connected to the at least one interface. The at least one metal pattern forms a second functional circuit, or the at least one metal pattern is directly connected to a second functional circuit. The at least one insulating layer is located on a side, close to the first face, of the integrated device and the molding layer, each insulating layer covers one redistribution layer, and the insulating layer exposing a part of the at least one metal pattern. | 2021-12-02 |
20210375815 | Redistribution Lines Having Nano Columns and Method Forming Same - A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched. | 2021-12-02 |
20210375816 | IC DEVICE WITH CHIP TO PACKAGE INTERCONNECTS FROM A COPPER METAL INTERCONNECT LEVEL - An integrated circuit device ( | 2021-12-02 |
20210375817 | SOLID-STATE IMAGE PICKUP ELEMENT, ELECTRONIC EQUIPMENT, AND SEMICONDUCTOR APPARATUS - The present technology relates to a solid-state image pickup element, electronic equipment, and a semiconductor apparatus that make it possible to reduce a surface reflection in an area in which a slit is formed and improve flare characteristics. A solid-state image pickup element includes a pixel area in which a plurality of pixels is two-dimensionally arranged in a matrix, a chip mounting area in which a chip is flip-chip mounted, and a dam area that is arranged around the chip mounting area and in which one or more slits that block an outflow of a resin are formed. In the dam area, the same OCL as that in the pixel area is formed. The present technology can be applied to a solid-state image pickup element etc. in which a chip is flip-chip mounted, for example. | 2021-12-02 |
20210375818 | ELECTRONIC-COMPONENT-EMBEDDED SUBSTRATE AND METHOD OF MAKING THE SAME - An electronic-component-embedded substrate includes a base having flexibility and cavities formed therethrough, electronic components disposed in the cavities, respectively, and interconnects disposed on the base and connected to the electronic components, wherein the interconnects include a metal foil having openings that abut the electronic components, and include a plating layer disposed on the metal foil and connected to the electronic components through the openings. | 2021-12-02 |
20210375819 | MULTI-LEVEL STACKING OF WAFERS AND CHIPS - In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias. | 2021-12-02 |
20210375820 | MAGNETIC INDUCED HEATING FOR SOLDER INTERCONNECTS - Magnetic structures may be incorporated into integrated circuit assemblies, which will enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates. Such magnetic structures will eliminate exposure of the entire integrated circuit assembly to elevated temperatures for an extended period of time, which eliminates associated warpage and thermal degradation consequences from such exposure. Additionally, such magnetic structures will allow for re-workability of specific solder interconnects. | 2021-12-02 |
20210375821 | CHIP PACKAGE STRUCTURE WITH RING-LIKE STRUCTURE - A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump. | 2021-12-02 |
20210375822 | SOLDERLESS INTERCONNECT FOR SEMICONDUCTOR DEVICE ASSEMBLY - Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies. | 2021-12-02 |
20210375823 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion. | 2021-12-02 |
20210375824 | ELECTRONIC DEVICE HAVING A SOLDERED JOINT BETWEEN A METAL REGION OF A SEMICONDUCTOR DIE AND A METAL REGION OF A SUBSTRATE - An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate. | 2021-12-02 |
20210375825 | FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE - Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package. | 2021-12-02 |
20210375826 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure. | 2021-12-02 |
20210375827 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a first die, a die stack structure, a support structure and an insulation structure. The die stack structure is bonded to the first die. The support structure is disposed on the die stack structure. A width of the support structure is larger than a width of the die stack structure and less than a width of the first die. The insulation structure at least laterally wraps around the die stack structure and the support structure. | 2021-12-02 |
20210375828 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug. | 2021-12-02 |
20210375829 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of arrays of memory cells, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm | 2021-12-02 |
20210375830 | COMPOSITE IC CHIPS INCLUDING A CHIPLET EMBEDDED WITHIN METALLIZATION LAYERS OF A HOST IC CHIP - Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip. | 2021-12-02 |
20210375831 | SEMICONDUCTOR PACKAGE - A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections. | 2021-12-02 |
20210375832 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip. | 2021-12-02 |
20210375833 | MICRO-LED DISPLAY AND MANUFACTURING METHOD THEREFOR - The disclosure describes a micro Light Emitting Diode (LED) display. The display may include a Printed Circuit Board (PCB) including a plurality of solder pads, a micro LED package including a plurality of micro LED chips, and a plurality of solder electrodes which bond the micro LED chips onto the solder pads of the PCB. The micro LED package may be re-arranged in an Red Green Blue (RGB) state on a temporary fixing film by using a pickup device in accordance with a display pixel configuration, after the micro LED chips are attached to a carrier film. | 2021-12-02 |
20210375834 | ELECTRONIC DEVICE - A method for manufacturing an electronic device including the following steps: a) forming a wafer of electronic chips; b) fixing the wafer of electronic chips to a first support made of a stretchable material; c) removing and/or etching the wafer; and d) stretching the first support so as to move the chips away from one another. | 2021-12-02 |
20210375835 | NON-PLANAR DISPLAY APPARATUS AND ELECTRONIC DEVICE - This disclosure provides a non-planar display apparatus including a substrate and a plurality of light-emitting elements, the substrate is non-planar and includes a plurality of pixel islands; a spacing is formed between each pair of the plurality of pixel islands, the plurality of pixel islands are mechanically connected, and each pixel island is surrounded by a plurality of spacings; the plurality of pixel islands support subsets of light-emitting elements among the plurality of light-emitting elements, respectively; herein, the plurality of pixel islands form a non-planar surface. | 2021-12-02 |
20210375836 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device includes: a substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; a light emitting diode between the first electrode and the second electrode and connected to the first and second electrodes; a first contact on the first electrode; and a second contact on the second electrode. The first contact contacts the first electrode and a first portion of the light emitting diode, and the second contact contacts the second electrode and a second portion of the light emitting diode. | 2021-12-02 |
20210375837 | SEMICONDUCTOR DEVICE WITH ACTIVE INTERPOSER AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. | 2021-12-02 |
20210375838 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module including a module substrate having a first main surface and a second main surface on opposite sides; a low-noise amplifier disposed on the second main surface; and a power amplifier circuit in a Doherty configuration. The power amplifier including a first phase circuit; a second phase circuit; a carrier amplifier disposed on the first main surface and including an input terminal connected to a first end of the first phase circuit and an output terminal connected to a first end of the second phase circuit; and a peaking amplifier disposed on the first main surface and including an input terminal connected to a second end of the first phase circuit and an output terminal connected to a second end of the second phase circuit. | 2021-12-02 |
20210375839 | SEMICONDUCTOR DIE WITH IMPROVED THERMAL INSULATION BETWEEN A POWER PORTION AND A PERIPHERAL PORTION, METHOD OF MANUFACTURING, AND PACKAGE HOUSING THE DIE - A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction. | 2021-12-02 |
20210375840 | IPD Modules with Flexible Connection Scheme in Packaging - A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package. | 2021-12-02 |
20210375841 | SEMICONDUCTOR COMPOSITE DEVICE AND PACKAGE BOARD USED THEREIN - A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole. | 2021-12-02 |
20210375842 | Packages and Methods of Forming Packages - Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM). | 2021-12-02 |
20210375843 | OPTOELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An optoelectronic device and a manufacturing method thereof are provided. The optoelectronic device includes a substrate, light emitting chips disposed on the substrate and electrically connected to the substrate, a first annular structure disposed on the substrate and around the light emitting chips, a first wavelength conversion layer disposed in the first annular structure and covering the light emitting chips, a second annular structure disposed on the substrate and around the light emitting chips and further being in contact with the first annular structure, and a second wavelength conversion layer disposed in the second annular structure and covering the first wavelength conversion layer and the light emitting chips. Wavelength conversion substances contained in the first wavelength conversion layer and the second wavelength conversion layer respectively are different in material. Therefore, the optoelectronic device can achieve improved uniformity of luminescence as well as light output quality. | 2021-12-02 |
20210375844 | METHOD AND DEVICE FOR MANUFACTURING FLEXIBLE LIGHT EMISSION DEVICE - According to a flexible light-emitting device production method of the present disclosure, after an intermediate region ( | 2021-12-02 |
20210375845 | PACKAGE CAVITY FOR ENHANCED DEVICE PERFORMANCE WITH AN INTEGRATED PASSIVE DEVICE - An integrated circuit (IC) package is described. The IC package includes a package die and die interconnects on an active surface of the package die. The IC package also includes an integrated passive device (IPD) coupled to the active surface of the package die, between the plurality of die interconnects. A portion of the IPD extends beyond a Z-height of the die interconnects. The IC package further includes a package substrate coupled to the die interconnects, the package substrate having a cavity to receive the portion of the IPD. | 2021-12-02 |
20210375846 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure for optically coupling a fiber includes a photonic die, an electronic die disposed on and electrically coupled to the photonic die, and an insulating layer disposed on the photonic die and extending along sidewalls of the electronic die. The photonic die includes a first portion and a second portion connected to the first portion, an optical device of the photonic die optically coupled to the fiber is within the first portion, and the second portion extends beyond lateral extents of the first portion. | 2021-12-02 |
20210375847 | STACKED DIE ASSEMBLY INCLUDING DOUBLE-SIDED INTER-DIE BONDING CONNECTIONS AND METHODS OF FORMING THE SAME - Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads. | 2021-12-02 |
20210375848 | STACKED DIE ASSEMBLY INCLUDING DOUBLE-SIDED INTER-DIE BONDING CONNECTIONS AND METHODS OF FORMING THE SAME - Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads. | 2021-12-02 |
20210375849 | MICROELECTRONIC PACKAGE WITH THREE-DIMENSIONAL (3D) MONOLITHIC MEMORY DIE - Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed. | 2021-12-02 |
20210375850 | TECHNIQUES FOR PROCESSING DEVICES - Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces. | 2021-12-02 |
20210375851 | STRUCTURE AND METHOD OF POWER SUPPLY ROUTING IN SEMICONDUCTOR DEVICE - A layout method and a layout system are disclosed. The layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region, a second source/drain region and a gate electrode, wherein the gate electrode define an odd-numbered track and an even-numbered track. The first cell also includes a first power rail, a first conductive via within the odd-numbered track, a second power rail and a second conductive via within the even-numbered track. The first source/drain region is electrically connected to the first power rail through the first conducive via, and the second source/drain region is electrically connected to the second power rail through the second conducive via. | 2021-12-02 |
20210375852 | MEMORY DEVICE - A memory device includes a first plurality of program lines of a first group, a second plurality of program lines of a second group, and a plurality of address lines. The second plurality of program lines are disposed next to and are parallel to the first plurality of program lines. The plurality of address lines are coupled to the first plurality of program lines and the second plurality of program lines respectively. The plurality of address lines are twisted and are intersected with the first plurality of program lines and the second plurality of program lines in a layout view. At least two adjacent program lines of the first plurality of program lines or the second plurality of program lines have lengths different from each other. A method is also disclosed herein. | 2021-12-02 |
20210375853 | INTEGRATED CIRCUIT DEVICE, SYSTEM AND METHOD - An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region. | 2021-12-02 |
20210375854 | STATIC RANDOM ACCESS MEMORY DEVICE - A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts. | 2021-12-02 |
20210375855 | SEMICONDUCTOR DEVICE - A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically. | 2021-12-02 |
20210375856 | METHODS FOR PILLAR CONNECTION ON FRONTSIDE AND PASSIVE DEVICE INTEGRATION ON BACKSIDE OF DIE - An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals. | 2021-12-02 |
20210375857 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate structure, a source/drain epitaxial structure, a front-side interconnection structure, a backside via, an isolation material, and a sidewall spacer. The source/drain epitaxial structure is on a side of the gate structure. The front-side interconnection structure is on a front-side of the source/drain epitaxial structure. The backside via is connected to a backside of the source/drain epitaxial structure. The isolation material is on a side of the backside via and in contact with the gate structure. The sidewall spacer is sandwiched between the backside via and the isolation material. A height of the isolation material is greater than a height of the sidewall spacer. | 2021-12-02 |
20210375858 | Gate Isolation for Multigate Device - Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation. | 2021-12-02 |
20210375859 | Nanosheet Thickness - According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks. | 2021-12-02 |
20210375860 | FINFET PITCH SCALING - According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack. | 2021-12-02 |
20210375861 | Backside Interconnect Structures for Semiconductor Devices and Methods of Forming the Same - Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure. | 2021-12-02 |
20210375862 | BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins. | 2021-12-02 |
20210375863 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction. | 2021-12-02 |
20210375864 | REDUCTION OF GATE-DRAIN CAPACITANCE - A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction. | 2021-12-02 |
20210375865 | SEMICONDUCTOR DEVICE WITH FIN TRANSISTORS AND MANUFACTURING METHOD OF SUCH SEMICONDUCTOR DEVICE - A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. | 2021-12-02 |
20210375866 | Integrated Circuit Device and Method of Forming the Same - An integrated circuit device includes a first device and a second device. The first device is disposed within a first circuit region, the first device including a plurality of first semiconductor strips extending longitudinally in a first direction. Adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, which is generally perpendicular to the first direction. The second device is disposed within a second circuit region, the second circuit region being adjacent to the first circuit region in the first direction. The second device includes a second semiconductor strip extending longitudinally in the first direction. A projection of a longitudinal axis of the second semiconductor strip along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips. | 2021-12-02 |
20210375867 | NON-VOLATILE MEMORY WITH DUAL GATED CONTROL - A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor. | 2021-12-02 |
20210375868 | Integrated Assemblies Comprising Hydrogen Diffused Within Two or More Different Semiconductor Materials, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies. | 2021-12-02 |
20210375869 | MEMORY AND FORMATION METHOD THEREOF - A memory and a formation method thereof are provided. The formation method includes: providing a substrate; forming a first mask layer on a surface of the substrate, in the first mask layer there being formed a plurality of strip-shaped patterns arranged in parallel; forming a second mask layer on the first mask layer, in the second mask layer there being formed a plurality of first patterns and a plurality of second patterns, the plurality of first patterns being arranged in an array and being overlapped with the strip-shaped patterns, the plurality of second patterns covering ends of a part of the strip-shaped patterns; and etching layer by layer into the substrate by using the first mask layer and the second mask layer as masks to transfer the strip-shaped patterns, the first patterns and the second patterns into the substrate. | 2021-12-02 |