48th week of 2010 patent applcation highlights part 48 |
Patent application number | Title | Published |
20100304499 | METHOD OF EXTRACTING FOOD COMPONENT, FOOD INSPECTION METHOD AND FOOD INSPECTION KIT - Provided is a technique of extracting a component in a food from the food by using a reducing agent that is inexpensive and has a mild reducing action. A component in a food is extracted by mixing the food with an extractant containing a sulfite. In addition, the resultant food extract is brought into contact with a specific antibody that specifically recognizes a substance included in a specified ingredient of interest for inspection, to thereby inspect the presence or absence and/or the amount of a specified ingredient in a food by utilizing an immunological measurement method. Further provided is a food inspection kit for inspection of the presence or absence and/or the amount of a specified ingredient in a food, including: (1) an extractant and a sulfite to be added to the extractant, or an extractant including a sulfite added; and (2) an antibody that specifically recognizes a substance included in a specified ingredient of interest for inspection. | 2010-12-02 |
20100304500 | NANO-BIOSENSOR FOR BIOMOLECULAR RECOGNITION AND A METHOD OF SYNTHESIZING THE SAME - The various embodiments herein provide a nano-biosensor for detecting avidin bio-conjugated antibodies and a method of manufacturing the same. The nano-biosensor comprises a core made up of Zns: Mn nanoparticles. The core is surrounded by mercaptoelthanol molecules. Biotin is attached to the mercaptoethanol molecules surrounding the core. The ZnS:Mn nano particles with a size of 5-10 nm are prepared by quaternary W/O micro-emulsion method. According to one embodiment, a nano-biosensor comprises a nano particle of ZnS:Mn wherein the nano particle of ZnS:Mn includes ZnSO | 2010-12-02 |
20100304501 | BIO LAB-ON-A-CHIP AND METHOD OF FABRICATING AND OPERATING THE SAME - Disclosed is a bio lab-on-a-chip. The bio lab-on-a-chip is provided on a piezoelectric thin film on a substrate, and includes a sensing unit to sense a bio signal and a fluidic control unit which controls a transfer of a microfluid adjacent to the sensing unit. Provided is also a method of fabricating the bio lab-on-a-chip. The method includes the steps of forming a piezoelectric thin film, forming a sensing unit to sense a bio signal of a microfluid on the piezoelectric thin film, and forming a fluidic control unit located adjacent to the sensing unit. | 2010-12-02 |
20100304502 | DETECTION METHOD AND DETECTION KIT - A detection method for detecting a substance such as a virus which achieves enhanced detection sensitivity even in trace amounts of a substance to be detected and is also simple and superior in visual determinability is disclosed, comprising contacting a complex of a substance to be detected and a semiconductor nanoparticle-labeled probe capable of bonding the substance with an immobilized capture reagent capable of bonding the substance to detect the substance. A detection kit is also disclosed. | 2010-12-02 |
20100304503 | PROCESS FOR PRODUCING POLYMER PARTICLES - A process for producing polymer particles having an antigen or an antibody introduced into the surface thereof, by carrying out miniemulsion polymerization using a monomer, a radical polymerization initiator, an emulsifier, and a hydrophobe in the presence of the antigen or antibody to thereby produce the polymer particles, is disclosed. According to the process, it is possible to provide a reagent for immunological analysis having an excellent detection sensitivity and capable of avoiding a nonspecific reaction which occurs in conventional methods. | 2010-12-02 |
20100304504 | PROCESS AND APPARATUS FOR FABRICATING MAGNETIC DEVICE - Process and apparatus for fabricating a magnetic device is provided. Magnetic and/or nonmagnetic layers i n the device are etched by a mixed gas of a hydrogen gas and an inert gas such as N | 2010-12-02 |
20100304505 | PROCESSING METHOD AND STORAGE MEDIUM - There is provided a processing method for performing a recovery process on a damaged layer formed on a surface of a low-k film of a target substrate by introducing a processing gas containing a methyl group into a processing chamber. The method includes: increasing an internal pressure of the processing chamber up to a first pressure lower than a processing pressure for the recovery process by introducing a dilution gas into the processing chamber maintained in a depressurized state; then stopping the introduction of the dilution gas, and increasing the internal pressure of the processing chamber up to a second pressure as the processing pressure for the recovery process by introducing the processing gas into a region where the target substrate exists within the processing chamber; and performing the recovery process on the target substrate while the processing pressure is maintained. | 2010-12-02 |
20100304506 | LASER IRRADIATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - The present invention is to provide a laser irradiation method for performing homogeneous laser irradiation to the irradiation object even when the thickness of the irradiation object is not even. In the case of irradiating the irradiation object having uneven thickness, the laser irradiation is performed while keeping the distance between the irradiation object and the lens for condensing the laser beam on the surface of the irradiation object constant by using an autofocusing mechanism. In particular, when the irradiation object is irradiated with the laser beam by moving the irradiation object relative to the laser beam in the first direction and the second direction of the beam spot formed on the irradiation surface, the distance between the irradiation object and the lens is controlled by the autofocusing mechanism before the irradiation object is moved in the first and second directions. | 2010-12-02 |
20100304507 | METHOD OF PRODUCING A STRUCTURE BY LAYER TRANSFER - The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm. | 2010-12-02 |
20100304508 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 2010-12-02 |
20100304509 | CONTACTLESS TECHNIQUE FOR EVALUATING A FABRICATION OF A WAFER - The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed. | 2010-12-02 |
20100304510 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle. | 2010-12-02 |
20100304511 | METHOD OF SENSING A HIGH VOLTAGE - In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor. | 2010-12-02 |
20100304512 | System for Diagnosis and Treatment of Photovoltaic and Other Semiconductor Devices - A diagnostic and self-healing treatment system for a semiconductor device, the system provides: i) a shunt busting/blocking treatment, ii) self-healing treatment, and iii) an in-situ non-contact diagnostic determination. | 2010-12-02 |
20100304513 | METHOD FOR FORMING AN ORGANIC LIGHT EMITTING DIODE DEVICE - A method for sealing an organic light emitting diode (OLED) device is disclosed wherein the OLED device comprises a color filter. A color filter is deposited on a first glass plate or substrate and a glass-based frit is then deposited in a loop around the color filter, The deposited fit loop is then heated by electromagnetic energy to evaporate organic constituents and to sinter the fit in a pre-sintering step. An OLED device may then be assembled by positioning a second glass plate comprising an organic light emitting material deposited thereon in overlying registration with the first glass plate, with the color filer and the organic light emitting material positioned between the plates. The fit is then heated with a laser to form a hermetic seal between the first and second glass plates. | 2010-12-02 |
20100304514 | EFFICIENT LIGHT COUPLER FROM OFF-CHIP TO ON-CHIP WAVEGUIDES - In an embodiment, light from a single mode light source may be deflected into a low index contrast (LIC) waveguide in an opto-electronic integrated circuit (OEIC) (or “opto-electronic chip”) by a 45 degree mirror. The mirror may be formed by polishing an edge of the die at a 45 degree angle and coating the polished edge with a metal layer. Light coupled into the LIC waveguide may then be transferred from the LIC waveguide to a high index contrast (HIC) waveguide by evanescent coupling. | 2010-12-02 |
20100304515 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region. | 2010-12-02 |
20100304516 | LIGHT-EMITTING CRYSTAL STRUCTURES - A method of manufacturing an apparatus, comprising forming a light-emitting crystalline structure. Forming the light-emitting crystalline structure includes forming a first barrier region on a substrate, the first barrier region having one or more inclined surfaces relative to a planar surface of the substrate. Forming the light-emitting crystalline structure also includes forming a second barrier region over the first barrier region, to form a junction at the inclined surfaces, wherein the first barrier region comprises one of an n-type or p-type semiconductor crystal, and the second barrier region comprises the other of the n-type or p-type semiconductor crystal. | 2010-12-02 |
20100304517 | MEMS DEVICE AND FABRICATION METHOD OF THE SAME - A microelectromechanical systems (MEMS) device includes a frame, an actuator formed on the same layer as the frame and connected to the frame to be capable of performing a relative motion with respect to the frame, and at least one stopper restricting a displacement of the actuator in a direction along the height of the actuator. The MEMS device is fabricated by bonding a second substrate to a first substrate, forming the frame and the actuator by partially removing the first substrate, and forming the at least one stopper by partially removing the second substrate. | 2010-12-02 |
20100304518 | Media-Compatible Electrically Isolated Pressure Sensor For High Temperature Applications - A method for manufacturing a Micro-Electro-Mechanical System pressure sensor. The method includes forming a gauge wafer including a diaphragm and a pedestal region. The method includes forming an electrical insulation layer disposed on a second surface of the diaphragm region and forming a plurality of sensing elements patterned on the electrical insulation layer disposed on the second surface in the diaphragm region. The method includes forming a cap wafer with a central recess in an inner surface and a plurality of through-wafer embedded vias made of an electrically conductive material in the cap wafer. The method includes creating a sealed cavity by coupling the inner recessed surface of the cap wafer to the gauge wafer, such that electrical connections from the sensing elements come out to an outer surface of the cap wafer through the vias. The method includes attaching a spacer wafer with a central aperture to the pedestal region with the central aperture aligned to the diaphragm region. | 2010-12-02 |
20100304519 | METHOD OF FABRICATING SOLAR CELL CHIPS - A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips. | 2010-12-02 |
20100304520 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein is a method for making a semiconductor device including the steps of: forming a light-receiving portion for carrying out photoelectric conversion in a semiconductor substrate; forming an insulating film to cover a light-receiving side of the semiconductor substrate; forming a metallic light-shielding film to partly cover the insulating film in correspondence to the light-receiving portion; and heating the metallic light-shielding film by irradiation of the metallic light-shielding film with a microwave to permit selective annealing of a laminated portion with the metallic light-shielding film in the insulating film. | 2010-12-02 |
20100304521 | Shadow Mask Methods For Manufacturing Three-Dimensional Thin-Film Solar Cells - Methods for manufacturing three-dimensional thin-film solar cells using a template. The template comprises a template substrate comprising a plurality of three-dimensional surface features. The three-dimensional thin-film solar cell substrate is formed by forming a sacrificial layer on the template, subsequently depositing a semiconductor layer, selectively etching the sacrificial layer, and releasing the semiconductor layer from the template. Select portions of the three-dimensional thin-film solar cell substrate are then doped with a first dopant, while other select portions are doped with a second dopant. Next, selective emitter and base metallization regions are formed using a PECVD shadow mask process. | 2010-12-02 |
20100304522 | ION IMPLANTATION FABRICATION PROCESS FOR THIN-FILM CRYSTALLINE SILICON SOLAR CELLS - A front contact thin-film solar cell is formed on a thin-film crystalline silicon substrate. Emitter regions, selective emitter regions, and a back surface field are formed through ion implantation processes. In yet another embodiment, a back contact thin-film solar cell is formed on a thin-film crystalline silicon substrate. Emitter regions, selective emitter regions, base regions, and a front surface field are formed through ion implantation processes. | 2010-12-02 |
20100304523 | Method of enhancing the conductive and optical properties of deposited indium tin oxide (ITO) thin films - Certain example embodiments of this invention relate to a method of activating an indium tin oxide (ITO) thin film deposited, directly or indirectly, on a substrate. The ITO thin film is baked in a low oxygen environment at a temperature of at least 450 degrees C. for at least 10 minutes so as to provide for (1) a post-baked resistivity of the ITO thin film that is below a resistivity of a corresponding air-baked ITO thin film, (2) a post-baked visible spectrum absorption and transmission of the ITO thin film that respectively are below and above the absorption and transmission of the corresponding air-baked ITO thin film, and (3) a post-baked infrared reflectivity of the ITO thin film that is above the reflectivity of the corresponding air-baked ITO thin film. The substrate with the activated ITO thin film may be used in a photovoltaic device, for example. | 2010-12-02 |
20100304524 | MANUFACTURING METHODS OF THIN FILM SOLAR CELL AND THIN FILM SOLAR CELL MODULE - A manufacturing method of a thin film solar cell comprises performing dry cleaning of an insulation substrate on which a transparent electrode is formed, patterning the transparent electrodes to be spaced apart from each other, performing dry cleaning of the patterned transparent electrodes, forming a semiconductor layer on surfaces of the transparent electrodes and patterning a metal electrode on the semiconductor layer. | 2010-12-02 |
20100304525 | FABRICATING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE - A fabricating method of a TFT array substrate includes following steps: providing a substrate having a pixel region and a bonding pad region surrounding the pixel region; forming a patterned polysilicon layer within the pixel region on the substrate; forming a first patterned insulating layer to cover the patterned polysilicon layer; forming a first patterned transparent conductive layer on the first patterned insulating layer; forming a first metal layer on the first patterned transparent conductive layer; forming a second patterned insulating layer to cover the first metal layer; forming a second patterned transparent conductive layer on the second patterned insulating layer; forming a second metal layer on the second patterned transparent conductive layer; forming a third patterned insulating layer to cover the second metal layer; and forming a third patterned transparent conductive layer on the third patterned insulating layer. | 2010-12-02 |
20100304526 | Method of making a photovoltaic module - Photovoltaic module comprising a transparent substrate ( | 2010-12-02 |
20100304527 | METHODS OF THERMAL PROCESSING A SOLAR CELL - Embodiments of the invention contemplate the formation of high efficiency solar cells and novel methods for forming the same. Embodiment of the invention can be used to form a solar cell that has doped regions that act as a back surface field. The methods and apparatus disclosed herein may include the use of a doping source, a rapid annealer and a slow annealer. One embodiment of the methods used to form an improved emitter structure include disposing an amount of a dopant atom in a substrate and performing two or more thermal processing steps to cause the dopant to diffuse deeper into the substrate to achieve a desirable multi-facet doping profile. | 2010-12-02 |
20100304528 | METHOD OF FABRICATING OXIDE THIN FILM TRANSISTOR - According to a method of fabricating an oxide thin-film transistor, when a thin-film transistor is fabricated by using an amorphous zinc oxide (ZnO)-based semiconductor as an active layer, it may be possible to reduce a tact time as well as attain an enhanced element characteristic by depositing an insulation layer having an oxide characteristic in-situ through controlling oxygen (O | 2010-12-02 |
20100304529 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a highly reliable semiconductor device including a thin film transistor having stable electric characteristics. In addition, another object is to manufacture a highly reliable semiconductor device at low cost with high productivity. In a method for manufacturing a semiconductor device including a thin film transistor including an oxide semiconductor layer as a channel formation region, the oxide semiconductor layer is heated under a nitrogen atmosphere to lower its resistance, thereby forming a low-resistance oxide semiconductor layer. Further, resistance of a region of the low-resistance oxide semiconductor layer, which is overlapped with a gate electrode layer, is selectively increased, thereby forming a high-resistance oxide semiconductor layer. Resistance of the oxide semiconductor layer is increased by forming a silicon oxide film in contact with the oxide semiconductor layer by a sputtering method. | 2010-12-02 |
20100304530 | METHOD OF FORMING A SEMICONDUCTOR DEVICE PACKAGE - Provided is a method of forming a semiconductor package. In the method, a first package including a first chip on a first substrate is formed, a second package including a second chip on a second substrate is formed, a moulding cap provided with a via hole and a recess structure configured to receive the first chip is formed, and the second package is provided on the first package with the moulding cap being therebetween such that the recess receives the first chip. The via hole and the recess structure are simultaneously foamed. | 2010-12-02 |
20100304531 | Method of manufacturing layered chip package - A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces. | 2010-12-02 |
20100304532 | Semiconductor Die Attachment Method Using Non-Conductive Screen Print and Dispense Adhesive - A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof. | 2010-12-02 |
20100304533 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive. | 2010-12-02 |
20100304534 | METHOD FOR CONNECTING A DIE ATTACH PAD TO A LEAD FRAME AND PRODUCT THEREOF - Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production costs. | 2010-12-02 |
20100304535 | PACKAGE STRUCTURE OF COMPOUND SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface of the first conductive film, and is electrically connected to the first conductive film and the second conductive film through the metal wire. The transparent encapsulation material overlays the first conductive film, second conductive film, and die. The surfaces of the first conductive film and second conductive film which is opposite the transparent encapsulation material act as electrodes. The insulating dielectric material is between the first conductive film and second conductive film. | 2010-12-02 |
20100304536 | DAM COMPOSITION FOR USE WITH MULTILAYER SEMICONDUCTOR PACKAGE UNDERFILL MATERIAL, AND FABRICATION OF MULTILAYER SEMICONDUCTOR PACKAGE USING THE SAME - A composition comprising (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler having an average particle size of 0.1-10 μm and a maximum particle size of up to 75 μm, and (D) a surface-silylated silica having an average particle size of 0.005 μm to less than 0.1 μm is suited as a dam composition for use with a underfill material in the fabrication of multilayer semiconductor packages. | 2010-12-02 |
20100304537 | Semiconductor Devices Including a Topmost Metal Layer with at Least one Opening and Their Methods of Fabrication - In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device. | 2010-12-02 |
20100304538 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To reduce variation among TFTs in manufacture of a semiconductor device including n-type thin film transistors and p-type thin film transistors. Further, another object of the present invention is to reduce the number of masks and manufacturing steps, and manufacturing time. A method of manufacturing a semiconductor device includes forming an island-shaped semiconductor layer of a first thin film transistor, then, forming an island-shaped semiconductor layer of the second thin film transistor. In the formation of the island-shaped semiconductor layer of the second thin film transistor, a gate insulating film in contact with the island-shaped semiconductor layer of the second thin film transistor is used as a protection film (an etching stopper film) for the island-shaped semiconductor layer of the first thin film transistor. | 2010-12-02 |
20100304539 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween. | 2010-12-02 |
20100304540 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device. | 2010-12-02 |
20100304541 | SYSTEMS AND METHODS FOR MEMORY STRUCTURE COMPRISING A PPROM AND AN EMBEDDED FLASH MEMORY - A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structures. | 2010-12-02 |
20100304542 | ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING - A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material. | 2010-12-02 |
20100304543 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern. | 2010-12-02 |
20100304544 | FRONT-END PROCESSING OF NICKEL PLATED BOND PADS - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 2010-12-02 |
20100304545 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film having a hydrogen diffusion coefficient smaller than that of the second insulation film is provided on the second insulation film. The hydrogen diffusion preventing film covers a part of the high resistance element. | 2010-12-02 |
20100304546 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR THIN FILM, WHICH IS SUBJECTED TO HEAT TREATMENT TO HAVE ALIGNMENT MARK, CRYSTALLIZING METHOD FOR THE SEMICONDUCTOR THIN FILM, AND CRYSTALLIZING APPARATUS FOR THE SEMICONDUCTOR THIN FILM - Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region. | 2010-12-02 |
20100304547 | REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 2010-12-02 |
20100304548 | Silicon Nitride Hardstop Encapsulation Layer for STI Region - A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer ( | 2010-12-02 |
20100304549 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer. | 2010-12-02 |
20100304550 | MANUFACTURING METHOD OF SOI SUBSTRATE - An object is to provide a manufacturing method of an SOI substrate in which a plurality of single crystal semiconductor layers uniform in quality is bonded to a substrate having a larger area than a single crystal silicon substrate. At the time of a heat treatment, uniform heat distribution in single crystal semiconductor substrates is realized by using a tray which has depression portions each with a large depth and is not in contact with the single crystal semiconductor substrate bonded to a base substrate as a tray for supporting the base substrate and holding the single crystal semiconductor substrates. Further, by providing a supporting portion for the base substrate between the depression portions of the tray, a contact area between the tray and the base substrate is reduced. | 2010-12-02 |
20100304551 | PROTECTIVE FILM AGENT FOR LASER DICING AND WAFER PROCESSING METHOD USING THE PROTECTIVE FILM AGENT - A protective film agent for laser dicing according to the present invention comprises a solution having, dissolved therein, a water-soluble resin and at least one laser light absorber selected from the group consisting of a water-soluble dye, a water-soluble coloring matter, and a water-soluble ultraviolet absorber. The protective film agent is coated on a surface of a wafer, which is to be processed, and is then dried to form a protective film. Laser dicing through the protective film produces chips from the wafer. As a result, deposition of debris can be effectively prevented on the entire face of the chips, including their peripheral edge portions. | 2010-12-02 |
20100304552 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE DEDICATED TO SEMICONDUCTOR DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor substrate dedicated to a semiconductor device, in which multi-photon absorption is generated in a micro-region inside the semiconductor substrate by condensing laser beams in any micro-region inside the semiconductor substrate, and a gettering sink is formed by changing the crystal structure of only the micro-region. | 2010-12-02 |
20100304553 | METHOD FOR MANUFACTURING QUANTUM DOT - A silicon oxide film ( | 2010-12-02 |
20100304554 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - In a production method for a semiconductor device relating to the present invention, first, a pattern of a resist film made of organic polymers is formed on a semiconductor substrate. Next, impurity ions with 1×10 | 2010-12-02 |
20100304555 | Semiconductor device and method of manufacturing semiconductor device - The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface. | 2010-12-02 |
20100304556 | INTEGRATED CIRCUIT SYSTEM WITH VERTICAL CONTROL GATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa. | 2010-12-02 |
20100304557 | METHOD OF FORMING FLASH MEMORY DEVICE HAVING INTER-GATE PLUG - A method of forming a non-volatile memory device includes the following steps. First and second cell gates are formed in a cell region. First and second peripheral gates are formed in a peripheral-region. A first insulating layer is formed over the first and second cell gates and the first and second peripheral gates. A second conductive layer is formed over the first insulating layer. A third insulating layer is formed over the second conductive layer. Selected portions of the third insulating layer, the second conductive layer, and the first insulating layer are removed to form an inter-gate plug provided between the first and second cell gates. The inter-gate plug completely fills a space defined between the first and second cell gates. | 2010-12-02 |
20100304558 | METHODS USING SILVER COMPOSITIONS FOR MICRO-DEPOSITION DIRECT WRITING SILVER CONDUCTOR LINES ON PHOTOVOLTAIC WAFERS - Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device. | 2010-12-02 |
20100304559 | METHOD OF PRODUCTION OF A CONTACT STRUCTURE - A probe card having a plurality of silicon finger contactors contacting pads provided on a tested semiconductor wafer and a probe board mounting the plurality of silicon finger contactors on its surface, wherein each silicon finger contactor has a base part on which a step difference is formed, a support part with a rear end side provided at the base part and with a front end side sticking out from the base part, and a conductive part formed on the surface of the support part, each silicon finger contactor mounted on the probe board so that an angle part of the step difference formed on the base part contacts the surface of the probe board. | 2010-12-02 |
20100304560 | SEMICONDUCTOR PROCESSING METHODS - The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region. | 2010-12-02 |
20100304561 | FILM FORMING METHOD AND SUBSTRATE PROCESSING APPARATUS - A barrier layer including a titanium film is formed at a low temperature, and a TiSi | 2010-12-02 |
20100304562 | ELECTROLESS DEPOSITION OF COBALT ALLOYS - Systems and methods for electroless deposition of a cobalt-alloy layer on a copper surface include a solution characterized by a low pH. This solution may include, for example, a cobalt(II) salt, a complexing agent including at least two amine groups, a pH adjuster configured to adjust the pH to below 7.0, and a reducing agent. In some embodiments, the cobalt-alloy is configured to facilitate bonding and copper diffusion characteristics between the copper surface and a dielectric in an integrated circuit. | 2010-12-02 |
20100304563 | MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS - A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide. | 2010-12-02 |
20100304564 | SELECTIVE LOCAL INTERCONNECT TO GATE IN A SELF ALIGNED LOCAL INTERCONNECT PROCESS - A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions. | 2010-12-02 |
20100304565 | PROCESSED WAFER VIA - An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer. | 2010-12-02 |
20100304566 | ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS OF MICROSTRUCTURE DEVICES BY IN SITU PLASMA TREATMENT - Silicon oxide based low-k dielectric materials may receive superior hydrophobic surface characteristics on the basis of a plasma treatment using hydrogen and carbon containing radicals. For this purpose, the surface of the low-k dielectric material may be exposed to these radicals, at least in one in situ process in combination with another reactive plasma ambient, for instance used for patterning the low-k dielectric material. Consequently, superior surface characteristics may be established or re-established without significantly contributing to product cycle time. | 2010-12-02 |
20100304567 | Method of manufacturing a semiconductor device and substrate processing apparatus - A TiN film is formed by a first step of forming a TiN intermediate film on a wafer by supplying TiCl | 2010-12-02 |
20100304568 | PATTERN FORMING METHOD - A pattern forming method includes forming a first photoresist on an underlying region, forming a second photoresist on the first photoresist, the second photoresist having an exposure sensitivity which is different from an exposure sensitivity of the first photoresist, radiating exposure light on the first and second photoresists via a photomask including a first transmissive region and a second transmissive region which cause a phase difference of 180° between transmissive light components passing therethrough, the first transmissive region and the second transmissive region being provided in a manner to neighbor in an irradiation region, and developing the first and second photoresists which have been irradiated with the exposure light, thereby forming a structure includes a first region where the underlying region is exposed, a second region where the first photoresist is exposed and a third region where the first photoresist and the second photoresist are left. | 2010-12-02 |
20100304569 | METHOD OF FORMING A CONTACT HOLE - A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance. | 2010-12-02 |
20100304570 | ETCHING METHOD AND METHOD FOR MANUFACTURING OPTICAL/ELECTRONIC DEVICE USING THE SAME - Disclosed is a semiconductor etching method whereby a semiconductor layer made of, for example, a Group III-V nitride semiconductor resistant to etching can be etched by a relatively easier process. This etching method comprises forming a metal-fluoride layer | 2010-12-02 |
20100304571 | FILM ADHESIVE FOR SEMICONDUCTOR VACUUM PROCESSING APPARATUS - A bonded assembly to reduce particle contamination in a semiconductor vacuum chamber such as a plasma processing apparatus is provided, including an elastomeric sheet adhesive bond between mating surfaces of a component and a support member to accommodate thermal stresses. The elastomeric sheet comprises a silicone adhesive to withstand a high shear strain of ≧800% at a temperature range between room temperature and 300° C. such as heat curable high molecular weight dimethyl silicone with optional fillers. The sheet form has bond thickness control for parallelism of bonded surfaces. The sheet adhesive may be cut into pre-form shapes to conform to regularly or irregularly shaped features, maximize surface contact area with mating parts, and can be installed into cavities. Installation can be manually, manually with installation tooling, or with automated machinery. Composite layers of sheet adhesive having different physical properties can be laminated or coplanar. | 2010-12-02 |
20100304572 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - An optimum application voltage for reducing deposits on a peripheral portion of a substrate as well as improving a process result in balance is effectively found without changing a height of a focus ring. A plasma processing apparatus includes a focus ring which includes a dielectric ring provided so as to surround a substrate mounting portion of a mounting table and a conductive ring provided on the dielectric ring; a voltage sensor configured to detect a floating voltage of the conductive ring; a DC power supply configured to apply a DC voltage to the conductive ring. An optimum voltage to be applied to the conductive ring is obtained based on a floating voltage actually detected from the conductive ring, and the optimum application voltage is adjusted based on a variation in the actually detected floating voltage for each plasma process. | 2010-12-02 |
20100304573 | STABILIZED ETCHING SOLUTIONS FOR CU AND CU/NI LAYERS - The present invention relates to new storage-stable solutions which can be used in semiconductor technology to effect specific etching of copper metallization layers and also Cu/Ni layers. With the new etch solutions it is possible to carry out etching and patterning of all-copper metallizations, layers of copper/nickel alloys, and also successive copper and nickel layers. | 2010-12-02 |
20100304574 | FILM FORMATION METHOD AND APPARATUS FOR SEMICONDUCTOR PROCESS - Disclosed is a method for using a film formation apparatus to form a silicon nitride film by CVD on target substrates while suppressing particle generation. The apparatus includes a process container and an exciting mechanism attached on the process container. The method includes conducting a pre-coating process by performing pre-cycles and conducting a film formation process by performing main cycles. Each of the pre-cycles and main cycles alternately includes a step of supplying a silicon source gas and a step of supplying a nitriding gas with steps of exhausting gas from inside the process container interposed therebetween. The pre-coating process includes no period of exciting the nitriding gas by the exciting mechanism. The film formation process repeats a first cycle set that excites the nitriding gas by the exciting mechanism and a second cycle that does not excite the nitriding gas by the exciting mechanism. | 2010-12-02 |
20100304575 | METHOD AND ARRANGEMENT FOR TEMPERING SIC WAFERS - The invention relates to a method and an arrangement for tempering SiC wafers. The invention is to provide a method and an arrangement for tempering SiC wafers for generating a sufficient silicon partial pressure in the processing chamber and while reducing the operating costs. This is achieved in that a source for at least vaporized or gaseous silicon to increase the silicon partial pressure is connected to the processing chamber ( | 2010-12-02 |
20100304576 | CHAMBER, DEVICE AND METHOD FOR ANNEALING A SEMI-CONDUCTOR MATERIAL OF II-VI TYPE - A chamber for annealing a semi-conductor material of II-VI type having a first area for storing an element of group II of the periodic table and a second area designed to receive the semi-conductor material of II-VI type. The chamber s equipped with a separating partition at the level of an intermediate area. This separating partition is provided with a passage aperture equipped with gas anti-reverse flow means to ensure one-way passage of the element of group II of the periodic table, in vapor phase, from the first area to the second area. This chamber is heated by heating means enabling the two areas to be heated independently. | 2010-12-02 |
20100304577 | Powered Patch Panel - A powered communications patch panel is adapted to power network devices connected to the communications patch panel. Power is supplied to the network devices by the powered communications patch panel over the communication cabling. The powered communications patch panel may be provided with a management port to allow remote management of the patch panel via a network connection. Multiple management ports may be provided, allowing patch panels to be connected to one another in a daisy-chain configuration. | 2010-12-02 |
20100304578 | Charging Interface for Rechargeable Devices - A novel charging interface for rechargeable devices is disclosed herein. The present charging interface has a male plug, formed from circuit board material, which electrically and slidably interconnects with a female socket in at least two orientations. The female socket has electrically conductive biasing means which retain the male plug within the female socket. The charging interface provides electrical contact between the master circuit board of a rechargeable device and a power source. | 2010-12-02 |
20100304579 | Low Resistance Connector For Printed Circuit Board - An electrical connector has first and second connector bodies. The first connector body has at least one groove and the second connector body has cantilevered arms that correspond to the groove. To unmate the connector bodies, the cantilevered arms are pressed causing the arms to move from the groove to allow the connector bodies to be moved axially away from one another. | 2010-12-02 |
20100304580 | Electrical component interface - An apparatus and method of providing an electrical component interface is disclosed. For one embodiment, the electrical component interface includes an electrical component adapter. The electrical component adapter includes an electronic component solder pattern for receiving and allowing attachment of an electrical component. An adhesive backing is adjacent a surface of the electrical component adapter. The adhesive backing provides attachment of the electrical component adapter to a second surface. | 2010-12-02 |
20100304581 | ORTHOGONAL CONNECTOR SYSTEM WITH POWER CONNECTION - An orthogonal connector system for connecting a first circuit board and a second circuit board oriented orthogonally with respect to the first circuit board includes a receptacle assembly and a header assembly mated with the receptacle assembly. The receptacle assembly is connected to the first circuit board and the header assembly is connected to the second circuit board. The receptacle assembly and the header assembly both have a housing and contact modules held within the corresponding housing. Each contact module has a dielectric body and mating contacts extending from the dielectric body. The mating contacts of the receptacle assembly are directly connected to the mating contacts of the header assembly. At least some of the mating contacts of the receptacle assembly define power contacts configured to transmit power and at least some of the mating contacts of the receptacle assembly define power contacts configured to be mated with the power contacts of the receptacle assembly. | 2010-12-02 |
20100304582 | INVERSE COPLANAR ELECTRICAL CONNECTOR - A matable electrical connector, for connecting electrical modules, is described. The connector comprising a plug, the plug including a mating end, mating terminals at the mating end, a module mounting surface substantially perpendicular to the mating end, the module mounting surface including module terminals electrically connectable to the module, and at least one circuit connecting the module terminals to the mating terminals. The connector further comprising a receptacle, the receptacle including a mating end, mating terminals at the mating end, a module mounting surface substantially perpendicular to the mating end, the module mounting surface including module terminals electrically connectable to the module, and at least one circuit connecting the module terminals to the mating terminals. The plug and the receptacle are adapted to mate in a first mode wherein the module mounting surfaces of the plug and the receptacle are substantially coplanar and a second mode wherein the plane of the module mounting surfaces of the plug and the receptacle are substantially parallel but not coplanar. The modules to be connected include PCBs. | 2010-12-02 |
20100304583 | DISTRIBUTION FRAME MODULE - The invention relates to a distribution frame module ( | 2010-12-02 |
20100304584 | CONNECTOR SET AND JOINTER FOR USE THEREIN - A connector set includes at least one of a header and a socket and a jointer. The jointer extends in a direction and is configured to couple the header and the socket so as to be in parallel with each other. The jointer includes first jointer connecting portions provided at both end portions thereof and extending in a second direction perpendicular to the first direction, and which are configured to engage first connecting portions provided at both end portions of the header, and second jointer connecting portions provided at both end portions of the jointer body and extending in a third direction opposite to the second direction, and which are configured to engage the second connecting portions provided at both end portions of the socket. | 2010-12-02 |
20100304585 | ADAPTER DEVICE FOR HOUSING A MULTI-PHASE LOW VOLTAGE SWITCH INSIDE A SWITCHBOARD AND RELATIVE ADAPTER-SWITCH AND SWITCHBOARD ASSEMBLY - An adapter device ( | 2010-12-02 |
20100304586 | Computer Peripheral Device - A computer peripheral device is provided having a rotatable outer cover which is coupled to and selectively extends or retracts a connector of a printed circuit from a casing in which the printed circuit board is positioned when the outer cover is rotated. In one aspect, the cover includes a pin which extends through a groove formed in a seat coupled to an end of the circuit board. When the cover is rotated, the pin is urged against the groove to selectively extend or retract the connector from the casing. In another aspect, the cover includes a pin which extends into a groove formed in the printed circuit board. When the cover is rotated, the pin is urged against the groove to selectively extend or retract the connector from the casing. In another aspect, the cover is pivotally interconnected with the circuit bard, and when the cover is rotated, the casing selectively translates with respect to the circuit board to expose or cover the connector. | 2010-12-02 |
20100304587 | CONNECTOR COVER - To provide a connector cover that has dust preventing functions when the connector is not connected, and prevents inadvertent disengagement when a connector is connected. Provide a connector cover, comprising: a plate covering a receptacle open end; and an arm protruding from said plate; wherein the thickness of the arm is thinner than a gap between the latch lever of the plug and the body, when the plug is inserted into the open end. | 2010-12-02 |
20100304588 | PLUG-TYPE MOUNT - A plug-type mount is provided for releasably holding an equipment part such as a panel or an interior trim part on a sub-frame such as a fuselage. The plug-type mount ( | 2010-12-02 |
20100304589 | Miniature switch connector - The invention relates to a Switch connector for mounting on a printed circuit board, adapted to receive a mating connector in an insertion direction along an insertion axis. The switch connector comprises a shield, a contact element, and a contact spring having at least one fixed leg, at least one elastically deflectable switching leg, and at least one spring bend, the fixed leg and the switching leg extending from the spring bend in a common direction and passing the insertion axis. The switching leg is adapted to be moved by insertion of the mating connector from a rest position, at which the switching leg exerts a spring force onto the contact element, to a switching position, at which the switching leg is spaced apart from the contact element, at least one spring force flux that in the rest position is generated by the switching leg and guided in a closed loop to the fixed leg. To increase the reliability of the switching function, the shield is arranged in the closed loop of the spring force flux. | 2010-12-02 |
20100304590 | Device For Connecting An Electric Line To A Circuit Breaker - A device for connecting an electric line to a connection terminal for direct or indirect connection with a circuit breaker, which comprises at least one first electrically conducting body having a first end portion intended to be operatively connected to the terminal, and a second end portion intended to be operatively connected to a conductor element of the electric line, and at least one thermal conducting body comprising a hermetically sealed cavity containing a cooling fluid. The thermal conducting body is operatively coupled to the first electrically conducting body such that the hermetically sealed cavity has a first surface arranged in proximity to the first end portion and a second surface arranged in proximity to the second end portion. | 2010-12-02 |
20100304591 | FCP CONNECTOR HAVING ROTATING ACTUATOR - An FPC connector has a main body and an actuator movably attached thereto. When at an opened position, the actuator and the main body form a space therebetween into which an FPC can be inserted. The actuator can then be rotated towards the main body to close the space, such that the FPC is sandwiched and hold between the main body and the actuator. The actuator has a pair of pivots which are received by a pair of slots formed by the pair of support plates fixed to the main body. The actuator has a pair of latches which, when the actuator rotates to the locked position, act against a lock portion of the support plates and cause the lock portions to deform resiliently outwardly. When the latches pass over the lock portions, the lock portions resumes to the original position and lock the latches. | 2010-12-02 |
20100304592 | Connector Assemblies and Contacts for Implantable Medical Electrical Systems - A connector assembly of a medical electrical device includes a plurality of electrical contacts, wherein at least one contact of the plurality of electrical contacts includes an electrical coupling receptacle. The electrical coupling receptacle of the at least one contact includes a first portion, which is adapted to receive a connector element of a medical electrical lead, and a second portion, in which a part of a feedthrough member extends, and to which the part of the feedthrough member is fixedly coupled. | 2010-12-02 |
20100304593 | CONNECTOR IMPERMEABLE TO LIQUIDS - A connector ( | 2010-12-02 |
20100304594 | Connector - A plate-like connection target is inserted into a connector along a first direction. The connector has a first metal member having a first metal abutment portion, a second metal member having a second metal abutment portion, and an actuator operable to push the second metal abutment portion toward the first metal abutment portion for holding the plate-like connection target between the first metal abutment portion and the second metal abutment portion in a second direction perpendicular to the first direction in a state in which the plate-like connection target has been inserted in the connector. | 2010-12-02 |
20100304595 | BURN-IN SOCKET WITH INTENSIFIED SOCKET BODY - A burn-in socket for electrically connecting IC package to a printed circuit board, comprises a base, a sliding plate mounted to the base, and a plurality of contacts retained to the base and the sliding plate. The base has a plurality of protruding portions on a top surface thereof, the sliding plate is formed with a plurality of projecting portions on a bottom surface thereof, the protruding portions of the base abut against the bottom surface of the sliding plate, and the projecting portions of the sliding plate abut against the top surface of the base, so that the base and the sliding plate of the burin-in socket have an intensity. | 2010-12-02 |
20100304596 | WIRE TERMINATION APPARATUS AND METHOD - An electrical termination and method comprising an element and a conductive member is disclosed. A wire is manually or tool-lessly securable in electrical communication with the conductive member. | 2010-12-02 |
20100304597 | WIRE TERMINATION APPARATUS AND METHOD - An electrical termination and method comprising an element and a conductive member is disclosed. A wire is manually or tool-lessly securable in electrical communication with the conductive member. | 2010-12-02 |
20100304598 | Coaxial connector with coupling spring - The device includes an inner conductor, a dielectric material, an outer conductor, a coupling spring, and a sliding sleeve. The dielectric material surrounds the inner conductor. The outer conductor surrounds the dielectric material. The sliding sleeve is slidably attached to the outer conductor. The coupling spring is attached to the outer conductor. The coupling spring includes a plurality of beam tines. Each beam tine includes a lever tine. An adjacent pair of beam tines is separated by a slot where the slot has a root. A first distance is defined from the root to an edge of the beam tine. A second length is defined from the root to a distal end of the lever tine. The first length is greater than the second length. | 2010-12-02 |