48th week of 2012 patent applcation highlights part 46 |
Patent application number | Title | Published |
20120302014 | METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR WITH AIR SIDEWALLS - A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit. | 2012-11-29 |
20120302015 | METHODS OF MAKING JFET DEVICES WITH PIN GATE STACKS - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 2012-11-29 |
20120302016 | MANUFACTURING METHOD OF LOW TEMPERATURE POLY-SILICON TFT ARRAY SUBSTRATE - A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a third mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, and the source and drain electrodes being provided on the active layer. | 2012-11-29 |
20120302017 | Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device - A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor. | 2012-11-29 |
20120302018 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR - A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall. | 2012-11-29 |
20120302019 | NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES - A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure. | 2012-11-29 |
20120302020 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 2012-11-29 |
20120302021 | FABRICATION OF MOS DEVICE WITH VARYING TRENCH DEPTH - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth. | 2012-11-29 |
20120302022 | METHOD FOR FORMING AN ASYMMETRIC SEMICONDUCTOR DEVICE - A method for fabricating at least three different types of devices on a semiconductor substrate comprises forming a first electrode region and a second electrode region for a first semiconductor device at the same time as forming a first electrode region of a asymmetrical semiconductor device, and forming a first electrode region and a second electrode region for a second semiconductor device at the same time as forming a second electrode region of the asymmetrical semiconductor device. | 2012-11-29 |
20120302023 | PMOS Threshold Voltage Control by Germanium Implantation - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region. | 2012-11-29 |
20120302024 | SEMICONDUCTOR DEVICE WITH STRAINED CHANNEL AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern. | 2012-11-29 |
20120302025 | Method for Manufacturing a Semiconductor Structure - The present application provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate; forming a gate dielectric layer on the substrate; forming a dummy gate structure on the gate dielectric layer, wherein the dummy gate is formed from a polymer material; implanting dopants into portions of the substrates on opposite sides of the dummy gate structure to form source/drain regions; removing the dummy gate; annealing the source/drain regions to activate the dopants; and forming a metal gate. According to the present invention, it is proposed to manufacture a dummy gate structure with a polymer material, which significantly simplifies the subsequent etching process for removing the dummy gate structure and alleviates the etching difficulty accordingly. | 2012-11-29 |
20120302026 | METHOD FOR FORMING A TRANSISTOR - A method for forming a transistor includes providing a substrate, forming a well region in the substrate, and forming a gate structure on a surface of the well region. The gate structure includes a gate oxide layer on the surface of the well region and a gate on the gate oxide layer. The method further includes forming source/drain regions in the substrate at opposite sides of the gate structure and performing an ion doping to the substrate to adjust a threshold voltage. The ion doping is performed after the source/drain regions are formed to reduce the impact to the diffusion of the ions caused by heat treatments performed before the ion doping. The method further includes heating the substrate after the ion doping at a temperature from about 400° C. to about 500° C. | 2012-11-29 |
20120302027 | Method for Fabricating Silicon Nanowire Field Effect Transistor Based on Wet Etching - Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle. | 2012-11-29 |
20120302028 | MIXED VALENT OXIDE MEMORY AND METHOD - Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure. | 2012-11-29 |
20120302029 | PUNCH-THROUGH DIODE STEERING ELEMENT - A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device. | 2012-11-29 |
20120302030 | METHOD OF FABRICATING A DEEP TRENCH DEVICE - A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole. | 2012-11-29 |
20120302031 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS FOR PREPARING HIGH-ASPECT-RATIO STRUCTURES - The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (T | 2012-11-29 |
20120302032 | Methods for Forming Strained Channel Dynamic Random Access Memory Devices - DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. | 2012-11-29 |
20120302033 | CAPACITOR AND METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented. | 2012-11-29 |
20120302034 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a protruding channel region, forming a gate insulation layer surrounding the protruding channel region, forming a sacrificial layer having an etch selectivity varying in a thickness direction of the sacrificial layer, on the gate insulation layer, and performing a gate-last process to form a gate electrode on the gate insulation layer in place of the sacrificial layer. | 2012-11-29 |
20120302035 | SEMICONDUCTOR DEVICE HAVING AN OXIDE FILM FORMED ON A SEMICONDUCTOR SUBSTRATE SIDEWALL OF AN ELEMENT REGION AND ON A SIDEWALL OF A GATE ELECTRODE - A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film. | 2012-11-29 |
20120302036 | SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region. | 2012-11-29 |
20120302037 | Method of Protecting STI Structures From Erosion During Processing Operations - Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure. | 2012-11-29 |
20120302038 | METHOD FOR PREPARING A SHALLOW TRENCH ISOLATION STRUCTURE WITH THE STRESS OF ITS ISOLATION OXIDE BEING TUNED BY ION IMPLANTATION - A method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation comprises: step a: forming a protective layer on a semiconductor substrate; step b: forming trenches for isolating PMOS active regions and NMOS active regions on the semiconductor substrate and the protective layer; step c: forming a filling material layer in the trenches, so that the trenches are fully filled with the filling material layer to form shallow trench isolation structures. The advantageous is that, as for a device where a HARP process is applied to its shallow trench isolation, the stress in the STI can be tuned so as to be changed from tensile stress into compressive stress by performing ion implantation to the STI around the PMOS, therefore the stress state of the PMOS channel region may be changed and the performance thereof is improved. | 2012-11-29 |
20120302039 | ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX - Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion. | 2012-11-29 |
20120302040 | METHOD OF FABRICATION OF A THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE USING A WAFER SCALE MEMBRANE - Methods of fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO | 2012-11-29 |
20120302041 | Energy Ray-Curable Polymer, an Energy Ray-Curable Adhesive Composition, an Adhesive Sheet and a Processing Method of a Semiconductor Wafer - In a pressure-sensitive adhesive composition or a pressure-sensitive adhesive sheet containing an energy ray-curable polymer, problems associated with the volatilization of a low molecular weight compound contained in the composition are overcome. An energy ray-curable polymer characterized by comprising a radical generating group, which is capable of initiating a polymerization reaction upon excitation with an energy ray, and an energy ray-polymerizable group bonded together in the main or side chain. | 2012-11-29 |
20120302042 | ADHESIVE COMPOSITION FOR PRODUCING SEMICONDUCTOR DEVICE AND ADHESIVE SHEET FOR PRODUCING SEMICONDUCTOR DEVICE - An object of the present invention is to provide an adhesive composition that can form an adhesive sheet for producing a semiconductor device capable of suppressing deterioration in ion scavengeability after the adhesive sheet goes through thermal history. It is an adhesive composition for producing a semiconductor device containing at least an organic complex-forming compound that forms a complex with cations, and the 5% weight loss temperature of the organic complex-forming compound measured by thermogravimetry is 180° C. or more. | 2012-11-29 |
20120302043 | PROCESS FOR DECARBURIZATION OF A SILICON MELT - The present invention relates to a novel process for decarburizing a silicon melt, and to the use thereof for production of silicon, preferably solar silicon or semiconductor silicon. | 2012-11-29 |
20120302044 | METHOD FOR DEPOSITION OF NANOPARTICLES ONTO SUBSTRATES - A method for electrodepositing nanoparticles onto a substrate, including heating a nonaqueous polar suspension of a plurality of semiconducting nanoparticles to a temperature between about 30 degrees Celsius and about 100 degrees Celsius, placing a substrate into the suspension, imparting opposite surface charges onto the plurality of semiconducting particles and onto the substrate, establishing an electric field in the suspension, depositing a film of semiconducting particles onto the substrate to define a coated substrate, removing the coated substrate from the suspension into air, and coating the film of semiconducting particles with an electrically conducting metal layer. | 2012-11-29 |
20120302045 | METHOD FOR PRODUCING MOSAIC DIAMOND - The present invention discloses a method for producing a mosaic diamond comprising implanting ions in the vicinity of the surfaces of a plurality of single-crystal diamond substrates arranged in the form of a mosaic, or in the vicinity of the surfaces of mosaic single-crystal diamond substrates whose back surfaces are bonded by a single-crystal diamond layer, so as to form non-diamond layers; growing a single-crystal diamond layer by a vapor-phase synthesis method; and separating the single-crystal diamond layer above the non-diamond layers by etching the non-diamond layers. The method of the present invention prevents the destruction of single-crystal diamond substrates by using a process that is simpler than conventional methods, thus allowing a large quantity of mosaic diamond to be produced in a stable and efficient manner. | 2012-11-29 |
20120302046 | ELECTRONIC CIRCUIT STRUCTURE AND METHOD FOR FORMING SAME - A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods. | 2012-11-29 |
20120302047 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PARTIALLY OPEN SIDEWALL - A method for fabricating a semiconductor device includes forming a structure having first surfaces at a height above a second surface, which is provided between the first surfaces, forming a first silicon layer on the structure, performing a tilt ion implantation process on the first silicon layer to form a crystalline region and an amorphous region, forming a second silicon layer on the amorphous region, removing the second silicon layer and the first silicon layer until a part of the second surface is exposed, thereby forming an etch barrier, and etching using the etch barrier to form an open part that exposes a part of a sidewall of the structure. | 2012-11-29 |
20120302048 | PRE OR POST-IMPLANT PLASMA TREATMENT FOR PLASMA IMMERSED ION IMPLANTATION PROCESS - Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, flowing a gas mixture including a hydride dopant gas and a fluorine-containing dopant gas into the processing chamber, wherein the hydride dopant gas comprises P-type hydride dopant gas, N-type hydride dopant gas, or a combination thereof, and the fluorine-containing dopant gas comprises a P-type or N-type dopant atom, generating a plasma from the gas mixture, and co-implanting ions from the gas mixture into a surface of the substrate. | 2012-11-29 |
20120302049 | METHOD FOR IMPLANTING WAFER - The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different. | 2012-11-29 |
20120302050 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively. | 2012-11-29 |
20120302051 | MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer. | 2012-11-29 |
20120302052 | Methods of Forming Electrical Contacts - Some embodiments include methods of forming contacts. A row of projections may be formed over a semiconductor substrate. The projections may include a plurality of repeating components of an array, and a terminal projection. The terminal projection may have a sacrificial material spaced from semiconductor material of the substrate by a dielectric structure. An electrically conductive line may be formed along the row. The line may wrap around an end of the terminal projection and bifurcate into two branches that are along opposing sides of the repeating components. The individual branches may have regions spaced from the sacrificial material by segments of gate dielectric. The sacrificial material may be removed, together with the segments of gate dielectric, to form a contact opening. An electrically conductive contact may be formed within the contact opening and directly against the regions of the branches. | 2012-11-29 |
20120302053 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE NONVOLATILE MEMORY DEVICE INCLUDING GIVING AN UPPER PORTION OF AN INSULATING LAYER AN ETCHING SELECTIVITY WITH RESPECT TO A LOWER PORTION - A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure. | 2012-11-29 |
20120302054 | CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES - Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate. | 2012-11-29 |
20120302055 | DEPOSITION AND REDUCTION OF MIXED METAL OXIDE THIN FILMS - In one aspect, methods of forming mixed metal thin films comprising at least two different metals are provided. In some embodiments, a mixed metal oxide thin film is formed by atomic layer deposition and subsequently reduced to a mixed metal thin film. Reduction may take place, for example, in a hydrogen atmosphere. The presence of two or more metals in the mixed metal oxide allows for reduction at a lower reduction temperature than the reduction temperature of the individual oxides of the metals in the mixed metal oxide film. | 2012-11-29 |
20120302056 | PATTERN FORMING METHOD - A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture. | 2012-11-29 |
20120302057 | SELF ALIGNING VIA PATTERNING - A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch. | 2012-11-29 |
20120302058 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film. | 2012-11-29 |
20120302059 | ALIGNMENT TO MULTIPLE LAYERS - A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction. | 2012-11-29 |
20120302060 | METHOD FOR MANUFACTURING MEMORY DEVICE - The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide. | 2012-11-29 |
20120302061 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P | 2012-11-29 |
20120302062 | METHOD FOR VIA FORMATION IN A SEMICONDUCTOR DEVICE - A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth. | 2012-11-29 |
20120302063 | NON-POLISHED GLASS WAFER, THINNING SYSTEM AND METHOD FOR USING THE NON-POLISHED GLASS WAFER TO THIN A SEMICONDUCTOR WAFER - A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0. | 2012-11-29 |
20120302064 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE AND CHEMICAL MECHANICAL POLISHING APPARATUS - A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value of the measured torques N and a fluctuation range Y of the measured torques N. | 2012-11-29 |
20120302065 | PULSE-PLASMA ETCHING METHOD AND PULSE-PLASMA ETCHING APPARATUS - The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (T | 2012-11-29 |
20120302066 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, which includes forming a resist layer on a substrate, performing an exposure and development process on the resist layer to form a resist pattern, performing a slimming process to slim the resist pattern, forming a mask material layer on side walls of the slimmed resist pattern, and removing the slimmed resist pattern. The slimming process further includes coating an extensive agent on the substrate, expanding the expansive agent, and removing the expanded expansive agent. | 2012-11-29 |
20120302067 | Methods of Etching Trenches into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes - A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF | 2012-11-29 |
20120302068 | METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - A method for manufacturing a semiconductor integrated circuit includes providing a substrate having at least a metal hard mask formed thereon. Subsequently a patterning step is performed to the metal hard mask to form a patterned metal hard mask and followed by performing a H | 2012-11-29 |
20120302069 | METHOD OF PATTERNED IMAGE REVERSAL - A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern. | 2012-11-29 |
20120302070 | METHOD AND SYSTEM FOR PERFORMING PULSE-ETCHING IN A SEMICONDUCTOR DEVICE - A method for performing pulse-etching in a semiconductor device includes the steps of providing a semiconductor substrate, wherein a metal layer is disposed on the semiconductor substrate, and a hard mask layer is blanketed over the metal layer; introducing the semiconductor substrate into a processing container; introducing, into the processing container, etching gases in which a deposition-type gas composed of at least two of C, H, and F is added to etching gas selected from the group consisting of Cl | 2012-11-29 |
20120302071 | Forming Substrate Structure by Filling Recesses with Deposition Material - A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure. | 2012-11-29 |
20120302072 | STRADDLE MOUNTING ELECTRICAL CONNECTOR - An electrical connector adapted to be straddle mounted to a PCB and a method for mounting such an electrical connector. The electrical connector includes a housing defining a datum to abut the bottom side of the PCB and an upper row of contacts fastened in the housing. Each upper contact has a flexible mounting portion extending from the housing to abut the top side of the PCB. The mounting portions of the top contacts and the datum of the housing is adapted to clip the PCB thereby positioning the electrical connector related to the PCB. | 2012-11-29 |
20120302073 | CONNECTOR MECHANISM FOR CONNECTING A BOARD CARD - A connector mechanism for connecting a board card is disclosed. The connector mechanism includes a circuit board whereon at least one metal contact is formed, and a connector installed on the circuit board. An end of the board card is for inserting into the connector. The connector mechanism further includes at least one signal transmitting component fixed on the other end of the board card and electrically connected to the board card. The at least one signal transmitting component includes at least one conductive clip for resiliently contacting the at least one metal contact on the circuit board as the end of the board card is inserted into the connector so as to electrically connect to the circuit board. | 2012-11-29 |
20120302074 | SURFACE MOUNT ANTENNA CONTACTS - A method and system for connecting a vertical printed circuit board with a horizontal printed circuit board where a contact device is biased in a first position when not contacting a vertical printed circuit board and is biased in a second position when the vertical printed circuit is coupled to the horizontal printed circuit board. | 2012-11-29 |
20120302075 | Signal Wiring Board and Signal Transmission Circuit - The present invention maintains plugging-unplugging durability of connector pins for connecting to a signal wiring board, as well as reduces a stub length of a through hole connecting to a signal wiring. In the signal wiring board according to the present invention, a through hole connecting to the inner-layer signal wiring is formed to be shorter than the other through holes. A through hole in which a connector pin connecting to the inner-layer signal wiring is inserted is formed to have a length corresponding to a depth of the inner-layer signal wiring. | 2012-11-29 |
20120302076 | ELECTRICAL SOCKET - An electrical socket includes a plastic seat having a connection surface, a connection slot disposed in the plastic seat and rows of first and second terminals disposed on the plastic seat. A plug may be inserted into the connection slot, in which the connection surface facing an insert-connection surface of the plug is disposed. The plastic seat has rows of first and second terminal slots. A front section of the second terminal slot has an opening communicating with the connection slot. The first and second terminals are assembled into the first and second terminal slots, respectively. Fixing portions of the first and second terminals are fixed to the first and second terminal slots, respectively. A front section of an extension of the second terminal rests against a resting surface of the second terminal slot. The second contact is exposed to the connection slot through the opening. | 2012-11-29 |
20120302077 | CABLE ASSEMBLY WITH AN IMPROVED DUSTPROOF LID - A cable assembly comprises an insulative housing receiving a plurality of mating terminals therein, a cable extending beyond the housing and having a plurality of wires, a plurality of connecting terminals electrically terminated to the wires respectively, and an outer cover enclosing the housing and having a dustproof lid being delectably between an open position while the connecting terminals being exposed to an exterior and a closed position while the connecting terminals being covered by the dustproof lid for dustproof protection. The connecting terminals penetrate into the corresponding wires, respectively. | 2012-11-29 |
20120302078 | PULL-OUT STRUCTURE FOR CONNECTOR - A pull-out structure for connector includes a connector and a pull unit. The connector has a locking unit movably arranged thereon and the locking unit includes a retaining section located at a rear end thereof. The pull unit includes an insertion section located at a lower front end thereof, and is engaged with the locking unit by inserting the insertion section into the retaining section of the locking unit. The pull unit and the locking unit have sufficient structural strength. When it is necessary to replace or remove the connector from a shielding cage thereof, a user may directly apply a pulling force on the pull unit to move the locking unit rearward and accordingly easily pull the connector out of the shielding cage without damaging the connector. | 2012-11-29 |
20120302079 | Connection unit for fluorescent tubes - A connection unit for fluorescent tubes includes a base connected to each of two ends of a light unit and the base has an extension. Two conductive plates are connected to two reception areas of the extension. A cover is removably connected to the base and has a room and a recessed area is defined in the top of the cover. A rotatable member is removably connected to the recessed area and has a face board which has a reception hole communicating with the room. A shank is connected to the periphery of the reception hole and the rotatable member is rotatable about an axis of the recessed area. The base and the conductive plates are pulled out from the recessed area and the room respectively. | 2012-11-29 |
20120302080 | Connection unit for fluorescent tubes - A connection unit for fluorescent tubes includes a base having an extension which has an opening and an engaging portion is defined along an inner periphery of the opening. A cover is removably mounted to the base and a rotatable member is located in the cover. The cover has a terminal entrance defined in the base portion thereof so that terminals of a fluorescent tube are inserted into the terminal entrance. A shank extends from the base portion and a disk is connected to a distal end of the shank. The disk is engaged with the engaging portion of the base. The extension of the base and the cover position the disk so that the rotatable member is secured when being rotated. | 2012-11-29 |
20120302081 | ELECTRICAL CONNECTION SYSTEM HAVING DIELECTRIC SPRING TO ABSORB AXIAL POSITIONAL MATING TOLERANCE VARIATION FOR MULTIPLE CONNECTORS - A ganged electrical connection system includes an arrangement having a spring including a plurality of engagement portions. A plurality of first connectors is receivably coupled in a plurality of receptacles in the arrangement and a plurality of second connectors is matable to the coupled first connectors along mating axes. The plurality of coupled first connectors have floatable movement in the plurality of receptacles. The floatable movement is in at least an axial direction in relation to the plurality of receptacles and the axial positional mating tolerance variation of each second connector in the plurality of second connectors in relation to each first connector in the plurality of coupled first connectors that manifests at each receptacle in the plurality of receptacles is assimilated by each respective spring engagement portion when the plurality of second connectors mate to the plurality of coupled first connectors. | 2012-11-29 |
20120302082 | ELECTRICAL CONNECTOR HAVING RETENTION-PLATE TO BE RELEASED BY INWARD PRESSING ABOUT A PIVOT - A socket connector which includes a socket body having a plurality of contacts received therein, and a retention plate pivotally connected to a rear end of the socket body. The socket body has a substantially rectangular structure defining a rear wall, a front wall, and a pair of opposite sidewalls. Each sidewall is formed with a latching block and a pivot adjacent each other. The retention plate has a pair of latching arms in correspondence to the latching blocks and the pivots. The latching arm includes a latching section engageable with the lathing block, a lever section engageable with the pivot, and a handle at a free end thereof. | 2012-11-29 |
20120302083 | SOCKET CONNECTOR - A socket connector includes a main body, a fastener for locking an electric element on the main body, and a cover. The fastener includes a fixed plate defining a through hole. The fixed plate includes two opposite inner sidewalls. A first slide rail protrudes inward from one inner sidewall, and a second slide rail protrudes inward from the other inner sidewall. The cover includes two blocks. Each of the blocks includes an L-shaped main portion and a stop portion connected to L-shaped main portion. The L-shaped main portion and the stop portion of each block cooperatively define a slide groove. The first rail and the second rail slide into the slide grooves, respectively, and are stopped by the corresponding stop portions, such that the cover is detachably positioned on the fixed plate. | 2012-11-29 |
20120302084 | BI-DIRECTIONAL CPA MEMBER TO PREVENT UNMATING OF MULTIPLE CONNECTORS - A ganged electrical connection system includes a plurality of first connectors matable to a plurality of second connectors along mating axes, and a connector position assurance (CPA) member. The CPA member includes a plurality of tabs and a plurality of release fingers. The plurality of first connectors include a plurality of lock arms and the plurality of second connectors include a plurality of inclined ramps. The plurality of tabs receive the plurality of lock arms and the plurality of inclined ramps deflectingly engage said plurality of release fingers to allow movement of the CPA member in to a position of the CPA member, that when disposed in the position, keeps the plurality of second connectors from unmating from the plurality of coupled first connectors. Methods of fabricating an electrical connection system and a ganged electrical connection system that include the CPA member are also presented. | 2012-11-29 |
20120302085 | LOCKING COVER FOR ELECTRICAL CONNECTION APPLIANCE - A locking cover for an electrical connecting appliance, to be mounted on a second electrical connecting appliance connected to a first electrical connecting appliance, for preventing a disconnection between the first electrical connecting appliance and the second electrical connecting appliance. The locking cover includes a cover main body externally fitted onto the second electrical connecting appliance, first locking pieces formed on the cover main body, and second locking pieces formed on the cover main body. The first locking pieces elastically engages first appliance side locking portions, and release an elastic engagement by receiving an external force to an engagement releasing position. The second locking pieces elastically disengageably engage second appliance side locking portions provided on the second electrical connecting appliance. The second locking pieces are pressed by the first locking pieces displaced to the engagement releasing position to restrict releasing an engagement with the second appliance side locking portions. | 2012-11-29 |
20120302086 | CONNECTOR - The connector matable with a mating connector comprises a housing, a lever and an attached member. The housing has a front end, a rear end and an accommodating portion. The accommodating portion communicates with the front end and the rear end. The accommodating portion has an upper portion, a lower portion and side portions. The side portions are formed on respective opposite ends in a width direction of the accommodating portion so as to couple the upper portion and the lower portion with each other. The lever is configured to mate the connector with the mating connector and accommodated in the accommodating portion so as to be pivotable. The attached member is other than the housing. The attached member is attached to the housing so as to couple the upper portion and the lower portion with each other at a position located between the side portions in the width direction. | 2012-11-29 |
20120302087 | ELECTRICAL SOCKET WITH A GUIDE TO URGE A LEAD OF AN ELECTRICAL COMPONENT TO A TERMINAL - A leaded device socket includes a lead guide that contacts and urges the leads on an electrical component into the correct position in the device when the component is pressed into the socket. The leaded device socket may also include a receiver for retaining a functional portion of the electrical component in a predetermined position in the circuit. The lead guide and receiver may both be integrally molded with the socket. | 2012-11-29 |
20120302088 | Capacitivly Coupled Flat Conductor Connector - A capacitivly coupled flat conductor connector provided with a male connector body and a female connector body. An alignment insert is coupled to the male connector body, the alignment insert dimensioned to support a predefined length of an inner conductor. An alignment receptacle coupled to the female connector body, the alignment receptacle dimensioned to receive a connector end of the alignment insert to seat an overlapping portion of an inner conductor and an inner conductor trace parallel with one another against opposite sides of a spacer. | 2012-11-29 |
20120302089 | GROUND TERMINAL ASSEMBLY FOR A VEHICLE - A ground terminal is provided for a vehicle. The ground terminal includes a hub having an opening extending therethrough. The opening is configured to receive a fastener for attaching the hub to the vehicle. A plurality of electrical contacts extend radially outward from the hub. Each electrical contact extends outwardly from the hub to a free end portion. The free end portions of the electrical contacts are arranged in an arcuate pattern. | 2012-11-29 |
20120302090 | CONNECTOR - A connector is provided which can prevent damage to cables, and hold and waterproof the ends of the cables. | 2012-11-29 |
20120302091 | WIRING SYSTEM WITH ELECTRICAL DEVICE, BOX, AND MODULE - A color-coded wiring system for electrical devices such as outlets, switches, lighting fixtures, ceiling fans, smoke detectors, thermostats, chimes, etc. is described. For residential structures, the wiring system is comprised of an electrical device, a box with two open sides, and a module. The back side of the electrical device comprises at least one male plug and the front side comprises at least one female outlet receptacle. The male plug(s) inserts into the female outlet receptacle(s) through the open sides of the box. The back, top, or bottom side of the module has a section(s) comprising at least two stab holes. At least one female outlet receptacle is continuous with at least one stab hole. For commercial structures, the commercial box is open on only the side facing the electrical device, comprises knockouts for wires to enter through conduits, and front and back stops to hold the module in place. | 2012-11-29 |
20120302092 | MULTIFUNCTIONAL ELECTRICITY OUTLET - A multifunctional electricity outlet for a building automation and building information system has a first interface to a line to the electricity supply, and a second interface to an electrical load. Furthermore, the multifunctional electricity outlet contains an apparatus for measurement of at least one electrical variable, a memory for the at least one measured electrical variable, a communication module with a third interface for sending and receiving data and a control module for producing a profile for at least one of the measured electrical variables over time and for comparison of the profile over time with predetermined stored profiles of loads which can be connected, over time, in order to determine the load which is connected to the second interface. | 2012-11-29 |
20120302093 | ASSEMBLY OF A LOW-NOISE BLOCK CONVERTER AND A FILTER FOR A SATELLITE ANTENNA SYSTEM, AND CONNECTING COMPONENT THEREOF - An assembly of a low-noise block converter and a filter for a satellite antenna includes a low-noise block converter, a filter, and a connecting component. The low-noise block converter includes an output circuit, and the filter includes a filtering circuit. The connecting component includes a sleeve part for engaging threadedly the low-noise block converter and the filter, and a core extending through the sleeve part and interconnecting electrically the output circuit and the filtering circuit. By virtue of the sleeve part of the connecting component, connection between the low-noise block converter and the filter can be reinforced to reduce interference. The sleeve part can also serve as a ground circuit between the low-noiseblock converter and the filter so as to shorten a ground path, thereby reducing signal loss. | 2012-11-29 |
20120302094 | CONNECTOR HOUSING WITH MAT SEAL - A connector housing with a mat seal, includes a connector housing a mat seal. At an outer surface of a rear wall of the connector housing, a plurality of passages for a silicone gum forming material are provided outside an area where a plurality of terminal insertion holes are formed. On the outer surface of the rear wall and outside the passages, an annular rib is protruded and surrounds an area inside the annular rib. The mat seal is molded by using the area inside the annular rib as a reservoir space in which the silicone gum forming material overflowing from the seal forming cavity is retained, and using at least one of the passages as a passage for a gate through which the silicone gum forming material is injected into the seal forming cavity, and the other of the passages as passages for overflow. | 2012-11-29 |
20120302095 | INTERPOSER CONNECTORS - High-speed interposer connectors that may be space-efficient, reliable, and may be readily manufactured. One example may provide an interposer connector that may be particularly space-efficient in a vertical direction by using an interposer to form an electrical connection between conductors and a main-logic board or other appropriate substrate. Another example may provide a reliable connection between conductors and a main-logic board by using fasteners to fix an interposer to the main-logic board. Another example may provide connectors that are well-suited to handling high-speed signals by providing a shield to at least partially cover a top of an interposer connector. | 2012-11-29 |
20120302096 | ELECTRICAL CONNECTOR - An electrical connector includes a connector housing, a plurality of electrical contacts carried by the housing, including respective pluralities of signal contacts and ground contacts configured as crosstalk shields. Electrical characteristics exhibited by the electrical connector during operation can be tuned by modifying physical characteristics of one or more of the crosstalk shields, for instance by modifying the respective shield body of one or more of the plurality of crosstalk shields so as to alter a corresponding shield area defined by the shield body of each of the plurality of crosstalk shields. | 2012-11-29 |
20120302097 | LAMP HOLDER CONNECTOR - A lamp holder connector includes a lower holder having a bottom board with two positioning pillars protruding upward thereon, and an upper holder covered on the lower holder to together define a receiving chamber. An electrical terminal is fastened in the receiving chamber, and has a base plate with two positioning holes apart opened therein for inserting the positioning pillars therein, and a pair of clamping plates connected with two opposite side edges of the base plate and apart facing to each other for clamping one end of a lamp therebetween. A top end of each positioning pillar projects upward beyond a top side of the base plate and then is pressed downward by an external jig to have a deformation and form a blocking eave so as to tightly clip the base plate between the bottom board and the blocking eave. | 2012-11-29 |
20120302098 | FUSE UNIT - A fuse unit includes a fuse element and an insulative resin part. The fuse element includes a power supply connecting part fixed to a battery post of a battery so as to receive power supply and arranged along an upper surface of the battery, a terminal connecting part to which a terminal is connected, and a fusible part provided between the power supply connecting part and the terminal connecting part. The insulative resin part is arranged on outer surface of the fuse element. The fuse element is bent upwards at a position between the power supply connecting part and the terminal connecting part. The terminal connecting part is arranged at a position above the upper surface of the battery and along a side surface direction of the battery. | 2012-11-29 |
20120302099 | ELECTRONIC DEVICES CONNECTOR - A connector includes an enclosure and a body. The enclosure includes a top plate and a side plate perpendicularly connected to the top plate. The side plate has a second side edge substantially perpendicular to the top plate. The body is received in the enclosure and includes a sidewall. The sidewall abuts the side plate and is substantially parallel to the side plate. The sidewall includes a first part and a second part, and the second part defines a first mounting hole. The top plate abuts the body. A mounting piece extends from the top plate; the first part of the sidewall is in a first side of the side edge and covered by the side plate. The second part of the sidewall is in a second side opposite to the first side and exposed out of the side plate. The mounting piece is engaged in the first mounting hole. | 2012-11-29 |
20120302100 | Conduit Adaptor - An adaptor may include a body portion and a conduit receptacle. The body portion may include a cross-member and first and second arms extending from the cross-member. The first and second arms may include first and second engagement features, respectively. The conduit receptacle may extend from the cross-member in a direction opposite the first and second arms and may include an aperture and a third engagement feature. The third engagement feature may retain an outer surface of a conduit. The conduit may receive and protect a plurality of wires transmitting electrical power to an electrically powered component. | 2012-11-29 |
20120302101 | Adapter For Cordless Power Tools - An electrical combination including a power tool, charger and an adapter separate from and connectable between the battery and the tool housing or battery charger to support the battery on the tool housing or the battery charger, the adapter having adapter leads for electrically coupling the battery to the power tool or the battery charger, the adapter having a mechanical lockout for allowing an electrical coupling between the adapter and the power tool while preventing an electrical coupling between the adapter and the battery charger. | 2012-11-29 |
20120302102 | Electrical Contact With Contact Area Geometry Enlargement - An electrical contact including a male termination end configured to be removably inserted into a female termination end of a mating contact. The male termination end having a slot between two beam sections. The slot is formed by a section of the male termination end having had material removed between the two beam sections. The two beam sections are outwardly deformed in opposite directions. The two beam sections are substantially parallel to each other along a majority of length of the male termination end. | 2012-11-29 |
20120302103 | CABLE CONNECTOR - A cable connector ( | 2012-11-29 |
20120302104 | SOCKET WITH SEVERAL MATING PORTS - A cable assembly comprises an insulative, a plurality of contacts received in the insulative housing and a cable extending beyond the insulative housing and electrically connecting with the contacts. The insulative housing has a first mating port, a second mating port and a third mating port located on two opposite sides of the first mating port, respectively. These three ports are insulated with each other. The contacts include a first contact extending into the first mating port, a power contacts extending into the second mating port and a grounding contact extending into the third mating port, by this arrangement, the cable assembly can obtain a well signal transmission quality. | 2012-11-29 |
20120302105 | Connector Assembly and Device and Methods of Assembling Same - A device and an assembly related to connecting cables, wires, and electrical devices are described herein. The device can include a retainer, subretainer, and at least one contact pin in some embodiments. The retainer and subretainer can be removably coupled. The at least one contact pin can be positioned within channels of the retainer and the subretainer. In other aspects, a device can include a retainer, a subretainer, a retainer clip, a circuit web, and at least contact pin. The at least one contact pin can be position within channels of the retainer, the subretainer, and the retainer clip. Also described herein are methods of manufacturing a connector device. | 2012-11-29 |
20120302106 | CONNECTOR APPARATUS HAVING A DETACHABLE MODULE - A connector apparatus having a detachable module includes a connector base and a detachable module. The connector base has an insulating body and a plurality of press-contacting terminals. A plurality of grooves are inwardly formed on a rear surface of the insulating body. The press-contacting terminals are correspondingly located in the grooves. A press-contacting portion of each of the press-contacting terminals extends along the upper surface of the insulating body and protrudes out from the upper surface. The detachable module is composed of a circuit board, an integrated circuit electrically connecting to the circuit board and a plurality of connecting pins arranged on the circuit board. When the detachable module is connected to the connector base, the connecting pins are electrically connected to the press-contacting portions, and the mainboard of a computer connected to the connector base can execute the function of the integrated circuit in the detachable module. | 2012-11-29 |
20120302107 | METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTIVE CONNECTION - Method for producing an electrically conductive connection, in particular between a contact pin ( | 2012-11-29 |
20120302108 | Electrical Contact Normal Force Increase - An electrical connector including a housing; and a plurality of first ground contacts. The first ground contacts each comprise a male contact blade configured to be inserted into a contact channel of a housing of a mating electrical connector. The male contact blade has a portion configured to contact the housing of the mating electrical connector, after the male contact blade makes electrical contact with the deflectable beam, to move the male contact blade in the contact channel, increase deflection of the deflectable beam by the male contact blade, and increase or maintain normal force between the mating contact and the ground contact generally. | 2012-11-29 |
20120302109 | ELECTRICAL TERMINAL HAVING A PAIR OF STRENGTHENING ARMS - An electrical terminal has a soldering plate having a front end soldered onto a printed circuit board and a rear end edge bent upward to raise beyond a plane of the soldering plate, an elastic plate extending rearward from a substantial middle of the rear end edge of the soldering plate and inclined upward, a contact portion protruding rearward from a distal end of the elastic plate, and two strengthening arms extending rearward from two ends of the rear end edge of the soldering plate. The strengthening arms are inclined downward and towards the printed circuit board in process of extending rearward, so as to make distal ends thereof resist against the printed circuit board to strengthen the restoring elasticity of the elastic plate, when an external force presses the contact portion and the elastic plate downward. | 2012-11-29 |
20120302110 | CONNECTION ARRANGEMENT FOR THE CONNECTION OF BUS BARS - A connection arrangement includes a connector for connecting at least two bus bars in an electrically conductive manner. The connector has a first hook-shaped projection which engages in a receptacle of one of the bus bars. The first hook-shaped projection can be constructed to embrace a peripheral area of the receptacle. | 2012-11-29 |
20120302111 | CONTACT PIECE OF GOLD FINGER, GOLD FINGER AND CONNECTOR COMPRISING THE GOLD FINGER - A contact piece of a gold finger comprises: a first main body segment; a second main body segment; and a transition segment connected to the first main body segment and the second main body segment, respectively, in a vertical direction, in which an upper edge and a lower edge of the transition segment are inclined with respect to a lateral direction respectively. A gold finger and a connector comprising the same are also provided. | 2012-11-29 |
20120302112 | SHIP DRIVE SYSTEM HAVING A PLURALITY OF ELECTRIC DRIVE SHAFTS - A ship drive system includes a first and one second drive shaft for driving a respective propulsion unit, wherein each of the electric drive shafts includes at least one speed-variable generator driven by an internal combustion engine for generating a motor voltage having a variable amplitude and variable frequency, and at least one speed-variable drive motor that is supplied with the voltage and coupled to the propulsion unit. The first and second drive shafts can be switched from a first operating state, in which they are electrically disconnected from each other, to a second operating state, in which they are electrically coupled to each other such energy can be transmitted from the at least one generator of the one drive shaft to the at least one drive motor of the other drive shaft. To this end, the at least one generator includes a superconductor winding. | 2012-11-29 |
20120302113 | Marine Propulsion Assembly - A marine propulsion assembly comprises or consists of a marine engine, a pair of parallel laterally spaced propeller shafts and a pair of marine propellers with one of the propeller fixed to each of the shafts for rotation. Each of the propellers includes a hub and four equally spaced blades and wherein the hub has a forward portion having the shape of a frustum of a cone with a decreasing radius from a forward edge thereof to the middle of the hub and a rear or second continuous portion having the shape of a frustum of a cone with an increasing radius from the middle of the hub to the rear of the hub. The bases or larger ends of the frustums are of equal size as are the tops of the frustums. In addition, each of the blades has a complex concave shape wherein an arcuate leading edge curves outwardly and upwardly at a reduced radius from a shallow forward portion to an outwardly extending rear portions and with a relatively straight trailing edge that is generally perpendicular to the axis of rotation and wherein the leading edge of one of the propellers face the leading edge of the other of said propellers as they rotate inwardly and in which they are spaced apart by about ½ or less of the trailing edge of one of the blades. | 2012-11-29 |