48th week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120299013 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure including a substrate, a patterned structure, a first semiconductor layer, an active layer and a second semiconductor layer is provided. The patterned structure is protruded from or indented into a surface of the substrate, so that the surface of the substrate becomes a roughed surface. The patterned structure has an asymmetrical geometric shape. The first semiconductor layer is disposed on the roughed surface. The active layer is disposed on the first semiconductor layer. The second semiconductor is disposed on the active layer. | 2012-11-29 |
20120299014 | SEMICONDUCTOR LIGHT EMITTING DEVICE, NITRIDE SEMICONDUCTOR LAYER GROWTH SUBSTRATE, AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)≦0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion. | 2012-11-29 |
20120299015 | NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR LAYER GROWTH SUBSTRATE - According to one embodiment, a nitride semiconductor device includes a substrate and a semiconductor functional layer. The substrate is a single crystal. The semiconductor functional layer is provided on a major surface of the substrate and includes a nitride semiconductor. The substrate includes a plurality of structural bodies disposed in the major surface. Each of the plurality of structural bodies is a protrusion provided on the major surface or a recess provided on the major surface. An absolute value of an angle between a nearest direction of an arrangement of the plurality of structural bodies and a nearest direction of a crystal lattice of the substrate in a plane parallel to the major surface is not less than 1 degree and not more than 10 degrees. | 2012-11-29 |
20120299016 | ORGANIC LAYER DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE USING THE ORGANIC LAYER DEPOSITION APPARATUS - An organic layer deposition apparatus capable of protecting or preventing a patterning slit sheet from sagging, and a method of manufacturing an organic light-emitting display device by using the organic layer deposition apparatus. | 2012-11-29 |
20120299017 | BATWING LED WITH REMOTE PHOSPHOR CONFIGURATION - An LED emitter uses a molded lens with phosphor material embedded in a circumferential trench to generate a batwing beam pattern. After the lens is molded over a package substrate with connected LED dies thereon, the phosphor material is molded, injected, or dispensed into a circumferential trench. The molded lens is shaped such that a majority of the light emitted by the one or more LED dies is reflected by the top surface to the side surfaces through the phosphor material. | 2012-11-29 |
20120299018 | BAT-WING LENS DESIGN WITH MULTI-DIE - A batwing beam is produced from an optical emitter having a primary LED lens over a number of LED dies on a package substrate. The LED lens includes a batwing surface formed by rotating a parabolic arc about an end of the parabolic arc over a center of the optical emitter. A center of each of the LED dies is mounted to the package substrate about the focus of a parabola whose arc forms the batwing surface, for example, between about 0.5 to 1.5 of a focal distance from the vertex of the parabola. The batwing surface reflects light from the number of LED dies through total internal reflection (TIR) or through a reflectivity gel coating. | 2012-11-29 |
20120299019 | Systems and Methods Providing Semiconductor Light Emitters - A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board. | 2012-11-29 |
20120299020 | LED PACKAGE MODULE FOR LIGHTING - An LED package module for lighting includes a plurality of LED chips spacedly arranged on a hard substrate and a plurality of dome-shaped encapsulants arranged on the hard substrate in such a way that the encapsulants enclose the LED chips respectively. By means of the dome-shaped encapsulants, the light extracting rate of the LED chips is enhanced. On the surface of the hard substrate, no dam structure is needed; therefore, the amount of the encapsulant material used in the LED package module can be effectively saved. | 2012-11-29 |
20120299021 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - Drive units arranged on a transistor array substrate include faulty drive units. The pixel electrodes include first pixel electrodes and second pixel electrodes, the first pixel electrodes corresponding one-to-one to the faulty drive units, and the second pixel electrodes corresponding one-to-one to the non-faulty drive units, a portion of each second pixel electrode is embedded in the contact hole corresponding thereto, and is in contact with a power supply pad of the non-faulty drive unit corresponding thereto, so that the second pixel electrode is electrically connected to the non-faulty drive unit. Each first pixel electrode is electrically insulated from the faulty drive unit corresponding thereto, and is connected by a connector to any of the second pixel electrodes adjacent thereto. A surface of each connector facing the interlayer insulation film is entirely in contact with the interlayer insulation film. | 2012-11-29 |
20120299022 | LIGHT EMITTING DEVICES AND METHODS - Light emitting devices and methods are disclosed. In one embodiment a light emitting device can include a submount and a light emission area disposed over the submount. The light emission area can include one or more light emitting diodes (LEDs), a fillet at least partially disposed about the one or more the LEDs, and filling material. The filling material can be disposed over a portion of the one or more LEDs and a portion of the fillet. | 2012-11-29 |
20120299023 | ORGANIC LAYER DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - An organic layer deposition apparatus for forming an organic layer on a substrate includes: a deposition source configured to discharge a deposition material; a deposition source nozzle unit arranged at a side of the deposition source and including a plurality of deposition source nozzles; and a patterning slit sheet facing the deposition source nozzle unit and including a plurality of patterning slits and at least one spacer arranged between a pair of adjacent patterning slits of the plurality of patterning slits, the patterning slit sheet being smaller than the substrate in at least one of a first direction or a second direction perpendicular to the first direction, and the substrate is spaced apart from the organic layer deposition apparatus by a predetermined distance, and at least one of the substrate or the organic layer deposition apparatus is movable relative to the other. | 2012-11-29 |
20120299024 | PATTERNING SLIT SHEET ASSEMBLY, ORGANIC LAYER DEPOSITION APPARATUS, METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS, AND THE ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A patterning slit sheet assembly for performing a deposition process to form a thin film on a substrate in a desired fine pattern. The patterning slit sheet assembly includes a patterning slit sheet having a plurality of slits, a frame combined with the patterning slit sheet to support the patterning slit sheet, and a support unit including an upper member that is allowed to be moved or fixed to support the patterning slit sheet when a gravitational force is applied to the patterning slit sheet and a lower member disposed more apart from the patterning slit sheet than the upper member, wherein the upper member is fixed on the lower member. | 2012-11-29 |
20120299025 | MANUFACTURING METHOD OF LIGHT EMITTING DEVICE AND MANUFACTURING DEVICE THEREOF - The present invention provides a structure in which a pixel region | 2012-11-29 |
20120299026 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device comprises a substrate having a plurality of light emitting elements mounted thereon; a side wall structure having a partition wall portion separating a plurality of light emitting areas that each include at least one of the light emitting elements; and encapsulating resin filled in the light emitting areas to bury the light emitting elements therein. The side wall structure is separated by a space from the substrate at, at least, the partition wall portion so as to be in noncontact with the substrate, and the encapsulating resin is formed so as to integrally, continuously fill the light emitting areas and the space without producing any interface therein. | 2012-11-29 |
20120299027 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film. | 2012-11-29 |
20120299028 | MANUFACTURING METHOD FOR LIQUID CRYSTAL DISPLAY DEVICE - A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode. | 2012-11-29 |
20120299029 | DISPLAY DEVICE - It is an object to provide a highly reliable display device. It is a feature an IC is over a substrate and a material layer having the same height is thereover. An IC is provided on one side of the substrate, and a material layer having the same height as the IC is provided on at least another side. Further, an IC is provided on one side of the substrate, and material layers having the same height as the IC are provided on the other sides. Further, an IC is provided on one side of the substrate, and a material layer having the same height as the IC is provided at a corner of the substrate. | 2012-11-29 |
20120299030 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT, LIGHTING DEVICE AND LENS - An optoelectronic semiconductor component for a lighting device including a carrier, at least one optoelectronic semiconductor chip mounted on the carrier and which includes a radiation passage face remote from the carrier, by which a plane is defined, and a lens comprising 1) a radiation exit face, which, relative to a height above the plane, exhibits a minimum, in particular in a central region, and at least two local maxima, and at least two local maxima, and 2) at least two connecting embankments which each extend from one of the maxima to another of the maxima, and each connecting embankment comprises a saddle point higher than the minimum and lower than the maxima adjoining the connecting embankment. | 2012-11-29 |
20120299031 | LIGHT EMITTING DEVICE, ELECTRONIC APPARATUS, AND MANUFACTURING METHOD OF LIGHT EMITTING DEVICE - D={(2πm+φ | 2012-11-29 |
20120299032 | LIGHT EMITTING DEVICE WITH PHOSPHOR WAVELENGTH CONVERSION - A light emitting device comprises a substantially planar light transmissive substrate having a light emitting surface and an opposite surface. The substrate is configured as a light guiding medium. The light emitting device also comprises at least one phosphor material disposed as a layer on the light emitting surface with a plurality of window areas and at least one source of excitation radiation of a first wavelength positioned adjacent to at least one peripheral edge of the substrate. The source is configured to couple excitation radiation into the substrate such that it is waveguided within the substrate by total internal reflection. Additionally, the light emitted by the device from the light emitting surface comprises first wavelength radiation and second, longer wavelength photoluminescent light emitted by the phosphor layer as a result of excitation by the source. | 2012-11-29 |
20120299033 | LIGHT-EMITTING DEVICE - To provide a light-emitting device ( | 2012-11-29 |
20120299034 | COLLIMATING LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A collimating light emitting device comprises a patterned optical layer able to redirect divergent light to light beam with uniform direction without utilizing external lenses thereby decreasing the size. The collimating light emitting device of the present invention may be utilized as a micro array projection device. The patterned optical layer may also be utilized in a single-die light-emitting device, thereby enhancing collimation. The manufacturing methods of the collimating light emitting device are also presented. | 2012-11-29 |
20120299035 | LIGHT-EMITTING DEVICE AND DISPLAY DEVICE - There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided. | 2012-11-29 |
20120299036 | THERMALLY ENHANCED LIGHT EMITTING DEVICE PACKAGE - A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip. | 2012-11-29 |
20120299037 | Organic light-emitting device and method of manufacturing the same - An organic light-emitting device including a substrate, an anode layer on the substrate, the anode layer including WO | 2012-11-29 |
20120299038 | LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS - A light emitting device may be provided that includes a substrate, a light emitting structure, a first electrode under the first semiconductor layer, a reflective electrode layer under the second conductive semiconductor layer, a second electrode under the reflective electrode layer, and a support member under the first semiconductor layer and the reflective electrode layer around the first and second electrodes. A first connection electrode may be provided under the first electrode. At least a part of the first connection electrode is provided in the support member. A second connection electrode may be provided under the second electrode At least a part of the second connection electrode may be provided in the support member. | 2012-11-29 |
20120299039 | EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR DEVICE AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an epoxy resin composition for an optical semiconductor device, including the following ingredients (A) to (E): (A) an epoxy resin; (B) an acid anhydride curing agent; (C) a curing accelerator; (D) a specific silicone resin; and (E) a specific alcohol compound. | 2012-11-29 |
20120299040 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor light emitting device including: a light transmissive substrate; a light emitting part; first and second electrodes electrically connected to the first and second conductivity type semiconductor layers, respectively; and a rear reflective part including a reflective metallic layer, and a light transmissive dielectric layer interposed between the light transmissive substrate and the reflective metallic layer. | 2012-11-29 |
20120299041 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor component includes a radiation emitting semiconductor chip having a radiation coupling out area. Electromagnetic radiation generated in the semiconductor chip leaves the semiconductor chip via the radiation coupling out area. A converter element is disposed downstream of the semiconductor chip at its radiation coupling out area. The converter element is configured to convert electromagnetic radiation emitted by the semiconductor chip. The converter element has a first surface facing away from the radiation coupling out area. A reflective encapsulation encapsulates the semiconductor chip and portions of the converter element at side areas in a form-fitting manner. The first surface of the converter element is free of the reflective encapsulation. | 2012-11-29 |
20120299042 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE USING THE SAME - There is provided a semiconductor light emitting device, a method of manufacturing the same, and a semiconductor light emitting device package using the same. A semiconductor light emitting device having a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a second electrode layer, and insulating layer, a first electrode layer, and a conductive substrate sequentially laminated, wherein the second electrode layer has an exposed area at the interface between the second electrode layer and the second conductivity type semiconductor layer, and the first electrode layer comprises at least one contact hole electrically connected to the first conductivity type semiconductor layer, electrically insulated from the second conductivity type semiconductor layer and the active layer, and extending from one surface of the first electrode layer to at least part of the first conductivity type semiconductor layer. | 2012-11-29 |
20120299043 | LIGHT-EMITTING SEMICONDUCTOR DEVICE AND PACKAGE THEREOF - The present application discloses a light-emitting semiconductor device including a transparent layer having an upper surface, a lower surface, and a sidewall; a wavelength conversion structure arranged on the upper surface; an epitaxial structure arranged on the lower surface and having a side surface devoid of the transparent layer and the wavelength conversion structure; and a reflective wall arranged to cover the sidewall. | 2012-11-29 |
20120299044 | LIGHTING SET, LIGHTING DEVICE, AND DISPLAY DEVICE - Disclosed are: a lighting device that stably supplies high-quality surface light; a lighting set that is one part of the lighting device; and a display device equipped with the lighting device. In an LED package (PG), supporting sections ( | 2012-11-29 |
20120299045 | ORGANIC ELECTROLUMINESCENT DEVICE WITH INTEGRATED LAYER FOR COLOUR CONVERSION - The invention relates, inter alia, to an opto-electronic device having at least two electrodes ( | 2012-11-29 |
20120299046 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a light emitting layer, a second semiconductor layer of a second conductivity type, a first electrode layer and a second electrode layer. The first semiconductor layer includes a first portion and a second portion thicker than the first portion. The second portion includes a side surface rising from a major surface of the first portion. The light emitting layer is provided on the second portion. The second semiconductor layer is provided on the light emitting layer. The first electrode layer is provided along the major surface of the first portion and is in contact with the side surface of the second portion. The second electrode layer is provided on the second semiconductor layer. | 2012-11-29 |
20120299047 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHT UNIT - Provided are a light emitting device, a light emitting device package, and a light unit. The light emitting device includes: a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer. A surface of the light emitting structure has a plurality of first sides and second sides having curvatures in respectively different directions, which are alternately disposed. | 2012-11-29 |
20120299048 | SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING CURRENT BLOCKING LAYER - There is provided a semiconductor light emitting device including: a semiconductor light emitting laminate including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed therebetween; a first electrode having at least one bonding pad formed on a portion of an upper surface of the first conductive semiconductor layer; a second electrode having an ohmic contact layer formed on the second conductive semiconductor layer; and a current blocking layer between the second conductive semiconductor layer and the ohmic contact layer having a plurality of patterns formed thereon, the plurality of patterns being arrayed such that intervals between patterns adjacent to a region overlapped with the bonding pad are smaller an interval between patterns of another regions. | 2012-11-29 |
20120299049 | Optoelectronic Semiconductor Chip and Method for Adapting a Contact Structure for Electrically Contacting an Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip has a first semiconductor functional region with a first terminal and a second terminal. A contact structure electrically contacts the optoelectronic semiconductor chip. The contact structure is connected electrically conductively to the first semiconductor functional region. The contact structure has a disconnectable conductor structure. An operating current path is established via the first terminal of the first semiconductor functional region and the second terminal if the conductor structure is not disconnected. This path is interrupted if the conductor structure is disconnected. Alternatively, an operating current path is established via the first terminal of the first semiconductor functional region and the second terminal if the conductor structure is disconnected. The conductor structure connects the first terminal to the second terminal and short circuits the first semiconductor functional region if the conductor structure is not disconnected. | 2012-11-29 |
20120299050 | ELECTRO-OPTICAL DEVICE, ELECTRODE THEREFORE, AND METHOD AND APPARATUS OF MANUFACTURING AN ELECTRODE AND THE ELECTRO-OPTICAL DEVICE PROVIDED THEREWITH - The present invention relates to an electro-optical device provided with an electrode ( | 2012-11-29 |
20120299051 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE HAVING THE SAME - Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer, an electrode electrically connected to the first conductive semiconductor layer, a reflective layer under the second conductive semiconductor layer, a protective layer disposed around a lower surface of the second conductive semiconductor layer, and a buffer layer disposed on at least one of top and lower surfaces of the protective layer. | 2012-11-29 |
20120299052 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND OPTICAL DEVICE - A semiconductor light-emitting device capable of inhibiting a semiconductor light-emitting element from deterioration and capable of inhibiting the size of a package from enlargement is obtained. The semiconductor light-emitting device includes a semiconductor light-emitting element and a package sealing the semiconductor light-emitting element. The package includes a base portion mounted with the semiconductor light-emitting element and a cap portion mounted on the base portion for covering the semiconductor light-emitting element. At least either one of the base portion and the cap portion is made of a mixture of resin and a gas absorbent. | 2012-11-29 |
20120299053 | Semiconductor Device and Integrated Circuit Including the Semiconductor Device - A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body also includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A voltage tap including a semiconductor region within the semiconductor body is electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure. | 2012-11-29 |
20120299054 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a four-layer structure having layers arranged in order: (i) a cathode layer of a first conductivity type with a central area being surrounded by a lateral edge, the cathode layer being in direct electrical contact with a cathode electrode, (ii) a base layer of a second conductivity type, (iii) a drift layer of the first conductivity typehaving a lower doping concentration than the cathode layer, and (iv) an anode layer of the second conductivity type which is in electrical contact with an anode electrode. The base layer includes a first layer as a continuous layer contacting the central area of the cathode layer. A resistance reduction layer, in which the resistance at the junction between the lateral edge of the cathode and base layers is reduced, is arranged between the first layer and the cathode layer and covers the lateral edge of the cathode layer. | 2012-11-29 |
20120299055 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween. | 2012-11-29 |
20120299056 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p | 2012-11-29 |
20120299057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling. | 2012-11-29 |
20120299058 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion. | 2012-11-29 |
20120299059 | TRANSISTOR AND METHOD FOR MANUFACTURING SAME - The transistor includes an underlying layer | 2012-11-29 |
20120299060 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor device includes: a silicon substrate; a buffer layer formed on the silicon substrate and comprised of a nitride semiconductor; and an active layer formed on the buffer layer and comprised of a nitride semiconductor. The buffer layer includes a first layer formed in contact with the silicon substrate, and a second layer formed in contact with the first layer and the active layer. The carbon concentration at an interface between the first layer and the second layer is in the range of 1×10 | 2012-11-29 |
20120299061 | METHOD FOR MANUFACTURING EPITAXIAL CRYSTAL SUBSTRATE, EPITAXIAL CRYSTAL SUBSTRATE AND SEMICONDUCTOR DEVICE - Disclosed is a technology of manufacturing, at low cost, an epitaxial crystal substrate provided with a high-quality and uniform epitaxial layer, said technology being useful in the case of growing the epitaxial layer composed of a semiconductor having a lattice constant different from that of the substrate. The substrate, which is composed of a first compound semiconductor, and which has a step-terrace structure on the surface, is used, and on the surface of the substrate, a composition modulation layer composed of a second compound semiconductor is grown by step-flow, while changing the composition in the same terrace. Then, the epitaxial crystal substrate is manufactured by growing, on the composition modulation layer, the epitaxial layer composed of the third compound semiconductor having the lattice constant different from that of the first compound semiconductor. | 2012-11-29 |
20120299062 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 2012-11-29 |
20120299063 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor memory device according to the embodiment includes: forming a first stacked-structure; forming a first stripe part and a first hook part at the first stacked-structure; forming a second stacked-structure on the first stacked-structure; forming a second stripe part and a second hook part at the second stacked-structure; repeating the above-described four steps for a certain number of times; and forming a contact plug contacting the first or second hook parts. The etching is conducted to remove the first stacked-structure in a region at which the second hook part is to be formed in the second stacked-structure higher than the first stacked-structure by one layer. The etching is conducted to remove the second stacked-structure in a region at which the first hook part is to be formed in the first stacked-structure higher than the second stacked-structure by one layer. | 2012-11-29 |
20120299064 | SEMICONDUCTOR DEVICE - A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor. | 2012-11-29 |
20120299065 | SEMICONDUCTOR DEVICE - There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout rule introduced in accordance with microfabrication of a MISFET is provided. For example, a protruding wiring PL | 2012-11-29 |
20120299066 | SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP DEVICE, AND METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE - In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion. | 2012-11-29 |
20120299067 | CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS - An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins. | 2012-11-29 |
20120299068 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer. | 2012-11-29 |
20120299069 | COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT - Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device. | 2012-11-29 |
20120299070 | PHOTOELECTRIC CONVERSION ELEMENT AND PHOTOELECTRIC CONVERTER - Disclosed herein is a photoelectric conversion element including: a first semiconductor layer of a first conductivity type provided above a substrate; a second semiconductor layer of a second conductivity type provided in a higher layer than the first semiconductor layer; a third semiconductor layer of a third conductivity type provided between the first and second semiconductor layers and lower in electrical conductivity than the first and second semiconductor layers; and a light-shielding layer provided between the substrate and first semiconductor layer. | 2012-11-29 |
20120299071 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a solid-state imaging device includes a photodiode includes an N-type region and a P-type region, a floating diffusion region, and a transfer transistor. The N-type diffusion region of the photodiode comprises a first semiconductor region and a second semiconductor region formed shallower than the first semiconductor region. An end portion of the first semiconductor region is positioned on the floating diffusion region side rather than an end portion of a gate electrode of the transfer transistor. An end portion of the second semiconductor region is set in substantially the same position as that of the end portion of the gate electrode of the transfer transistor. | 2012-11-29 |
20120299072 | SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF FORMING THE SAME - Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide. | 2012-11-29 |
20120299073 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region. | 2012-11-29 |
20120299074 | SEMICONDUCTOR DEVICE - A semiconductor device in which light leakage due to misalignment is prevented even when a black matrix layer is not expanded to a designed value or more is provided. In a semiconductor device including a dual-gate thin film transistor in which a semiconductor layer is sandwiched between a bottom gate electrode and a top gate electrode, the top gate electrode is formed of a first black matrix layer, and the top gate electrode overlaps with the semiconductor layer. | 2012-11-29 |
20120299075 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 2012-11-29 |
20120299076 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region. | 2012-11-29 |
20120299077 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point. | 2012-11-29 |
20120299078 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, there is disclosed a semiconductor storage device comprising a semiconductor substrate and a plurality of electrical rewritable nonvolatile memory cells. Each of the memory cells includes a floating gate and a control gate on the semiconductor substrate. Each of the memory cells shares a source/drain region with an adjacent memory cell. The memory cells are connected serially and configure a NAND cell unit. The source/drain region includes silicide layer. | 2012-11-29 |
20120299079 | FIELD SIDE SUB-BITLINE NOR FLASH ARRAY AND METHOD OF FABRICATING THE SAME - Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density. | 2012-11-29 |
20120299080 | STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY - A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed. | 2012-11-29 |
20120299081 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer. | 2012-11-29 |
20120299082 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a semiconductor substrate having a peripheral circuit region and a cell region, wherein the cell region of the semiconductor substrate is lower in height than the peripheral circuit region of the semiconductor substrate, a control gate structure disposed over the cell region of the semiconductor substrate and comprising a plurality of inter-layer dielectric layers that are alternately stacked with a plurality of control gate electrodes, a first insulation layer covering the cell region of the semiconductor substrate where the control gate structure is formed, a selection gate electrode disposed over the first insulation layer, and a peripheral circuit device disposed over the peripheral circuit region of the semiconductor substrate. | 2012-11-29 |
20120299083 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode. | 2012-11-29 |
20120299084 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film | 2012-11-29 |
20120299085 | SELECT TRANSISTOR, METHOD FOR MAKING SELECT TRANSISTOR, MEMORY DEVICE, AND METHOD FOR MANUFACTURING MEMORY DEVICE - A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode. | 2012-11-29 |
20120299086 | SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed. | 2012-11-29 |
20120299087 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction. | 2012-11-29 |
20120299088 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 2012-11-29 |
20120299089 | Semiconductor Device and Method for Manufacturing the same - It is disclosed a semiconductor device and a method for manufacturing the same. One method comprises providing a semiconductor layer that is formed on an insulating layer; forming a mask pattern on the semiconductor layer, which exposes a portion of the semiconductor layer; removing the exposed portion of the semiconductor layer of a predetermined thickness, thereby forming a groove; forming a gate stack in the mask pattern and the groove; removing the mask pattern to expose a portion of sidewalls of the gate stack. The method not only meets the requirement for a precise thickness of the SOI, but also increases the thickness of the source/drain regions as compared to a device having a uniform SOI thickness at the gate stack, thereby facilitating a reduction of the parasitic resistance of the source/drain regions. | 2012-11-29 |
20120299090 | Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods - A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed. | 2012-11-29 |
20120299091 | TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode. | 2012-11-29 |
20120299092 | SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged. | 2012-11-29 |
20120299093 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width. | 2012-11-29 |
20120299094 | SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction. | 2012-11-29 |
20120299095 | SEMICONDUCTOR DEVICE - The invention is directed to realizing a power MOS transistor of high efficiency by enhancing the switching performance of a power MOS transistor having a low on-resistance characteristic more than conventional. A semiconductor chip which includes a gate electrode extending between a source electrode and a drain electrode which include finger form electrodes from one end portion to another end portion of the finger form electrodes, gate drawing electrodes connected to the end portions of the gate electrode through contact holes formed in an interlayer insulation film, a passivation film covering the interlayer insulation film, gate connection electrodes which are portions of the gate drawing electrodes and exposed in openings of the passivation film, and protrusion electrodes formed on the gate connection electrodes, is connected to a low resistance substrate wiring for shunting the gate electrode formed on the front surface of a BGA substrate by the protrusion electrodes. | 2012-11-29 |
20120299096 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 2012-11-29 |
20120299097 | Semiconductor Architecture Having Field-effect Transistors Especially Suitable for Analog Applications - An insulated-gate field-effect transistor ( | 2012-11-29 |
20120299098 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) DEVICE WITH BOTTOM ERASE GATE - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; an insulator layer disposed over the semiconductor substrate; a fin structure disposed over the insulator layer, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region; a gate structure disposed adjacent to the channel region of the fin structure; and a doped region disposed in the semiconductor substrate below the channel region of the fin structure. The gate structure includes a first gate dielectric layer disposed adjacent to the fin structure, a second gate dielectric layer, a charge storing layer disposed between the first gate dielectric layer and the second gate dielectric layer, and a gate electrode layer disposed adjacent to the second gate dielectric layer. | 2012-11-29 |
20120299099 | FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure. | 2012-11-29 |
20120299100 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode. | 2012-11-29 |
20120299101 | THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS - A thin-silicon-on-insulator transistor with borderless self-aligned contacts includes a buried oxide layer above a substrate. A silicon layer overlays the buried oxide layer. A gate stack is on the silicon layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode on the gate oxide layer. An off-set spacer surrounds the gate stack. Raised source/drain regions each have a first part overlying a portion of the silicon layer, a second part adjacent to off-set spacer, and a third part extending about a top portion of the gate stack. | 2012-11-29 |
20120299102 | FET with FUSI Gate and Reduced Source/Drain Contact Resistance - A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer. | 2012-11-29 |
20120299103 | RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion. | 2012-11-29 |
20120299104 | SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS - A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate. | 2012-11-29 |
20120299105 | ETSOI CMOS with Back Gates - A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage. | 2012-11-29 |
20120299106 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device is provided that includes a first inverter having a first p-channel FinFET and a first n-channel FinFET each coupled to a first shared contact forming a first cell node and having a first common gate. A second inverter is included having a second p-channel FinFET and a second n-channel FINFET each coupled to a second shared contact forming a second cell node and having a second common gate aligned with the first shared contact of the first inverter forming a latch circuit. Additionally, a pair of FinFET passgates are included each having a drain contact respectively coupled the first and second cell nodes and a source contact connected to one of a complementary bit line. Finally, a word line is connected to a gate contact of each of the pair of FinFET passgates to provide a static random access memory cell. | 2012-11-29 |
20120299107 | High Performance Devices and High Density Devices on Single Chip - A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner. | 2012-11-29 |
20120299108 | SEMICONDUCTOR DEVICE - By connecting a protection diode ( | 2012-11-29 |
20120299109 | TRENCH POWER MOSFET STRUCTURE WITH HIGH SWITCHING SPEED AND FABRICATION METHOD THEREOF - A fabrication method of trench power semiconductor structure with high switching speed is provided. An epitaxial layer with a first conductivity type is formed on a substrate. Then, gate structures are formed in the epitaxial layer. A shallow doped region with the first conductivity type is formed in the surface layer of the epitaxial layer. After that, a shielding structure is formed on the shallow doped region. Then, wells with a second conductivity type are formed in the epitaxial layer by using the shielding structure as an implantation mask. Finally, a source doped region with the first conductivity type is formed on the surface of the well. The doping concentration of the shallow doped layer is smaller than that of the source doped region and the well. The doping concentration of the shallow doped layer is larger than that of the epitaxial layer. | 2012-11-29 |
20120299110 | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights - A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate. | 2012-11-29 |
20120299111 | ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME - Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 2012-11-29 |
20120299112 | Integration of Low and High Voltage CMOS Devices - A semiconductor device includes a semiconductor substrate having a first portion and a second portion and a first transistor of a first type formed in the first portion of the substrate, the first transistor being operable at a first voltage, and the first transistor including a doped channel region of a second type opposite of the first type. The semiconductor device also includes a second transistor of the second type formed in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage, the second transistor including an extended doped feature of the second type. Further, the semiconductor device includes a well of the first type in the semiconductor substrate under a gate of the second transistor, wherein the well does not extend directly under the extended doped feature and the extended doped feature does not extend directly under the well. | 2012-11-29 |