48th week of 2008 patent applcation highlights part 59 |
Patent application number | Title | Published |
20080294882 | DISTRIBUTED LOOP CONTROLLER ARCHITECTURE FOR MULTI-THREADING IN UNI-THREADED PROCESSORS - In one aspect, a virtually multi-threaded distributed instruction memory hierarchy that can support the execution of multiple incompatible loops in parallel is disclosed. In addition to regular loops, irregular loops with conditional constructs and nested loops can be mapped. The loop buffers are clustered, each loop buffer having its own local controller, and each local controller is responsible for indexing and regulating accesses to its loop buffer. | 2008-11-27 |
20080294883 | Mock exceptions in a host add-in environment - Mock exceptions, including mock exception types, are defined by a host to be raised in a plug-in. The mock exceptions might be sanitized. They might be transported from the plug-in to the host. Mock exceptions might also be mapped to real exceptions, which are raised in the host and handled by the host. | 2008-11-27 |
20080294884 | Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors - A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread. | 2008-11-27 |
20080294885 | Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation Execution - A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in response to the flush count exceeding a threshold. The single step mode instructions are issued in serial such that an instruction is not issued for execution until a prior instruction has completed execution. | 2008-11-27 |
20080294886 | Method for resetting bios - A method for resetting a basic input/output system (BIOS) suitable for a desktop computer having the BIOS is provided. The BIOS is reset when a reset or power button of the desktop computer is pressed. Accordingly, the problem that the desktop computer cannot be booted up can be resolved quickly. | 2008-11-27 |
20080294887 | ACTIVATION METHOD FOR MULTIPLE OPERATION SYSTEMS OF A COMPUTER - An activation method for multiple operation systems of a computer, comprising selectively pressing a function key in a keyboard while pressing a power supply key, receiving a signal of the pressed power supply key and a key code of the pressed function key by an embedded controller, determining the operation system desired to be activated according to the received key code by the embedded controller, and informing a basic input/output system by the embedded controller to activate the specific operation system. Therefore, the waiting time spent on selecting operation system in the prior art is eliminated. | 2008-11-27 |
20080294888 | DEPLOY TARGET COMPUTER, DEPLOYMENT SYSTEM AND DEPLOYING METHOD - A deploy target computer is connected to a storage device including a replication source logical disk used to store a boot disk image. A disk mapping processing part in the deploy target computer changes over access destination so as to set the access destination to the replication source logical disk in the storage device when an I/O request is issued from the deploy target computer to the storage device and the I/O request specifies reading the boot disk image, and so as to set the access destination to a replication destination logical disk for conducting writing concerning the boot disk image when the I/O request specifies writing concerning the boot disk image. | 2008-11-27 |
20080294889 | Method and apparatus to store initialization and configuration information - Briefly, in accordance with an embodiment of the invention, an apparatus and method to store initialization and configuration information is provided. The method may include storing basic input/output system (BIOS) software in a polymer memory. The method may further include copying a first portion of the BIOS software from the polymer memory to a random access memory (RAM) buffer of a memory controller, wherein the RAM buffer has a storage capacity of at least about two kilobytes (KB). | 2008-11-27 |
20080294890 | METHOD AND APPARATUS FOR CONTROLLING OUTPUT OF CONTENT DEVICE - Provided are a method and apparatus for controlling an output of a content device. The method includes: receiving a request signal that requests the use of encrypted content; executing software for decrypting the encrypted content in response to the received request signal; and controlling the decrypted content to be output through an output port that is allowed by the executed software. | 2008-11-27 |
20080294891 | Method for Authenticating a Mobile Node in a Communication Network - A method for authenticating a mobile node ( | 2008-11-27 |
20080294892 | METHOD AND SYSTEM FOR A KERNEL LOCK VALIDATOR - An embodiment relates generally to a method of preventing resource access conflicts in a software component. The method includes intercepting a lock operation in the software component and testing an associated lock type of the lock operation against a set of rules. The method also includes determining an action based on the associated lock type conflicting one of the rules of the set of rules. | 2008-11-27 |
20080294893 | DEVICE AND METHOD FOR SECURITY RECONFIGURATION - A security reconfigurable device is adapted for use in an integrated wireless network integrating at least two wireless networks, and includes a plurality of security modules and a control unit. The security modules are used to respectively realize security mechanisms related to the wireless networks. According to security requirements, the control unit selects one of the security modules for operation. The security reconfigurable device can reduce time and cost for updating the security mechanisms. A method for security reconfiguration is also disclosed. | 2008-11-27 |
20080294894 | Binding Content Licenses to Portable Storage Devices - Systems, methods, and/or techniques (“tools”) for binding content licenses to portable storage devices are described. In connection with binding the content licenses to the portable storage devices (“stores”), a host may perform authentication protocols that include generating a nonce, sending the nonce to a store, and receiving a session key from the store, with the session key being generated using the nonce. The store may perform authentication protocols that include receiving the nonce from the host, generating a random session key based on the nonce, and sending the session key to the host. | 2008-11-27 |
20080294895 | Disaggregation/reassembly method system for information rights management of secure documents - The present invention pertains to a computerized system and method that provides for the secure storage and retrieval of electronic digital information; and, more particularly, to such a computerized system and method that provides for multiple access levels of such secure information; provides for secure access to portions of secure information dependent upon access privileges of the authorized user; provides virtually limitless data expansion capabilities; and provides for rapid access to such secure information by authorized users. | 2008-11-27 |
20080294896 | Method and System for Transmitting and Receiving User's Personal Information Using Agent - A method and system for transmitting and receiving user's personal information using an agent are provided. An information management server managing user's personal information provides an agent including user's personal information in response to a user's personal information request message from a client. A client receives the agent and requests user's personal information from the agent. Then, the agent determines whether the client is authorized and provides the user's personal information to the client when it is determined that the client is authorized. Accordingly, the user's personal information is safely managed and transmitted. | 2008-11-27 |
20080294897 | METHOD AND APPARATUS FOR EFFICIENT SUPPORT FOR MULTIPLE AUTHENTICATIONS - Disclosed is a method for multiple EAP-based authentications in a wireless communication system. In the method, a first master session key (MSK) is generated in a first EAP-based authentication for a first-type access. A first temporal session key (TSK) is generated from the first master session key (MSK). A second EAP-based authentication is performed, using the first temporal session key (TSK), for a second-type access. First-type access and second-type access are provided after the first and second EAP-based authentications are successfully completed. | 2008-11-27 |
20080294898 | Mobile Terminal for Secure Electronic Transactions and Secure Electronic Transaction System - The present invention relates to a roaming electronic transaction terminal. It also relates to a secure system for electronic transactions comprising one or more roaming terminals. The terminal ( | 2008-11-27 |
20080294899 | SECURE MANAGEMENT OF DOCUMENT IN A CLIENT-SERVER ENVIRONMENT - A computer-implemented method for securely handling a document in a client-server environment includes receiving at a server a request from a user to initiate a session to access a plurality of documents stored in a server. The documents include a first type that is allowed to be accessed only while the user is online and a second type that is allowed to be accessed while the user is both online and offline. The server transfers at least one offline vault key and at least one online vault key to a client enable the client to load the documents and enable the user to access the documents, the documents including at least one document of first type and at least one document of second type. | 2008-11-27 |
20080294900 | Authenticity Verification of Articles Using a Database - A digital signature is obtained by digitising a set of data points obtained by scanning a coherent beam over a paper, cardboard or other article, and measuring the scatter. A thumbnail digital signature is also determined by digitising an amplitude spectrum of a Fourier transform of the set of data points. A database of digital signatures and their thumbnails can thus be built up. The authenticity of an article can later be verified by re-scanning the article to determine its digital signature and thumbnail, and then searching the database for a match. Searching is done on the basis of the Fourier transform thumbnail to improve search speed. Speed is improved, since, in a pseudo-random bit sequence, any bit shift only affects the phase spectrum, and not the amplitude spectrum of a Fourier transform represented in polar coordinates. The amplitude spectrum stored in the thumbnail can therefore be matched without any knowledge of the unknown bit shift caused by registry errors between the original scan and the re-scan. | 2008-11-27 |
20080294901 | Media Storage Structures for Storing Content, Devices for Using Such Structures, Systems for Distributing Such Structures - Some embodiments of the invention provide a content-distribution system for distributing content under a variety of different basis. For instance, in some embodiments, the content-distribution system distributes device-restricted content and device-unrestricted content. Device-restricted content is content that can only be played on devices that the system associates with the particular user. Device-unrestricted content is content that can be played on any device without any restrictions. However, for at least one operation or service other than playback, device-unrestricted content has to be authenticated before this operation or service can be performed on the content. In some embodiments, the system facilitates this authentication by specifying a verification parameter for a piece of device-unrestricted content. The content-distribution system of some embodiments has a set of servers that supply (1) media storage structures that store content, (2) cryptographic keys that are needed to decrypt device-restricted content, and (3) verification parameters that are needed to verify device-unrestricted content. In some embodiments, the device that receives the media storage structure inserts the received cryptographic key or verification parameter in the received media storage structure. In some embodiments, the set of servers also supply cryptographic content keys for the device-unrestricted content. These keys are used to decrypt the content upon arrival, upon first playback, or at some other time. However, some embodiments do not store these cryptographic keys in the media storage structures for the device-unrestricted content. | 2008-11-27 |
20080294902 | METHOD AND SYSTEM FOR IMPROVING SECURITY OF THE KEY DEVICE - The present invention provides a method and a system for improving security of a key device in the information security filed. In order to solve the problem that the security performance of the key device is lower due to the possible tamper of the data needed for encryption and signature in prior art, the present invention provides the method, including steps in which the key device is connected to a computer, then is used to receive the data input by the user through a computer and display the same after a user makes a successful authentication; and to make digital signature or encryption of the data input after the user confirms the content displayed. The above-mentioned system comprises an authentication module, a data receiving module, a display module, a confirmation information receiving module, and a key module. The present invention makes relative display on the key device according to the data input by the user, and provides an input device or generates a random authentication code for confirmation and therefore prevents invalid digital signature or encryption, and improves the security of the key device greatly. | 2008-11-27 |
20080294903 | AUTHENTICITY ASSURANCE SYSTEM FOR SPREADSHEET DATA - A method is provided for applying a redactable signature method capable of verification even after deletion (blacking-out) of a part of a signed electronic document to spreadsheet data. | 2008-11-27 |
20080294904 | METHOD TO PREVENT ACCESS OF WEB APPLICATIONS FROM BOOKMARKED LINKS - An improved solution for accessing a web application is provided. In an embodiment of the invention, a method for controlling access to a web application includes: receiving a request for a first web page application, wherein the first web application is connected to a second web page application via a link at the second web page application; determining if the request is likely from a book marked link to the first web page application or from the link at the second web page application; and providing one of the second web page application and the first web page application based on the determining | 2008-11-27 |
20080294905 | SECURE APPROACH TO SEND DATA FROM ONE SYSTEM TO ANOTHER - A secure approach for sending a original message from a sender to a receiver. The sender may encrypt the original message by performing an XOR (or XNOR) operation of the original message and a first random message (same size as original message) on a bit by basis to generate a second message. The receiver may also perform an XOR of the second message with a locally generated second random message. The resulting message is sent to the sender system. The sender system may again perform XOR operation of the received message and the first random message, and send the resulting message to receiver. The receiver may perform XOR operation on the received output to generate the original message sent by the sender. Other technologies such as digital signatures and key pairs (public key infrastructure) may be used in each communication between the sender and receiver to further enhance security. | 2008-11-27 |
20080294906 | Retrieval and Display of Encryption Labels From an Encryption Key Manager Certificate ID Attached to Key Certificate - A method, system and program in which a certificate identifier (ID) is associated with an encryption certificate. In certain embodiments, the certificate ID is stored in a cartridge memory (CM). Thus, keystore or key manager administrators can trace keystore locations, versions of keystores, etc. when a cart cannot locate a correct key. This certificate ID, as it is stored on the cartridge memory, is viewable by all. | 2008-11-27 |
20080294907 | Methods for using a biometric parameter in the identification of persons - Brain waves are used as a biometric parameter to provide for authentication and identification of personnel. The brain waves are sampled using EEG equipment and are processed using phase-space distribution functions to compare digital signature data from enrollment of authorized individuals to data taken from a test subject to determine if the data from the test subject matches the signature data to a degree to support positive identification. | 2008-11-27 |
20080294908 | Recording Device, Content Key Processing Device, Recording Medium, and Recording Method - A recording device has a content encryption unit for writing a content encrypted with a content key in a recording medium, and a key encryption unit for encrypting the content key and writing the encrypted content key in the recording medium. A content key processing device has a key decryption unit that decrypts the content key that has been encrypted and recorded in a recording medium, and a key encryption unit that re-encrypts the decrypted content key with predetermined information and writes the re-encrypted content key in the recording medium. | 2008-11-27 |
20080294909 | Method for Private Keyword Search on Streaming Data - A method for private keyword searching on streaming data such that the searching does not reveal what keywords are being searched for and does not reveal whether any such keywords have been located nor which documents in the data stream are saved. | 2008-11-27 |
20080294910 | SYSTEM AND METHOD FOR PROTECTING NUMERICAL CONTROL CODES - A system, method, and computer program for protecting numerical control codes, comprising decrypting an encrypted text file that defines how an event for a tool path data set is processed; processing said decrypted text file to obtain a set of instructions; formatting said set of instructions according to a definition file; and outputting said set of formatted instructions; whereby postprocessed machine controls are written and appropriate means and computer-readable instructions. | 2008-11-27 |
20080294911 | Method and Apparatus for Secure Storing of Private Data on User Devices in Telecommunications Networks - A system for securely storing data is provided. The system includes a transformation component operable to scramble or encrypt the data, a dissection component operable to divide the data into a plurality of segments, and a storage component operable to store the plurality of segments in a plurality of memory locations. These components can operate various schemes identified by encoded identifiers and new schemes can be added to the system at any time. A user device can use a combination of a transformation scheme, a dissection scheme, and a storage scheme to protect stored private data at any point in time. The combination can be changed quickly by the user device autonomously or upon receiving an instruction to do so. | 2008-11-27 |
20080294912 | SEMICONDUCTOR MEMORY DEVICE - The present invention provides a semiconductor memory device capable of allocating scrambling data different every chip without the need for management and writing of seed data for scramble. If an authentication key inputted from a user to an authentication key register and a decision key set to a decision key register in advance coincide with each other, then read data RD read from a memory chip is outputted as data DT via a selector as it is. If they are found not to coincide with each other, then read data RD (scrambled data SRD) scrambled using, as seed data SD, position information on each defective memory cell, which is outputted from a fuse circuit, is selected by the selector, followed by being outputted as data DT. | 2008-11-27 |
20080294913 | DISK ARRAY CONTROLLER, DISK ARRAY CONTROL METHOD AND STORAGE SYSTEM - Provided is a disk array controller capable of speeding up the processing by simultaneously execution the encryption/decryption of a non parallel block cipher modes of operation. In a disk array controller for controlling a disk array according to a disk access request from a host system, a plurality of non parallel mode encryption/decryption target data are divided into a plurality of messages unrelated to the encryption/decryption processing, partitioning non parallel mode encryption/decryption target data belonging to the respective messages into a plurality of block data, storing each block data belonging to the respective messages by allocating it each line of Rnd[ | 2008-11-27 |
20080294914 | Trusted storage - In one embodiment, a method for authenticating access to encrypted content on a storage medium, wherein the encrypted content is encrypted according to a full disk encryption (FDE) key, the storage medium including an encrypted version of the FDE key and an encrypted version of a protected storage area (PSA) key, and wherein the encrypted version of the FDE key is encrypted according to the PSA key, the method comprising: providing an authenticated communication channel between a host and a storage engine associated with the storage medium; at the storage engine, receiving a pass code from the host over the authenticated communication channel; hashing the pass code to form a derived key, wherein the encrypted version of the PSA key is encrypted according to the derived key; verifying an authenticity of the pass code; if the pass code is authentic, decrypting the encrypted version of the PSA key to recover the PSA key; decrypting the encrypted FDE key using the recovered PSA key to recover the FDE key; and decrypting the encrypted content using the FDE key. | 2008-11-27 |
20080294915 | ETHERNET INTERFACE - A network adaptor is disclosed that uses Power over Ethernet (PoE) protocols to derive power from an Ethernet port and provide the derived power to a field device. The network adapter communicates analog data with the field device and converts the analog data to digital data using an analog to digital converter before transmitting the digital data through the Ethernet port to a central office. The network adapter is uniquely assigned to the field device allowing an IP address to be assigned to the network adapter/field device system which may be accessed using IP protocols from any suitable browser. | 2008-11-27 |
20080294916 | Dynamic voltage converter topology switching circuit, system, and method for improving light load efficiency - A voltage converter includes a plurality of voltage converter circuits, each voltage converter circuit having a topology, and a control circuit coupled to the voltage converter circuits. The control circuit is operable to select one of the voltage converter circuits to provide an output power on an output node. The control circuit selects one of the voltage converter circuits in response to a parameter associated with the operation of the voltage converter, such as a parameter associated with the output power on the output node. | 2008-11-27 |
20080294917 | Power Management for Power-Over-Ethernet-Capable Switch - A system and method is described that allows a PoE-capable switch to selectively provide power to one or more remote devices in an instance where power being supplied to the switch itself is limited or failing. In one embodiment, the switch receives a notification from an uninterruptable power supply (UPS) and, in response to receiving the notification, selectively provides power to one or more devices powered by the switch. Selectively providing power to one or more of the devices may include providing power to only a subset of the devices, providing a different amount of power to different ones of the devices, or providing power for different durations to different ones of the devices. In an alternate embodiment, in response to receiving the notification, the switch communicates with a remote device and causes the remote device to activate at least one power saving feature. | 2008-11-27 |
20080294918 | POWER SIGNAL MERGING FOR NETWORK INTERFACE DEVICES - Embodiments disclosed herein describe a network interface device including a first powered device controller coupled to first and second power supply lines. A second powered device controller coupled to third and fourth input power supply lines. A dc-dc converter coupled to receive a single signal representing a sum of power signals output by the first and second powered device controllers. | 2008-11-27 |
20080294919 | ETHERNET LOW POWER PARTIAL FUNCTIONALITY COMMUNICATION LINK - Methods and devices for a low power partial functionality communication link having an Ethernet mode of operation and a low power partial functionality mode of operation. The communication link may process only frames containing predefined data types while in the low power partial functionality mode. | 2008-11-27 |
20080294920 | METHOD FOR CONTROLLING ELECTRIC POWER OF COMPUTER SYSTEM - To reduce the electric power consumption of the computer system, the computer system includes at least one server and at least one data processing apparatus, the data processing apparatus includes an electric power consumption state control module by which electric power consumption of the data processing apparatus can be changed, obtains a use relationship between each server and each processing apparatus included in the computer system, monitors a change in a state of the server, searches for a related data processing apparatus in the use relationship with the server, obtains a state of at least one related server in the use relationship with the related data processing apparatus, and determines whether an electric power consumption state of the related data processing apparatus is to be changed or not based on the state of the related server, and changes the electric power consumption state of the related data processing apparatus. | 2008-11-27 |
20080294921 | DATA PROCESSING DEVICE, AND CONTROL METHOD OF DATA PROCESSING DEVICE - A multifunctional device shifts the states of plural reception units from a state that the device operates in a power saving state to a state that the device operates in an operating state, according to which of the plural reception units a reception request of data is input to. The multifunctional device can shorten a time from the reception of the reception request of the data to the reception unit to a start of a data process of the data. | 2008-11-27 |
20080294922 | MATCHING SYSTEM OF ELECTRONIC DEVICE AND PERIPHERAL DEVICE AND MATCHING METHOD THEREOF - A matching system of an electronic device and a peripheral device and a matching method thereof are described. The system includes an electronic device, having an identification mechanism for identifying a specific identification code and generating a control signal or a control instruction according to an identification result; and a peripheral device, electrically coupled to the electronic device selectively. The peripheral device includes an identification code unit for storing a group identification code; and a power control unit, for controlling an operation state of the peripheral device according to the control signal or the control instruction, when the peripheral device is electrically coupled to the electronic device. If the identification result is that the specific identification code is consistent with the group identification code, the power control unit controls the entire peripheral device to work normally according to the control signal or the control instruction. | 2008-11-27 |
20080294923 | SYSTEM AND METHOD FOR INTERFACING AN ELECTRONIC DEVICE WITH A HOST SYSTEM - The invention relates to a system and method for controlling interfacing parameters for a device when connected to a host is provided. The method comprises: monitoring for an initial connection by the device to the host; then, while the device is establishing the connection with the host, utilizing a communication bus controller contained in a microprocessor in the device to process communications with the host at a first data transmission rate; and after a predetermined condition, re-establishing the connection with the host using a second bus controller in the device that processes the communications at a second transmission rate that is higher the first data transmission rate. | 2008-11-27 |
20080294924 | STRUCTURE FOR ANALYZING DYNAMIC CPU VOLTAGE - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a system is disclosed for monitoring a voltage supplied by a voltage regulation module to a processor in response to a dynamic VID generated by the processor. The voltage monitoring system monitors the voltage generated by the voltage regulation module to ensure the supplied voltage is within regulation thresholds. The voltage monitoring system acquires an analog reading of the supplied voltage and converts it to a digital value. If the VID changes during the conversion, the result of the A/D conversion is discarded. If the VID does not change, the voltage monitoring system accepts the result of the A/D conversion and compares the supplied voltage to the voltage expected in response to the VID. The voltage monitoring system may also compute the error between the actual and expected voltage for each accepted A/D conversion. | 2008-11-27 |
20080294925 | SERIAL COMMUNICATION SYSTEM AND SERIAL COMMUNICATION METHOD - In a serial communication system in which data is transmitted from a first unit to a second unit in synchronization with a clock signal, the mode of communication between the first and second units is switched between a first communication mode in which data is transmitted from the second unit to the first unit in synchronization with the clock signal, and a second communication mode in which a signal asynchronous to the clock signal is transmitted from the first unit to the second unit. | 2008-11-27 |
20080294926 | Globally synchronized timestamp value counter - The present invention relates to a synchronized timestamp mechanism in a packet processing system. This synchronized timestamp mechanism provides a globally synchronized counter value so counters located on separate packet processing cards can be synchronized. The synchronizing of these packet processing cards provides tracking of how long it takes for packets to be processed, provides the ability to generate packet headers that include sequence numbers for robust header compression, and allows the use of encryption protocols without a time reference signal. The synchronization is provided by sending the cards with counter value information and this information can be used to update the card's internal counter value information so that the card is synchronized with other cards. | 2008-11-27 |
20080294927 | Method and System for Clock Skew Reduction in Clock Trees - A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value. | 2008-11-27 |
20080294928 | Coarsely controlling memory power states - In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed. | 2008-11-27 |
20080294929 | Data processing apparatus and method for controlling a transfer of payload data over a communication channel - A data processing apparatus and method are provided for controlling a transfer of payload data over a communication channel. The data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data the subject of the transfer in a later clock cycle. A communication channel is provided over which the payload data is passed from the initiator circuitry to the recipient circuitry along with associated transfer control information, timing of receipt of the payload data by the recipient circuitry being controlled by the transfer control information. Timing easing circuitry located within the communication channel is then used to temporarily buffer at least the transfer control information generated by the initiator circuitry before outputting that transfer control information to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered, whereby the number of clock cycles that elapse between the first clock cycle and the later clock cycle is dependent on the specified timing easing value. This hence enables a multi-cycle path to be provided for the transfer of payload data from the initiator circuitry to the recipient circuitry. | 2008-11-27 |
20080294930 | IC CARD WITH LOW PRECISION CLOCK - An IC Card may include electronic components to receive a power supply and a main clock signal by a reader device. The power supply may be provided to a subset of the electronic components during a main clock stop status wherein the main clock signal is suspended for avoiding a maximum power consumption threshold. The IC Card may also include a low precision clock included in the subset of electronic components for measuring time in the main clock stop status. | 2008-11-27 |
20080294931 | Assisted Problem Remediation - A method (which can be computer implemented) for assisted remediation of at least one problem with a computer system includes the steps of obtaining data from the computer system, the data being indicative of the at least one problem; hypothesizing at least a first candidate remediation process for the problem from among a plurality of annotated remediation process descriptions, based at least in part on the data; associating at least a first attribute with the at least first candidate remediation process; and facilitating presentation of the at least first candidate remediation process with the associated attribute to a remediation agent. | 2008-11-27 |
20080294932 | INCREASING SOFTWARE FAULT TOLERANCE BY EMPLOYING SURPRISE-REMOVAL PATHS - The subject invention relates to systems and methods for automatic recovery from errors in a computing environment. A system is provided to facilitate failure recovery in the computing system. The system includes at least one driver component that enumerates at least one layer of a driver stack. A module associated with the driver component requests re-enumeration of the driver stack upon detection of an error in the computing system. When an error is detected by a driver or operating system component, a protocol can be established whereby a new copy of the driver's stack or system resources is re-enumerated in parallel to existing resources that may be in an unknown or error state. The new copy of the stack may allow the driver to become operational in lieu of the previous stack which can be reclaimed for other system uses over time. | 2008-11-27 |
20080294933 | FAIL-OVER METHOD, COMPUTER SYSTEM, MANAGEMENT SERVER, AND BACKUP SERVER SETTING METHOD - A management server obtains configuration information of an active server and creates a logical partition in a backup server so as to correspond to the active server. The backup server starts up the created logical partition. And when the created logical partition reaches a predetermined state, the backup server releases allocation of the first processor resource to the logical partition, thereby the logical partition stands by. The management server, when detecting an error occurred in the active server, stops the active server and searches the logical partition having same configuration as the active server in which error is detected, and enables allocation of the first processor resource to the searched logical partition, thereby completing the start-up of the logical partition. | 2008-11-27 |
20080294934 | Semiconductor memory device having an error correction function and associated method - A semiconductor memory device may include a parity generating circuit, a memory cell array, an error calculating circuit and an error corrector. The parity generating circuit generates parities having different number of bits according to types of a partial array self-refresh mode, and selects one of the parities to output a first parity. The error calculating circuit calculates an error based on a first data corresponding to the input data and a second parity corresponding to the first parity and outputs a first error data. The error corrector corrects the first data based on the first data and the first error data. | 2008-11-27 |
20080294935 | DATA STRUCTURE FOR FLASH MEMORY AND DATA READING/WRITING METHOD THEREOF - A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively. | 2008-11-27 |
20080294936 | SOFTWARE MEMORY LEAK ANALYSIS USING MEMORY ISOLATION - A computerized method, program product, and a service that allocates and isolates leaky memory during the execution of an application in a data processing system. A memory controller having several components first identifies a leaky section of memory and delegates to an allocation component to allocate more memory if possible. If, however, the problematic memory section should not be allocated more memory, an isolator component can isolate the memory section and further divide the memory section into subsections and so on. Each section and each subsection may then be tested to determine if more memory can be allocated, tested to determine if memory resources are strained so as to identify the application or its component causing the strain and then binding the memory. Each section and subsection and further divided and isolated until the leaky portion of memory is identified, and as a result, the software component causing the leak can also be identified. The software component associated with the leaky memory section or subsection can also be taken out-of-service. | 2008-11-27 |
20080294937 | DISTRIBUTED PROCESSING METHOD - According to an aspect of the embodiment provides a method for controlling a processing device for distributing jobs among a plurality of job processing devices for executing the jobs, respectively. The method comprises the steps of: transmitting a job to one of the job processing devices to have the job executed by the one of the job processing devices; generating a procedure information for transmitting a continuation data from the one of the job processing devices before completion of execution of the job back to the processing device, the continuation data enabling another job processing device to continue execution of the job; and transmitting the procedure information to and receiving the continuation data from the one of the job processing devices. | 2008-11-27 |
20080294938 | Semiconductor integrated circuit device having fail-safe mode and memory control method - An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode. | 2008-11-27 |
20080294939 | DEBUGGING DEVICE AND METHOD USING THE LPC/PCI BUS - A debug device include a programmable logic device ( | 2008-11-27 |
20080294940 | METHOD AND DEVICE FOR MANAGING COMPUTING SYSTEM - In a computing system comprising plural processor modules possessing plural processors, plural I/O devices serving as an interface of communication between the plural processor modules and external equipment, and a connection mechanism possessing plural switching units to which the plural processor modules and the plural I/O devices are coupled, the plural switching units possessed by the connection mechanism are managed as a network. In particular, the management information which defines each of plural paths by a line of two or more switching units among the plural switching units is acquired, the path status on the plural paths is grasped by analyzing the acquired management information, and the path status information on the grasped path status is created and outputted. | 2008-11-27 |
20080294941 | Method and System for Test Case Generation - A method and apparatus is described for generating a test case for an application or system modelled using a Stochastic Automata Network model. The method contemplates the inclusion of a plurality of automata and including the steps of: (a) setting an initial global state as the current global state, wherein a global state comprises a set of local states each corresponding to one of the automata; (b) creating a record of the initial global state; (c) selecting an event from a set of events that can be applied to the current global state; creating record of the selected event; (e) identifying those of the automata affected by the selected event and updating the current global state by updating the states of the affected automata; (f) creating a record of the current global state; and repeating steps (c) to (f) until a termination condition is satisfied. The invention may also be used for the generation of test scripts. In terms of specific usage case, the invention may be used for software reliability testing and for fault-tolerance measurements. | 2008-11-27 |
20080294942 | SELF-HEALING SYSTEM AND METHOD - Systems and methods for optimizing performance in a computing environment are provided. The system comprises means for monitoring execution of annotated logic code associated with a software component to determine whether a condition has been satisfied, wherein annotations in the logic code provide one or more details about the software component, the details being useful to a healing agent to correct a problem associated with said condition during the execution of the logic code. | 2008-11-27 |
20080294943 | SATA INTERFACE TESTER AND TESTING METHOD - A serial advanced technology attachment (SATA) interface tester includes a memory, a signal converter, at least one SATA interface, and an indicator. The at least one SATA interface is adapted to connect with SATA interfaces of a motherboard, and is electrically connected to the memory via the signal converter. The signal converter receives serial signals from the motherboard via the at least one SATA interface and converts them to parallel signals and then passes the parallel signals to the memory to perform a writing process. The signal converter receives parallel signals from the memory and converts them to serial signals and passes the serial signals to the motherboard via the at least one SATA interface to perform a reading process. The indicator is electrically connected to the memory for indicating testing result of the SATA interfaces of the motherboard. | 2008-11-27 |
20080294944 | PROCESSOR BUS FOR PERFORMANCE MONITORING WITH DIGESTS - A method for monitoring event occurrences from a plurality of processor units at a centralized location via a dedicated bus coupled between the plurality of processor units and the centralized location. In particular, the method comprises receiving, at the centralized location, data indicative of cumulative events occurring at one of the processor units, and storing the data in a first temporary memory. The data is then stored in a register based on a tag identifier affixed to the data in an instance where the tag identifier provides indicia of one of the plurality of processor units. | 2008-11-27 |
20080294945 | PROGRAM AND METHOD FOR ERROR DETERMINATION, AND ELECTRONIC APPARATUS - There is provided an error determination program executed by an information processor included in an electronic apparatus that includes a device installation section capable of installing any one of a plurality of devices having different formats, a host controller acting as an intermediary between the information processor and the device installed in the device installation section, and a storage circuit storing an error determination information table that includes a plurality of pieces of error determination information for determining a presence or absence of any error in a plurality of responses to a plurality of commands from the devices installable in the device installation section, by associating the pieces of error determination information with a combination of the formats of the installable devices and the commands executable by the devices. The program includes instructing the host controller to issue a desired command in the commands executable by the device installed in the device installation section to the installed device; acquiring the error determination information associated with the combination of the format of the installed device and the desired command from the error determination information table; acquiring response content information regarding a content of a response to the desired command from the installed device from the host controller; and determining the presence or absence of any error in the response based on the error determination information and the response content information. | 2008-11-27 |
20080294946 | System and Method for Problem Determination Using Dependency Graphs and Run-Time Behavior Models - A problem determination system and method reduces the time and effort required by system administrators to trouble shot transaction processing difficulties in a large distributed I/T environment by monitoring system component performance and computing operational performance threshold limits based on dependency graphs for the system. Using this data, a prioritized list of suspect components for the I/T system is generated. | 2008-11-27 |
20080294947 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 2008-11-27 |
20080294948 | Protocol Tester and Method for Performing a Protocol Test - Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for the decoding of data, and an output for providing the decoded data, the protocol tester also comprising a device for measuring the bit error rate. A corresponding method for performing a protocol test is also provided. | 2008-11-27 |
20080294949 | MEMORY ACCESS SYSTEM - When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts. | 2008-11-27 |
20080294950 | DOUBLE DRAM BIT STEERING FOR MULTIPLE ERROR CORRECTIONS - A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits | 2008-11-27 |
20080294951 | Methods and devices for testing computer memory - A method, and a corresponding device, provides for testing computer memory having a number of memory elements. The method includes the steps of initializing each memory element to zero, using a seeded random number generator, determining a random address that corresponds to a start point in the memory range, using the seeded random number generator, writing a random data value to the random address, repeating the two previous steps until all memory elements have been written to with random data values, conducting a refresh test of the memory range, and using the same seeded random number generator and the same written random data values, reading each of the memory elements in the memory range. | 2008-11-27 |
20080294952 | TEST APPARATUS AND DEVICE - It is aimed to efficiently test devices that can transfer data at a very high bit rate. A test apparatus for testing a device under test includes a capture memory that stores thereon an output pattern received from the device under test, a header detecting section that reads the output pattern from the capture memory and detects a portion matching a predetermined header pattern in the output pattern, and a judging section that judges whether the output pattern is acceptable based on a result of comparison between a pattern, in the output pattern, which starts with the portion matching the predetermined header pattern and a corresponding expected value pattern. | 2008-11-27 |
20080294953 | Removing the effects of unknown test values from compacted test responses - Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the compacted test response includes one or more compacted test response values that are dependent on one or more respective unknown values. The compacted test response is filtered to remove the dependency of at least some of the compacted test response values on the one or more respective unknown values, and a filtered test response is output. Various filtering circuits and testing systems are also disclosed. | 2008-11-27 |
20080294954 | SYSTEM, METHOD AND PROGRAM FOR PROCESSING READ ERROR - A system for processing a data read error from a tape medium in one embodiment includes a reading section for reading data in data units from a tape medium; a reading control section for controlling said reading section to read data, and on condition that if an error occurs in reading one of said data units, the data unit where the error occurs is considered an error data unit and the reading control section issues an instruction to skip the error data unit and read the next readable data unit immediately after the error data unit; a computation section for computing a number of records and a number of boundary marks included in the error data unit where said error occurs from information about the records and boundary marks included in the data unit preceding the error data unit that is read immediately before said error occurs, and information about the records and boundary marks included in the data unit next to said error data unit, the boundary marks indicating the boundary of a record block; and a communication section for outputting the number information about said computed number of records and said computed number of boundary marks. | 2008-11-27 |
20080294955 | Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time. | 2008-11-27 |
20080294956 | Encryption Via Induced Unweighted Errors - A method for encrypting data is provided. The method includes formatting data represented in a weighted number system into data blocks. The method also includes converting the data blocks into a residue number system representation. The method further includes generating a first error generating sequence and inducing errors int he data blocks after converting the data blocks into a residue number system representation. It should be understood that the errors are induced in the data blocks by using the first error generating sequence. After inducing errors into the data blocks, the data of the data blocks is formatted into a form to be sorted or transmitted. The method also includes generating a second error generating sequence synchronized with and identical to the first error generating sequence and correcting the errors in the data blocks using an operation which is an arithmetic of a process used in inducing errors. | 2008-11-27 |
20080294957 | Communication Apparatus - A communication apparatus for converting signal between differential interchange circuit and multiple devices having input and output terminals comprising:
| 2008-11-27 |
20080294958 | Method of Transmitting Control Information in Wireless Communication System and Transmission Window Updating Method Using the Same - A method of transmitting control information in a wireless communication system and transmission window updating method using the same are disclosed, by which transmission efficiency in a transmitting side can be enhanced. The present invention includes the steps of receiving a first control information block including a first status report information from a receiving side, the first status information providing reception acknowledge information for a plurality of data blocks transmitted to the receiving side, receiving a second control information block including a second status report information placed as a last status report information in the second control information block, and updating the transmission window using the reception acknowledge information in the first status report information. | 2008-11-27 |
20080294959 | Decoder - An H-ARQ system wherein the transmission of two consecutive, or sequential, blocks of information bits are considered jointly; i.e., one of the blocks of information being embedded within the other one of the blocks of information. If a retransmission for the first block is necessary, the system processes both blocks jointly. The system is provided with cross-packet coding which extends current H-ARQ schemes for point-to-point communications wherein the transmission of two consecutive block of information bits is considered jointly. If a retransmission for the first block is necessary, the system processes both blocks jointly. This allows both blocks to be decoded without errors at the receiver after the retransmission. | 2008-11-27 |
20080294960 | MEMORY-EFFICIENT LDPC DECODING - To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes. | 2008-11-27 |
20080294961 | Method and apparatus for reading data - A reading apparatus reads data from a storage device based on which an error correcting code is to be generated. An error determining unit reads the data from the storage device, and determines whether a read error has occurred in the data. A reading unit re-reads, when the error determining unit determines that a read error has occurred in the data, the same data from the storage device. | 2008-11-27 |
20080294962 | Efficient Encoding/Decoding of a Sequence of Data Frames - Encoding data by first performing a transformation of predicted data and input data, and then performing a subtraction of the resulting outputs. In an embodiment, the prediction approach is chosen such that fewer elements of different values (compared to a number of elements in the input data) are generated, and the different values are generated in a predictable position. The transformation approach is chosen such that the output expressly represents variations in the input data as well as satisfies a distributive property. The decoding may be performed based on the same concepts. As a result, the data can be encoded and/or decoded efficiently. | 2008-11-27 |
20080294963 | METHOD AND APPARATUS FOR DESIGNING LOW DENSITY PARITY CHECK CODE WITH MULTIPLE CODE RATES, AND INFORMATION STORAGE MEDIUM THEREOF - A method and apparatus for generating a low density parity check (LDPC) code having a variable code rate, the method of generating the LDPC code having a variable code rate including: generating a first parity check matrix by combining a parity matrix or a parity check matrix and a first information word matrix; and generating a second parity check matrix by combining the first parity check matrix and a second information word matrix. According to the method and apparatus, error correction performance is enhanced. | 2008-11-27 |
20080294964 | SERIAL CONCATENATION OF INTERLEAVED CONVOLUTIONAL CODES FORMING TURBO-LIKE CODES - A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one. | 2008-11-27 |
20080294965 | Data Writing Method For Flash Memory and Error Correction Encoding/Decoding Method Thereof - A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (2 | 2008-11-27 |
20080294966 | DATA TRANSMISSION APPARATUS, DATA TRANSMISSION DEVICE, DATA RECEPTION DEVICE AND DATA TRANSMISSION SYSTEM - A data transmission apparatus includes a packet generation section, a frame encoding section, a transmission section, a reception section, a frame decoding section and a packet extraction section. The packet generation section generates a packet upon request. The frame encoding section generates a frame having a predetermined length by dividing the packet or adding dummy data to the packet and generates an error-correcting-code-added frame by adding an error correcting code to the frame. The transmission section transmits the generated error-correcting-code-added frame through a transmission line. The reception section receives the error-correcting-code-added frame. The frame decoding section performs an error detection and an error correction for the error-correcting-code-added frame. The packet extraction section extracts the packet by removing the error correcting code from the error-correcting-code-added frame for which the error detection and the error correction have been performed. | 2008-11-27 |
20080294967 | Incremental Redundancy Coding System - In packet digital communications using a two way communications medium such as wireless each received packet is subject to noise and/or interference which causes errors in some of the received symbols. A common method known as Incremental Redundancy (IR), Hybrid Automatic Repeat Request (HARQ) for corrects these transmission errors by using error detection in conjunction with transmission of additional redundant symbols forming a sequence of forward error correcting codes. Any residual errors are detected by means of a Cyclic Redundancy Check (CRC). The CRC symbols represent transmission overhead and degrade the throughput regardless of the quality of the transmission channel. This invention is concerned with providing error detection without the need for a CRC thereby improving the throughput. In a further embodiment of the invention for those systems that employ a CRC increased reliability of detection is provided which also leads to an improvement in throughput. It is shown that by adjustment of a simple threshold value, the overall packet error rate may be traded off against throughput in a flexible manner. A method of construction of a sequence of codes from a nested block code is described and an example is provided based on a nested block code of length 128. The associated performance graphs of the invention, both using and not using a CRC, for this sequence of codes are given showing the performance improvements of the invention compared to the standard arrangement using a CRC for the same sequence of error correcting codes. | 2008-11-27 |
20080294968 | Ultra High-Speed Optical Transmission Based on LDPC-Coded Modulation and Coherent Detection for All-Optical Network - An optical communication system includes a bit-interleaved coded modulation (BICM) coder; and a low-density parity-check (LDPC) coder coupled to the BICM coder to generate codes used as component codes and in combination with a coherent detector. | 2008-11-27 |
20080294969 | RATE-COMPATIBLE PROTOGRAPH LDPC CODE FAMILIES WITH LINEAR MINIMUM DISTANCE - Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero. LDPC codes built from the protographs created by these methods can simultaneously have low error floors and low iterative decoding thresholds, and families of such codes of different rates can be decoded efficiently using a common decoding architecture. | 2008-11-27 |
20080294970 | Method for implementing stochastic equality nodes - The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state. | 2008-11-27 |
20080294971 | TRANSPARENT ENVELOPE FOR XML MESSAGES - Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination. | 2008-11-27 |
20080294972 | SYSTEM AND METHOD FOR ADDING A LAYER OF MARKS ON TOP OF WEB-PAGES - A system and method to put graphical marks such as post-it style notes, stickers and bookmarks on top of web pages is disclosed. | 2008-11-27 |
20080294973 | SYSTEM AND METHOD FOR GENERATING DOCUMENTS FROM MULTIPLE IMAGE OVERLAYS - The subject application is directed to a system and method for construction of layered documents, such as advertisements, educational materials, graphic designs, and the like. In multiple image data files generated, for example, by scanning multiple document pages, a user is capable of selecting a color in a particular page, or region of a page, to be eliminated. A user is further capable of selecting a tint level associated with a corresponding image data file, such as, for example, 0%, 50%, and the like. Once desired color transparency data and tint level data are selected, a document processing device generates a composite image by superimposition of each of the image data files. The composite image is generated in accordance with the overlay order designated by the user. A tangible, humanly cognizable document is then generated by the document processing device. | 2008-11-27 |
20080294974 | WEBPAGE HISTORY VIEW - A system and method of selecting a web page from a plurality of web pages, wherein the plurality of web pages are represented using a plurality of thumbnails is provided. In addition, the plurality of web pages can comprise previously visited web pages and previewed web pages. The system and method further provides a visual indicator that is either displayed by default upon the selection of the web page or is drawn by a user. The visual indicator substantially encompasses a desired portion of the selected web page for initial viewing upon loading or re-loading of the selected web page. Alternatively, the visual indicator can be positioned so that at a predetermined proximity to a desired portion of the web page, the desired portion of the web page is focused on for initial viewing. Remaining portions of the selected web page not encompassed by the visual indicator are not initially displayed. | 2008-11-27 |
20080294975 | SELECTABLE REVELATION OF CONTENT ATTRIBUTES FOR A HYPERLINK - Embodiments of the present invention address deficiencies of the art in respect to attribute revelation for a hyperlinked selection and provide a novel and non-obvious method, system and computer program product for user customizable hyperlink hover properties. In an embodiment of the invention, a method for selectable revelation of content attributes for a hyperlink can be provided. The method can include detecting a proximity event for a hyperlink referencing content including multiple attribute values for respective attributes. The method also can include retrieving hover properties for the hyperlink including a subset of the attributes. The method even also can include selecting a subset of attribute values corresponding to the subset of attributes. Finally, the method can include displaying the subset of attributes in a popup box for the hyperlink. | 2008-11-27 |
20080294976 | System and method for generating and communicating digital documents - A document may be sent to a virtual printer which may be a software module configured as a print driver to receive the printer file, retrieve further information from a data repository, and produce a file including both the document image and additional information. The software module may further transmit the document to a central hub, from which it may be further processed and/or transmitted to an intended recipient. | 2008-11-27 |
20080294977 | METHOD AND APPARATUS FOR CREATION, PERSONALIZATION, AND FULFILLMENT OF GREETING CARDS WITH GIFT CARDS - An automated fulfillment system enables gift cards to be embedded or sent along with personalized greeting cards. The present invention, a method, system and apparatus enables a person to 1) purchase a gift card from either a Internet Website, Catalog, and/or retail kiosk, 2) choose a retail quality greeting card, 3) personalize the greeting card, and 4) send the personalized greeting cards as a gift with a gift card embedded inside the greeting card. The reverse is also possible, i.e. a user can purchase a greeting card, personalize the greeting card, and then assign that greeting card to have a gift card inserted inside therein. | 2008-11-27 |
20080294978 | SEMANTIC NAVIGATION THROUGH WEB CONTENT AND COLLECTIONS OF DOCUMENTS - The present invention provides method and apparatus, including computer program products, A method for marking-up a plurality of electronic documents, comprising: semantic marking-up electronic documents according to a predetermined domain model presented in the form of domain ontology, thereby creating mark-up results represented in Ontology Web Language, OWL, format; and storing the mark-up results and the links to the marked-up electronic documents represented by Universal Resource Locators, URLs, in a Resource Description Framework, RDF, storage. | 2008-11-27 |
20080294979 | PRESENTING MULTIMODAL WEB PAGE CONTENT ON SEQUENTIAL MULTIMODE DEVICES - A method of accessing an Extensible Hypertext Markup Language Plus Voice Web page can include the step of receiving a request for an Extensible Hypertext Markup Language Plus Voice Web page from a source that lacks the ability to directly render the Web page. The Web page can be segmented into a multitude of fragments, where each fragment can consist of a single interface category, such as a graphical user interface category or a voice category. These fragments can be used to provide the requesting source with information from the Web page. | 2008-11-27 |
20080294980 | Methods and Devices for Compressing and Decompressing Structured Documents - The invention relates to a method of compressing a structured document having a tree-like structure comprising elements nested in each other, each element comprising attributes and a value field which may comprise other elements, the method comprising defining a simplified type comprising only a part of attributes of an original type, and for each element of the original type, replacing the type identifier in the element with an identifier of the simplified type when the element differs from a previous element having the original type only in the attribute values or presences of the simplified type attributes. | 2008-11-27 |
20080294981 | Page clipping tool for digital publications - Systems, methods, graphical user interface and other implementations are disclosed for capturing, saving, managing, and processing a plurality of sections of content of interest (e.g. page clippings) of a page or a plurality of pages from one or more digital publications based on the semantics of the content selected and or descriptive metadata attributes associated with the content selected and or semantically-rich description of information selected and or a combination thereof. The invention also consisting of user interface elements (e.g. publication components) that incorporate one or more tools (e.g. applications) that let the user perform specific tasks on the stored page clippings. | 2008-11-27 |