48th week of 2008 patent applcation highlights part 19 |
Patent application number | Title | Published |
20080290874 | APPLICATIONS OF WIDEBAND EM MEASUREMENTS FOR DETERMINING RESERVOIR FORMATION PROPERTIES - A method for determining reservoir formation properties that consists of exciting the reservoir formation with an electromagnetic exciting field, measuring an electromagnetic signal produced by the electromagnetic exciting field in the reservoir formation, extracting from the measured electromagnetic signal a spectral complex resistivity as a function of frequency, fitting the spectral complex resistivity with an induced polarization model and deducing the reservoir formation properties from the fitting with the induced polarization model. | 2008-11-27 |
20080290875 | Seismic activity detector - A system for detecting precursor seismic electromagnetic waveforms. | 2008-11-27 |
20080290876 | Method of characterizing hydrocarbon reservoir fractures in situ with artificially enhanced magnetic anisotropy - Reservoir fractures are characterized directly in situ without need to acquire and analyze formation sample cores. A magnetic fluid is injected into an isolated section of the reservoir. The magnitude and directional properties of the enhanced magnetic susceptibility in the section where magnetic fluid injection occurs is measured with a down hole magnetometer. Logs obtained of the enhanced magnetic susceptibility are analyzed to characterize fractures, and petrophysical properties of interest, such as porosity, permeability, and permeability anisotropy of the formation in the vicinity of the fluid injection. | 2008-11-27 |
20080290877 | Apparatus and Method of Testing for Battery - The present invention relates to an apparatus and method for testing batteries, which can prevent errors from occurring due to the tolerance of voltage sensors when the charged states of batteries are measured, and can charge a battery having a charged state deteriorated due to the difference in the resistance of each battery. The apparatus includes a voltage circuit for measuring voltages of N batteries. A resistance circuit decreases voltages of batteries, which are greater than a reference voltage. A connection switch unit selects any one of the N batteries. A divert change unit separates polarities of each battery and changes positions of an cathode and a anode of the battery depending on separated polarities. A selection switch unit selectively connects the cathode and anode of the battery to an cathode and a anode of the voltage circuit or the resistance circuit. | 2008-11-27 |
20080290878 | Ic Testing Methods and Apparatus - A testing circuit has a shift register circuit ( | 2008-11-27 |
20080290879 | CAPACITIVE MEASUREMENTS WITH FAST RECOVERY CURRENT RETURN - An apparatus and method for measuring the leakage current of capacitive components. A switch that grounds a terminal of a component being tested is closed while the component is charged to a desired test voltage. When this charging is complete, the switch opens so that the diode terminal is at the same potential as the input amplifier's virtual ground. An accurate and fast measurement of the leakage current of the component can be measured. | 2008-11-27 |
20080290880 | Network Analyzer Comprising a Switchable Measuring Bridge - The invention relates to a network analyzer comprising a signal generator for generating an excitation signal which can be supplied to a measuring object connectable to a network analyzer by means of a measuring line, and a measuring bridge which is connected to the measuring line by means of signal transmission. A reference signal corresponding to the excitation signal can be extracted from a reference channel, and a measuring signal corresponding to a signal corresponding to a signal reflected from the measuring object can be extracted from a measuring channel. the measuring bridge comprises a resistive bridge and at least one hybrid coupler which is connected to the resistive bridge in series. the measuring bridge is operated as a resistive bridge in a low frequency range and as a hybrid coupler in a upper frequency range. | 2008-11-27 |
20080290881 | Wafer edge detection and capacitive probe therefor - A wafer edge detection system comprising a probe assembly having one or more capacitive plates conforming in edge shape to an edge shape of a wafer; and processing electronics for electronically driving the one or more capacitive plates and for sensing an electrical signal representing capacitance between each one or more plates and the wafer. Filtering and demodulation techniques enhance the signal to noise ratio. | 2008-11-27 |
20080290882 | PROBE NEEDLE PROTECTION METHOD FOR HIGH CURRENT PROBE TESTING OF POWER DEVICES - A test system, apparatus and method for applying high current test stimuli to a semiconductor device in wafer or chip form includes a plurality of probes for electrically coupling to respective contact points on the semiconductor device, a plurality of current limiters electrically coupled to respective ones of the plurality of probes, and a current sensor electrically coupled to the plurality of probes. The current limiters are operative to limit current flow passing through a respective probe, and the current sensor is operative to provide a signal when detected current in any contact of the plurality of probes exceeds a threshold level. | 2008-11-27 |
20080290883 | Testboard with ZIF connectors, method of assembling, integrated circuit test system and test method introduced by the same - This invention discloses a test board with detachably adjustable ZIF connectors. The test board comprises a test substrate, a plurality of ZIF connectors and a plurality of detachably adjustable fastening means for assembling and disassembling the ZIF connectors on the test substrate. The test substrate has a first surface, a second surface and a plurality of first through-holes perpendicular to the first surface. Pairs of first electrical pads are provided on the first surface adjacent to both sides of first through-holes. A plurality of second electrical pads are provided on the second surface of the test substrate for electrically connecting the first electrical pads. The ZIF connectors are arranged on the first surface of the substrate. Each ZIF connector has a plurality of parallel second through-holes arranged from the top to the bottom of the connector and pairs of electrical terminals are disposed on the bottom of each ZIF connector for contacting the first electrical pads of the test substrate. The detachably adjustable fastening means are disposed through the first and second through-holes to assembling and disassembling the ZIF connectors on the first surface of the substrate. | 2008-11-27 |
20080290884 | Probe card assembly with ZIF connectors, method of assembling, wafer testing system and wafer testing method introduced by the same - This invention discloses a probe card assembly with adjustable ZIF connectors. The probe card assembly comprises a substrate, a plurality of ZIF connectors and a plurality of adjustable fastening means for assembling and disassembling the ZIF connectors on the substrate. The substrate is a disc-like plate, having a first surface, a second surface, a plurality of concave sections disposed on the second surface and a plurality of first through holes perpendicular to the first surface. The first through holes are circularly arranged toward the substrate center. Pairs of first contacts are provided on the first surface adjacent to both sides of first through holes. A plurality of terminals are protruded from the second surface of the substrate for contacting and testing the wafer. The ZIF connectors are also circularly arranged toward the substrate center. Each ZIF connector has parallelly arranged second through holes from the top to the bottom of the connector and pairs of contact terminals for contacting the first contacts of the substrate. The adjustable fastening means are disposed from the concave section through the first and second through holes to assembling and disassembling the ZIF connectors on the first surface of the substrate. | 2008-11-27 |
20080290885 | Probe test system and method for testing a semiconductor package - In a method and system for testing a device under test (DUT), a replaceable test connector (RTC) is disposed between a probe pin of a tester and the DUT. The RTC includes an upper test bond pad that is electrically coupled to a lower test bond pad. The probe pin is capable of being positioned to make a physical contact with the upper test bond pad, the physical contact enabling an electrical coupling there between. The lower test bond pad is capable of being positioned to make physical contact with a device bond pad of the DUT, the physical contact enabling an electrical coupling between the lower test bond pad and the device bond pad. The device bond pad is protected from potential damage from the probe pin by the RTC that is replaceable. | 2008-11-27 |
20080290886 | PROBE APPARATUS - A prove apparatus includes a first and a second loading port for mounting therein two carriers facing each other, a wafer transfer mechanism having a rotation center between the loading ports, and a first and a second inspection unit being symmetrical to each other and disposed in accordance with the arrangement of the loading ports. In this configuration, wafers are directly transferred between the carrier and a wafer chuck of the inspection unit by the wafer transfer mechanism. The wafer transfer mechanism has three arms for unloading two wafers from the carrier. The prove apparatus has a compact size and achieves a high throughput. | 2008-11-27 |
20080290887 | Testing method for semiconductor device having ball-shaped external electrode - Disclosed is a method of testing electrical characteristics of a semiconductor device having a ball-shaped external electrode. The method comprises preparing a plurality of cantilever-type contactors each supported by a support plate at a given position, and formed in such a manner that a tip thereof has a flat surface with an arc-shaped edge in an outer peripheral region thereof, and a cross-sectional diameter in a vicinity of the tip is greater than a radius of the ball-shaped external electrode, and pairing the cantilever-type contactors to provide paired two contactors. The method includes the steps of: pressing either one of the support plate and the semiconductor device toward the other in such a manner that the arc-shaped edges of the paired two contactors are brought into contact with respective ones of two surface regions of the ball-shaped external electrode divided by an axis of the ball-shaped external electrode passing through a middle point between the two positions where the paired two contactors are supported, so as to form Kelvin contacts; and further overly driving either one of the support plate and the semiconductor device relative to the other in such a manner that the arc-shaped edges of the paired two contactors are slidingly moved along respective ones of the two surface regions of the ball-shaped external electrode to perform a wiping operation. | 2008-11-27 |
20080290888 | PROBE SUBSTRATE FOR TEST AND MANUFACTURING METHOD THEREOF - A probe substrate includes a probe having a plurality of beams and a contactor formed at one end of the beam, and a support substrate for supporting the probe and having a bending space in which the probe moves upwards and downwards. The beam and the contactor are made of the same metal, and the sidewall of the contactor has a staircase configuration. Therefore, the probe substrate and the manufacturing method thereof repeats the lithographic process and the plating process to form the probe having the beam and the contactor combined, thereby increasing the bending degree and structural stability of the probe. | 2008-11-27 |
20080290889 | Method of destructive testing the dielectric layer of a semiconductor wafer or sample - In a method of testing a semiconductor wafer or sample having a dielectric layer overlaying a substrate of semiconducting material, a contact is caused to touch a top surface of the dielectric layer. At least a portion of the contact touching the dielectric layer is formed of iridium. A controlled electrical stimulus that causes the dielectric layer to breakdown and an electrically conductive path to form through the dielectric layer is applied to the contact touching the top surface of the dielectric layer. Either a value of the controlled electrical stimulus where breakdown of the dielectric layer occurs or a time for the breakdown of the dielectric layer to occur in response to the application of the controlled electrical stimulus is determined. From the thus determined value or time, a determination can be made whether the dielectric layer is within acceptable tolerance. | 2008-11-27 |
20080290890 | TESTING SYSTEM FOR TESTING ELECTRONIC ASSEMBLY - A testing system for testing performance of a number of image sensor modules includes a data transforms module, a number of selection switches and a testing processor. The data transform module has a pin assembly corresponding to the input/output pin assembly. The pin assembly includes a first pin and a second pin. The selection switches are configured for selecting the high level signal or the low level signal and providing the signal level to the control signal pins of the electronic assemblies. The testing processor is electronically connected to the data transform module and configured for processing data from the data transform module. In testing, the image sensor modules coupled together through a base do not need to be separated from each other, thus facilitating the next process. Therefore, the failure rate of the image sensor modules is decreased and cost is reduced. | 2008-11-27 |
20080290891 | METHOD OF PERFORMING PARALLEL TEST ON SEMICONDUCTOR DEVICES BY DIVIDING VOLTAGE SUPPLY UNIT - Provided is a method of performing a parallel test on semiconductor devices, the method including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test. | 2008-11-27 |
20080290892 | EVALUATION DEVICE AND EVALUATION METHOD USING EVALUATION DEVICE - In an evaluation device a plurality of evaluation cells, a signal wiring for applying a voltage to the evaluation cells, and an output terminal pad for a signal taking out wiring for measuring outputs from the evaluation cells through a signal taking out wiring are provided on an insulating substrate. Thus, the in-plane distribution of electric characteristics can be easily measured. Further, the electric characteristics related to the particle diameter of the crystal of a poly-crystal silicon film are evaluated so that the in-plane unevenness of the particle diameter of the crystal of the poly-crystal silicon film can be managed. | 2008-11-27 |
20080290893 | LOCAL CLOCK BUFFER (LCB) WITH ASYMMETRIC INDUCTIVE PEAKING - A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (V | 2008-11-27 |
20080290894 | ON DIE TERMINATION (ODT) CIRCUIT HAVING IMPROVED HIGH FREQUENCY PERFORMANCE - An On Die Termination (ODT) circuit for performing an ODT operation. The ODT circuit includes a resistor having a first end to receive an ODT enable signal; and a switch unit coupled to a second end of the resistor. The ODT operation is performed in response to the ODT enable signal passing through the resistor. | 2008-11-27 |
20080290895 | SYSTEM AND METHOD FOR LOCAL GENERATION OF PROGRAMMING DATA IN A PROGRAMABLE DEVICE - An apparatus for and method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions. The method comprises the steps of receiving initial programming data for programming the plurality of serially connected programmable logic regions and receiving transformation data related to the presence and location of at least one faulty serially connected programmable logic region. The method also comprises the steps of generating bypass programming data which, in use, renders a serially connected programmable logic region logically invisible and generating effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data. Finally, the method comprises the step of programming the programmable logic device using the effective programming data such that the at least one faulty serially connected programmable logic region is programmed with the bypass programming data. | 2008-11-27 |
20080290896 | System and Method for Dynamically Executing a Function in a Programmable Logic Array - A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR | 2008-11-27 |
20080290897 | PROGRAMMABLE LOGIC DEVICE HAVING LOGIC MODULES WITH IMPROVED REGISTER CAPABILITIES - A PLD that has more flip flops per logic module by providing more registered outputs than combinational outputs; and/or a combinational output that can drive more than one register is disclosed. The PLD includes a plurality of logic array blocks arranged in an array and a plurality of inter-logic array block lines interconnecting the logic array blocks of the array. At least one of the logic array blocks includes at least one logic module that includes a first combinational element configured to generate a first combinational output signal in response to inputs provided to the one logic module, a first register capable of being driven by the first combinational output signal and a second register capable of being driven by the first combinational output signal. The logic module therefore has more registered outputs than combinational outputs and a combinational output that can drive more then one output register. In alternative embodiments, the logic module may have one or more combinational element configured to generate one or more combinational output signals in response to inputs provided to the one logic module and a plurality of registers capable of being driven by the one or more combinational outputs signals. In these alternative embodiments, the number of registers exceeds the number of combinational output signals in the one logic module. | 2008-11-27 |
20080290898 | PROGRAMMABLE LOGIC DEVICE HAVING COMPLEX LOGIC BLOCKS WITH IMPROVED LOGIC CELL FUNCTIONALITY - A CLB-based PLD with logic cells having improved logic, register, arithmetic, logic packing and timing functions and capabilities is disclosed. The CLBs of the PLD are arranged in rows and columns of an array and are interconnect by a plurality of interconnect lines. Each of the plurality of CLBs has a first slice of logic cells and a second slice of logic cells arranged in a first column and a second column. First and second carry chains are provided between each of the logic cells of each column. At least one of the logic cells includes one or more Look Up Tables for implanting logic functions on a set of inputs provided to the one logic cell and an arithmetic logic circuit configured to receive a carry-in signal and to generate a carry-out signal forming part of the first carry chain. In one embodiment, the logic cell further includes a first output register and a second output register and the set of outputs generated by the logic cell are partitioned among the first output register and the second output register. In another embodiment, an output of one of the registers is provided as an input to one of the Look Up Tables of the cell through a register feedback connection. In yet another embodiment, the set of inputs provided to a first and a second of the Look Up Tables are different, enabling a higher degree of logic efficiency or “packing” by enabling each cell to perform logic functions on two different sets of inputs as opposed to only the same set of inputs. Finally, in another embodiment, the arithmetic logic circuit is capable of generating two SUM output signals. | 2008-11-27 |
20080290899 | Integrated circuit and method of detecting a signal edge transition - The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level. | 2008-11-27 |
20080290900 | Two-Stage Level Shifting Module - For raising low voltage levels of a voltage range without over-broadening the voltage range, a first stage voltage level shifting circuit, which is capable of raising an upper bound of its input voltage range, is coupled to a second voltage level shifting circuit, which is capable of raising both an upper bound and a lower bound of its input voltage range. Therefore, a two-stage voltage level shifting module, which is generated by coupling the first voltage level shifting circuit to the second voltage level shifting circuit, is capable of providing appropriate voltages for external I/O devices having different biasing voltage ranges, where an upper bound and a lower bound of each of the provided biasing voltage ranges precisely indicates a digital logic 0 or a digital logic 1 indicated by a digital signal. | 2008-11-27 |
20080290901 | Voltage Shifter Circuit - The present invention provides a voltage shifter circuit, in which a control circuit is used to control the pull-up circuit, so that the pull-up circuit is kept as off when the signal from the input signal source changes from a low voltage to a high voltage. Hence, the competition between the pull-up circuit and the pull-down circuit is avoided. The speed of the voltage shifter circuit is improved and the voltage shifter circuit can operate within a wider voltage range. The delay time of the pull-up circuit and the pull-down circuit is small and the duty cycle is small. In addition, since no direct current path is established, no current is wasted. Additionally, the voltage shifter circuit uses the second delayer to compensate the delay time between the pull-up circuit and the pull-down circuit and optimizes the duty cycle. | 2008-11-27 |
20080290902 | LEVEL CONVERTER - A level converter comprising an input circuit, coupled to a low power source and a first high power source, which generates a complementary first signal and second signal; and a shift circuit that outputs an output signal generated by shifting a voltage level of the input signal, the shift circuit including: a latch circuit having: a first inverter circuit provided in a first path between a second high power source and the low power source; and a second inverter circuit provided in a second path between the second high power source and the low power source, wherein the latch circuit is formed by coupling an input terminal and an output terminal of the first inverter circuit and the second inverter circuit; a first transistor coupled to the first path; and a second transistor coupled to the second path. | 2008-11-27 |
20080290903 | METHOD AND RADIATION HARDENED PHASE FREQUENCY DETECTOR FOR IMPLEMENTING ENHANCED RADIATION IMMUNITY PERFORMANCE - A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD. | 2008-11-27 |
20080290904 | Frequency Monitor - A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step. | 2008-11-27 |
20080290905 | Peak or Zero Current Comparator - The present invention relates to a simple and small-sized circuit configuration ( | 2008-11-27 |
20080290906 | CONSTANT-CURRENT DRIVING CIRCUIT - A constant-current driving circuit includes a first current source, a reference voltage generating circuit and an output signal generating circuit. A terminal of the first current source is coupled to a terminal of a first LED string, wherein the terminal of the first current source has a first voltage. The reference voltage generating circuit is used for generating a reference voltage and comparing the first voltage with a first predetermined voltage to generate a first comparing signal to thereby adjust the reference voltage. The output signal generating circuit is used for outputting an output signal to another terminal of the first LED string and receiving the input signal, wherein the output signal generating circuit decides whether or not to output the input signal serving as the output signal according to the comparison result of the reference voltage with the second voltage. | 2008-11-27 |
20080290907 | THRESHOLD CONTROL CIRCUITRY FOR MULTIPLE CURRENT SIGNAL RECEIVERS - Calibration circuitry and method for maintaining constant signal detection thresholds for multiple signal receivers that receive data signals in the form of current signals. A value of one of the incoming current signals having a predetermined signal pattern is detected and used to generate threshold control signals for each of the signal receivers to control the data signal detection thresholds. | 2008-11-27 |
20080290908 | Variable Power Write Driver Circuit - A storage system (e.g., a magnetic disk system or a magnetic tape system) employing a write head, a write controller and a write driver circuit. In operation, the write head records data on a magnetic media (e.g., a magnetic tape or a magnetic disk) based on a flow of a write current through the write head, and the write driver circuit includes a variable power supply network and a variable power return network driving the write current through the write head based on a selection by the write controller of an operating power mode among a plurality of selectable power modes of the variable power supply network and the variable power return network. Each power mode of the variable power supply network and the variable power return network drives the write current with a different magnitude from the variable power supply network through the write head to the variable power return network. | 2008-11-27 |
20080290909 | Source driver in liquid crystal display device, output buffer included in the source driver, and method of operating the output buffer - Provided is an output buffer, which may be included in a source driver of a liquid crystal display (LCD) device. The output buffer may include a differential amplification unit and an output unit. The differential amplification unit may generate control currents by amplifying the difference between the voltages of an analog image signal and a signal output from the output buffer. The output unit outputs the amplified analog image signal in response to the control currents. The amount of bias current used to drive the differential amplification unit increases during a charge recycling period, and the amount of quiescent current flowing through the output unit decreases during the charge recycling period. The amount of the bias current used to drive the differential amplification unit decreases during a driving period, and the amount of the quiescent current flowing through the output unit increases during the driving period. | 2008-11-27 |
20080290910 | METHOD AND APPARATUS FOR A VOLTAGE TRIGGERED CURRENT SINK CIRCUIT - A current sink circuit is disclosed. An apparatus according to aspects of the present invention includes a sensing element, a pass element coupled to the sensing element and a setting element coupled to the pass element. The setting element provides both a voltage threshold level and a current regulation reference. The pass element is to pass current conducted through the current sink circuit in response to the setting element. The current conducted through the current sink circuit is substantially zero when a voltage applied across the current sink circuit is below the voltage threshold level. A signal generated by the sensing element is regulated in response to the current regulation reference by regulating a current conducted through the pass element when a voltage applied across the current sink circuit is above the voltage threshold level. | 2008-11-27 |
20080290911 | MOSFET gate drive with reduced power loss - A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition. | 2008-11-27 |
20080290912 | ANALOG PSEUDO RANDOM BIT SEQUENCE GENERATOR - A Pseudo Random Bit Sequence (PRBS) generator is provided with components to enable operation at very high microwave frequencies with inexpensive components. The PRBS generator initially replaces the D flip-flops of a conventional PRBS generator with delay lines connected in a similar manner. Further, an exclusive OR (EXOR) gate used in a conventional device is replaced in one embodiment by a mixer and amplifier. In another embodiment, the EXOR gate is replaced by a Gilbert Cell. In some embodiments, complementary outputs of an EXOR gate are connected to separate delay lines to reduce components needed for the PRBS generator. | 2008-11-27 |
20080290913 | CLOCK SIGNAL SWITCHING DEVICE, CLOCK SIGNAL SWITCHING METHOD, DATA BUS SWITCHING DEVICE, AND DATA BUS SWITCHING METHOD - A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals. | 2008-11-27 |
20080290914 | Self-Clearing Asynchronous Interrupt Edge Detect Latching Register - A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one. | 2008-11-27 |
20080290915 | SYSTEM AND METHOD FOR FAST RE-LOCKING OF A PHASE LOCKED LOOP CIRCUIT - A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles. | 2008-11-27 |
20080290916 | System Clock Generation Circuit - A system clock signal generator circuit comprising a first PLL circuit that is frequency and phase locked to a wobble signal; a frequency and phase comparator for comprising a first output signal from the first PLL circuit with a system clock signal as frequency divided by M and for outputting a second output signal based on the differences in frequency and in phase; a PLL filter for providing a predetermined cutoff to the second output signal to output a third output signal; a pulse width modulating circuit for generating a pulse wave, the carrier frequency of which is a second reference clock signal, and for outputting a fourth output signal obtained by modulating the pulse width of the pulse wave by the third output signal; a low pass filter for smoothing the fourth output signal to output a fifth output signal; a VCO circuit the control voltage of which is the fifth output signal; a first frequency divider circuit for frequency dividing an output signal of the VCO circuit by N to output a system clock signal; and a second frequency divider circuit for frequency dividing, by M, and feeding the system clock signal back to the frequency and phase comparator. | 2008-11-27 |
20080290917 | MULTI-BAND FREQUENCY GENERATION METHOD AND APPARATUS - A frequency generation unit (FGU) | 2008-11-27 |
20080290918 | DLL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DELAYING AND LOCKING CLOCK IN SEMICONDUCTOR MEMORY APPARATUS - A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals. | 2008-11-27 |
20080290919 | CLOCK GENERATOR FOR SEMICONDUCTOR MEMORY APPARATUS - The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator. | 2008-11-27 |
20080290920 | DUTY CYCLE CORRECTION CIRCUIT AND METHOD THEREOF - A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock. | 2008-11-27 |
20080290921 | Level converting flip-flop and method of operating the same - A level converting flip-flop may include a data input circuit, a clocking circuit, a current mirror circuit, and/or a latch circuit. The data input circuit may be configured to generate a pull-up current in response to an input data signal having one of an input supply voltage smaller than an output supply voltage and a ground voltage. The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage. The current mirror circuit may be configured to pull-up an output node to the output supply voltage in response to the pull-up current provided to the internal node. The latch circuit may be configured to latch an output data signal generated at the output node. | 2008-11-27 |
20080290922 | DELAY CIRCUIT - A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different. | 2008-11-27 |
20080290923 | SYSTEMS AND METHODS FOR PROVIDING DELAYED SIGNALS - A variable delay apparatus comprises a calibrating unit receiving a signal from a variable delay unit and from a plurality of fixed delay sources, the calibrating unit comparing the signal from the variable delay unit with a plurality of signals from the fixed delay sources to control operation of the variable delay unit over a delay range independently of environmentally-induced drift. | 2008-11-27 |
20080290924 | METHOD AND APPARATUS FOR PROGRAMMABLE DELAY HAVING FINE DELAY RESOLUTION - An programmable delay apparatus includes a first delay stage having a delay cell which includes a passive network, where the first delay stage is capable of providing a first time delay. The apparatus further includes a second delay stage which includes a plurality of delay cells, where each delay cell is capable of providing a second time delay which is larger than the first time delay. A method for delaying an input signal includes receiving a delay select command based upon the desired time delay, establishing a circuit path which includes at least one delay element, selected from a plurality of delay cells, according to the delay select command, wherein at least one of the plurality of delay cells includes a delay element which comprises a passive network. | 2008-11-27 |
20080290925 | Clock generator - A multiphase clock with high resolution is generated. A first clock generator circuit ( | 2008-11-27 |
20080290926 | Mass Coupling at Clocked HF-Elements - A circuit for a fill-level measuring device is for the fast switching-on of a high-frequency element on a ground port is disclosed. The circuit comprises a switching unit with a circuit mass; a high-frequency element with a high-frequency mass; and a coupling element that couples the two masses together and at the same time insulates them from each other in a direct-current manner. In this way the switching unit can be arranged on the GND port of the HF-element, without influencing the HF characteristics of said HF element. | 2008-11-27 |
20080290927 | Half-bridge circuits employing normally on switches and methods of preventing unintended current flow therein - A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETS) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply. | 2008-11-27 |
20080290928 | SWITCHING CIRCUIT - A switching circuit is disclosed. The switching circuit is provided with first and second signal terminals, a control terminal, first and second resisters, and a field-effect transistor having a drain, a source, a gate and a back-gate. One end of the first resister is connected with the control terminal. The field-effect transistor is connected between the first and second signal terminals. The gate of the field-effect transistor is connected with the other end of the first resister. The back-gate of the field-effect transistor is connected with one end of the second resister. One of the source and drain of the first field-effect transistor is connected with the other end of the second resister. | 2008-11-27 |
20080290929 | Proximity detection system and method - Proximity detection is accomplished by determining with a moving average calculation a moving average level of input data; setting a threshold level in response to the average level and a sensitivity factor; producing a proximity detection output when the input data meets the threshold level; and changing the weighting used by the average level calculation in response to a proximity detection output. | 2008-11-27 |
20080290930 | LOW VOLTAGE CHARGE PUMP - A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor. | 2008-11-27 |
20080290931 | Charge pump systems and methods - Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry. | 2008-11-27 |
20080290932 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits. | 2008-11-27 |
20080290933 | Method and circuit for an efficient and scalable constant current source for an electronic display - The present invention uses two transistors instead of a sensing resistor to provide a constant current source for a load such as an array of light emitting diodes (“LEDs”). In the present invention, a bias current is applied to a branch of the circuit. The drain-to-source voltages of two transistors are matched. The voltage at the gate of both transistors is controlled based on the bias current and the drain-to-source current of the first of the two transistors. The second of the two transistors is sized such that source current of the second transistor is a multiple of the source current of the first transistor for a given gate voltage. By the techniques of this invention, the load current in a circuit is efficiently kept constant at a multiple of the input bias current. | 2008-11-27 |
20080290934 | REFERENCE BUFFER CIRCUITS - A reference buffer circuit is disclosed, providing a reference voltage at an output node and comprising a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising third and fourth MOS transistors and a tracking circuit. The first MOS transistor has a gate coupled to an output terminal of the amplifier and a source coupled to a negative input terminal of the amplifier. The second MOS transistor is coupled to the source of the first MOS transistor. The third MOS transistor has a gate coupled to the output terminal and a source coupled to the output node. The fourth MOS transistor has a drain coupled to the source of the third MOS transistor. A gate voltage of the fourth MOS transistor tracks a drain voltage of the third MOS transistor through the tracking circuit. | 2008-11-27 |
20080290935 | APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLTAGE DOMAIN IS POWERED DOWN - An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down. | 2008-11-27 |
20080290936 | NANOCRYSTAL-METAL OXIDE COMPLEX AND METHOD FOR PREPARING THE SAME - Disclosed herein is a nanocrystal-metal oxide complex. The nanocrystal of the nanocrystal-metal oxide complex is substituted with two or more different types of surfactants which are miscible with a metal oxide precursor and enable maintenance of luminescent and electrical properties of the nanocrystal. The nanocrystal-metal oxide complex exhibits superior optical and chemical stability and secures high luminescent efficiency of the nanocrystal. Accordingly, when the nanocrystal-metal oxide complex is used as a luminescent material of an electroluminescent device, it can improve luminescent efficiency and reliability of products. Further disclosed herein is a method for preparing the nanocrystal-metal oxide complex. | 2008-11-27 |
20080290937 | Constant gain amplifier system with positive and negative feedback - Constant and accurate signal gain systems based on controlling oscillator loop gain. A constant gain positive feedback network and an amplifier form an oscillator. Only when the oscillator loop gain is at least one does the oscillator produces an AC signal. Negative feedback of the oscillator's AC signal level is used to keep the loop gain close to or at the value of one by controlling the loop gain of the oscillator circuit. By maintaining the loop gain of the oscillator circuit substantially constant the signal gain is also maintained substantially constant. | 2008-11-27 |
20080290938 | Multibit digital amplifier for radio-frequency transmission - A broadband multibit digital radio-frequency (RF) signal is synthesized digitally. to convert the digital signal to a high-power analog signal for RF transmission. Each bit (or cluster of bits) of the digital signal is first separately amplified using a fast switching amplifier with a controlled dc power supply voltage. The DC voltages are weighted to match the significance of the bits, and controlled by a set of calibrated DC reference sources to maintain high precision. The amplified digital signals from the various bits are then combined and passed through an appropriate analog filter to generate the RF signal to be transmitted. Such a signal can exhibit broad bandwidth, high dynamic range, excellent linearity, and low noise. Preferred embodiments of this system can incorporate superconducting electronic elements. For ultimate precision, a set of primary or secondary DC voltage standards can be used to regulate the switching amplifier supply voltages. | 2008-11-27 |
20080290939 | Method and apparatus for distortion correction of RF amplifiers - A method of reducing distortion in the output of an amplifier is provided. The method comprises subtractively combining baseband error signals with the appropriate phase shift with baseband input signals, the baseband error signals generated by subtractively combining delayed fed-forward portions of the baseband input signals with baseband converted portions of a fed-back amplified output signal, the amplified output signal being a distorted replica of combined up-converted baseband input signals. The baseband error signals being filtered prior to the combining function, and also providing inputs to a controller which adjusts active elements of the amplification and fed-back paths in order to minimize the distortion within the output of the amplifier. | 2008-11-27 |
20080290940 | DIFFERENTIAL LOW NOISE AMPLIFIER (LNA) WITH COMMON MODE FEEDBACK AND GAIN CONTROL - A method, algorithm, architecture, circuits, and/or systems for low noise amplification are disclosed. In one embodiment, an amplifier can include an input stage, including a first differential input configured to receive a differential signal, a first current source coupled to the first differential input, a first current load receiving a first bias voltage and coupling the input stage to a first power supply, and a first pair of common mode feedback transistors, coupled to an output of the first current load and configured to limit a current to the first current source. The input stage provides an amplified signal to an additional stage having a structure similar to the input stage, configured to further amplify the amplified signal. | 2008-11-27 |
20080290941 | NANOELECTRONIC DIFFERENTIAL AMPLIFIERS AND RELATED CIRCUITS HAVING CARBON NANOTUBES, GRAPHENE NANORIBBONS, OR OTHER RELATED MATERIALS - Small-signal and other circuit design techniques realized by carbon nanotube field-effect transistors (CNFETs) to create analog electronics for analog signal handling, analog signal processing, and conversions between analog signals and digital signals. As the CNFETs exist and operate at nanoscale, they can be readily collocated or integrated into carbon nanotube sensing and transducing systems. The resulting collocation and integration may be at, or adequately near, nanoscale. One embodiment implements an analog differential amplifier having transistors which include carbon nanotubes, electrical contacts, and insulating material. The differential amplifier may be used in isolation or as an element of an operational amplifier. Negative feedback may be used to implement a wide range of analog signal processing functions, and to provide conversions among analog and digital signals. In some cases, an entire analog differential amplifier is implemented with a single carbon nanotube. | 2008-11-27 |
20080290942 | DIFFERENTIAL AMPLIFIER - A cascode current mirror circuit is connected as an active load to the input differential pair. A tail current source supplies a tail current to the input differential pair. A constant current source is connected in parallel with the input differential pair, and supplies a constant current to the tail current source. The constant current supplied by the constant current source is set to a value at which a transistor is not cut off. | 2008-11-27 |
20080290943 | MULTI-MODE AMPLIFIER ARRANGEMENT AND METHOD FOR CONTROLLING AN AMPLIFIER ARRANGEMENT - A multi-mode amplifier arrangement comprises an amplifier having a plurality of field effect transistors selectable in response to a control signal at a control terminal, said plurality of field effect transistors coupled to an input terminal to receive a signal to be amplified, said amplifier arranged between a supply terminal and a ground terminal. A tunable current source is coupled to the amplifier to provide in operation of the amplifier a constant drain current through the plurality of field effect transistors. | 2008-11-27 |
20080290944 | MICROPOWER NEURAL AMPLIFIER WITH ADAPTIVE INPUT-REFERRED NOISE - A micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays is provided. The micropower neural amplifier includes a low noise gain stage. The low noise gain stage is implemented using an amplifier and pseudoresistor elements. | 2008-11-27 |
20080290945 | CLASS AB OUTPUT STAGE AND METHOD FOR PROVIDING WIDE SUPPLY VOLTAGE RANGE - A class AB output stage includes first (M | 2008-11-27 |
20080290946 | Semiconductor integrated circuit device - To save power consumption in a semiconductor integrated circuit | 2008-11-27 |
20080290947 | RECONFIGURABLE TUNABLE RF POWER AMPLIFIER - A multi-band, multi-standard programmable power amplifier having tunable impedance matching input and output networks and programmable device characteristics. The impedance of either or both of the impedance matching input and output networks is tunable responsive to one or more control signals. In one example, the programmable power amplifier incorporates a feedback control loop and the control signal(s) are varied responsive to the feedback loop. | 2008-11-27 |
20080290948 | IMPEDANCE TRANSFORMER FOR AMPLIFIER AND AMPLIFIER INCLUDING THE SAME - An amplifier has an input port, an output port, N gain elements in parallel, an input power splitter coupled between the input port of the amplifier and the input ports of the N gain elements, an output resistor chain extending between the output ports of the first through Nth gain elements, and an output power combiner coupled between the output ports of the N gain elements and the output port of the amplifier. The output power combiner presents a corresponding input impedance to each of the N gain elements. At least two of the input impedances presented by the output power combiner to the N gain elements are substantially different from each other. | 2008-11-27 |
20080290949 | APPARATUS AND METHOD FOR ASYMMETRIC CHARGE PUMP FOR AN AUDIO AMPLIFIER - An audio amplifier with an integrated asymmetric charge pump is provided. The audio amplifier receives VDD and VSS as power supply signals. The integrated charge pump is arranged to provide VSS from VDD, such that VSS is a negative voltage that is lower in magnitude than VDD. | 2008-11-27 |
20080290950 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes a constant voltage regulator | 2008-11-27 |
20080290951 | SEMICONDUCTOR DEVICE - A current limiting circuit is connected to the gate (input terminal) of an amplifying transistor. The current limiting circuit includes a protecting transistor, a first protecting resistor connecting the drain to the gate of the protecting transistor, and a second protecting resistor connecting the source to the gate of the protecting transistor. The current limiting circuit limits current, so that electric power larger than the maximum electric power allowable for the amplifying transistor does not pass. | 2008-11-27 |
20080290952 | Dvd Reading Apparatus - A photodiode ( | 2008-11-27 |
20080290953 | System and Method for Generating LO Frequencies with Phase Locking in 2 Steps - System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal. | 2008-11-27 |
20080290954 | Fractional-N phase locked loop - An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal. The fractional frequency divider incrementally selects among all the outputs of the multi-phased VCO according to either a forward phase shifting operation or a backward phase shifting operation to generate a true fractional division factor. | 2008-11-27 |
20080290955 | LOW COST AND LOW VARIATION OSCILLATOR - An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements. | 2008-11-27 |
20080290956 | SURFACE-MOUNT TYPE CRYSTAL OSCILLATOR - A surface-mount type crystal oscillator includes a container body having a recess and made up of laminated ceramic, a crystal blank accommodated in the container body, and an IC chip made up of a semiconductor substrate in which at least an oscillation circuit using the crystal blank is formed. The IC chip is electrically and mechanically connected to an inner bottom surface of the recess so that a circuit formation surface thereof faces the inner bottom surface. The IC chip has a first electrode formed on a surface thereof which is opposite the inner bottom surface, and a second electrode is formed on a surface which is disposed in the recess, the first and second electrodes being connected together by wire bonding. Alternatively, an outer peripheral side surface of the IC chip is thermally coupled to an inner peripheral surface of the recess by a conductive adhesive. | 2008-11-27 |
20080290957 | RECEIVER WITH COLPITTS DIFFERENTIAL OSCILLATOR, COLPITTS QUADRATURE OSCILLATOR, AND COMMON-GATE LOW NOISE AMPLIFIER - Embodiments of the present invention include a common-gate amplifier having an input terminal and an output terminal, a transistor having a source, a drain, and a gate, four inductors, and two capacitors, and a negative amplification circuitry. The negative amplification circuitry has an input terminal to receive an RF signal. The negative amplification circuitry applies negative or zero amplification to the RF signal and outputs the negative or zero amplified signal on an output terminal. Alternative embodiments include a Colpitts differential oscillator, which includes two Colpitts single-ended oscillators. Each Colpitts single-ended oscillator includes a transistor. The source of the transistor in one Colpitts single-ended oscillator may be capacitively coupled to the gate of the transistor in the other Colpitts single-ended oscillator. | 2008-11-27 |
20080290958 | Resonator with adjustable capacitance for medical device - Systems and methods for a resonator with an adjustable capacitance for a medical device. In one embodiment, a resonator system includes a resonator device with an LC resonator circuit that has an adjustable capacitance, an inductor coil in series with the adjustable capacitance, and an adjustable capacitance control that can control the adjustable capacitance to obtain different particular capacitance values. This embodiment also includes a medical device, positioned with the resonator device, so that at least a portion of the inductor coil surrounds a space that is surrounded by at least a portion of the medical device. | 2008-11-27 |
20080290959 | MILLIMETER WAVE INTEGRATED CIRCUIT INTERCONNECTION SCHEME - A millimeter-wave integrated circuit (IC) package is disclosed. The package includes a substrate having a plurality of layers and a vertical interconnection. The vertical interconnection comprises a shielded transition between the plurality of layers and a compensation structure to minimize the parasitic effect of the transition. | 2008-11-27 |
20080290960 | APPARATUS OF IMPEDANCE MATCHING FOR BIDIRECTIONAL DATA LINE - An apparatus includes a bidirectional data line to couple to a device and an impedance to provide an impedance matching between the data line and the device. In some embodiments, when a direction of data flow in the data line is away from the device, the impedance is of a first impedance value, and when the direction of the data flow is toward the device, the impedance is of a second impedance value. In one embodiment, the second impedance value is substantially zero. | 2008-11-27 |
20080290961 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including an input/output circuit having a terminal capacitance adjustment circuit connected to a signal line between an external pin and an initial-stage circuit; a command decoder for decoding an entered command and detecting a terminal capacitance adjustment command; and a terminal capacitance control circuit, which has a terminal capacitance adjustment register that holds information for controlling terminal capacitance, for controlling a capacitance value of the terminal capacitance adjustment circuit based upon the information in the terminal capacitance adjustment register. The information held by the terminal capacitance adjustment register is set based upon the output from the command decoder. | 2008-11-27 |
20080290962 | Radio frequency switch - An RF switch is provided. In the RF switch, a T-junction slot line has a horizontal slot line and a vertical slot line. An open-end circuit is provided at each end portion of the horizontal and vertical slot lines. A first transmission line delivers signals from and to one portion of the horizontal slot line, and a second transmission line delivers signals from and to the other portion of the horizontal slot line. A third transmission line delivers signals from and to the vertical slot line. A switching circuit selectively switches the signal path of the one or the other portion of the horizontal slot line to the vertical slot line according to an external switching control signal. | 2008-11-27 |
20080290963 | Radio frequency switch - An RF switch is provided. In the RF switch, a slot line is divided into a first slot line and a second slot line and an open-end circuit is provided at each end portion of the first and second slot lines. A first transmission line delivers signals from and to the first slot line, and a second transmission line delivers signals from and to the second slot line. A third transmission line delivers signals from and to the portion of the slot line that separates the first slot line from the second slot line. A variable sub open-end circuit portion includes at least one open-end circuit which is selectively switched to the first or second slot line according to an external switching control signal. | 2008-11-27 |
20080290964 | Branching filter package - A branching filter package has a SAW filter chip housing area which houses a piezo electric base, on which a transmitting SAW filter and a receiving SAW filter having a different frequency passing band with each other, are formed, and an impedance matching circuit and a branching circuit for the transmitting SAW filter and the receiving SAW filter. | 2008-11-27 |
20080290965 | Component Operating on Acoustic Waves - A component operating with acoustic waves is described herein. The component includes a substrate having an underside subdivided into a center area and an edge area surrounding die center area on all sides. The component also includes a plurality of outer terminals in the edge area, and a plurality of inner terminals in the center area comprising at least a first inner terminal configured as a signal terminal. | 2008-11-27 |
20080290966 | ADAPTIVE RADIO TRANSCEIVER WITH FILTERING - An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims. | 2008-11-27 |
20080290967 | Offset footprint of a connector on a printed board - The present invention relates to a board receiving at least one connector, said board being constituted by a dielectric substrate comprising, on a first face, a first ground plane and on a second face, at least two transmission lines between which the connector and a footprint are mounted, characterized in that the footprint comprises a first element positioned between the two transmission lines under the connector, said first element forming with the first ground plane, a capacitive element and, at each extremity of the first element, second elements forming with the first element, a self-inductive and capacitive element, said second elements each extending by a second ground plane, the second ground planes being connected to the first ground plane. | 2008-11-27 |
20080290968 | BOUNDARY ACOUSTIC WAVE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A boundary acoustic wave device includes a first medium, a second medium, and an IDT electrode disposed at an interface between the first medium and the second medium, the IDT electrode having an Au layer defining a main electrode layer, wherein a Ni layer is laminated so as to contact at least one surface of the Au layer, and a portion of Ni defining the Ni layer is diffused from the Ni layer side surface of the Au layer toward the inside of the Au layer. | 2008-11-27 |
20080290969 | Piezoelectric Resonator, Piezoelectric Filter, and Duplexer and Communication Device Using the Same - Three or more piezoelectric resonators having resonance frequencies different from one another are realized on the same substrate. First through third frequency adjustment layers | 2008-11-27 |
20080290970 | DEVICE FOR MONITORING MULTIPLE BROADCAST SIGNALS - A media content monitoring system uses a rack adapted to receive multiple carrier boards to improve the system's ability to be configured to specific applications. Each carrier board contains tuner modules for receiving AM/FM broadcasts, satellite radio broadcasts, TV audio broadcasts, HD, IBOC, DAB and DRM digital radio broadcasts, etc. The tuner modules produce a USB output that is combined by a USB hub on the carrier boards into a single USB output. The carrier board outputs are in turn combined by a rack based USB hub into single USB output that is provided to a host computer. The host computer includes content identification software that automatically identifies selected media content received by the tuner modules and stores the selected content in a database. The host computer can send control codes to the tuner modules to alter their reception parameters. | 2008-11-27 |
20080290971 | ELECTRICAL SERVICE SWITCHING DEVICE - The disclosure relates to an electrical service switching device, e.g., a circuit breaker, having a magnetic release with a magnet armature, a thermal release, a fixed and moving contact piece, a switching mechanism which can be tripped by the thermal and magnetic release and has a latching point which is formed by a tripping lever and a catch lever which is mounted in a fixed position such that it can rotate and has an elongated hole in order to guide a clip, wherein the magnet armature can act on the contact lever, to which the moving contact piece is fitted, in order to open the contact point in the event of a short, and the switching mechanism can hold the contact lever permanently in the open position, having a switching toggle for manual operation of the switching mechanism, and having an intermediate lever which is articulated at one of its ends with the contact lever and at its other end on the clip, wherein the clip is articulated with at least one limb on the switching toggle. | 2008-11-27 |
20080290972 | ACTUATION MAGNET FOR MOVING A CLOSURE NEEDLE OF A HOT-RUNNER NOZZLE OF AN INJECTION MOLDING TOOL - An actuation magnet is provided for moving a closure needle of a hot-runner nozzle of an injection molding tool. The actuation magnet has an armature which is coupled in movement to the closure needle and may be displaced between first and second cores by subjecting at least one coil to current. A permanent magnet is arranged in a manner such that it exerts an additional magnetic force on the armature in at least one, preferably two, movement directions. | 2008-11-27 |
20080290973 | Magnetic holding apparatus for holding workpieces - An electro permanent magnetic apparatus with monolithic working face for holding workpieces magnetically or mechanically comprises a base plate and a ferrous monolithic working face. The base plate has a pocket or recess which houses reversible magnets and electrical windings; the working face has magnetic poles which are demarked by slots. On the opposite side of the working face recesses are provided beneath the slots for housing non-reversible permanent magnets. | 2008-11-27 |