48th week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150340427 | CAPACITOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A capacitor structure including at least one capacitor unit is provided. The capacitor unit includes a dielectric layer, an inner metal layer and an outer metal layer. The inner metal layer is disposed in the dielectric layer. The outer metal layer is disposed in the dielectric layer and surrounds the inner metal layer. The outer metal layer includes a first metal layer, two second metal layers and a third metal layer. The first metal layer is disposed under the inner metal layer. The second metal layers are disposed at two sides of the inner metal layer, and lower surfaces of the second metal layers are located equal to or below a lower surface of the inner metal layer. The third metal layer is disposed over the inner metal layer and connects to the second metal layers. | 2015-11-26 |
20150340428 | INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING THE SAME - Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure. | 2015-11-26 |
20150340429 | INTEGRATED RF FRONT END SYSTEM - Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements. | 2015-11-26 |
20150340430 | SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE LAYERS AND OVERLYING SEMICONDUCTOR LAYERS HAVING CLOSELY MATCHING COEFFICIENTS OF THERMAL EXPANSION, AND RELATED METHODS - Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments. | 2015-11-26 |
20150340431 | ZENER DIODE HAVIING A POLYSILICON LAYER FOR IMPROVED REVERSE SURGE CAPABILITY AND DECREASED LEAKAGE CURRENT - A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material. | 2015-11-26 |
20150340432 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer. | 2015-11-26 |
20150340433 | Power Semiconductor Device of Stripe Cell Geometry - A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad. | 2015-11-26 |
20150340434 | SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination. | 2015-11-26 |
20150340435 | Multi-chip Package Module And A Doped Polysilicon Trench For Isolation And Connection - A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements. | 2015-11-26 |
20150340436 | THREE-DIMENSIONAL TEXTURING OF TWO-DIMENSIONAL MATERIALS - A method of creating crumples in a monolayer entails contacting a monolayer comprising a two-dimensional material with a thermally contractible polymer, and heating the thermally contractible polymer to contract the polymer and induce buckling of the monolayer, where a plurality of crumples are formed in the monolayer due to the buckling. A device having a crumpled microstructure includes a monolayer comprising a two-dimensional material and including a plurality of crumples. | 2015-11-26 |
20150340437 | Zero-Dimensional Electron Devices and Methods of Fabricating the Same - A semiconductor device comprises a substrate and quantum dots, wherein a peak emission of the quantum dots has a FWHM of less than 20 meV when the semiconductor is measured at a temperature of 4 Kelvin. | 2015-11-26 |
20150340438 | SEMICONDUCTOR ARRANGEMENTS AND METHODS OF MANUFACTURING THE SAME - Semiconductor arrangements and methods for manufacturing the same. The arrangement may include: a substrate; a back gate formed on the substrate; at least one pair of nanowires disposed on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective nanowires. | 2015-11-26 |
20150340439 | INCOHERENT TYPE-III MATERIALS FOR CHARGE CARRIERS CONTROL DEVICES - A semiconductor junction may include a first semiconductor material and a second material. The first and the second semiconductor materials are extrinsically undoped. At least a portion of a valence band of the second material has a higher energy level than at least a portion of the conduction band of the first semiconductor material (type-III band alignment). A flow of a majority of free carriers across the semiconductor junction is diffusive. A region of generation and/or recombination of a plurality of free carriers is confined to a two-dimensional surface of the second material, and at the interface of the first semiconductor material and the second material. | 2015-11-26 |
20150340440 | BIPOLAR TRANSISTOR - A modified bipolar transistor is provided which can provide improved gain, Early voltage, breakdown voltage and linearity over a finite range of collector voltages. It is known that the gain of a transistor can change with collector voltage. This document teaches a way of reducing this variation by providing structures for the depletion regions with the device to preferentially deplete with. As a result the transistor's response can be made more linear. | 2015-11-26 |
20150340441 | HIGH VOLTAGE SEMICONDUCTOR APPARATUS - A vertical high voltage semiconductor apparatus includes a first conductivity semiconductor substrate; a first conductivity semiconductor layer disposed on the semiconductor substrate and having an impurity concentration lower than the semiconductor substrate; a second conductivity semiconductor layer disposed on the first conductivity semiconductor layer; a second conductivity base layer disposed on the first conductivity semiconductor layer and the second conductivity semiconductor layer and, having an impurity concentration lower than the second conductivity semiconductor layer; and a first conductivity source region selectively disposed inside the base layer. In an edge termination portion, after a region of the second conductivity semiconductor layer is removed, in the first conductivity semiconductor layer having an impurity concentration lower than that of the semiconductor substrate, second conductivity layers having a low concentration are formed such that the second conductivity layer at the innermost perimeter, the second conductivity semiconductor layer, and the base layer do not contact. | 2015-11-26 |
20150340442 | Drain Extended Field Effect Transistors and Methods of Formation Thereof - In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. | 2015-11-26 |
20150340443 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon carbide layer, a JTE region (first electric field relaxing region), an insulating film disposed on a first main surface and covering the JTE region, and a pad electrode electrically connected to the JTE region. The pad electrode includes an extension portion extending from an end of the JTE region close to the element region in a peripheral direction from the element region toward the JTE region, the extension portion being disposed on the insulating film. The extension portion overlies at least a portion of the JTE region. | 2015-11-26 |
20150340444 | GROUP III NITRIDE BULK CRYSTALS AND THEIR FABRICATION METHOD - In one instance, the invention provides a bulk crystal of group III nitride having a thickness of more than 1 mm without cracking above the sides of a seed crystal. This bulk group III nitride crystal is expressed as Ga | 2015-11-26 |
20150340445 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE ON THE SUBSTRATE STRUCTURE - A substrate structure include a lower substrate doped with n-type impurities having a first impurity concentration, an epitaxial layer on the lower substrate, and a metallic-contaminant collection area spaced apart from the epitaxial layer in the lower substrate, the metallic-contaminant collection area doped with impurities having a second impurity concentration higher than the first impurity concentration, the metallic-contaminant collection area having lattice defects, and an upper surface of the metallic-contaminant collection area being spaced apart from a top surface of the lower substrate at a distance in a range of about 0.1 μm to about 3 μm. | 2015-11-26 |
20150340446 | THIN FILM TRANSISTOR SUBSTRATE, METHOD FOR FORMING THE SAME, AND DISPLAY - A thin film transistor substrate includes: a substrate; a gate disposed on the substrate; a gate insulating layer disposed on the substrate and covering the gate; an active layer disposed on the gate insulating layer and above the gate, and the active layer has a first oxygen vacancy portion and a second oxygen vacancy portion; a source electrode and a drain electrode disposed on the active layer, the source electrode is connected to the first oxygen vacancy portion, and the drain electrode is connected to the second oxygen vacancy portion. | 2015-11-26 |
20150340447 | SURFACE PROFILE FOR SEMICONDUCTOR REGION - One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region. | 2015-11-26 |
20150340448 | METHOD FOR CREATION OF THE GATE SHIELD IN ANALOG/RF POWER ED-CMOS IN SIGE BICMOS TECHNOLOGIES - A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies. | 2015-11-26 |
20150340449 | GALLIUM NITRIDE FIELD EFFECT TRANSISTOR WITH BURIED FIELD PLATE PROTECTED LATERAL CHANNEL - A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer. | 2015-11-26 |
20150340450 | TRENCH INSULATED GATE BIPOLAR TRANSISTOR AND EDGE TERMINAL STRUCTURE - An edge terminal structure of a power semiconductor device includes a second conductive-type substrate, a first conductive-type buffer layer, a first conductive-type epitaxial layer, a first and a second electrodes, and a first and a second field plates. A trench is in a surface of the first conductive-type epitaxial layer in an edge terminal area beside an active area of the power semiconductor device. The first field plate includes at least a L-shaped electric-plate, a gate insulation layer under the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes a portion of the first electrode and at least an insulation layer between the portion of the first electrode and the first conductive-type epitaxial layer. The insulation layer covers the tail of the trench and completely covers the L-shaped electric-plate. | 2015-11-26 |
20150340451 | METHOD FOR CMP OF HIGH-K METAL GATE STRUCTURES - A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device and forming a dielectric layer on the substrate. The front-end device includes a first dummy gate in a first type metal gate transistor region, a second dummy gate in a second type metal gate transistor region, and a polysilicon gate in a polysilicon gate region. The method also includes removing a thickness of the first, second, and polysilicon gates and forming a protective layer on the polysilicon layer to protect the polysilicon layer during a CMP process, thereby improving the performance and yield of the semiconductor device. | 2015-11-26 |
20150340452 | Buried fin contact structures on FinFET semiconductor devices - A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess. | 2015-11-26 |
20150340453 | SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench. | 2015-11-26 |
20150340454 | DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIELD EFFECT DEVICES - A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill. | 2015-11-26 |
20150340455 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE - The present invention provides a thin film transistor and a method of fabricating the thin film transistor, an array substrate and a method of fabricating the array substrate, and a display device. The thin film transistor includes a substrate and a gate, an insulation layer, an active layer, a source and a drain which are provided on the substrate. A spacer layer is also provided between the gate and the active layer, and the spacer layer overlaps at least with one of the gate and the active layer having a smaller area in an orthographic projection direction. The spacer layer can effectively prevent material forming the gate from being diffused into the active layer, thereby ensuring stability of performance of the thin film transistor. In the array substrate utilizing the thin film transistor, the spacer layer further extends to a region corresponding to a gate line. | 2015-11-26 |
20150340456 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved. | 2015-11-26 |
20150340457 | METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE WITH A LARGER METAL SILICIDE CONTACT AREA AND THE RESULTING DEVICES - One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material. | 2015-11-26 |
20150340458 | ZENER DIODE HAVIING A POLYSILICON LAYER FOR IMPROVED REVERSE SURGE CAPABILITY AND DECREASED LEAKAGE CURRENT - A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material. | 2015-11-26 |
20150340459 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a substrate; forming a plurality of first patterns on the substrate, the plurality of first patterns spaced apart from each other in the first direction and extending in a second direction, each first pattern having two opposite end portions in the second direction, and each first pattern having at least one different end portion location in the second direction from a corresponding end portion location of at least one adjacent first pattern; and using the plurality first patterns to form a plurality of respective conductive lines in a plurality of gaps formed in the substrate, the gaps corresponding to and formed to have the same shapes as the plurality of first patterns when viewed from a plan view. | 2015-11-26 |
20150340460 | ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES - An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×10 | 2015-11-26 |
20150340461 | METAL GATE STRUCTURE AND METHOD OF FORMATION - Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures. | 2015-11-26 |
20150340462 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 2015-11-26 |
20150340463 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE HAVING LATERAL CHANNEL AND METHOD OF MANUFACTURING THE SAME - A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. | 2015-11-26 |
20150340464 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device manufacturing method includes forming a gate opening in a semiconductor layer; forming a sacrificial gate in the gate opening; forming a source region and a drain region in the semiconductor layer in proximity to the gate opening; removing the sacrificial gate; and forming a gate stack comprising a replacement gate dielectric layer and a replacement gate conductor layer in the gate opening, wherein the gate opening is configured to define a thickness of a portion of the semiconductor layer for a channel region. Channel control in semiconductor devices formed according to the above method can be effectively improved. | 2015-11-26 |
20150340465 | METHOD FOR EMBEDDED DIAMOND-SHAPED STRESS ELEMENT - A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer. | 2015-11-26 |
20150340466 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE - A method for manufacturing a semiconductor device includes: forming a temporary gate electrode and a first dummy gate electrode located on a first side of the temporary gate electrode, on a semiconductor region with a first lattice constant; forming a first semiconductor layer with a second lattice constant different from the first lattice constant, between the temporary gate electrode and the first dummy gate electrode; removing the temporary gate electrode while leaving the first dummy gate electrode intact; and forming a gate electrode in a region from which the temporary gate electrode is removed. | 2015-11-26 |
20150340467 | MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE - Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged. | 2015-11-26 |
20150340468 | RECESSED CHANNEL FIN DEVICE WITH RAISED SOURCE AND DRAIN REGIONS - A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin. | 2015-11-26 |
20150340469 | Method For Non-Resist Nanolithography - A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings. | 2015-11-26 |
20150340470 | METHODS FOR FORMING SEMICONDUCTOR FIN SUPPORT STRUCTURES - One method includes forming trenches that define a fin structure including a first layer of a first semiconductor material and a second layer of a second semiconductor material positioned above a substrate, performing at least one etching process that exposes opposing end surfaces of the first and second layers, performing at least one recess etching process that removes end portions of the first layer and defines a cavity on opposite ends of the first layer, performing an epitaxial deposition process that fills each of the cavities with a support structure including a third semiconductor material, and performing an etching process to selectively remove remaining portions of the recessed first layer relative to the second layer and the support structures, the end portions of the second layer and the support structures defining pillars on opposite ends of the fin structure. | 2015-11-26 |
20150340471 | RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH - A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions. | 2015-11-26 |
20150340472 | FORMATION OF HIGH QUALITY FIN IN 3D STRUCTURE BY WAY OF TWO-STEP IMPLANTATION - The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed. | 2015-11-26 |
20150340473 | III-V Multi-Channel FinFETs - A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric. | 2015-11-26 |
20150340474 | FinFETs and Methods for Forming the Same - Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface. | 2015-11-26 |
20150340475 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity. | 2015-11-26 |
20150340476 | METHOD AND SYSTEM FOR PLANAR REGROWTH IN GAN ELECTRONIC DEVICES - A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources. | 2015-11-26 |
20150340477 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith. | 2015-11-26 |
20150340478 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction. | 2015-11-26 |
20150340479 | SEMICONDUCTOR DEVICE - The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. | 2015-11-26 |
20150340480 | SEMICONDUCTOR DEVICE - A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them. Then, upper surfaces of the third and fourth linear trench gate electrodes which are formed so as to sandwich both sides of the linear hole collector cell region and electrically connected to an emitter electrode are positioned to be lower than upper surfaces of the first and second linear trench gate electrodes which are formed so as to sandwich both sides of the linear active cell region and electrically connected to a gate electrode. | 2015-11-26 |
20150340481 | LATCH-UP ROBUST SCR-BASED DEVICES - An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. | 2015-11-26 |
20150340482 | HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device. | 2015-11-26 |
20150340483 | Group III-V Device Including a Shield Plate - There are disclosed herein various implementations of a group III-V device including a shield plate. Such a group III-V device includes a substrate, a transition body situated over the substrate, a device channel layer situated over the transition body, and a device barrier layer situated over the device channel layer and producing a device two-dimensional electron gas (2-DEG). The group III-V device also includes a drain electrode coupled to the device barrier layer, and a shield plate, which may be coupled to the drain electrode or may be a floating shield plate. The shield plate is configured to substantially shield the device 2-DEG from charge centers situated over the device barrier layer. | 2015-11-26 |
20150340484 | POWER DEVICE - This disclosure discloses a power device. The power device comprises a substrate; a first semiconductor layer having a first band gap and disposed on the substrate; a second semiconductor layer having a second band gap being lager than the first band gap and disposed on the first semiconductor layer; a third semiconductor layer having a third band gap smaller than the second band gap layer and disposed on the second semiconductor layer; a source electrode disposed on the third semiconductor layer; a base electrode electrically connecting the source electrode; and a p-type metal-oxide layer disposed between the base electrode and the third semiconductor layer. | 2015-11-26 |
20150340485 | High-voltage Nitride Device and Manufacturing Method Thereof - A high-voltage nitride device which can avoid vertical breakdown and has a high breakdown voltage includes: a silicon substrate; a nitride epitaxial layer, prepared on the silicon substrate; a source electrode and a drain electrode, both of which are contacted with the nitride epitaxial layer; a gate electrode, prepared between the source electrode and the drain electrode; and, at least one spatial isolation area, formed in a region between the silicon substrate and the nitride epitaxial layer vertically and between the source electrode and the drain electrode horizontally. | 2015-11-26 |
20150340486 | CONDUCTIVE SPLINE FOR METAL GATES - An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate. | 2015-11-26 |
20150340487 | Semiconductor Device Having a Lower Diode Region Arranged Below a Trench - A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes: a drift region, a source region, and a body region arranged between the source and drift regions; a diode region and a pn junction between the diode and drift regions; a trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; a gate electrode in the trench and dielectrically insulated from the body, diode and drift regions by a gate dielectric. The diode region has a lower diode region arranged below the trench bottom, and the lower diode region has a maximum of a doping concentration distant to the trench bottom. A corresponding method of manufacturing the device also is provided. | 2015-11-26 |
20150340488 | FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED EXTENSION PORTIONS OF EPITAXIAL ACTIVE REGIONS - A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an implantation mask to amorphize surface portions of the semiconductor fin into inverted U-shaped amorphous semiconductor portions. A gate spacer is formed around the gate structure, and the inverted U-shaped amorphous semiconductor portions are etched selective to a single crystalline portion of the semiconductor fin and the gate structure. A pair of inverted U-shaped cavities is formed underneath the gate spacer and above the remaining portion of the semiconductor fin. A doped epitaxial semiconductor material is deposited by a selective epitaxy process to form doped epitaxial active regions that include self-aligned extension portions underlying the gate spacer. | 2015-11-26 |
20150340489 | FIN TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel. | 2015-11-26 |
20150340490 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices and methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a fin disposed on a substrate. The fin may include an insulating layer pattern disposed in a top surface of the fin. The semiconductor devices may also include a wire pattern disposed on the insulating layer pattern to be separated from the insulating layer pattern and a gate electrode surrounding the wire pattern. | 2015-11-26 |
20150340491 | SPACER CHAMFERING FOR A REPLACEMENT METAL GATE DEVICE - Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching. | 2015-11-26 |
20150340492 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p | 2015-11-26 |
20150340493 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 2015-11-26 |
20150340494 | TRENCH POWER METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND EDGE TERMINAL STRUCTURE - An edge terminal structure of a trench power semiconductor device includes a first conductive-type substrate, a first conductive-type epitaxial layer thereon, a first electrode on a surface of the first conductive-type epitaxial layer, a second electrode on a back of the first conductive-type substrate, a first and a second field plates. The trench power semiconductor device includes an active area and an edge terminal area. A trench is in the surface of the first conductive-type epitaxial layer. The first field plate includes an L-shaped electric-plate, a gate insulation layer below the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes a portion of the first electrode and an insulation layer between the portion of the first electrode and the first conductive-type epitaxial layer. The insulation layer covers the tail of the trench and completely covers the L-shaped electric-plate. | 2015-11-26 |
20150340495 | VERTICAL COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR ON A GROUP IV SEMICONDUCTOR SUBSTRATE - Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor. | 2015-11-26 |
20150340496 | TRANSISTOR HAVING DOUBLE ISOLATION WITH ONE FLOATING ISOLATION - A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats. | 2015-11-26 |
20150340497 | METHODS OF INCREASING SILICIDE TO EPI CONTACT AREAS AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer. | 2015-11-26 |
20150340498 | METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS - A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences. | 2015-11-26 |
20150340499 | SEMICONDUCTOR DEVICE HAVING A STRESS-INTRODUCING LAYER BETWEEN CHANNEL REGION AND SOURCE AND DRAIN REGIONS - A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region. | 2015-11-26 |
20150340500 | SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS - Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation. | 2015-11-26 |
20150340501 | FORMING INDEPENDENT-GATE FINFET WITH TILTED PRE-AMORPHIZATION IMPLANTATION AND RESULTING DEVICE - Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET. | 2015-11-26 |
20150340502 | FINFET WITH UNDOPED BODY BULK - Systems and methods are provide to achieve undoped body bulk silicon based devices, such as field effect transistors (FETS) and Fin Field Effect Transistors (FinFETs). In an embodiment, an epitaxial growth technique is used to form the silicon of an active region of a fin of a FinFET once a punchthrough stop (PTS) layer has been formed. In an embodiment, the epitaxial growth technique according to embodiments of the present disclosure produces a fin with a small notch in the active region. | 2015-11-26 |
20150340503 | Method of Producing a III-V Fin Structure - A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate. | 2015-11-26 |
20150340504 | OXIDE THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - An oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method comprises: forming a gate electrode ( | 2015-11-26 |
20150340505 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a first gate electrode over a substrate while heated at a temperature higher than or equal to 450° C. and lower than the strain point of the substrate, forming a first oxide semiconductor film over the first insulating film, adding oxygen to the first oxide semiconductor film and then forming a second oxide semiconductor film over the first oxide semiconductor film, and performing heat treatment so that part of oxygen contained in the first oxide semiconductor film is transferred to the second oxide semiconductor film. | 2015-11-26 |
20150340506 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide a thin film transistor having favorable electric characteristics and high reliability and a semiconductor device which includes the thin film transistor as a switching element. An In—Ga—Zn—O-based film having an incubation state that shows an electron diffraction pattern, which is different from a conventionally known amorphous state where a halo shape pattern appears and from a conventionally known crystal state where a spot appears clearly, is formed. The In—Ga—Zn—O-based film having an incubation state is used for a channel formation region of a channel etched thin film transistor. | 2015-11-26 |
20150340507 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer. | 2015-11-26 |
20150340508 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a method for manufacturing a highly reliable semiconductor device which includes a thin film transistor using an oxide semiconductor and having stable electric characteristics. In manufacture of a semiconductor device in which an oxide semiconductor is used for a channel formation region, after an oxide semiconductor film is formed, a conductive film including a metal, a metal compound, or an alloy that can absorb or adsorb moisture, a hydroxy group, or hydrogen is formed to overlap with the oxide semiconductor film with an insulating film provided therebetween. Then, heat treatment is performed in the state where the conductive film is exposed; in such a manner, activation treatment for removing moisture, oxygen, hydrogen, or the like adsorbed onto a surface of or in the conductive film is performed. | 2015-11-26 |
20150340509 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al | 2015-11-26 |
20150340510 | DISPLAY DEVICE - According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size. | 2015-11-26 |
20150340511 | THIN FILM TRANSISTOR, AMORPHOUS SILICON FLAT DETECTION SUBSTRATE AND MANUFACTURING METHOD - A thin film transistor, an amorphous silicon flat detection substrate and a manufacturing method are provided. The material for a source electrode and a drain electrode of the thin film transistor is a conductor converted from the material for the amorphous metal oxide active layer by depositing an insulating substance containing hydrogen ions not less than a preset value, which reduces the valence band level difference between the source and the drain electrodes and the active layer, realizes good lattice matching and improves electricity characteristics of the thin film transistor. | 2015-11-26 |
20150340512 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE, METHOD OF FABRICATING SAME, AND DISPLAY DEVICE - A thin film transistor, an array substrate, a method of fabricating the same, and a display device are provided. The thin film transistor includes a substrate plate, and an active layer, a source, and a drain which are arranged on the substrate plate. The thin film transistor also includes an inclined portion which is arranged on the substrate plate in an inclined manner. The active layer is at least partially arranged on the inclined portion. The source and the drain are arranged over the active layer and at least partially overlap the active layer. In this manner, the size of the thin film transistor in a direction parallel with the substrate plate can be effectively reduced. | 2015-11-26 |
20150340513 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. | 2015-11-26 |
20150340514 | METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE - A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure. | 2015-11-26 |
20150340515 | REVERSE STACK STRUCTURES FOR THIN-FILM PHOTOVOLTAIC CELLS - In one embodiment, a method includes depositing a photoactive layer onto a first substrate, depositing a contact layer onto the photoactive layer, attaching a second substrate onto the contact layer, and removing the first substrate from the photoactive layer, contact layer, and second substrate. | 2015-11-26 |
20150340516 | FRONT SHEET OF SOLAR CELL, METHOD OF MANUFACTURING THE SAME AND PHOTOVOLTAIC MODULE COMPRISING THE SAME - A front sheet of solar cell, a method of manufacturing the same and a photovoltaic module are provided. The front sheet of solar cell can effectively block infrared rays (IRs) by forming an IR blocking layer including a cholesteric liquid crystal (CLC) material on a substrate. Thus, an increase in temperature of a cell can be suppressed so that the power generation efficiency of the cell can be improved. Also, the multi-layered sheet can be configured so that a UV blocking layer including a fluorine-based polymer and a wavelength conversion material can be formed on the IR blocking layer. Thus, wavelengths of a UV region can be converted into wavelengths of a VR region so that the power generation efficiency of the cell can be improved, and discoloration and deformation caused by UVs can be prevented so that the weather resistance can be improved. | 2015-11-26 |
20150340517 | ELECTRO-CONDUCTIVE PASTE COMPRISING COARSE INORGANIC OXIDE PARTICLES IN THE PREPARATION OF ELECTRODES IN MWT SOLAR CELLS - The invention relates to an electro-conductive paste comprising coarse SiO | 2015-11-26 |
20150340518 | PRINTABLE DIFFUSION BARRIERS FOR SILICON WAFERS - The present invention relates to a novel process for the preparation of printable, high-viscosity oxide media, and to the use thereof in the production of solar cells. | 2015-11-26 |
20150340519 | HIGHLY-FLUORESCENT AND PHOTO-STABLE CHROMOPHORES FOR WAVELENGTH CONVERSION - The invention provides highly fluorescent materials comprising a single (i=0) or a series (i=1, 2, etc.) of heterocyclic systems. The chromophores are particularly useful for absorption and emission of photons in the visible and near infrared wavelength range. The photo-stable highly luminescent chromophores are useful in various applications, including in wavelength conversion films. Wavelength conversion films have the potential to significantly enhance the solar harvesting efficiency of photovoltaic or solar cell devices. | 2015-11-26 |
20150340520 | THIN-FILM SEMICONDUCTOR OPTOELECTRONIC DEVICE WITH TEXTURED FRONT AND/OR BACK SURFACE PREPARED FROM TEMPLATE LAYER AND ETCHING - A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on a first layer. The template layer has significant inhomogeneity either in thickness or in composition, or both, including the possibility of forming one or more islands to provide at least one textured surface of the island layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The altered at least one textured surface is operative to cause scattering of light. | 2015-11-26 |
20150340521 | Methods and Systems for Controlling Phonon-Scattering - Structures and methods for controlling phonon-scattering are provided. In some embodiments, a metamaterial structure comprises a light absorbing layer ( | 2015-11-26 |
20150340522 | ELECTRONIC DEVICE INCLUDING HORIZONTAL TYPE DIODE USING 2D MATERIAL AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, an electronic device includes a substrate, an insulating layer on the substrate, and a diode layer on the insulating layer. The diode layer includes a two dimensional (2D) material layer. The 2D material layer includes an N-type region and a P-type region. According to example embodiments, a method of manufacturing an electronic device includes forming an insulating film on a substrate, forming a 2D material layer on the insulating film, and dividing the 2D material layer into an N-type region and a P-type region. | 2015-11-26 |
20150340523 | TRANSPARENT ELECTRODE OPTICAL DEVICE, METHOD, AND APPLICATIONS - An optical device including a shaped electrode on a substrate thereof utilizes total internal reflection to provide improved transmission of electromagnetic radiation (‘light’) to the substrate compared to standard electrode designs that involve flat electrode surfaces. Redirection of incident light by a tilted or otherwise shaped contact or material added on the contact provides otherwise reflected light to an open surface region of the substrate. Optional plasmon mediated focusing of incident p-polarized light may be realized. | 2015-11-26 |
20150340524 | Method of Fabricating a Flexible Photovoltaic Film Cell With an Iron Diffusion Barrier Layer - A method of fabricating a flexible photovoltaic film cell with an iron diffusion barrier layer. The method includes: providing a foil substrate including iron; forming an iron diffusion barrier layer on the foil substrate, where the iron diffusion barrier layer prevents the iron from diffusing; forming an electrode layer on the iron diffusion barrier layer; and forming at least one light absorber layer on the electrode layer. A flexible photovoltaic film cell is also provided, which cell includes: a foil substrate including iron; an iron diffusion barrier layer formed on the foil substrate to prevent the iron from diffusing; an electrode layer formed on the iron diffusion barrier layer; and at least one light absorber layer formed on the electrode layer. | 2015-11-26 |
20150340525 | METHOD FOR FORMING CHALCOGENIDE LAYERS - A method is provided for forming on a substrate a chalcogenide layer, the chalcogenide layer containing at least two metallic elements and containing Se. The method comprises depositing on the substrate a metallic layer containing the at least two metallic elements; and annealing the metallic layer in an environment comprising both a S-containing vapor such as H | 2015-11-26 |
20150340526 | NANOWIRE DEVICE WITH ALUMINA PASSIVATION LAYER AND METHODS OF MAKING SAME - In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array. | 2015-11-26 |