47th week of 2021 patent applcation highlights part 62 |
Patent application number | Title | Published |
20210366954 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING - A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure. | 2021-11-25 |
20210366955 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME - In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors. | 2021-11-25 |
20210366956 | COMPOSITE BSI STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure. | 2021-11-25 |
20210366957 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming photodiodes extending from a front-side surface of a semiconductor layer into the semiconductor layer; forming transistors on the front-side surface of the semiconductor layer; forming an interconnect structure over the transistors, the interconnect structure comprising an inter-metal dielectric and metal lines in the inter-metal dielectric; etching first regions of a backside surface of the semiconductor layer to form trenches in the semiconductor layer and non-overlapping the photodiodes; after forming the trenches, etching second regions of the backside surface of the semiconductor layer to form pits in the semiconductor layer and overlapping the photodiodes; and depositing a dielectric material in the trenches and the pits. | 2021-11-25 |
20210366958 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other. | 2021-11-25 |
20210366959 | IMAGE SENSOR, IMAGE CAPTURING APPARATUS AND IMAGE PROCESSING APPARATUS - An image sensor comprises: a pixel region including a plurality of microlenses arranged in a matrix, and a plurality of photoelectric conversion portions provided for each of the microlenses; a plurality of amplifiers that apply a plurality of different gains to signals output from the pixel region; and a scanning circuit that scans the pixel region so that a partial signal and an added signal are read out, the partial signal being a signal from some of the plurality of photoelectric conversion portions, and the added signal being a signal obtained by adding the signals from the plurality of photoelectric conversion portions. | 2021-11-25 |
20210366960 | CAPACITOR INCLUDING FIRST ELECTRODE, DIELECTRIC LAYER, AND SECOND ELECTRODE, IMAGE SENSOR, AND METHOD FOR PRODUCING CAPACITOR - A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer has a thickness of 10 nm or more. The first electrode contains carbon. At the interface between the dielectric layer and the first electrode, an elemental percentage of carbon is 30 atomic % or less. | 2021-11-25 |
20210366961 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes an imaging element group in which imaging elements each having a photoelectric conversion portion | 2021-11-25 |
20210366962 | IMAGE SENSING DEVICE - An image sensing device includes a substrate structured to include a first surface on a first side of the substrate and a second surface on a second side of the substrate opposite to the first side and to further include a first active region and a second active region in a portion of the substrate near the second surface, at least one photoelectric conversion element formed in the substrate, and structured to generate photocharges by performing photoelectric conversion of incident light received through the first surface of the substrate, a floating diffusion region formed near the second surface of the substrate, and structured to receive the photocharges from the photoelectric conversion element and temporarily store the received photocharges, a transistor formed in the first active region, and structured to include a first source/drain region coupled to the floating diffusion region, and a well pickup region formed in the second active region, and structured to apply a bias voltage to the substrate. The first source/drain region and the well pickup region have complementary conductivities and are formed to be in contact with each other. | 2021-11-25 |
20210366963 | RELIABLE SEMICONDUCTOR PACKAGES - A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. | 2021-11-25 |
20210366964 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE - A solid-state imaging device according to an embodiment includes: a semiconductor substrate including a photoelectric conversion element; a lens disposed above a first light incident surface of the photoelectric conversion element; and a plurality of columnar structures disposed on a surface parallel to the first light incident surface that is located between a second light incident surface of the lens and the first light incident surface of the photoelectric conversion element. The columnar structure includes at least one of silicon, germanium, gallium phosphide, aluminum oxide, cerium oxide, hafnium oxide, indium oxide, tin oxide, niobium pentoxide, magnesium oxide, tantalum pentoxide, titanium pentoxide, titanium oxide, tungsten oxide, yttrium oxide, zinc oxide, zirconia, cerium fluoride, gadolinium fluoride, lanthanum fluoride, and neodymium fluoride. | 2021-11-25 |
20210366965 | PHOTOELECTRIC CONVERSION ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS - A photoelectric conversion element including a first electrode and a second electrode that are disposed to face each other and a photoelectric conversion layer that is provided between the first electrode and the second electrode. The photoelectric conversion layer contains at least a subphthalocyanine or a subphthalocyanine derivative, and a carrier dopant, in which the carrier dopant has a concentration of less than 1% by volume ratio to the subphthalocyanine or the subphthalocyanine derivative. | 2021-11-25 |
20210366966 | Photosensitive Sensor, Preparation Method Thereof, and Electronic Device - A photosensitive sensor, a preparation method thereof, and an electronic device, wherein the photosensitive sensor includes a substrate, the substrate having a sensing area, a plurality of regularly arranged sensing units being provided in the sensing area, a shielding layer being provided on a side of the sensing units away from the substrate, the shielding layer covering the sensing area, a material of the shielding layer being a transparent conductive material, and the shielding layer being connected with a constant voltage signal terminal. | 2021-11-25 |
20210366967 | IMAGE SENSOR DEVICE - An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, and the first isolation structure has a first end portion in the substrate. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure surrounds a second portion of the light-sensing region, the second isolation structure has a second end portion in the substrate, and the second end portion of the second isolation structure is closer to the front surface of the substrate than the first end portion of the first isolation structure. | 2021-11-25 |
20210366968 | PLENOPTIC CAMERA FOR MOBILE DEVICES - A plenoptic camera for mobile devices is provided, having a main lens, a microlens array, an image sensor, and a first reflective element configured to reflect the light rays captured by the plenoptic camera before arriving at the image sensor, in order to fold the optical path of the light captured by the camera before impinging the image sensor. Additional reflective elements may also be used to further fold the light path inside the camera. The reflective elements can be prisms, mirrors or reflective surfaces of three-sided optical elements having two refractive surfaces that form a lens element of the main lens. By equipping mobile devices with this plenoptic camera, the focal length can be greatly increased while maintaining the thickness of the mobile device under current constraints. | 2021-11-25 |
20210366969 | IMAGE SENSING DEVICE - An image sensing device may include an image sensing pixel array including a plurality of image sensing pixels operable to respond to light and to produce imaging pixel signals, and a first grid structure disposed between image sensing pixels to separate adjacent image sensing pixels. The image sensing pixel array is structured to include a center area located at or near a center of the image sensing pixel array, first and second diagonal edge areas disposed on opposite sides of the center area in a first diagonal direction, and third and fourth diagonal edge areas disposed on opposite sides of the center area in a second diagonal direction that is different from the first diagonal direction. The first grid structure includes a bent portion in at least one of the first to fourth diagonal edge areas to cover one vertex and adjacent parts of each image sensing pixel. | 2021-11-25 |
20210366970 | IMAGE SENSOR DEVICE - Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die. | 2021-11-25 |
20210366971 | FABRICATION METHOD OF PHOTODETECTOR AND IMAGING SENSOR - Method for fabricating a photodetector includes providing a first substrate containing pixel circuits and common electrode connection members formed therein. A first wring board material layer is formed on the first substrate and electrically connected to the pixel circuits. A second wiring board material layer is formed on a second substrate and electrically connected to the pixel layers formed therein. The first and second wiring board material layers are bonded. The second substrate, and the second and first wiring board material layers are etched to form through holes with isolation wall members formed therein, the through holes dividing the pixel layer, and the second and first wiring board material layers into pixel units, and second and first wiring boards. Each isolation wall member includes a conductive member and a sidewall between the conductive member and the pixel unit. A transparent electrode layer is formed on the second substrate. | 2021-11-25 |
20210366972 | COMPACT PROXIMITY FOCUSED IMAGE SENSOR - An image sensor has a photocathode window assembly, an anode assembly, and a malleable metal seal. The photocathode window assembly has a photocathode layer. The anode assembly includes a silicon substrate that has an electron sensitive surface. The malleable metal seal bonds the photocathode window assembly and the silicon substrate to each other. A vacuum gap separates the photocathode layer from the electron sensitive surface. A first electrical connection and a second electrical connection are for a voltage bias of the photocathode layer relative to the electron sensitive surface. | 2021-11-25 |
20210366973 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - Provided are a solid-state imaging device and an electronic apparatus with further improved performance. The solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other. The solid-state imaging device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or the third multi-layered wiring layer to each other. The one through hole is provided by penetrating at least the first substrate from a back surface side of the first substrate. | 2021-11-25 |
20210366974 | THREE-DIMENSIONAL IMAGE SENSOR BASED ON STRUCTURED LIGHT - The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer. | 2021-11-25 |
20210366975 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. | 2021-11-25 |
20210366976 | STACKED PIXEL STRUCTURE FORMED USING EPITAXY - Generally, examples described herein relate to methods and processing chambers and systems for forming a stacked pixel structure using epitaxial growth processes and device structures formed thereby. In an example, a first sensor layer is epitaxially grown on a crystalline surface on a substrate. A first isolation structure is epitaxially grown on the first sensor layer. A second sensor layer is epitaxially grown on the first isolation structure. A second isolation structure is epitaxially grown on the second sensor layer. A third sensor layer is epitaxially grown on the second isolation structure. | 2021-11-25 |
20210366977 | METHOD FOR MANUFACTURING A MICROLENS - A resist layer is applied on a carrier, an opening with an overhanging or re-entrant sidewall is formed in the resist layer, the carrier being uncovered in the opening, a lens material is deposited, thus forming a lens on the carrier in the opening, and the resist layer is removed. | 2021-11-25 |
20210366978 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE LIGHT EMITTING DEVICE - A light-emitting device includes: a substrate; a unit light-emitting area disposed on the substrate; first and second electrodes disposed in the unit light-emitting area to be separated from each other; a plurality of rod-shaped LEDs disposed between the first and second electrodes; a reflective contact electrode disposed on opposite ends of the rod-shaped LEDs to electrically connect the rod-shaped LEDs to the first and second electrodes; and a light-transmitting structure disposed between the first and second electrodes and extending to cross the rod-shaped LEDs. | 2021-11-25 |
20210366979 | OPTOELECTRONIC DEVICE WITH ELECTRONIC COMPONENTS AT THE LEVEL OF THE REAR FACE OF THE SUBSTRATE AND MANUFACTURING METHOD - An optoelectronic device having a substrate and a plurality of sets of light-emitting diodes where each set includes a plurality of light-emitting diodes, a first lower electrode, a second upper electrode, an electronic component of an electronic circuit formed in a first portion of the substrate, on the side of the face of the substrate that does not bear the light-emitting diodes, and a first conductive means formed through the first portion and electrically connecting a first terminal of the electronic component to one amongst the first and second electrodes. The first conductive means of a given set is electrically-insulated from the first conductive means of the other sets. | 2021-11-25 |
20210366980 | LIGHT-EMITTING DEVICE, LIGHT SOURCE MODULE, AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE - A light-emitting device is provided. The light emitting device includes a support substrate having a light-emitting cell region, a pad region and an edge region, the edge region surrounding the light-emitting cell region and the pad region; a plurality of unit light-emitting devices arranged in a matrix in the light-emitting cell region and spaced apart from each other; a plurality of pads formed in the pad region; partition walls arranged on the plurality of unit light-emitting devices, the partition walls defining a plurality of cell spaces respectively corresponding to the plurality of unit light-emitting devices; and a plurality of fluorescent layers arranged on the plurality of unit light-emitting devices in the plurality of cell spaces. The light-emitting device has a cuboid shape, in which a first length in a first direction is greater than a second length in a second direction. | 2021-11-25 |
20210366981 | LED DISPLAY APPARATUS - A display device includes a circuit substrate including a driving circuit; an LED cell array disposed on the circuit substrate, and including a plurality of LED modules, each of the plurality of LED modules including at least two LED cells, from among a plurality of LED cells of the LED cell array, and an insulator coupling the at least two LED cells to each other; a gap-fill layer filling a gap between the plurality of LED modules; a partition disposed on the LED cell array, and defining a plurality of light emitting windows disposed in regions corresponding to the plurality of LED cells, respectively; and at least one color conversion layer disposed in at least a portion of the plurality of light emitting windows. | 2021-11-25 |
20210366982 | SEMICONDUCTOR LIGHT-EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor light-emitting device includes a light-emitting pixel region and a pad region, and includes light-emitting structures, a partition wall structure, a passivation structure, and a fluorescent layer, positioned in the light-emitting pixel region, and a pad unit positioned in the pad region. The partition wall structure includes partition walls defining pixel spaces. The passivation structure surrounds the partition walls and includes a first passivation layer including a first insulating material and a second passivation layer including a second insulating material different from the first insulating material. The passivation structure includes a first portion on a top surface of the partition walls, a second portion on a sidewall of the partition walls, and a third portion between the light-emitting structures and the fluorescent layer. A first thickness of the first portion is less than or equal to a second thickness of the second portion. | 2021-11-25 |
20210366983 | METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE WITH SELF-ALIGNING LIGHT-CONFINEMENT WALLS - The manufacture of an optoelectronic device includes the formation of wire-like shaped light-emitting diodes and the formation of spacing walls transparent to the light radiation originating from the diodes. The lateral sidewalls of each diode are surrounded by at least one of the spacing walls. Light confinement walls directly cover the lateral sidewalls of the spacing walls by being in contact with the latter. The radiation originating from each diode and directed in the direction of the adjacent diodes is blocked by the confinement wall. The upper borders of the diodes are covered by the light confinement material so as to ensure a light extraction by the rear face of the optoelectronic device. An optoelectronic device is also described as such. | 2021-11-25 |
20210366984 | SOI SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING AN SOI SEMICONDUCTOR STRUCTURE - An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type. | 2021-11-25 |
20210366985 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a transistor and a memory device. The transistor includes a gate stack and a nanosheet penetrating through the gate stack. The memory device has a first portion and a second portion. A first portion of the gate stack is sandwiched between the first portion and the second portion of the memory device. | 2021-11-25 |
20210366986 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region. | 2021-11-25 |
20210366987 | 3D RRAM CELL STRUCTURE FOR REDUCING FORMING AND SET VOLTAGES - An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell. | 2021-11-25 |
20210366988 | INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device. | 2021-11-25 |
20210366989 | THIN FILM TRANSISTOR, MANUFACTURING METHOD OF SAME, AND CMOS INVERTER - A thin film transistor, a manufacturing method of the same, and a CMOS inverter are provided. The thin film transistor includes a base substrate, a dielectric layer, and a semiconductor layer. A first channel is provided between the source and the drain. Carbon nanotubes are provided in the first channel. A second channel is provided between the drain and the gate. An ion gel is provided in the second channel. By regulating a composition of the ion gel and a content of a dopant, a threshold voltage of a carbon nanotube thin film transistor is effectively controlled. | 2021-11-25 |
20210366990 | DISPLAY PANEL AND FABRICATING METHOD THEREOF - A display panel and a fabricating method thereof are provided. The display panel includes: a substrate; and an array of pixels on the substrate, each pixel having a sub-pixel region and a photosensitive region, wherein the sub-pixel region includes a light emitting structure; the photosensitive region is configured to sense light emitted by the light emitting structure and reflected by a finger; and the photosensitive region includes a photosensitive thin film transistor having a vertical channel with respect to the substrate. | 2021-11-25 |
20210366991 | ORGANIC IMAGE SENSORS WITHOUT COLOR FILTERS - An organic image sensor may be configured to obtain a color signal associated with a particular wavelength spectrum of light absorbed by the organic image sensor may omit a color filter. The organic image sensor may include an organic photoelectric conversion layer including a first material and a second material. The first material may absorb a first wavelength spectrum of light, and the second material may absorb a second wavelength spectrum of light. The organic photoelectric conversion layer may include stacked upper and lower layers, and the respective material compositions of the lower and upper layers may be first and second mixtures of the first and second materials. A ratio of the first material to the second material in the first mixture may be greater than 1/1, and a ratio of the first material to the second material in the second mixture may be less than 1/1. | 2021-11-25 |
20210366992 | IMAGING DEVICE - An imaging device including: a semiconductor substrate including a pixel region and a peripheral region; an insulating layer that covers the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer that covers the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry configured to be electrically connected to the first electrodes; peripheral circuitry configured to be electrically connected to the detection circuitry, and including analog circuitry; and a third electrode electrically connected to the second electrode. The third electrode overlaps the analog circuitry in a plan view, and in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the third electrode, no transistor of the digital circuitry is located directly below the third electrode. | 2021-11-25 |
20210366993 | OLED DISPLAY PANEL AND MANUFATURING METHOD THEREOF - An organic light emitting diode (OLED) display panel and a manufacturing method thereof are provided. The OLED display panel includes a display device substrate, an encapsulation layer disposed on the display device substrate, and a color filter substrate disposed on the encapsulation layer. The display device substrate includes a display zone; and the color filter substrate includes a light-transmitting zone corresponding to a display zone, and a shading zone. The light-transmitting zone on the color filter substrate is provided with a scattering structure including a plurality of bulges to scatter ambient light. | 2021-11-25 |
20210366994 | OLED DEVICE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY PANEL - Embodiments of the present disclosure provide an OLED device, a method of manufacturing the OLED device, and a display panel. The OLED device comprises: a substrate, a first electrode layer, a color filter layer, a light emitting layer and a second electrode layer. The first electrode layer is one of an anode layer and a cathode layer and comprises: a first sub-electrode layer disposed on the substrate; and a second sub-electrode layer electrically connected with the first sub-electrode layer. The color filter layer is disposed on the first sub-electrode layer and the second sub-electrode layer is disposed on the color filter layer. The second electrode layer is the other of the anode layer and the cathode layer and the light emitting layer is disposed between the second electrode layer and the second sub-electrode layer of the first electrode layer. | 2021-11-25 |
20210366995 | WHITE OLED DISPLAY DEVICE AND METHOD OF MANUFACTURING SAME - A white organic light emitting diode (OLED) display device and a method of manufacturing the same are provided. By making an organic fluorescent color conversion film including a first conversion film and a second conversion film respectively disposed on a green color resist and a red color resist, the first conversion film converts cyan light into green light, and the second conversion film converts yellow orange light into red light. This can improve color gamut and color conversion rate of the white OLED display device and improve density of the organic color conversion film and stability of a device. | 2021-11-25 |
20210366996 | DISPLAY PANEL AND ELECTRONIC DEVICE - The present application provides a display panel and an electronic device. The display panel includes a control circuit, a light emitting layer, a color film layer, and a cover plate, wherein the color film layer is disposed between the light emitting layer and the cover plate, and the color film layer comprises a photosensitive region comprising a plurality of color film units and a plurality of photosensors which are spaced apart. Wherein, a first light shielding film is disposed on surfaces of the plurality of photosensors facing the light emitting layer. | 2021-11-25 |
20210366997 | LIGHT-EMITTING DEVICE AND IMAGE DISPLAY APPARATUS INCLUDING THE SAME - It is an object of the present invention to provide an image display apparatus capable of inhibiting or preventing the deterioration of a light conversion layer while high luminous efficiency and high color reproducibility are achieved. The present invention provides a light-emitting device including a pair of electrodes, an electroluminescent layer disposed between a first electrode and a second electrode, a light conversion layer including multiple pixels and converting light that is emitted from the electroluminescent layer and that has a blue emission spectrum into light having a different wavelength. The light conversion layer includes pixels of three primary colors of red (R), green (G), and blue (B) and contains a light-emitting nanocrystal having an emission spectrum in any of red (R), green (G), and blue (B) when light from the electroluminescent layer is incident on at least one of the three primary colors. | 2021-11-25 |
20210366998 | DISPLAY DEVICE - A display device including a display panel including a light emitting element configured to generate light, and an input detection layer disposed on the display panel and including a plurality of sensing electrodes disposed on the display panel and arranged in one direction, and a plurality of trace lines electrically connected to the plurality of sensing electrodes, respectively, in which at least one of the trace lines includes a single layer part including one conductive layer, and a multilayer part including at least two conductive layers disposed on different layers. | 2021-11-25 |
20210366999 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a display device with a display panel, an input sensing unit, and a protective member. The input sensing unit is disposed on the display panel. The protective member includes an insulating material and is disposed on the input sensing unit. The protective member includes a first protective portion and a second protective portion disposed on the first protective portion, where a first modulus of the first protective portion is greater than a second modulus of the second protective portion. The second protective portion with the lower modulus absorbs external impacts, and the protective portion with the higher modulus disperses the absorbed impact and prevents the display panel from being deformed by an external force. Therefore, the impact resistance of the display device is improved. | 2021-11-25 |
20210367000 | DISPLAY DEVICE - A display device includes a display panel including a hole area, a display area around the hole area, and a non-display area around the display area, a first-first insulating layer disposed in the hole area, sensing electrodes disposed on the display area, a crack detection pattern disposed on the first-first insulating layer in the hole area, a crack detection line disposed on the non-display area, and a connection pattern disposed in a first sensing electrode of the sensing electrodes disposed on the display area to be insulated from the sensing electrodes, and connected to the crack detection pattern and the crack detection line, the first sensing electrode being disposed between the hole area and the non-display area. An edge of the first-first insulating layer disposed at a boundary between the display area and the hole area has a step structure of at least two steps. | 2021-11-25 |
20210367001 | OLED TOUCH AND DISPLAY DRIVER INTEGRATION CHIP AND OLED TOUCH DISPLAY APPARATUS INCLUDING THEREOF - An OLED touch and display driver integration chip is provided, including: at least one group of display driving pads for providing display driving signals to the OLED touch display panel; at least one group of touch pads for providing touch driving signals to touch electrodes on the OLED touch display panel, and alternately arranged in groups with the at least one group of display driving pads; at least one group of isolation pads, each group of isolation pads includes at least one isolation pad and is arranged between a group of display driving pads and a group of touch pads that are adjacent, an isolation pad is configured to apply a specific signal to isolate signal interference between adjacent groups of display driving pads and touch pads, or configured to apply a specific signal or be in a floating state, to reduce load of data lines or the touch electrodes. | 2021-11-25 |
20210367002 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel a display device are provided. The display panel includes a plurality of pixel units arranged in a row direction and in a column direction, the display panel includes a display region. An edge of the display region includes a fold line formed by connecting a line segment extending in the row direction and a line segment extending in the column direction, a parallelogram region formed in the display region taking two adjacent line segments as adjacent sides includes the pixel units; directions from an intersection point of the two adjacent line segments to end points of the two adjacent line segments other than those at the intersection point are a first direction and a second direction, respectively; in the parallelogram region, aperture ratios of the pixel units arranged in at least one of the first direction and the second direction increase gradually. | 2021-11-25 |
20210367003 | DISPLAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING DISPLAY SUBSTRATE - The present application provides a display substrate having a plurality of subpixel areas. The display substrate includes a base substrate; a first electrode layer on the base substrate and including a plurality of first electrodes respectively in the plurality of subpixel areas; an auxiliary electrode layer; and an insulating layer between the first electrode layer and the auxiliary electrode layer. The first electrode layer and the auxiliary electrode layer are spaced apart and insulated from each other by the insulating layer. An orthographic projection of each individual one of the plurality of first electrodes on the base substrate at least partially overlap with an orthographic projection of the auxiliary electrode layer on the base substrate. Each of the plurality of first electrodes is electrically connected to a pixel circuit configured to drive light emission in a respective one of the plurality of subpixel areas. | 2021-11-25 |
20210367004 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes a display region and a sensor region. The sensor region is provided with multiple sensors in the display panel. Multiple first pixels are arranged in the display region. The first pixels are arranged as a first array in the display region. Multiple second pixels are arranged in the sensor region, and the second pixels are arranged as a second array in the sensor region. A pixel unit area of the first array is equal to a pixel unit area of the second array, and the pixel unit area is a number of the pixels multiplied by an area of each pixel in a unit area. The display device includes the display panel and the sensors. The sensors are disposed on one side of the display panel. | 2021-11-25 |
20210367005 | TRANSPARENT DISPLAY PANEL AND DISPLAY DEVICE - A transparent display panel and a display device are disclosed. The orthographic projection of light-emitting region of electroluminescent structure on a base substrate overlaps with the orthographic projection of the region of the pixel circuit on the base substrate to form an overlap region, so that the area occupied by the electroluminescent structures in the sub-pixels is enlarged, thus increasing the pixel aperture ratio of the transparent display panel at the sides, away from the pixel circuits, of the electroluminescent structures. | 2021-11-25 |
20210367006 | Camera in Display - A display with both sensing diodes and emitting diodes constructed on a common backplane, where each sensing diode includes a lens having a focal length configured for a particular imaging distance from the display is presented herein. The sensing diodes may be used to detect environmental characteristics, e.g., light levels, presence of a user, etc., where the sensing and/or emitting diodes are then configured responsive to the detected environmental characteristics. | 2021-11-25 |
20210367007 | DISPLAY PANEL AND DISPLAY DEVICE - The present invention provides a display panel and a display device, the display panel has an array substrate, and the array substrate has a substrate, a first inorganic film layer, at least one auxiliary cathode, a second inorganic film layer, and at least one via hole. The via hole is arranged in at least two voltage drop regions that are arranged sequentially. The via hole in each of the voltage drop regions is distributed evenly. A first voltage drop region is disposed opposite to a center or a side edge of the substrate. | 2021-11-25 |
20210367008 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - A display substrate and a manufacturing method thereof, and a display panel are provided. The display substrate includes a first insulating layer, a pixel defining layer, a first electrode layer and organic light-emitting functional layers, the pixel defining layer is located at a side of the first insulating layer, a plurality of first openings in the first insulating layer are in a one-to-one correspondence relationship with and communicate with a plurality of second openings in the pixel defining layer, the plurality of organic light-emitting functional layers are located in the second opening, the first electrode layer is located at a side of the first insulating layer opposite to the pixel defining layer, and an orthographic projection of the first insulating layer on a plane where the display substrate is located at least partially overlaps with an orthographic projection of a peripheral region of the second openings on the plane. | 2021-11-25 |
20210367009 | ORGANIC LIGHT-EMIITING DIODE DISPLAY - The present application provides an organic light-emitting diode display. The display includes a plurality of pixel defining units, the pixel defining unit includes a first portion formed on a switch array layer which is not covered by anode electrodes and a second portion formed on the anode electrode, a groove is defined at the first portion, and at least one opening is defined at the second portion; an organic light-emitting layer including a plurality of organic light-emitting units, the organic light-emitting layer is formed on the anode electrodes which are not covered by the second portion. | 2021-11-25 |
20210367010 | DISPLAY PANEL AND MANUFACTURING METHOD OF DISPLAY PANEL - A display panel and a manufacturing method of a display panel are provided. The display panel includes an, a plurality of pixel definition portions, and a plurality of light-emitting portions. The plurality of pixel definition portions are disposed on the array substrate and separated apart from each other. A quantum dot material is provided on a side of one of the pixel definition portions, and the side of the pixel definition portions faces an adjacent pixel definition portion. Each of the light-emitting portions is disposed between two adjacent pixel definition portions, the light-emitting portions are configured to emit light, and the quantum dot material on the side of the pixel definition portion is illuminated under excitation of the light. | 2021-11-25 |
20210367011 | OLED DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND OLED DISPLAY - The present application discloses an OLED display panel, a manufacturing method thereof, and an OLED display. In this application, by designing that heights of the first bank and the second bank are greater than the height of the third bank, the higher first bank and second bank can block the ink of a large amount for thicker film in the first grooves as much as possible, and in addition, it is also beneficial to block the ink of a small amount for a thinner film to prevent it from flowing toward the first grooves, so as to prevent mixing between inks in which different organic light-emitting materials are dissolved, and thus prevent OLED display panels from the problem of poor light emission such as pixel color shift and color mixing. | 2021-11-25 |
20210367012 | METHOD FOR MANUFACTURING PIXEL DEFINITION LAYER AND DISPLAY PANEL, AND DISPLAY PANEL - A method for manufacturing the pixel definition layer includes forming a photolithographic material film on a substrate; performing a pre-drying treatment, a first exposure treatment, and a development treatment sequentially on the photolithographic material film to form an initial pattern of the pixel definition layer; and performing a second exposure treatment and a curing treatment sequentially on the initial pattern to form a final pattern of the pixel definition layer. | 2021-11-25 |
20210367013 | ELECTRONIC DEVICE AND DISPLAY APPARATUS - An electronic device and a display apparatus are disclosed, wherein the electronic device includes a display apparatus and a camera module. The display apparatus includes a pixel definition layer, an organic light emitter, a common electrode layer, and a filling layer; the common electrode layer covers the organic light emitter and the pixel definition layer; a filling member of the filling layer is provided on one side of the common electrode layer away from the organic light emitter and provided opposite to a pixel hole; a difference between the refractive indexes of the pixel definition layer and the filling member is smaller than the difference between the refractive indexes of the pixel definition layer and vacuum; and the camera module acquires an image through the display apparatus. | 2021-11-25 |
20210367014 | DISPLAY DEVICE - Disclosed is a display device possessing: a substrate having a display region and a peripheral region surrounding the display region; a pixel over the display region; a passivation film over the pixel; a resin layer over the passivation film; a first dam over the peripheral region and surrounding the display region; and a second dam surrounding the first dam. The passivation film includes; a first layer containing an inorganic compound; a second layer over the first layer, the second layer containing an organic compound; and a third layer over the second layer, the third layer containing an inorganic compound. The second layer is selectively arranged in a region surrounded by the first dam. The resin layer is selectively arranged in a region surrounded by the second dam. | 2021-11-25 |
20210367015 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a planarization layer disposed on a substrate, a first electrode disposed on the planarization layer and including silver (Ag), a contact preventing layer disposed on the first electrode, including a light absorbing material, and including a top surface and a side surface extending from an end of the top surface, and a pixel defining layer disposed on the contact preventing layer and including a bottom surface facing the top surface of the contact preventing layer, and a side surface extending from an end of the bottom surface. The first electrode includes a first region overlapping pixel defining layer. The contact preventing layer includes a second region overlapping the first region between the first electrode and the pixel defining layer. A first edge where the top and side surfaces of the contact preventing layer meet is located on the bottom surface of the pixel defining layer. | 2021-11-25 |
20210367016 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY PANEL THEREOF - The present invention relates to a thin film transistor, an array substrate and a display panel thereof. The present invention obtains SiNx layers with different densities and hydrogen contents by adjusting a SiNx film forming process of an interlayered insulating layer in a thin film transistor. The second layer having a lower density has a higher hydrogen content, but has a poor hydrogen barrier capability, while the first layer having a higher density has less hydrogen content, but has a better hydrogen barrier capability. Through a combination of SiNx layers having different densities, the hydrogen replenishment capability can be differentiated, thereby achieving different degrees of adjustment of electrical properties of the low-temperature polysilicon thin film transistor, simplifying the channel doping process, thus reducing the production cost. | 2021-11-25 |
20210367017 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - An array substrate, a method for manufacturing the array substrate and a display device are provided. The array substrate includes: a base substrate, and a thin film transistor, a storage capacitor, and a lapping pattern for connecting the thin film transistor to the storage capacitor arranged on the base substrate; wherein the thin film transistor includes a semiconductor layer, a gate insulation layer, a gate electrode, an interlayer insulation layer, a source electrode and a drain electrode arranged sequentially in that order; the interlayer insulation layer includes at least two inorganic insulation layers and at least one organic insulation layer laminated one on another, and both a layer proximate to the base substrate and a layer distal to the base substrate in the interlayer insulation layer are the inorganic insulation layers. | 2021-11-25 |
20210367018 | ORGANIC EL DISPLAY APPARATUS AND METHOD OF MANUFACTURING ORGANIC EL DISPLAY APPARATUS - The present invention is equipped with: a substrate ( | 2021-11-25 |
20210367019 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a substrate, a thin film transistor located on the substrate, a light emitting device located on the substrate and spaced apart from the thin film transistor in a direction parallel to a surface of the substrate, and a light shielding portion located between the thin film transistor and the light emitting device for shielding a light from the light emitting device. The light shielding portion surrounds the light emitting layer. | 2021-11-25 |
20210367020 | FOLDABLE DISPLAY DEVICE, ROLLABLE DISPLAY DEVICE, AND DISPLAY DEVICE - A foldable display device includes a display panel including a front surface and a rear surface opposite the front surface, the front surface including a first component area including a first transmissive portion, a second component area including a second transmissive portion, and a main display area at least partially surrounding the first component area and the second component area, wherein, in a state in which the foldable display device is folded about a first folding axis that crosses the main display area such that two areas of the front surface or two areas of the rear surface face each other, the first component area and the second component area overlap each other on a plane. | 2021-11-25 |
20210367021 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit and pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels includes a first sub-pixel, and the display substrate further includes a first data line extended in the first direction and connected with the first sub-pixel. The sub-pixels further includes a second sub-pixel directly adjacent to the first sub-pixel in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other; and the first capacitor electrode in the first sub-pixel is overlapped with the first data line in a direction perpendicular to the base substrate to provide a first capacitor. | 2021-11-25 |
20210367022 | DOUBLE-SIDED DISPLAY PANEL AND PREPARATION METHOD THEREOF - A double-sided display panel includes a base substrate, a thin film transistor array, a first OLED light emitting layer located in a top light emitting area and a second OLED light emitting layer located in a bottom light emitting area; the thin film transistor array is located in the top light emitting area; a thin film transistor of the thin film transistor array simultaneously controls a top light emitting subpixel and a bottom light emitting subpixel. Through one OLED back plate to realize double-sided simultaneous display, can reduce whole thickness of the OLED double-sided display panel, simplify manufacturing process, thereby saving manufacturing costs. | 2021-11-25 |
20210367023 | DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - A display substrate includes a source-drain metal layer and a common electrode layer. A pattern of the source-drain metal layer includes a power supply voltage line; the power supply voltage line includes a wire inlet portion; the display substrate further includes a barrier wall, there is a gap between an orthographic projection of the barrier wall on the base substrate and an orthographic projection of the effective display area on the base substrate. The wire inlet portion includes a first part and a second part; an orthographic projection of the first part on the base substrate and an orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at a side of the barrier wall away from the effective display area and located between the barrier wall and the binding area, and used for receiving power supply voltage signal. | 2021-11-25 |
20210367024 | DISPLAY DEVICE - A display device including: a substrate; a conductive layer on the substrate and including a first voltage line and a second voltage line extending in a first direction; a first electrode and a second electrode on the conductive layer, extending in the first direction, and spaced apart from each other; a plurality of light-emitting elements on the first electrode and the second electrode; and an electrode pattern on the conductive layer and separated from the first electrode. The electrode pattern overlaps the first voltage line in a thickness direction and directly contacts the first voltage line. | 2021-11-25 |
20210367025 | ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides an array substrate and a display device. The array substrate includes: a sub-pixel, in a display region and including a light-emitting element, the light-emitting element including a first electrode, a light-emitting layer and a second electrode; a positive power line, connected to the first electrode; a positive power bus, connected to the positive power line; three positive power access ends, at a side of the positive power bus away from a display region, and respectively connected to the positive power bus; a negative power line; an auxiliary electrode, respectively connected to the negative power line and the second electrode; three negative power access ends, at the side of the positive power bus away from the display region, and respectively connected to the negative power line; and a negative power auxiliary line, respectively connected to the negative power access end and the auxiliary electrode. | 2021-11-25 |
20210367026 | ARRAY SUBSTRATE, DISPLAY APPARATUS, METHOD OF REDUCING CURRENT-RESISTANCE DROP AND DATA LOSS IN DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE - The present application provides an array substrate. The array substrate includes a base substrate; a plurality of light emitting elements on the base substrate; a plurality of driving thin film transistors for driving light emission of the plurality of light emitting elements, each of the plurality of driving thin film transistors including a first active layer; one or more power supply lines configured to supply a driving current respectively to the plurality of light emitting elements; and a light shielding layer configured to shield light from irradiating on the first active layer, the light shielding layer being electrically connected to at least one of the one or more power supply lines. | 2021-11-25 |
20210367027 | DISPLAY DEVICE - In a display region, each first power-source line and each second power-source line intersecting with the first power-source line are electrically connected together via a contact hole in a second inorganic insulating film. In addition, each source line and each second power-source line intersect with each other via the second inorganic insulating film and a first organic insulating film. | 2021-11-25 |
20210367028 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE - A termination structure in which a semiconductor active region is surrounded with a guard ring and capable of preventing corrosion of a metal layer connected to the guard ring includes: an active region and a guard ring region surrounding the active region. A guard ring is formed on the semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate so as to cover the guard ring. A field plate is disposed on the interlayer insulating film and is electrically connected to the guard ring via a contact penetrating the interlayer insulating film. A protective film covers the field plate, which has a laminated structure including a first metal in contact with the guard ring and a second metal which is disposed in contact with the first metal and has a lower standard potential than the first metal. | 2021-11-25 |
20210367029 | SUPERJUNCTION POWER SEMICONDUCTOR DEVICES FORMED VIA ION IMPLANTATION CHANNELING TECHNIQUES AND RELATED METHODS - Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/−1.5° of a crystallographic axis of the silicon carbide material forming the drift region. | 2021-11-25 |
20210367030 | DEVICE ISOLATOR WITH REDUCED PARASITIC CAPACITANCE - Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator. | 2021-11-25 |
20210367031 | BJT Device Structure and Method for Making the Same - The present application provides a BJT device structure and a method for making the same, the structure comprising an N+ region located on a P-well; a barrier layer structure located on the N+ region, the barrier layer structure being a frame structure surrounding the periphery of the N+ region, wherein a region in the barrier layer structure is an emitter region, a plurality of mutually spaced STI regions are provided on the N+ region of the emitter region; a base region located at the periphery of the emitter region; and a collector region located at the periphery of the base region. The STI region of the emitter region of the BJT device structure of the present application is a discontinuous structure, which can significantly reduce a recombination current of the emitter region and the base region, thereby effectively increasing the amplification factor of the BJT device. | 2021-11-25 |
20210367032 | SOURCE/DRAIN ISOLATION STRUCTURES FOR LEAKAGE PREVENTION - The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers. | 2021-11-25 |
20210367033 | SHALLOW TRENCH ISOLATION (STI) CONTACT STRUCTURES AND METHODS OF FORMING SAME - A method of forming a semiconductor device includes forming a first semiconductor strip protruding above a first region of a substrate and a second semiconductor strip protruding above a second region of the substrate, forming an isolation region between the first semiconductor strip and the second semiconductor strip, forming a gate stack over and along sidewalls of the first semiconductor strip and the second semiconductor strip, etching a trench extending into the gate stack and isolation regions, the trench exposing the first region of the substrate and the second region of the substrate, forming a dielectric layer on sidewalls and a bottom surface of the trench and filling a conductive material over the dielectric layer and in the trench to form a contact, where the contact extends below a bottommost surface of the isolation region. | 2021-11-25 |
20210367034 | MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature. | 2021-11-25 |
20210367035 | SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS - Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise source, drain and gate finger electrodes on active regions of a plurality of sections of a multi-section transistor, and a contact structure comprising source and drain contact areas, e.g. drain and source pads extending over active regions of each section, interconnected by conductive micro-vias to respective underlying drain and source finger electrodes. Alternatively, source contact areas comprise parts of a source bus which runs over inactive regions. For reduced gate loop inductance, the source bus may be routed over or under the to gate bus. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of the drain finger electrodes. Example CUP device structures provide for higher current carrying capability and reduced drain-source resistance. | 2021-11-25 |
20210367036 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width. | 2021-11-25 |
20210367037 | INTEGRATED CIRCUIT STRUCTURE - An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin. | 2021-11-25 |
20210367038 | Semiconductor Device with Implant and Method of Manufacturing Same - A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 10 | 2021-11-25 |
20210367039 | POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A power semiconductor device includes a semiconductor layer of SiC, a gate insulating layer, a gate electrode layer, a drift region including at least one protruding portion in the semiconductor layer and having a first conductivity type, a well region including a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type, a source region including a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type, and a channel region under the gate electrode layer, in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type. | 2021-11-25 |
20210367040 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region. | 2021-11-25 |
20210367041 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a first conductive semiconductor layer; an active layer; and a second conductive semiconductor layer, wherein the semiconductor device includes first to fourth points that are defined by using In ion intensity, Si concentration, and C concentration which are obtained from SIMS data. The active layer may be a first region between the first point and the second point. The C concentration in a third region between the third point and the fourth point may be higher than the C concentration in a second region adjacent to the fourth region along a second direction. The Si concentration in the second region may be higher than the Si concentration in the third region. | 2021-11-25 |
20210367042 | Semiconductor Device and Method of Manufacture - Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack. | 2021-11-25 |
20210367043 | VERTICAL INTERCONNECT FEATURES AND METHODS OF FORMING - Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled. | 2021-11-25 |
20210367044 | TRANSISTOR WITH FIELD PLATE OVER TAPERED TRENCH ISOLATION - An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees. | 2021-11-25 |
20210367045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The disclosure relates to a semiconductor device having a first active region, a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively, a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively, and a first additional gate region, wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region, and a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction, and wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region. | 2021-11-25 |
20210367046 | SEMICONDUCTOR MANUFACTURING PLATFORM WITH IN-SITU ELECTRICAL BIAS AND METHODS THEREOF - A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage. | 2021-11-25 |
20210367047 | GROUP III-NITRIDE (III-N) DEVICES WITH REDUCED CONTACT RESISTANCE AND THEIR METHODS OF FABRICATION - A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure. | 2021-11-25 |
20210367048 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, first and second conductive members disposed on opposite sides of the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a surface electrode and gate wirings. The semiconductor substrate has active regions formed with elements, and an inactive region not formed with an element. The inactive region includes an inter-inactive portion disposed between at least two active regions and an outer peripheral inactive portion disposed on an outer periphery of the at least two active regions. The surface electrode is disposed to continuously extend above the at least two active regions and the inter-inactive portion. The gate wirings are disposed above the inactive region, and include a first gate wiring disposed on an outer periphery of the surface electrode, and a second gate electrode disposed at a position facing the surface electrode. | 2021-11-25 |
20210367049 | INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME - An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points. | 2021-11-25 |
20210367050 | Source/Drain Contacts For Semiconductor Devices And Methods Of Forming - A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers. | 2021-11-25 |
20210367051 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit. | 2021-11-25 |
20210367052 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - The present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source drain layer, and a planarization layer. The gate insulating layer is formed on the active layer and the buffer layer. The interlayer dielectric layer is formed on the gate layer and the gate insulating layer. The source drain layer is patterned to form a source and a drain, and is connected to the active layer through via holes. The planarization layer in the present invention is easier to fill in. | 2021-11-25 |
20210367053 | Semiconductor Devices - A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane. | 2021-11-25 |