| 47th week of 2021 patent applcation highlights part 61 |
| Patent application number | Title | Published |
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| 20210366854 | Chiplets 3D SoIC System Integration and Fabrication Methods - A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip. | 2021-11-25 |
| 20210366855 | SEMICONDUCTOR DIE CONTAINING DUMMY METALLIC PADS AND METHODS OF FORMING THE SAME - A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric layers embedding first metal interconnect structures and located over the first semiconductor devices, a first pad-level dielectric layer embedding first bonding pads and located over the first interconnect-level dielectric layers, and first edge seal structures laterally surrounding the first semiconductor devices. Each of the first edge seal structures vertically extends from the first substrate to a distal surface of the first pad-level dielectric layer, and includes a respective first pad-level ring structure that continuously extends around the first semiconductor devices. At least one row of first dummy metal pads is embedded in the first pad-level dielectric layer between a respective pair of first edge seal structures. Second pad-level ring structures embedded in a second semiconductor die can be bonded to the rows of first dummy metal pads. | 2021-11-25 |
| 20210366856 | SEMICONDUCTOR DEVICE INCLUDING STACKED SUBSTRATE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a second semiconductor substrate vertically stacked on a first semiconductor substrate. The first semiconductor substrate includes a first diffusion barrier layer covering a first surface of a first semiconductor substrate body, and a first through via having a third surface exposed to a second surface of the first diffusion barrier layer. The second semiconductor substrate includes a second semiconductor substrate body, a second diffusion barrier layer directly bonded to a surface of the first diffusion barrier layer, and a front pad having a smaller surface area than the third surface of the first through via and directly bonded to the third surface of the first through via. | 2021-11-25 |
| 20210366857 | 3d-Interconnect - A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces. | 2021-11-25 |
| 20210366858 | SEMICONDUCTOR PACKAGE USING CORE MATERIAL FOR REVERSE REFLOW - Provided is a semiconductor package including a first bump pad on a first substrate, a second bump pad on a second substrate, a core material for reverse reflow between the first bump pad and the second bump pad, and a solder member forming a solder layer on the core material for reverse reflow. The solder member is in contact with the first bump pad and the second bump pad. Each of a first diameter of the first bump pad and a second diameter of the second bump pad is at least about 1.1 times greater than a third diameter of the core material for reverse reflow. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer. | 2021-11-25 |
| 20210366859 | SEMICONDUCTOR DEVICE PACKAGES WITH ANGLED PILLARS FOR DECREASING STRESS - Semiconductor devices having mechanical pillar structures, such as angled pillars, that are rectangular and orientated with respect to a semiconductor die to reduce bending stress and in-plane shear stress at a semiconductor die to which the angled pillars are attached, and associated systems and methods, are disclosed herein. The semiconductor device can include angled pillars connected to the semiconductor die and to a package substrate. The angled pillars can be configured such that they are orientated relative to a direction of local stress to increase section modulus. | 2021-11-25 |
| 20210366860 | ARCHITECTURE TO MANAGE FLI BUMP HEIGHT DELTA AND RELIABILITY NEEDS FOR MIXED EMIB PITCHES - Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads. | 2021-11-25 |
| 20210366861 | Hybrid Thermal Interface Material and Low Temperature Solder Patterns to Improve Package Warpage and Reliability - Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure. | 2021-11-25 |
| 20210366862 | ELECTRONIC PACKAGE WITH STUD BUMP ELECTRICAL CONNECTIONS - An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component. | 2021-11-25 |
| 20210366863 | Semiconductor Package and Method - In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate. | 2021-11-25 |
| 20210366864 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials. | 2021-11-25 |
| 20210366865 | ELECTRONIC DEVICE INCLUDING ELECTRICAL CONNECTIONS ON AN ENCAPSULATION BLOCK - An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block. | 2021-11-25 |
| 20210366866 | UNFOLDABLE LAYERED CONNECTION, AND METHOD FOR MANUFACTURING AN UNFOLDABLE LAYERED CONNECTION - The present inventive concept relates to an unfoldable layered connection comprising: a substrate; a node of connector material arranged to contact the substrate; a first extension comprising a core of connector material arranged to be in contact with the node, and flexible material arranged to at least partially enclose the core; a second extension comprising a core of connector material arranged to be in contact with the first extension via a second node of connector material, wherein the first extension is configured to be hingedly connected to the node, thereby allowing unfolding of the first extension along a z-axis being perpendicular to an extension plane of a major surface of the substrate; and wherein the second extension is hingedly connected to the second node, thereby allowing unfolding of the second extension along the z-axis, and wherein the second node is moveable along the z-axis via unfolding of the first extension. | 2021-11-25 |
| 20210366867 | PALLADIUM-COATED COPPER BONDING WIRE, WIRE BONDING STRUCTURE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The bonding wire being a Pd-coated copper bonding wire includes: a copper core material; and a Pd layer and containing a sulfur group element, in which with respect to the total of copper, Pd, and the sulfur group element, a concentration of Pd is 1.0 mass % to 4.0 mass % and a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of S is 5 mass ppm to 2 mass ppm, a concentration of Se is 5 mass ppm to 20 mass ppm, or a concentration of Te is 15 mass ppm to 50 mass ppm or less. A wire bonding structure includes a Pd-concentrated region with the concentration of Pd being 2.0 mass % or more relative to the total of Al, copper, and Pd near a bonding surface of an Al-containing electrode of a semiconductor chip and a ball bonding portion. | 2021-11-25 |
| 20210366868 | BACKSIDE METALIZATION WITH THROUGH-WAFER-VIA PROCESSING TO ALLOW USE OF HIGH Q BONDWIRE INDUCTANCES - A method of forming a flip-chip integrated circuit die that includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry, at least two through-wafer vias in electrical communication with the active circuitry and extending at least partially though the die and having portions at a rear side of the die, and a bond wire external to the die and electrically coupling the portions of the at least two through-wafer vias to one another at the rear side of the die. | 2021-11-25 |
| 20210366869 | WIRE BONDING METHOD AND WIRE BONDING DEVICE - Provided is a wire bonding method capable of suppressing the occurrence of wire breakage. One aspect of the present invention provides a wire bonding method for bringing a capillary and a wire | 2021-11-25 |
| 20210366870 | TRANSFER METHOD AND TRANSFER DEVICE OF MICRO LED - A transfer method and a transfer device of micro LEDs are provided. By horizontally and vertically stretching a tensile substrate evenly to make horizontal distances and vertical distances between the adjacent micro LEDs achieve predetermined target values, and at last, bonding the micro LEDs spaced apart into the target values to an array substrate. The method does not need to manufacture a patterned mold or a patterned transfer head, and production period is reduced, and production cost is lowered, which effectively improves current transfer methods of the micro LEDs. | 2021-11-25 |
| 20210366871 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients. | 2021-11-25 |
| 20210366872 | SEMICONDUCTOR DEVICE, CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer. | 2021-11-25 |
| 20210366873 | MODULAR STACKED SILICON PACKAGE ASSEMBLY - A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost. | 2021-11-25 |
| 20210366874 | STACK PACKAGE INCLUDING CORE DIE STACKED OVER A CONTROLLER DIE - A stack package includes a core die disposed over a package substrate, and a controller die disposed between the core die and the package substrate to control the core die. The core die includes banks each including memory cell arrays, an interbank region in which row decoders and column decoders are arranged, and a pad region in which first connection pads electrically connected to the row decoders and column decoders through first wirings are disposed. The controller die includes a through via region in which controller die through vias penetrating the controller die to be connected to the first connection pads are disposed, and a circuit region in which controlling circuitry electrically connected to the controller die through vias through second wirings is disposed. | 2021-11-25 |
| 20210366875 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL WIRE BONDS - A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced. | 2021-11-25 |
| 20210366876 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity. | 2021-11-25 |
| 20210366877 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A structure includes core substrates attached to a first side of a redistribution structure, wherein the first redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the first redistribution structure. | 2021-11-25 |
| 20210366878 | INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips. The first redistribution conductor electrically connects the first chip to some electrical connection structures, the second redistribution conductor electrically connects the second chip to some electrical connection structures, and the third redistribution conductor electrically connects the first and second chips. | 2021-11-25 |
| 20210366879 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads. | 2021-11-25 |
| 20210366880 | MULTI-LAYER CONVERSION MATERIAL FOR DOWN CONVERSION IN SOLID STATE LIGHTING - Light emitting diodes are disclosed that utilize multiple conversion materials in the conversion process in order to achieve the desired emission color point. Different embodiments of the present invention can comprise different phosphor types in separate layers on, above or around one or a plurality of LED chips to achieve the desired light conversion. The LEDs can then emit a desired combination of light from the LED chips and conversion material. In some embodiments, conversion materials can be applied as layers of different phosphor types in order of longest emission wavelength phosphor first, followed by shorter emission phosphors in sequence as opposed to applying in a homogeneously mixed phosphor converter. The conversion material layers can be applied as a blanket over the LED chips and the area surrounding the chip, such as the surface of a submount holding the LED chips. | 2021-11-25 |
| 20210366881 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - An array substrate, a method of manufacturing the array substrate, and a display device are provided. The array substrate includes: a transparent rigid base; light-emitting chips on the transparent rigid base, each light-emitting chip including a chip body and a pin coupled to the chip body, a light-exiting surface of the chip body facing towards the transparent rigid base, and the pin being on a side of the chip body facing away from the transparent rigid base; a driving wire layer on a side of the pin facing away from the transparent rigid base; and a driving chip structure on a side of the driving wire layer facing away from the transparent rigid base. The driving chip structure is coupled to pins of the plurality of light-emitting chips through the driving wire layer, and is used for provide driving signals for the light-emitting chips. | 2021-11-25 |
| 20210366882 | COMBINED DISPLAY PANEL - A combined display panel including a first sub-screen and a second sub-screen. The first sub-screen includes a first display surface and a second display surface disposed on a back of the first display surface, the first display surface includes a plurality of first sub-pixels, the second display surface includes a plurality of second sub-pixels, and the second sub-screen includes a plurality of third sub-pixels. The combined display panel provided by the present application can improve the aperture ratio of the display panel in the prior art. | 2021-11-25 |
| 20210366883 | INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FOR PLATFORM MINIATURIZATION - Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed. | 2021-11-25 |
| 20210366884 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer. | 2021-11-25 |
| 20210366885 | PACKAGE AND MANUFACTURING METHOD THEREOF - A package includes a first die, a second die, a bridge structure, a first redistribution structure, and an encapsulant. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die. The bridge structure includes a plurality of routing patterns and a plurality of connectors disposed on the plurality of routing patterns. The first redistribution structure is sandwiched between the first die and the bridge structure and is sandwiched between the second die and the bridge structure. The plurality of connectors of the bridge structure is in physical contact with the first redistribution structure. The encapsulant encapsulates the bridge structure. The plurality of routing patterns and the plurality of connectors of the bridge structure are completely spaced apart from the encapsulant. | 2021-11-25 |
| 20210366886 | SEMICONDUCTOR DEVICE - A plurality of semiconductor elements connected in parallel with one another include a plurality of first semiconductor elements and a plurality of second semiconductor elements. A drive circuit to provide a gate signal to each of the plurality of semiconductor elements EL includes a main circuit and a plurality of inserted circuits including a first inserted circuit and a second inserted circuit. The first inserted circuit is inserted between the main circuit and the plurality of first semiconductor dements. The second inserted circuit is inserted between the main circuit and the plurality of second semiconductor elements. Each of the first inserted circuit and the second inserted circuit includes a first diode having a forward direction toward the main circuit and a second diode connected in anti-parallel with the first diode. | 2021-11-25 |
| 20210366887 | METHOD FOR EFFICIENT MANUFACTURE OF DISPLAY PANEL - A method for efficient manufacture of a color or monochrome display panel by an masse transfer of a large number of light emitting elements includes providing crystal blocks, providing a driving substrate, transferring the crystal blocks to the driving substrate, patterning the crystal blocks, and applying wavelength-converting elements to each light source, for a monochrome or color display device. | 2021-11-25 |
| 20210366888 | DISPLAY DEVICE - A display device includes a conductive layer including a first voltage line and a second voltage line extending in a first direction; an interlayer insulating layer on the conductive layer and including a plurality of contact holes that expose parts of the conductive layer; a plurality of first-type electrodes on the interlayer insulating layer and electrically connected to the conductive layer through the plurality of contact holes, a plurality of second-type electrodes on the interlayer insulating layer and extending in the first direction, a plurality of light-emitting elements on pairs of the first-type and the second-type electrodes that are spaced from each other in the second direction; first-type contact electrodes on the first-type electrodes and in contact with the light-emitting elements; and second-type contact electrodes on the second-type electrodes and in contact with the light-emitting elements, each of the second-type contact electrodes includes contact electrode extensions on the second-type electrodes. | 2021-11-25 |
| 20210366889 | PACKAGE STRUCTURE - A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation. | 2021-11-25 |
| 20210366890 | DISPLAY DEVICE - The disclosure relates to a display device, which includes a cover plate, a backlight unit, a display module disposed between the backlight unit and the cover plate, the display module including a first substrate close to the light exiting side of the backlight unit and a second substrate close to the cover plate, and a camera module arranged on the first substrate, the camera module including an infrared cut-off filter, wherein the first substrate extends horizontally beyond the second substrate and the backlight unit to form a mounting section for the camera module, and the infrared cut-off filter is arranged in the mounting section. | 2021-11-25 |
| 20210366891 | ELECTRONIC APPARATUS - An electronic apparatus including a display module having a front surface and a rear surface opposing the front surface and including pixels disposed on the front surface and a display pad connected to the pixels and exposed from the rear surface, a protective film disposed on the rear surface of the display module, a circuit board disposed between the display module and the protective film and having a front surface facing the rear surface of the display module and a rear surface, the circuit board including a first substrate pad connected to the display pad and exposed from the front surface of the circuit board and a second substrate pad exposed from the rear surface of the circuit board, and a driving element connected to the second substrate pad to drive the pixels, in which the second substrate pad and the protective film are spaced apart from each other. | 2021-11-25 |
| 20210366892 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction. | 2021-11-25 |
| 20210366893 | Semiconductor Device that Uses Bonding Layer to Join Semiconductor Substrates Together - Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device. | 2021-11-25 |
| 20210366894 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure over the semiconductor substrate, the multilevel wiring structure including a first insulating layer, a first conductive layer on the first insulating layer, a second conductive layer on the first insulating layer, a third conductive layer on the first and second conductive layer, a fourth conductive layer on the third conductive layer, and a second insulating layer on the fourth conductive layer. The multilevel wiring structure includes: a first gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and first, third and fourth conductive films in the first, third and fourth conductive layers, respectively; and a second gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and second, third and fourth conductive films in the second, third and fourth conductive layers, respectively. | 2021-11-25 |
| 20210366895 | TAP CELL, INTEGRATED CIRCUIT STRUCTURE AND FORMING METHOD THEREOF - Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region. | 2021-11-25 |
| 20210366896 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor. | 2021-11-25 |
| 20210366897 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad. | 2021-11-25 |
| 20210366898 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad. | 2021-11-25 |
| 20210366899 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT, ARRAY SUBSTRATE AND DISPLAY DEVICE - An ESD protection circuit, an array substrate and a display device are disclosed. The ESD protection circuit includes a plurality of first ESD units, each of which includes: a first active layer a first insulating layer, a first metallic layer, a second insulating layer and a second metallic layer which are disposed on a base substrate; the first active layer includes a plurality of first connection terminals; the first metallic layer includes a plurality of first conductive terminals; the second metallic layer includes a plurality of second conductive terminals an orthographic projection of the first metallic layer and an orthographic projection of the second metallic layer the base substrate are at least partly overlapped with an orthographic projection of the first active layer on the base substrate respectively; and the first conductive terminals and the second conductive terminals are electrically connected with different first connection terminals, respectively. | 2021-11-25 |
| 20210366900 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD - A semiconductor apparatus comprises a first semiconductor region including a first surface and a second surface, in which a semiconductor of a first conductivity type is arranged, a second semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface, a third semiconductor region of a second conductivity type, which is arranged in a region between the second semiconductor region and the second surface and on a side portion of the second semiconductor region, a fourth semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; and a fifth semiconductor region of the second conductivity type, which is arranged in a region between the fourth semiconductor region and the second surface and on a side portion of the fourth semiconductor region. | 2021-11-25 |
| 20210366901 | SEMICONDUCTOR DEVICE - Reliability of a gate resistor element during high-temperature operation is enhanced. A semiconductor device includes a drift layer, a base layer, an emitter layer, a gate insulation film, a gate electrode, a gate pad electrode, a first resistance layer, and a first nitride layer. A resistor of the first resistance layer has a negative temperature coefficient. The first resistance layer is made of hydrogen-doped amorphous silicon. The first nitride layer is made of a silicon nitride layer or an aluminum nitride layer. | 2021-11-25 |
| 20210366902 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A layout structure of a capacitive element using a complementary FET (CFET) and having a high breakdown voltage is provided. In the capacitive element, first and second transistors overlap as viewed in plan, and the gates thereof are mutually connected. Third and fourth transistors overlap as viewed in plan, and the gates thereof are mutually connected. Nodes of the first and third transistors are mutually connected through a local interconnect, and nodes of the second and fourth transistors are mutually connected through a local interconnect. | 2021-11-25 |
| 20210366903 | THREE-DIMENSIONAL OPTOELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A three-dimensional optoelectronic device package is disclosed. The three-dimensional optoelectronic device package comprises a first board having at least one surface on which a plurality of optoelectronic devices is disposed, and a second board having at least one surface on which a plurality of optoelectronic devices is disposed. A side of the second board is attached to the surface of the first board on which a plurality of optoelectronic devices is disposed to form an angle between the surface of the first board on which a plurality of optoelectronic devices is disposed and the surface of the second board on which a plurality of optoelectronic devices is disposed. A method for manufacturing a three-dimensional optoelectronic device package is also disclosed. | 2021-11-25 |
| 20210366904 | METHOD OF ARCHITECTURE DESIGN FOR ENHANCED 3D DEVICE PERFORMANCE - Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device | 2021-11-25 |
| 20210366905 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns. | 2021-11-25 |
| 20210366906 | STACKING CMOS STRUCTURE - A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types. | 2021-11-25 |
| 20210366907 | Source/Drain Contact Structure - A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure. | 2021-11-25 |
| 20210366908 | Semiconductor Devices with Dielectric Fins and Method for Forming the Same - A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench. | 2021-11-25 |
| 20210366909 | FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis. | 2021-11-25 |
| 20210366910 | SEMICONDUCTOR DEVICE - A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers. | 2021-11-25 |
| 20210366911 | SEMICONDUCTOR MEMORY STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact. | 2021-11-25 |
| 20210366912 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a bit line structure on a top surface of the substrate; forming a spacer structure on the bit line structure, the spacer structure including a sacrificial layer sandwiched by a first dielectric layer and a second dielectric layer; removing the sacrificial layer to form a gap between the first dielectric layer and the second dielectric layer; reducing a width of the gap; and forming a seal layer to seal the gap. | 2021-11-25 |
| 20210366913 | STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) includes a substrate having a first active region and a second active region adjacent to the first active region. A first gate structure is disposed on the substrate and across the first active region and the second active region. A second gate structure is adjacent to a first side of the first gate structure. A first lower contact structure is disposed on the first active region and adjacent to a second side of the first gate structure. A first upper contact structure is disposed on and in direct contact with the first lower contact structure. A top surface of the first lower contact structure and a sidewall of the first upper contact structure comprise a step profile therebetween. | 2021-11-25 |
| 20210366914 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer. | 2021-11-25 |
| 20210366915 | 4CPP SRAM CELL AND ARRAY - A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell. | 2021-11-25 |
| 20210366916 | MEMORY DEVICE, SRAM CELL, AND MANUFACTURING METHOD THEREOF - A device includes a first semiconductor fin, a second semiconductor fin, first source/drain features, second source/drain features, a first gate structure, a second gate structure, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first semiconductor fin and the second semiconductor fin are adjacent to each other. The first source/drain features are on opposite sides of the first semiconductor fin. The second source/drain features are on opposite sides of the second semiconductor fin. The first gate structure is over the first semiconductor fin. The second gate structure is over the second semiconductor fin. The first VGAA transistor is over one of the first source/drain features. The second VGAA transistor is over one of the second source/drain features. | 2021-11-25 |
| 20210366917 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits. | 2021-11-25 |
| 20210366918 | ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT AND MANUFACTURING METHOD THEREOF - A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor. | 2021-11-25 |
| 20210366919 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor. | 2021-11-25 |
| 20210366920 | THROUGH-STACK CONTACT VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE AND METHODS OF FORMING THE SAME - A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Contact via structures are formed through the vertically alternating stack or the dielectric pillar structures, through the first retro-stepped dielectric material portion, and directly on a first subset of the electrically conductive layers. | 2021-11-25 |
| 20210366921 | SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than eight microns, where the second level includes a layer transferred and bonded level, where the bonded includes oxide to oxide bonds, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells. | 2021-11-25 |
| 20210366922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance. | 2021-11-25 |
| 20210366923 | MEMORY DEVICE AND FORMATION METHOD THEREOF - Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure. | 2021-11-25 |
| 20210366924 | THROUGH-STACK CONTACT VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE AND METHODS OF FORMING THE SAME - A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Contact via structures are formed through the vertically alternating stack or the dielectric pillar structures, through the first retro-stepped dielectric material portion, and directly on a first subset of the electrically conductive layers. | 2021-11-25 |
| 20210366925 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region. | 2021-11-25 |
| 20210366926 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region. | 2021-11-25 |
| 20210366927 | Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies - Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies. | 2021-11-25 |
| 20210366928 | SEMICONDUCTOR DEVICE - A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions. | 2021-11-25 |
| 20210366929 | SEMICONDUCTOR DEVICE - A semiconductor device includes a source structure penetrated by a first penetrating portion, a first stack structure disposed on the source structure and penetrated by a second penetrating portion overlapping the first penetrating portion. | 2021-11-25 |
| 20210366930 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF - A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate; forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack; forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface; forming a channel layer to cover the functional layer in each channel hole; and forming a filling structure to cover the channel layer and fill each channel hole. | 2021-11-25 |
| 20210366931 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION - Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain. | 2021-11-25 |
| 20210366932 | SEMICONDUCTOR DEVICE OF THREE-DIMENSIONAL STRUCTURE INCLUDING FERROELECTRIC LAYER - A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer. | 2021-11-25 |
| 20210366933 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof, a display panel and a display device are disclosed. The array substrate includes a base substrate, a light shielding layer, an active layer of a thin film transistor, and an insulating layer. The light shielding layer includes light transmission holes on the base substrate. The active layer of the thin film transistor is located on the side of the light shielding layer away from the base substrate. An insulating layer is located on the base substrate. The insulating layer includes a first through hole in communication with the light transmission hole. | 2021-11-25 |
| 20210366934 | ARRAY SUBSTRATE - An array substrate provided. Since arranging a second metal layer into a grid structure, the grid structure and a constant voltage signal trace disposed on a third metal layer are connected in parallel, and a storage capacitor is used as a connection point for the grid structure. The grid structure ensures a high pixel density and also reduces voltage drop, thereby improving brightness uniformity. Moreover, in the manufacturing process, the grid structure and the second metal layer can be formed simultaneously, thereby eliminating a need for additional processes and saving cost. | 2021-11-25 |
| 20210366935 | TRANSPARENT DISPLAY AND MANUFACTURING METHOD THEREOF - The present invention provides a transparent display and a manufacturing method thereof. The transparent display includes a substrate and a plurality of frame traces. The substrate includes a transparent display region and a frame region surrounding the transparent display region. The plurality of frame traces are disposed in the frame region, and each frame trace includes a hollow portion and a conductive portion surrounding the hollow portion. By disposing the hollow portion in each the frame trace to improve a transmittance of each the frame trace, thereby improving a transparency of the frame region, reducing a risk of disconnection, and improving a product yield. | 2021-11-25 |
| 20210366936 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL - A display substrate and a manufacturing method thereof and a display panel are disclosed. The display substrate includes a base substrate, a connection electrode, a conductive sealant, a plurality of via-holes respectively in different layers and a bridge electrode. The connection electrode is on the base substrate; the conductive sealant is at a side, away from the base substrate, of the connection electrode and is electrically connected with the connection electrode via the plurality of via-holes respectively in different layers; the bridge electrode is at least partially in at least one via-hole of the plurality of via-holes, and is electrically connected with the connection electrode and the conductive sealant; in a direction perpendicular to the base substrate, the plurality of via-holes are at least partially not overlapped with each other. | 2021-11-25 |
| 20210366937 | PIXEL LAYOUT AND DISPLAY PANEL HAVING PIXEL LAYOUT - A pixel layout and a display panel having the pixel layout are provided. The pixel layout includes a plurality of pixel repeating groups, and each of the pixel repeating groups is formed by two adjacent pixels. Two through-holes are positioned between the two pixels, and first ends of the two through-holes are respectively connected to pixel electrodes of the pixels. When one of the pixel electrodes of the two pixels has a voltage loss and the pixel thereof presents a dark spot, second ends of the two through-holes are connected to allow the pixel having the dark spot to display normally with help of the other pixel, thereby repairing the dark spot. | 2021-11-25 |
| 20210366938 | ARRAY SUBSTRATE AND METHOD OF MOUNTING INTEGRATED CIRCUIT USING THE SAME - An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion. | 2021-11-25 |
| 20210366939 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device comprises a display panel, at least one signal generator, and a plurality of wires. The display panel has a plurality of input ends to receive data signal. The at least one signal generator has a plurality of output ends to supply the data signal to the input ends of the display panel, respectively. The wires connects the output ends of the at least one signal generator to the input ends of the display panel, respectively, the wires having lengths measured between the output ends of the at least one signal generator and the input ends of the display panel, respectively, the length of the wires being different from each other according to location of the output ends of the at least one signal generator. | 2021-11-25 |
| 20210366940 | MANUFACTURING METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure discloses a manufacturing method of an array substrate, an array substrate, a display panel and a display device. The manufacturing method includes: forming a metal layer on a base substrate; forming a protective layer on the side, away from the base substrate, of the metal layer, wherein the protective layer is configured to protect the metal layer; forming photoresist on the side, away from the base substrate, of the protective layer; and processing the base substrate, on which the metal layer, the protective layer and the photoresist are formed, by means of a photoetching process to obtain a metal pattern. | 2021-11-25 |
| 20210366941 | DISPLAY SUBSTRATE, METHOD OF FORMING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE - A display substrate, a method of forming the same, a display panel and a display device are provided. The display substrate includes a thin film transistor array layer, where a semiconductor material layer pattern of a driving transistor in the thin film transistor array layer includes a first channel portion, and the first channel portion includes a first sub-channel portion. and a second sub-channel portion; the semiconductor material layer pattern further includes a first conductive portion, an included angle between a straight line where a current conduction direction of the first sub-channel portion is located and a straight line Where an extending, direction of a data line in the thin film transistor array layer is located is a first included angle. | 2021-11-25 |
| 20210366942 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate and a manufacturing method thereof, the array substrate includes a glass substrate, a barrier layer, a buffer layer, an active layer, a gate insulating layer, a gate electrode layer, an interlayer insulation layer, a source/drain electrode layer, a passivation layer, and a pixel electrode which are disposed layer by layer. The manufacturing method includes providing the glass substrate, manufacturing the barrier layer, manufacturing the buffer layer, manufacturing the active layer, manufacturing the gate insulating layer, manufacturing the gate electrode layer, a patterning step, a step of doping plasma, manufacturing the interlayer insulation layer, manufacturing the source/drain electrode layer, manufacturing the passivation layer, and manufacturing the pixel electrode. | 2021-11-25 |
| 20210366943 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE - A manufacturing method of a thin film transistor substrate and a thin film transistor substrate are provided. In the manufacturing method of the thin film transistor substrate, a buffer layer, a metal oxide semiconductor layer, and a first insulating layer are sequentially deposited on a substrate, and then the first insulating layer and the metal oxide semiconductor layer are patterned according to a pattern of an active layer. The metal oxide semiconductor layer forms the active layer. A second insulating layer and a gate metal layer are then sequentially deposited. The first insulating layer and the second insulating layer together form a gate insulating layer. The first insulating layer can be used to protect the metal oxide semiconductor layer, such that defects on a contact surface between the active layer and the gate insulating layer are reduced, thereby improving the stability of a device. | 2021-11-25 |
| 20210366944 | TRANSISTOR AND DISPLAY DEVICE - It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided. | 2021-11-25 |
| 20210366945 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first circuit element, the first circuit element including: a first semiconductor layer having a concave part; a first insulating layer arranged above the first semiconductor layer, the first insulating layer having a first through hole in a region overlapping with the concave part. A method of manufacturing a semiconductor device, the method including: forming a first semiconductor layer having a concave part on a substrate; forming a first insulating layer on the first semiconductor layer; forming a first through hole in a region of the first insulating layer overlapping with the concave part; and forming a first conductive layer arranged in the concave part and the first through hole. | 2021-11-25 |
| 20210366946 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE, INTERMEDIATE ARRAY SUBSTRATE PRODUCT, AND ARRAY SUBSTRATE - An array substrate manufacturing method includes forming a plurality of first lead lines, a plurality of pixel electrodes, and a plurality of connecting lines over a substrate. Each first lead line is insulated from any pixel electrode, and each connecting line is insulated from any first lead line and is configured to electrically couple at least two pixel electrodes such that a set of pixel electrodes electrically coupled by each set of connecting lines substantially form an equivalent lead line. The method further includes detecting whether there is a short circuit between one equivalent lead line and a first lead line, and severing each of the plurality of connecting lines such that any two of the plurality of pixel electrodes are not electrically coupled. | 2021-11-25 |
| 20210366947 | ARRAY SUBSTRATE AND DISPLAY DEVICE - Disclosed are an array substrate and a display device. The array substrate includes: a plurality of sub-pixel elements in an array, wherein each row of sub-pixel elements includes a common electrode; the common electrode includes a plurality of sub-common electrodes, each of which corresponds to one of the sub-pixel elements; the sub-common electrode includes a body connection section, a plurality of comb teeth connected with the body connection section, and a shielding section connected with the body connection section, wherein the first comb teeth and the shielding section are on the same side of the body connection section, and the shielding section is on the outermost side of the first comb teeth; and the body connection sections of two adjacent sub-common electrodes in the common electrode are on two opposite sides. The body connection sections of two adjacent sub-common electrodes in each common electrode are arranged on two opposite sides. | 2021-11-25 |
| 20210366948 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present application discloses an array substrate and a display panel, which includes gate on array (GOA) signal lines disposed in a film layer of the array substrate and driving signal lines disposed on a surface of the array substrate. The GOA signal lines are electrically connected to the driving signal lines by through holes. The through holes are correspondingly disposed on the GOA signal lines, and the through holes are disposed on the GOA signal lines according to an area ratio. | 2021-11-25 |
| 20210366949 | DISPLAY PANEL AND DISPLAY DEVICE - The disclosure provides a display panel including a substrate layer, a thin film transistor (TFT) layer, and a gate on array (GOA) drive circuit. The TFT layer is disposed on the substrate layer, and a bending region is disposed on at least one side of the substrate layer near the TFT layer. The GOA drive circuit is disposed on the substrate layer, and the bending region is disposed between at least one side of the TFT layer and the GOA drive circuit. The auxiliary circuit is disposed on the substrate layer and is disposed correspondingly to the bending region. | 2021-11-25 |
| 20210366950 | DISPLAY PANEL AND DISPLAY DEVICE - The present application provides a display panel and a display device. The display panel comprises: a base substrate; an insulating layer arranged on the base substrate, the insulating layer being provided with recesses spaced from each other; metal lines arranged on one side of the insulating layer away from the base substrate, portions of the metal lines corresponding to the recesses being located in the recesses, the metal lines having a corrugated longitudinal cross-section in an extending direction of the metal lines to reduce a risk of the metal lines breaking during bending and improve flexibility of the display panel. | 2021-11-25 |
| 20210366951 | TFT ARRAY SUBSTRATE, FABRICATING METHOD THEREOF, AND DISPLAY PANEL THEREOF - The present invention provides a thin film transistor (TFT) array substrate including a base layer. A function layer is disposed on the base layer, and a planarization layer is disposed on the function layer. The planarization layer includes a vertical insertion extending into the function layer, and a side of the vertical insertion horizontally extends outwardly into the function layer to from a horizontal insertion. The invention provides a TFT array substrate, which adopts a novel inter-layers structure arrangement, which effectively reduces risk of potential mutual detachment between different layers, thereby improving product stability. | 2021-11-25 |
| 20210366952 | IN-PIXEL EMBEDDED ANALOG IMAGE PROCESSING - An in-pixel embedded analog image processing system performs analog image computation within an image pixel. In embodiments, each in-pixel processing element includes a photodetector, photodetector control circuitry, analog circuitry configured to process both neighbor-in-space and neighbor-in-time functions for analog data representing an electrical current from the photodetector control circuitry, and a set of north-east-west-south (NEWS) registers, each register interconnected between a unique pair of neighboring in-pixel processing elements to transfer analog data between the pair of neighboring in-pixel processing elements. In embodiments, the in-pixel embedded analog image processing device takes advantage of high parallelism because each pixel has its own processor, and takes advantage of locality of data because all data is located within a pixel or within a neighboring pixel. | 2021-11-25 |
| 20210366953 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING - A semiconductor arrangement is provided. The semiconductor arrangement includes a first component in a substrate. The semiconductor arrangement includes a gap fill layer. A first portion of the gap fill layer overlies the first component. The first portion of the gap fill layer has a tapered sidewall. A first portion of the substrate separates the first portion of the gap fill layer from the first component. | 2021-11-25 |
