47th week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210366754 | STORAGE DEVICE FOR STORING WAFER CASSETTES FOR USE WITH A BATCH FURNACE - A storage device for use with at least one batch furnace for batch treatment of wafers supported in a wafer boat is disclosed. The storage device comprises a cassette storage carousel for storing a plurality of wafer cassettes on rotatable platform stages. A carousel housing bounds a mini-environment chamber in which the platform stages are accommodated. A gas recirculation circuit of the storage device subsequently comprises a gas inlet channel, a gas inlet filter, the mini-environment chamber, a plurality of gas outlet openings in a bottom wall of the carousel housing, a plenum housing bounding a plenum chamber, a plenum chamber outlet, a gas circulation pump connecting the plenum chamber outlet to an inlet end of the gas inlet duct. | 2021-11-25 |
20210366755 | MASS TRANSFER DEVICE AND TRANSFER METHOD THEREFOR - A mass transfer device and a transfer method therefor are provided. The mass transfer device includes a transfer container. The transfer container is filled with insulating liquid and provided with two electrode plates. The two electrode plates are arranged opposite to each other and have opposite electrical polarities. One of the two electrode plates is provided with a second substrate on a surface of the electrode plate opposite to the other one of the two electrode plates. The second substrate is configured to hold transferred light-emitting diode (LED) chips. The transfer container is externally provided with a laser emitter. The laser emitter is aligned with LED chips on a first substrate. The first substrate is arranged between the two electrode plates and mounted on a first displacement device. The first displacement device is configured to control the first substrate to move vertically downward. | 2021-11-25 |
20210366756 | SYSTEM APPARATUS AND METHOD FOR ENHANCING ELECTRICAL CLAMPING OF SUBSTRATES USING PHOTO-ILLUMINATION - A method may include providing a substrate on a clamp, and directing radiation from an illumination source to the substrate when the substrate is disposed on the clamp during substrate processing, wherein the radiation is characterized by a radiation energy, wherein at least a portion of the radiation energy is equal to or greater than 2.5 eV. | 2021-11-25 |
20210366757 | SYSTEM APPARATUS AND METHOD FOR ENHANCING ELECTRICAL CLAMPING OF SUBSTRATES USING PHOTO-ILLUMINATION - A method may include providing a substrate in a process chamber, directing radiation from an illumination source to the substrate when the substrate is disposed in the process chamber, and processing the substrate by providing a processing species to the substrate, separate from the radiation, when the substrate is disposed in the process chamber. As such, the radiation may be characterized by a radiation energy, wherein at least a portion of the radiation energy is equal to or greater than 2.5 eV. | 2021-11-25 |
20210366758 | DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING - Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates. | 2021-11-25 |
20210366759 | SYSTEM APPARATUS AND METHOD FOR ENHANCING ELECTRICAL CLAMPING OF SUBSTRATES USING PHOTO-ILLUMINATION - An apparatus may include a clamp to clamp a substrate wherein the clamp is arranged opposing a back side of the substrate; and an illumination system, disposed to direct radiation to the substrate, when the substrate is disposed on the clamp, wherein the radiation comprises a radiation energy, equal to or above a threshold energy to generate mobile charge in the substrate, where the illumination system is disposed to direct radiation to the back side of the substrate. | 2021-11-25 |
20210366760 | GLASS SUBSTRATE, LAMINATED SUBSTRATE, LAMINATED SUBSTRATE MANUFACTURING METHOD, LAMINATE, PACKAGE, AND GLASS SUBSTRATE MANUFACTURING METHOD - A glass substrate is laminated with a substrate containing silicon to thereby form a laminated substrate. The glass substrate has a concave surface and a convex surface and has one or more marks that distinguish between the concave surface and the convex surface. | 2021-11-25 |
20210366761 | SEMICONDUCTOR STRUCTURE HAVING AIR GAP DIELECTRIC - The present disclosure provides a semiconductor structure for reducing capacitive coupling between adjacent conductive features. The semiconductor structure includes a base layer, a plurality of conductive lines, a plurality of dielectric pillars, and a sealing layer having a plurality of sealing caps. The conductive lines are disposed on the base layer. The dielectric pillars are disposed on the base layer and separated from the conductive layer. The sealing caps are disposed between the conductive lines and the dielectric pillars, wherein the sealing caps are in contact with the conductive lines and the dielectric pillars, and separated from the base layer. | 2021-11-25 |
20210366762 | SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP - A semiconductor device structure includes a first conductive structure and a second conductive structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer disposed over the first conductive structure, and a second spacer disposed over the second conductive structure. The semiconductor device structure further includes a third spacer disposed over a sidewall of the first spacer, and a fourth spacer disposed over a sidewall of the second spacer. A lower portion of the third spacer adjoins a lower portion of the fourth spacer, and an air gap is covered by the lower portion of the third spacer and the lower portion of the fourth spacer. | 2021-11-25 |
20210366763 | SEMICONDUCTOR ON INSULATOR STRUCTURE FOR A FRONT SIDE TYPE IMAGER - A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate. | 2021-11-25 |
20210366764 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided. | 2021-11-25 |
20210366765 | VIA STRUCTURE AND METHODS FOR FORMING THE SAME - Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material. | 2021-11-25 |
20210366766 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap. | 2021-11-25 |
20210366767 | Different Isolation Liners for Different Type FinFETs and Associated Isolation Feature Fabrication - Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner). | 2021-11-25 |
20210366768 | IMPROVING SUBSTRATE WETTABILITY FOR PLATING OPERATIONS - Various embodiments include methods and apparatuses to moisturize a substrate prior to an electrochemical deposition process. In one embodiment, a method to control substrate wettability includes placing a substrate in a pre-treatment chamber, controlling an environment of the pre-treatment chamber to moisturize a surface of the substrate; and placing the substrate into a plating cell. Other methods and systems are disclosed. | 2021-11-25 |
20210366769 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided. A substrate is provided. The substrate has an active area. A plurality of word lines are formed on the substrate. Each of the word lines is extended along a first direction, and the word lines are arranged on both sides of the active area along a second direction. A first dielectric layer is formed on the substrate. The first dielectric layer covers the active area and the word lines. A contact is formed on the active area. The contact penetrates through the first dielectric layer and is electrically connected to the active area. A heating process is performed on the first dielectric layer to shrink the first dielectric layer inward, and the contact is correspondingly expanded outward. | 2021-11-25 |
20210366770 | CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure. | 2021-11-25 |
20210366771 | NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT - A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs). | 2021-11-25 |
20210366772 | METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT - A method of manufacturing a semiconductor element includes a first irradiation step in which a laser beam is irradiated to form, in the interior of the substrate, a plurality of first modified portions aligned along a first direction; a second irradiation step in which a laser beam is irradiated to form a plurality of second modified portions aligned along the first direction at a position adjacent to the plurality of first modified portions in the second direction; and a third irradiation step which a laser beam is irradiated to form a plurality of third modified portions aligned along the first direction at a position closer to the first surface than the first modified portions and overlapping the plurality of first modified portions in a thickness direction of the substrate. | 2021-11-25 |
20210366773 | WAFER LEVEL DICING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line. | 2021-11-25 |
20210366774 | INTEGRATED CIRCUIT - A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration. | 2021-11-25 |
20210366775 | In-Situ Formation of Metal Gate Modulators - A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode. | 2021-11-25 |
20210366776 | ASYMMETRIC FIN TRIMMING FOR FINS OF FINFET DEVICE - Disclosed are approaches for forming finFET devices having asymmetric fins achieved via fin trimming. In some embodiments, a method may include providing a substrate within a process chamber, the substrate including a plurality of fins, and forming a capping layer over the plurality of fins, wherein the capping layer extends along a first sidewall and a second sidewall of each of the plurality of fins. The method may further include removing a portion of the capping layer to expose a target area of the first sidewall of each of the plurality of fins, and trimming the target area of the first sidewall of each of the plurality of fins to reduce a lateral width of an upper section of each of the plurality of fins. | 2021-11-25 |
20210366777 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom. | 2021-11-25 |
20210366778 | GATE STACK TREATMENT - The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere. | 2021-11-25 |
20210366779 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer. | 2021-11-25 |
20210366780 | GAP PATTERNING FOR METAL-TO-SOURCE/DRAIN PLUGS IN A SEMICONDUCTOR DEVICE - A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers. | 2021-11-25 |
20210366781 | METHOD OF MANUFACTURING INVERTER AND INVERTER - A method of manufacturing an inverter and an inverter are provided. The method of manufacturing the inverter includes following steps: forming a substrate and forming a first insulating layer on the substrate; forming a semiconductor-type carbon nanotube film on the first insulating layer; patterning the semiconductor-type carbon nanotube film to form a first active layer and a second active layer arranged at an interval; forming a first barrier layer on the first active layer and forming a second barrier layer on the second active layer, wherein the first barrier layer is an electrophilic film layer, and the second barrier layer is an electron donor film layer; and forming a first source and a first drain which are in contact with and spaced apart from two ends of the first active layer and forming a second source and a second drain which are in contact with and spaced with two ends of the second active layer, wherein the first drain is connected to the second source. By using the semiconductor-type carbon nanotube as the active layer to cooperate with the electrophilic film layer and the electron donor film layer as a barrier layer, manufacturing process of the inverter can be simplified, and manufacturing cost of the inverter can be reduced. | 2021-11-25 |
20210366782 | REDUCED SOURCE/DRAIN COUPLING FOR CFET - A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device. | 2021-11-25 |
20210366783 | Dipole Patterning for CMOS Devices - A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer. | 2021-11-25 |
20210366784 | FinFET Device with Different Liners for PFET and NFET and Method of Fabricating Thereof - A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials. | 2021-11-25 |
20210366785 | GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer. | 2021-11-25 |
20210366786 | Semiconductor Device and Method - In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having a upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material. | 2021-11-25 |
20210366787 | METAL CONNECTIONS AND ROUTING FOR ADVANCED 3D LAYOUT DESIGNS - A semiconductor device can include a pad layer including at least one pad structure having a core area surrounded by a peripheral area, and a transistor over the core area. The transistor includes a channel structure extending vertically and a gate structure all around a sidewall portion of the channel structure. The channel structure has a source region and a drain region on opposing ends of a vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device can further include a first vertical interconnect structure that contacts a top surface of the channel structure, a second vertical interconnect structure that contacts the peripheral area and is configured to be coupled to a bottom surface of the channel structure via the pad structure, and a third vertical interconnect structure that is positioned away from the channel structure and contacts the gate structure. | 2021-11-25 |
20210366788 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING POWER CONTROL CIRCUIT - In a method for manufacturing a semiconductor device, a back surface of each of plurality of current-carrying semiconductor elements each having a plurality of P-N junction diodes built-in is connected to a first principal surface of a conductor plate. Further, a conductor piece is connected to a front surface of each of the plurality of current-carrying semiconductor elements. Then, a current-carrying test is conducted on the plurality of P-N junction diodes with a second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece. | 2021-11-25 |
20210366789 | PRECISION THIN ELECTRONICS HANDLING INTEGRATION - One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications. | 2021-11-25 |
20210366790 | MULTIPLE-TOOL PARAMETER SET CALIBRATION AND MISREGISTRATION MEASUREMENT SYSTEM AND METHOD - A multiple-tool parameter set calibration and misregistration measurement method useful in the manufacture of semiconductor devices including using at least a first reference misregistration metrology tool using a first set of measurement parameters to measure misregistration between at least two layers on a wafer of a batch of wafers, thereby generating a first misregistration data set, transmitting the first set of parameters and the data set to a calibrated set of measurement parameters generator (CSMPG) which processes the first set of parameters and the data set thereby generating a calibrated set of measurement parameters which are transmitted from the CSMPG to calibrate at least one initially-uncalibrated misregistration metrology tool based on the calibrated set of measurement parameters. Thereafter, misregistration is measured between at least two layers of at least one wafer, using at least the initially-uncalibrated misregistration metrology tool using the calibrated set of measurement parameters for the measuring. | 2021-11-25 |
20210366791 | PLASMA PROCESSING DEVICE AND METHOD FOR PROCESSING SAMPLE USING SAME - There is provided a sample processing method including: an adsorption step forming a reactant layer on a sample surface inside a processing chamber in a state where plasma is generated by a plasma generation unit in a plasma generation chamber connected to the processing chamber; a desorption step of desorbing the reactant layer from the surface of the sample by heating the sample with a heating lamp disposed outside the processing chamber and a heater disposed inside the sample stage; a cooling step of cooling the sample heated in the desorption step; and repeating the above steps a plurality of times, wherein in the adsorption step, a control unit performs feed-forward control over the heating lamp and the heater to set the sample to a first temperature state, and in the desorption step, the heater is subjected to feed-back control to set the sample to a second temperature state. | 2021-11-25 |
20210366792 | BACKSIDE DEPOSITION TUNING OF STRESS TO CONTROL WAFER BOW IN SEMICONDUCTOR PROCESSING - A method of microfabrication is provided. A substrate having a working surface and having a backside surface opposite to the working surface is received. The substrate has an initial wafer bow resulting from one or more micro fabrication processing steps executed on the working surface of the substrate. The initial wafer bow of the substrate is measured and the initial wafer bow is used to generate an initial wafer bow value that identifies a degree of first order wafer bowing of the substrate. A correction film recipe based on the initial wafer bow value is identified. The correction film recipe specifies parameters of a correction film to be deposited on the backside surface of the substrate to change wafer bow of the substrate from the initial wafer bow to a modified wafer bow. The correction film on the backside surface of the substrate according to the correction film recipe is deposited. The correction film physically modifies internal stresses on the substrate and causes the substrate to have a modified bow with the predetermined wafer bow value. | 2021-11-25 |
20210366793 | TESTING BONDING PADS FOR CHIPLET SYSTEMS - Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads. | 2021-11-25 |
20210366794 | METHOD FOR DETECTING DEFECTS IN SEMICONDUCTOR DEVICE - A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit. | 2021-11-25 |
20210366795 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a case having an opening; a semiconductor element contained in the case; a control substrate which is disposed above the semiconductor element in the case and on which a control circuit to control the semiconductor element is disposed; a lid to cover the opening of the case; and a control terminal having one end portion connected to the control circuit disposed on the control substrate and the other end portion protruding out of the case. The control terminal has a bend in the case, and a side portion of the case or the lid is provided with a support capable of supporting the bend. | 2021-11-25 |
20210366796 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member. | 2021-11-25 |
20210366797 | IC PACKAGING STRUCTURE AND IC PACKAGING METHOD - Embodiments of the present disclosure provide an IC packaging structure and an IC packaging method, relating to the chip packaging field. The IC packaging structure includes: a substrate, a stress buffer sheet mounted on the substrate; a packaged chip mounted on the stress buffer sheet, and a plastic package body coated outside the packaged chip, wherein the packaged chip is electrically connected to the substrate, and the stress buffer sheet is used for buffering stress acting on the packaged chip. Compared with the prior art, in the IC packaging structure provided in the present disclosure, the stress buffer sheet is mounted on the substrate through silver glue, the packaged chip is mounted on the stress buffer sheet through silver glue. | 2021-11-25 |
20210366798 | PACKAGED STRUCTURE AND FORMING METHOD THEREOF - A packaged structure and a forming method thereof are provided. The packaged structure includes: a substrate having a first surface and a second surface opposite to each other, the first surface including at least one strip-shaped groove having two ends extending to edges of the substrate and open to the exterior, with a depth less than the thickness of the substrate; a chip fastened onto the first surface in a flipping manner and electrically connected to the substrate, and at least partially located within the projection of the chip on the substrate; a bottom filling layer filling the gap between the chip and the first surface; and a plastic packaging layer covering the bottom filling layer and packaging the chip. The packaged structure effectively removes the gas inside the packaged structure in the injection molding process without affecting the connection area on the back surface of the substrate. | 2021-11-25 |
20210366799 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor package including: at least one first substrate including at least one first substrate terminal extended therefrom; at least one second substrate joined to the upper surface of the first substrate using ultrasonic welding; at least one semiconductor chip joined to the upper surface of the second substrate; a package housing covering the at least one semiconductor chip and an area of the second substrate, where ultrasonic welding is performed; and terminals separated from the first substrate, electrically connected to the at least one semiconductor chip through electric signals, and at least one of them is exposed to the outside of the package housing, wherein a thickness of the terminals formed inside the package housing is same as or smaller than a thickness of the first substrate and the second substrate includes at least one embossing groove on the upper surface thereof. | 2021-11-25 |
20210366800 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In one example, a semiconductor device comprises a main substrate comprising a first side and a main conductive structure, and a first component module over the first side of the main substrate. The first component module comprises a first electronic component and a first module encapsulant contacting a lateral side of the first electronic component. The semiconductor device further comprises a second component module over the first side of the main substrate. The second component module comprises a second electronic component and a second module encapsulant contacting a lateral side of the second electronic component. The semiconductor device further comprises a main encapsulant over a first side of the main substrate and between the first component module and the second component module. Other examples and related methods are also disclosed herein. | 2021-11-25 |
20210366801 | METHOD OF MANUFACTURING ELECTRONIC COMPONENT MODULE, AND ELECTRONIC COMPONENT MODULE - A method of manufacturing an electronic component module includes a sacrificial-body arrangement step of disposing a sacrificial body on a first principal surface of a support, the support including the first principal surface and a second principal surface, the sacrificial body being smaller than the first principal surface when viewed in a thickness direction of the support, a resin molding step of molding a resin structure on the first principal surface so as to cover the sacrificial body disposed on the first principal surface, a recess forming step of forming a recess in the resin structure by removing the sacrificial body, a wiring-layer forming step of forming a wiring layer on a side surface of the recess and on a principal surface of the resin structure, the principal surface connecting with the side surface, and a component mounting step of mounting an electronic component in the recess. | 2021-11-25 |
20210366802 | SEMICONDUCTOR PACKAGE, INTEGRATED OPTICAL COMMUNICATION SYSTEM - A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure. | 2021-11-25 |
20210366803 | TEMPERATURE SENSOR CIRCUITS FOR INTEGRATED CIRCUIT DEVICES - An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced. | 2021-11-25 |
20210366804 | TEMPERATURE SENSOR CIRCUITS FOR INTEGRATED CIRCUIT DEVICES - An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced. | 2021-11-25 |
20210366805 | SEMICONDUCTOR STRUCTURE - The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack. | 2021-11-25 |
20210366806 | Spring Loaded Compliant Coolant Distribution Manifold for Direct Liquid Cooled Modules - Systems and methods for using spring force based compliance to minimize the bypass liquid flow gaps between the tops of chip microfins and bottom side of manifold ports are disclosed herein. A fluid delivery and exhaust manifold structure provides direct liquid cooling of a module. The manifold sits on top of a chip with flow channels. Inlet and outlet channels of the manifold in contact with flow channels of the chip creates an intricate crossflow path for the coolant resulting in improved heat transfer between the chip and the working fluid. The module is also designed with pressure reduction features using internal leakage flow openings to account for pressure differential between fluid entering and being expelled from the module. | 2021-11-25 |
20210366807 | Direct Liquid Cooling With O-Ring Sealing - Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket. | 2021-11-25 |
20210366808 | THROUGH-STACK CONTACT VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE AND METHODS OF FORMING THE SAME - A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. Retro-stepped dielectric material portions are formed in each of the first-tier structure and the second-tier structure. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Laterally-isolated contact via structures can be formed through the second-tier structure and a first-tier retro-stepped dielectric material portion on first electrically conductive layers in the first-tier structure. Sacrificial landing pad structures can be employed to enable concurrent formation of contact via cavities through the retro-stepped dielectric material portions. | 2021-11-25 |
20210366809 | MANUFACTURING METHOD FOR REFLOWED SOLDER BALLS AND THEIR UNDER BUMP METALLURGY STRUCTURE - Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed. | 2021-11-25 |
20210366810 | POWER SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING THE SAME - An object is to suppress a decrease in reliability due to peeling of an insulating layer and another member of a power semiconductor device. A power semiconductor device according to the present invention includes: a power semiconductor element; a conductor portion that transmits a current to the power semiconductor element; an insulating layer in contact with a surface of the conductor portion on a side opposite to a side on which the power semiconductor element is arranged; a metallic heat dissipating portion that opposes the conductor portion while sandwiching the insulating layer; and an output terminal that is connected to the conductor layer and outputs a different signal depending on a contact state of the insulating portion, the insulating layer having an insulating portion and a conductor layer sandwiched between the conductor portion and the metallic heat dissipating portion via the insulating portion. | 2021-11-25 |
20210366811 | INTEGRATED CIRCUIT PACKAGE ELECTRONIC DEVICE - A surface mount electronic device providing an electrical connection between an integrated circuit (IC) and a printed circuit board (PCB) is provided and includes a die and a dielectric material formed to cover portions of the die. Pillar contacts are electrically coupled to electronic components in the die and the pillar contacts extend from the die beyond an outer surface of the die. A conductive ink is printed on portions of a contact surface of the electronic device package and forms electrical terminations on portions of the dielectric material and electrical connector elements that connect an exposed end surface of the pillar contacts to the electrical terminations. | 2021-11-25 |
20210366812 | Power Semiconductor Device - An object of the present invention is to provide a power semiconductor device capable of improving seismic resistance while suppressing a decrease in assembly efficiency. According to the present invention, a power semiconductor device | 2021-11-25 |
20210366813 | POWER SEMICONDUCTOR MODULE - This power semiconductor module includes: a bus bar to which each of first main electrodes of semiconductor switching elements is joined; a heat-dissipating metal substrate to which each of second main electrodes of the semiconductor switching elements is joined; and a control gate terminal connected to each of gate pads of the semiconductor switching elements by a bonding wire, wherein at least two of the plurality of semiconductor switching elements are arranged adjacently to each other on the heat-dissipating metal substrate and electrically connected in parallel to form one arm. | 2021-11-25 |
20210366814 | Giga Interposer Integration through Chip-On-Wafer-On-Substrate - A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die. | 2021-11-25 |
20210366815 | PACKAGE STRUCTURE, RDL STRUCTURE COMPRISING REDISTRIBUTION LAYER HAVING GROUND PLATES AND SIGNAL LINES - A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace. | 2021-11-25 |
20210366816 | SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via. | 2021-11-25 |
20210366817 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first board that has a first end surface and a second end surface opposite to the first end surface; a second board that is attached to the second end surface of the first board; a plurality of first electrodes that are provided on the first end surface; a second electrode that is provided on the second end surface and electrically coupled to an electrode of the second board; an internal wiring that is provided inside the first board and electrically coupled to the second electrode; a plurality of third electrodes that are provided inside the first board and electrically couple the first electrodes to the internal wiring; and a strain sensor that is provided inside the first board and measures a strain generated in the first board, in which a linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the first board. | 2021-11-25 |
20210366818 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, and a plurality of underfills between the package substrate and the semiconductor chip. The package substrate includes a trench formed in the package substrate and a plurality of dams on both sides of the trench, respectively. The top surfaces of the plurality of dams may be positioned at a lower level than the bottom surface of the semiconductor chip in a cross-sectional view of the semiconductor package with the package substrate providing a base reference level. | 2021-11-25 |
20210366819 | CRYOGENIC INTEGRATED CIRCUITS - Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer. | 2021-11-25 |
20210366820 | LATERALLY UNCONFINED STRUCTURE - Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. | 2021-11-25 |
20210366821 | THROUGH PLATE INTERCONNECT FOR A VERTICAL MIM CAPACITOR - An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via. | 2021-11-25 |
20210366822 | HYBRID VIA INTERCONNECT STRUCTURE - A hybrid via interconnect structure includes a first metal filling at least partially surrounded by a first barrier metal layer, a second metal filling at least partially surrounded by a second barrier metal layer, and a hybrid via formed between the first metal filling and the second metal filling. The hybrid via provides an electrical connection between the first metal filling and the second metal filling and is formed of a different material than the first metal filling, the second metal filling, the first barrier metal layer, and the second barrier metal layer. The hybrid via interconnect structure can be formed during the back end of line (BEOL) portion of an integrated circuit (IC) fabrication process to provide reduced interconnect resistance and improved ease of fabrication. | 2021-11-25 |
20210366823 | BACK END OF LINE INTEGRATION FOR SELF-ALIGNED VIAS - Disclosed herein are methods for manufacturing an integrated circuit (IC) structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the back end of line (BEOL), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to both a metal line above it and a metal line below it. Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability if the final IC structures. | 2021-11-25 |
20210366824 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line. | 2021-11-25 |
20210366825 | VERTICAL MEMORY DEVICE - A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts. | 2021-11-25 |
20210366826 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a die, a plurality of dielectric layers over the die, a via and at least one ring. The dielectric layers include a plurality of first surfaces facing the die. The via penetrates through the plurality of dielectric layers and includes at least one second surface facing the die. The ring surrounds the via and is disposed in at least one of the plurality of dielectric layers. The ring includes a third surface facing the die, wherein the third surface of the at least one ring is inserted between the at least one second surface of the via and the first surface of the at least one of the plurality of dielectric layers. | 2021-11-25 |
20210366827 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends. | 2021-11-25 |
20210366828 | SEMICONDUCTOR STRUCTURE WITH ULTRA THICK METAL AND MANUFACTURING METHOD THEREOF - The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches. | 2021-11-25 |
20210366829 | SEMICONDUCTOR DEVICES INCLUDING LINE IDENTIFIER - A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged m the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group. | 2021-11-25 |
20210366830 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A device includes a first semiconductor layer that includes a first region provided between a first insulating portion and first conductive layers, a second region provided between a second insulating portion and second conductive layers, and a third region provided between the first region and the second region. A first insulating layer includes a thickness (t1) from a surface in the first region to a gate insulating film. The first insulating layer includes a thickness (t2) from a surface in the second region to the gate insulating film. The first insulating layer includes a thickness (t3) from a surface in the third region to the gate insulating film, which is larger than t1-2 nanometers (nm), and larger than t2-2 nm. | 2021-11-25 |
20210366831 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THEREOF - An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width. | 2021-11-25 |
20210366832 | SEMICONDUCTOR PACKAGE AND A METHOD OF FABRICATING THE SAME - A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole. | 2021-11-25 |
20210366833 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion. | 2021-11-25 |
20210366834 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate. | 2021-11-25 |
20210366835 | EMBEDDED DIE MICROELECTRONIC DEVICE WITH MOLDED COMPONENT - Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated. substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding. | 2021-11-25 |
20210366836 | A SUBSTRATE OF A DISPLAY PANEL WITH ALIGNMENT MARKS, AND A METHOD OF MAKING THE SAME - Disclosed herein is a substrate of a display panel, comprising: a support; a first alignment mark on the support; a first dielectric layer covering the first alignment mark; an auxiliary alignment mark aligned with the first alignment mark, wherein the auxiliary alignment mark comprises a recess into the first dielectric layer. Further disclosed herein is a display panel comprising the substrate, and a system comprising the display panel. Also disclosed herein is a method comprising: forming a first alignment mark on a support; forming a first dielectric layer covering the first alignment mark; and forming an auxiliary alignment mark aligned with the first alignment mark; wherein the auxiliary alignment mark comprises a recess into the first dielectric layer. | 2021-11-25 |
20210366837 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP AND METHOD OF DICING A SEMICONDUCTOR SUBSTRATE - A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure. | 2021-11-25 |
20210366838 | RADIO-FREQUENCY (RF) INTEGRATED CIRCUIT (IC) (RFIC) PACKAGES EMPLOYING A SUBSTRATE SIDEWALL PARTIAL SHIELD FOR ELECTRO-MAGNETIC INTERFERENCE (EMI) SHIELDING, AND RELATED FABRICATION METHODS - Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate. | 2021-11-25 |
20210366839 | MODULE | 2021-11-25 |
20210366840 | DC AND AC MAGNETIC FIELD PROTECTION FOR MRAM DEVICE USING MAGNETIC-FIELD-SHIELDING STRUCTURE - In some embodiments, the present application provides a method for manufacture a memory device. The method includes forming a multilayer stack including a first magnetic layer and a first dielectric layer and forming another magnetic layer. The multilayer stack and the another magnetic layer are tailored to meet dimensions of a package structure. The package structure includes a chip having a memory cell and an insulating material enveloping the chip, where an outer surface of the package structure comprises the insulating material. The tailored multilayer stack and the tailored another magnetic layer are attached to the outer surface of the package structure. | 2021-11-25 |
20210366841 | Weight Optimized Stiffener and Sealing Structure for Direct Liquid Cooled Modules - A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate. | 2021-11-25 |
20210366842 | CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure. A width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure. | 2021-11-25 |
20210366843 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device. | 2021-11-25 |
20210366844 | VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION - The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures. | 2021-11-25 |
20210366845 | Air Channel Formation in Packaging Process - A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring. | 2021-11-25 |
20210366846 | ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD OF FORMING THE SAME - A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails. | 2021-11-25 |
20210366847 | SEMICONDUCTOR PACKAGE INCLUDING CAPACITOR - A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively. | 2021-11-25 |
20210366848 | GROUND REFERENCE SHAPE FOR HIGH SPEED INTERCONNECT - Apparatus and methods are provided for providing provide high-speed interconnect using bond wires. According to various aspects of the subject innovation, the provided techniques may provide a ground shape to shield a high-speed signal wire from the substrate in a semiconductor assembly. In an exemplary embodiment, there is provided an assembly that may comprise a substrate, a semiconductor die attached to the substrate, a signal bond wire connecting a bond pad on the semiconductor die and a bond finger on the substrate, and a ground shape on the substrate to shield the signal wire from the substrate. | 2021-11-25 |
20210366849 | ELECTRONIC MODULE AND METHOD OF MANUFACTURING ELECTRONIC MODULE - A high-frequency module includes a semiconductor element, a first insulating layer, an acoustic wave element, a second insulating layer, a first intermediate layer, and a second intermediate layer. The first intermediate layer is interposed between the acoustic wave element and the semiconductor element, and has a thermal conductivity lower than the first and second insulating layers. The second intermediate layer is interposed between the first insulating layer and the second insulating layer, and has a thermal conductivity lower than the first and second insulating layers. A step is provided between a first principal surface of the first insulating layer and one principal surface of the semiconductor element. The distance between first and second principal surfaces of the first insulating layer is greater than the distance between the second principal surface of the first insulating layer and the one principal surface of the semiconductor element. | 2021-11-25 |
20210366850 | Display Panel, Manufacturing Method of Display Panel, and Display Device - A display panel, a manufacturing method thereof, and a display device are disclosed. The display panel includes: a base substrate, provided with a terminal a terminal protection layer pattern; the terminal protection layer pattern includes a first shielding region and a first opening region, an orthographic projection of the first shielding region on the base substrate and an orthographic projection of the terminal on the base substrate have an overlapping region, the overlapping region is located at an edge of the orthographic projection of the terminal on the base substrate, and an orthographic projection of the first opening region on the base substrate is located in the orthographic projection of the terminal on the base substrate. | 2021-11-25 |
20210366851 | METHOD OF TREATMENT OF AN ELECTRONIC CIRCUIT FOR A HYBRID MOLECULAR BONDING - A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding. | 2021-11-25 |
20210366852 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first substrate, a first redistribution line (RDL) pad, and a first bond pad. The first substrate has a first conductive pad. The RDL pad is disposed over the first conductive pad and extending to a top surface of the first substrate. The first bond pad is disposed on a first portion of the first RDL pad, in which the first portion of the first RDL pad overlaps with the top surface of the first substrate. | 2021-11-25 |
20210366853 | SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR CHIP HAVING A REDISTRIBUTION LAYER - A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is omitted. | 2021-11-25 |