47th week of 2010 patent applcation highlights part 42 |
Patent application number | Title | Published |
20100297799 | IMAGE CAPTURE UNIT - An image capture unit and its manufacturing method. The image capture unit includes a thinned-down integrated circuit chip having an image sensor on its upper surface side. A wall extends above a peripheral upper surface ring-shaped area, and a lens rests on the high portion of the wall. | 2010-11-25 |
20100297800 | SOLAR CELL PANELS AND METHOD OF FABRICATING SAME - A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover plate transparent to visible light; and placing an array of rows and columns of solar cell chips between the bottom cover plate and the top cover plate, each solar cell chip of the array of solar cell chips comprising an anode adjacent to a top surface and a cathode adjacent to a bottom surface of the solar cell chip, the bus bar electrically contacting each anode of each solar cell chip of the array of solar cell chips and the contact frame contacting each anode of each solar cell chip of the array of solar cell chips. | 2010-11-25 |
20100297801 | METHOD FOR PRODUCING ELECTRIC CONTACTS ON A SEMICONDUCTOR COMPONENT - Process for producing strip-shaped and/or point-shaped electrically conducting contacts on a semiconductor component like a solar cell, includes the steps of applying a moist material forming the contacts in a desired striplike and/or point-like arrangement on at least one exterior surface of the semiconductor component; drying the moist material by heating the semiconductor component to a temperature T | 2010-11-25 |
20100297802 | SOLAR CELL ASSEMBLIES AND METHOD OF MANUFACTURING SOLAR CELL ASSEMBLIES - Solar cell assemblies and method of making solar cell assemblies. The method, including: fabricating solar cell chips on solar cell wafers; dicing the solar cell wafers into individual solar cell chips; packaging the individual solar cell chips in molded plastic packages to form solar cell chip packages; and mounting on and electrically connecting one or more of the solar cell chip packages to a printed circuit board. The assemblies including a printed circuit board; one or more solar cell chip packages mounted on and electrically connected to the printed circuit board, each of said one or more solar chip packages comprising a solar cell chip and a lead frame encapsulated in a molded plastic body, top surfaces the solar cell chips exposed in top surfaces of the molded plastic bodies. | 2010-11-25 |
20100297803 | NANOPHOTOVOLTAIC DEVICES - The present invention provides nanophotovoltaic devices having sizes in a range of about 50 nm to about 5microns, and method of their fabrication. In some embodiments, the nanophotovoltaic device includes a semiconductor core, e.g., formed of silicon, sandwiched between two metallic layers, one of which forms a Schottky barrier junction with the semiconductor core and the other forms an ohmic contact therewith. In other embodiment, the nanophotovoltaic device includes a semiconductor core comprising a p-n junction that is sandwiched between two metallic layers forming ohmic contacts with the core. | 2010-11-25 |
20100297804 | METHOD OF MAKING BACKSIDE ILLUMINATION IMAGE SENSOR - An exemplary method for making a backside illumination image sensor includes the follow steps. A substrate having a top surface is firstly provided. Secondly, many recesses are formed in the top surface. Thirdly, a light pervious layer is applied on the top surface. The light pervious layer has a plurality of filling portions received in the recesses. Then, an epitaxial silicon layer is applied on the light pervious layer. Next, many light sensitive regions and circuits are formed on the epitaxial silicon layer. Finally, the substrate is etched to expose the filling portions of the light pervious layer, thereby forming the backside illumination image sensor with the filling portions functioning as micro-lenses. | 2010-11-25 |
20100297805 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD OF THE SAME, AND IMAGING APPARATUS - In a solid-state imaging device, the pixel circuit formed on the first surface side of the semiconductor substrate is shared by a plurality of light reception regions. The second surface side of the semiconductor substrate is made the light incident side of the light reception regions. The second surface side regions of the light reception regions formed in the second surface side part of the semiconductor substrate are arranged at approximately even intervals and the first surface side regions of the light reception regions formed in the first surface side part of the semiconductor substrate are arranged at uneven intervals, respectively, and the second surface side regions and the first surface side regions are joined respectively in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate. | 2010-11-25 |
20100297806 | METHOD OF MANUFACTURING SOLAR CELL MODULE - While using the same laser device, a slit (S | 2010-11-25 |
20100297807 | CMOS IMAGER HAVING A NITRIDE DIELECTRIC - An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen containing insulating material, preferably be one of a silicon nitride layer, an ONO layer, a nitrode/oxide layer and an oxide/nitrode layer. The nitrogen containing insulating layer provides an increased capacitance in the photogate region, higher breakdown voltage, a wider dynamic range and an improved signal to noise ratio. The invention also provides a method for fabricating a CMOS imager containing the nitrogen containing insulating layer. | 2010-11-25 |
20100297808 | MOLECULAR ELECTRONIC DEVICE INCLUDING ORGANIC DIELECTRIC THIN FILM AND METHOD OF FABRICATING THE SAME - Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an electrode formed on the molecular active layer. The organic dielectric thin film may be immobilized on the electrode or a Si layer by a self-assembled method. The organic dielectric thin film may include first and second molecular layers bound together through hydrogen bonds. An organic compound may be self-assembled over the substrate to form the organic dielectric thin film. The organic compound may include an M′-R-T structure, where M′, R and T represent a thiol or silane derivative, a saturated or unsaturated C | 2010-11-25 |
20100297809 | ORGANIC TRANSISTOR, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND ORGANIC TRANSISTOR - It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 10 | 2010-11-25 |
20100297810 | Power Semiconductor Device and Method for Its Production - A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic. | 2010-11-25 |
20100297811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer | 2010-11-25 |
20100297812 | METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME - A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked. | 2010-11-25 |
20100297813 | Semiconductor package with position member - The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package. | 2010-11-25 |
20100297814 | ELECTRONIC SYSTEM MODULES AND METHOD OF FABRICATION - A trace routing method for a multi-layer interconnection circuit includes the steps of providing stacked contacts with trace stubs at input/output pads of said interconnection circuit, and limiting contacts between conductive layers to two-level contacts in routing areas where maximum routing density is desired. | 2010-11-25 |
20100297815 | Transistor Layout for Manufacturing Process Control - A symmetrical circuit is disclosed (FIG. | 2010-11-25 |
20100297816 | NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME - A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region. | 2010-11-25 |
20100297817 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A method for manufacturing a thin film transistor (TFT) is disclosed. The method is achieved by forming and defining a source and a drain of a thin film transistor through two lithographic processes cycles so that the channel length (L) of the thin film transistor can be reduced to 1.5 to 4.0 μm. Besides, the I | 2010-11-25 |
20100297818 | Semiconductor Devices Having pFET with SiGe Gate Electrode and Embedded SiGe Source/Drain Regions and Methods of Making the Same - In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask. | 2010-11-25 |
20100297819 | Trench DRAM Cell with Vertical Device and Buried Word Lines - A DRAM array having trench capacitor cells of potentially 4F | 2010-11-25 |
20100297820 | Embedded Semiconductor Device Including Planarization Resistance Patterns and Method of Manufacturing the Same - An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs. | 2010-11-25 |
20100297821 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. The method includes forming an isolation region in a semiconductor substrate; forming a gate electrode over an element region defined by the isolation region formed in the semiconductor substrate; and forming a semiconductor lager in the element region at both sides of the gate electrode apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed. | 2010-11-25 |
20100297822 | Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions - The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location. | 2010-11-25 |
20100297823 | METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS - Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures. | 2010-11-25 |
20100297824 | MEMORY STRUCTURE WITH REDUCED-SIZE MEMORY ELEMENT BETWEEN MEMORY MATERIAL PORTIONS - A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer. | 2010-11-25 |
20100297825 | Passive Components in the Back End of Integrated Circuits - Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members. | 2010-11-25 |
20100297826 | Method of Manufacturing Nonvolatile Memory Device - In one embodiment of a method of manufacturing a nonvolatile memory device, a tunnel insulating layer and a charge trap layer are first formed over a semiconductor substrate that defines active regions and isolation regions. The tunnel insulating layer, the charge trap layer, and the semiconductor substrate formed in the isolation regions are etched to form trenches for isolation in the respective isolation regions. The trenches for isolation are filled with an insulating layer to form isolation layers in the respective trenches. A lower passivation layer is formed over an entire surface including top surfaces of the isolation layers. A first oxide layer is formed over an entire surface including the lower passivation layer. Meta-stable bond structures within the lower passivation layer are removed. A nitride layer, a second oxide layer, and an upper passivation layer are sequentially formed over an entire surface including the first oxide layer. | 2010-11-25 |
20100297827 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An adhesion layer and a supporting substrate are provided on the entire surface of the first surface side of a substrate with a metal seed film provided on the first surface side of the substrate. After the removal of the adhesion layer and the supporting substrate provided on the first surface of the substrate, an exposed part of the metal seed film is removed. After this, a plurality of semiconductor chips is stacked and first reflow is performed to the semiconductor chips. | 2010-11-25 |
20100297828 | METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR TYPE SUBSTRATE - A method for fabricating a substrate of the semiconductor on insulator type by forming an epitaxial layer of semiconducting material on a donor substrate having oxygen precipitates with a density of less than 10 | 2010-11-25 |
20100297829 | Method of Temporarily Attaching a Rigid Carrier to a Substrate - Method for temporarily attaching a substrates to a rigid carrier is described which includes forming a sacrificial layer of a thermally-decomposable polymer, e.g., poly(alkylene carbonate), and bonding the flexible substrate to the rigid carrier with the sacrificial layer positioned therebetween. Electronic components and/or circuits may then be fabricated or other semiconductor processing steps employed (e.g., backgrinding) on the attached substrate. Once fabrication is completed, the substrate may be detached from the rigid carrier by heating the assembly to decompose the sacrificial layer. | 2010-11-25 |
20100297830 | LASER PROCESSING METHOD FOR SEMICONDUCTOR WAFER - A laser processing method for a semiconductor wafer including a groove forming step of applying a pulsed laser beam having an absorption wavelength to the semiconductor wafer along a division line formed on the semiconductor wafer to thereby form a laser processed groove along the division lines on the semiconductor wafer, wherein the pulse width of the pulsed laser beam to be applied in the groove forming step is set to 2 ns or less, and the peak energy density is set in the range of 5 to 200 GW/cm | 2010-11-25 |
20100297831 | LASER PROCESSING METHOD FOR SEMICONDUCTOR WAFER - A laser processing method for a semiconductor wafer including a groove forming step of applying a pulsed laser beam having an absorption wavelength to the semiconductor wafer along a division line formed on the semiconductor wafer to thereby form a laser processed groove along the division line on the semiconductor wafer, wherein the pulse width of the pulsed laser beam to be applied in the groove forming step is set to 2 ns or less, and the peak energy density per pulse of the pulsed laser beam is set less than or equal to an inflection point where the depth of the laser processed groove steeply increases with an increase in the peak energy density. | 2010-11-25 |
20100297832 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, SUBSTRATE MANUFACTURING METHOD - Provided is a substrate processing apparatus, a semiconductor device manufacturing method, and a substrate manufacturing method. The substrate processing apparatus comprises: a reaction chamber configured to process substrates; a first gas supply system configured to supply at least a silicon-containing gas and a chlorine-containing gas or at least a gas containing silicon and chlorine; a first gas supply unit connected to the first gas supply system; a second gas supply system configured to supply at least a reducing gas; a second gas supply unit connected to the second gas supply system; a third gas supply system configured to supply at least a carbon-containing gas and connected to at least one of the first gas supply unit and the second gas supply unit; and a control unit configured to control the first to third gas supply systems. | 2010-11-25 |
20100297833 | COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF - Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotrubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates. | 2010-11-25 |
20100297834 | METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE - A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features. | 2010-11-25 |
20100297835 | METHODS FOR FABRICATING COPPER INDIUM GALLIUM DISELENIDE (CIGS) COMPOUND THIN FILMS - A method for fabricating a copper-indium-gallium-diselenide (CIGS) compound thin film is provided. In this method, a substrate is first provided. An adhesive layer is formed over the substrate. A metal electrode layer is formed over the adhesive layer. A precursor stacked layer is formed over the metal electrode layer, wherein the precursor stacked layer includes a plurality of copper-gallium (CuGa) alloy layers and at least one copper-indium (CuIn) alloy layer sandwiched between the plurality of CuGa alloy layers. An annealing process is performed to convert the precursor stacked layer into a copper-indium-gallium (CuInGa) alloy layer. A selenization process is performed to convert the CuInGa alloy layer into a copper-indium-gallium-diselenide (CuInGaSe) compound thin film. | 2010-11-25 |
20100297836 | PLASMA DOPING APPARATUS AND METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A top plate, disposed on an upper portion of a vacuum container so as to face a substrate-placing area of a sample electrode, is provided with an impurity-containing film that contains an impurity, and is formed on a top plate peripheral edge portion area that is a face exposable to a plasma generated in the vacuum container, and is located on a peripheral edge of a top plate center portion area that faces the center portion of the substrate-placing area. | 2010-11-25 |
20100297837 | Implantation using a hardmask - A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells. | 2010-11-25 |
20100297838 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 2010-11-25 |
20100297839 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE INSULATING LAYER - A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions. | 2010-11-25 |
20100297840 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process. | 2010-11-25 |
20100297841 | Method for providing a redistribution metal layer in an integrated circuit - A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability. | 2010-11-25 |
20100297842 | CONDUCTIVE BUMP STRUCTURE FOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than the UBM structure. Subsequently, a solder bump is mounted on the UBM structure and encapsulates the metal bump, so as to increase the bonding area and simultaneously allow the solder bump to be sufficiently wetted on the UBM structure to enhance bonding stress of the solder bump. | 2010-11-25 |
20100297843 | Method for Forming Vias in a Semiconductor Substrate and a Semiconductor Device having the Semiconductor Substrate - The present invention relates to a method for forming vias in a semiconductor substrate, including the following steps: (a) providing a semiconductor substrate having a first surface and a second surface; (b) forming a groove on the semiconductor substrate; (c) filling the groove with a conductive metal; (d) removing part of the semiconductor substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the semiconductor substrate; and (e) forming an insulating material in the accommodating space. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 2010-11-25 |
20100297844 | INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer. | 2010-11-25 |
20100297845 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an interlayer dielectric layer having a plurality of contact holes over a substrate, forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer, performing a first main etch process to partially etch the conductive layer to form a first conductive layer, performing a second main etch process to etch the first conductive layer using an etch gas having a slower etch rate with respect to the first conductive layer than an etch gas used in the first main etch process until an upper surface of the interlayer dielectric layer is exposed to form a second conductive layer, and performing an over-etch process to etch a certain portion of the second conductive layer, and at the same time, to etch a certain portion of the interlayer dielectric layer to form a landing plug. | 2010-11-25 |
20100297846 | Method of manufacturing a semiconductor device and substrate processing apparatus - A method of manufacturing a semiconductor device includes the steps of: forming a first metal film on the substrate placed in a processing chamber by alternately supplying at least one type of a metal compound that is an inorganic raw material and a reactant gas that has reactivity to the metal compound to the processing chamber more than once; forming a second metal film on the substrate by simultaneously supplying at least one type of a metal compound that is an inorganic raw material and a reactant gas that has reactivity to the metal compound to the processing chamber once so that the metal compound and the reactant gas are mixed with each other; and modifying at least one of the first metal film and the second metal film is modified using at least one of the reactant gas and an inert gas after at least one of the alternate supply process and the simultaneous supply process. It thus becomes possible to provide a dense, low-resistive metal film having a smooth film surface with a better quality in comparison with a titanium nitride film formed by the CVD method at a higher deposition rate, that is, at a higher productivity, in comparison with a titanium nitride film formed by the ALD method at a low temperature. | 2010-11-25 |
20100297847 | Method of forming sub-lithographic features using directed self-assembly of polymers - Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes. | 2010-11-25 |
20100297848 | ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE - The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF | 2010-11-25 |
20100297849 | PLASMA ETCHING METHOD FOR ETCHING AN OBJECT - The invention provides a plasma etching method capable of suppressing bowing of an opening of the object to be etched, and solving the lack of opening at a high aspect ratio portion in deep hole processing having a high aspect ratio. A plasma etching method for etching an object to be etched in a plasma etching apparatus using a mask patterned and formed on the object to be etched comprises sequentially performing a first step for etching the mask while attaching deposits on a side wall of an opening close to a surface of the mask pattern of the mask using fluorocarbon gas C | 2010-11-25 |
20100297850 | SELECTIVE SELF-ALIGNED DOUBLE PATTERNING OF REGIONS IN AN INTEGRATED CIRCUIT DEVICE - A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask. | 2010-11-25 |
20100297851 | COMPOSITIONS AND METHODS FOR MULTIPLE EXPOSURE PHOTOLITHOGRAPHY - Compositions for use in multiple exposure photolithography and methods of forming electronic devices using a multiple exposure lithographic process are provided. The compositions find particular applicability in semiconductor device manufacture for making high-density lithographic patterns. | 2010-11-25 |
20100297852 | METHOD OF FORMING LINE/SPACE PATTERNS - A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and the remaining second pattern structures as an etch mask, and etching the substrate using the hard mask as an etch mask. | 2010-11-25 |
20100297853 | METHOD FOR PURIFYING ACETYLENE GAS FOR USE IN SEMICONDUCTOR PROCESSES - Acetylene is treated to remove some residual storage solvent that may be present with the acetylene in a source of acetylene such as a container. Such treatment may be performed prior to supplying the acetylene to a deposition chamber or other reactor where acetylene is a reactant. After treatment, the acetylene gas stream has a relatively constant concentration of storage solvent, regardless of how much acetylene has been released from the acetylene source. The treatment may involve condensing the storage solvent from the gas stream at a certain temperature and separating the storage solvent from the gas stream. | 2010-11-25 |
20100297854 | HIGH THROUGHPUT SELECTIVE OXIDATION OF SILICON AND POLYSILICON USING PLASMA AT ROOM TEMPERATURE - Methods of fabricating an oxide layer on a semiconductor structure are provided herein. In some embodiments, a method of selectively forming an oxide layer on a semiconductor structure includes providing a substrate having one or more metal-containing layers and one or more non metal-containing layers to a substrate support in a plasma reactor; introducing a first process gas into the plasma reactor, wherein the first process gas comprises hydrogen (H | 2010-11-25 |
20100297855 | DEVICE PROCESSING METHOD - A device processing method for improving the die strength of a device divided from a semiconductor wafer. The device processing method includes a chamfering step of applying a pulsed laser beam having an absorption wavelength to the device along the periphery of the device to thereby chamfer the periphery of the device, wherein the pulse width of the pulsed laser beam to be applied in the chamfering step is set to 2 ns or less, and the peak energy density is set in the range of 5 to 200 GW/cm | 2010-11-25 |
20100297856 | PULSE TRAIN ANNEALING METHOD AND APPARATUS - The present invention generally describes apparatuses and methods used to perform an annealing process on desired regions of a substrate. In one embodiment, pulses of electromagnetic energy are delivered to a substrate using a flash lamp or laser apparatus. The pulses may be from about 1 nsec to about 10 msec long, and each pulse has less energy than that required to melt the substrate material. The interval between pulses is generally long enough to allow the energy imparted by each pulse to dissipate completely. Thus, each pulse completes a micro-anneal cycle. The pulses may be delivered to the entire substrate at once, or to portions of the substrate at a time. Further embodiments provide an apparatus for powering a radiation assembly, and apparatuses for detecting the effect of pulses on a substrate. | 2010-11-25 |
20100297857 | SUBSTRATE CONNECTING CONNECTOR AND SEMICONDUCTOR DEVICE SOCKET, CABLE CONNECTOR, AND BOARD-TO-BOARD CONNECTOR HAVING SUBSTRATE CONNECTING CONNECTOR - An electrode terminal supporting body fixed on a printed wiring board and an anisotropic conductive sheet which is positioned on the electrode terminal supporting body and on which a semiconductor device is placed are provided between first and second stiffening plates. The first and second stiffening plates are fastened by machine screws with the electrode terminal supporting body, the anisotropic conductive sheet, and the printed wiring board interposed therebetween. | 2010-11-25 |
20100297858 | ELELCTRICAL CONNECTOR WITH NOTCH FOR RECEIVING MATING COMPONENT - An electrical connector includes an insulative housing and a plurality of contacts. The insulative housing defines a base with opposite front and rear end regions along a front-to-back direction and a plurality of side walls upwardly extending from the base, the base cooperates with the sidewalls to commonly define a first receiving room. A notch defined in the front region of the base forms a second receiving room under the first receiving room, said second receiving room is smaller than the first receiving room. The contacts is disposed in the rear region of said housing with contacting sections extending upwardly beyond an upward mating face of the base and into the first receiving room. An optoelectronic module includes stacked upper portion and lower portion, said upper portion is received in the upper receiving room and said lower portion is received in the lower receiving room. Soldering tails of said contacts are located under the rear region of the base and do not extend into the second receiving room. | 2010-11-25 |
20100297859 | CONNECTOR WITH REMOVABLE COVERS - An electrical connector including a housing; one or more recesses formed in one or more sidewalls of the housing; a plurality of terminals disposed in respective portions of the housing such that solder tails of the terminals are accessible through the one or more recesses; and one or more cover elements removably coupled to the one or more sidewalls of the housing such that, in a mounted state of the connector on a PCB, the solder tails are enclosed by the one or more cover elements. | 2010-11-25 |
20100297860 | DUAL COMPRESSIVE CONNECTOR - An electrical connector for electrically connecting multiple photovoltaic bus bars. A casing includes first and second opposing walls. An elastic strip is bent into a bent elastic strip with a first leg and a second leg. The bent elastic strip is disposed between the first and second walls of the casing with the first leg pressing against the first wall and the second leg pressing against the second wall. The bent elastic strip is configured to hold at least one of the photovoltaic bus bars between the first leg and the first wall and another of the photovoltaic bus bars between the second leg and the second wall. The bent elastic strip may be formed of resilient spring metal with a thickness and an elastic modulus. The thickness and/or the elastic modulus of the elastic strip is/are configured so that the bus bars are inserted without requiring a tool to open a space and so that the bus bars are removed from the connector without requiring a tool to break the electrical connection. | 2010-11-25 |
20100297861 | SOCKET CONNECTOR HAVING IMPROVED ACTUATING MECHANISM FOR DRIVING MOVING PLATE - A socket connector includes a socket body, a moving plate movably mounted upon the socket body, and an actuating mechanism. The actuating mechanism comprises a lid, a first operating lever, and a second operating lever. The first and second operating levers are disposed between the lid and moving plate with opposite tilted angles. The first operating lever has a cam section engaged with a bearing section formed on the moving plate so as to drive the moving plate to move in a substantially horizontal direction. | 2010-11-25 |
20100297862 | CARD CONNECTOR WITH SELF-LOCKING MECHANISM - An electrical card connector ( | 2010-11-25 |
20100297863 | ELECTRICAL CONTACTOR, ESPECIALLY WAFER LEVEL CONTACTOR, USING FLUID PRESSURE - An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals. A plurality of freestanding, resilient contact elements, in one embodiment, are mechanically coupled to one of the flexible wiring layers or the semiconductor substrate and make electrical contacts between corresponding ones of the first contact terminals and the second contact terminals. In another embodiment, a method of making electrical interconnections includes joining a flexible wiring layer and a substrate together in proximity and causing a pressure differential between a first side and a second side of the flexible wiring layer. The pressure differential deforms the flexible wiring layer and causes a plurality of first contact terminals on the flexible wiring layer to electrically connect with a corresponding plurality of second contact terminals on the substrate. | 2010-11-25 |
20100297864 | DEVICE CONNECTOR PRODUCING METHOD, A DEVICE CONNECTOR AND A MOLDING STRUCTURE THEREFOR - A device connector producing method includes a primary molding step of forming a primary molded body ( | 2010-11-25 |
20100297865 | ELELCTRICAL CONNECTOR WITH LOCKING PORTIONS FOR RATAINING CARD THEREIN - An electrical connector for receiving a card includes an insulating housing, terminals and a metal frame attached to the housing. The housing includes a base having a terminal-location portion, a pair of sidewalls extending a first direction and a rear wall adjacent to the terminal-location portion. The terminals are arranged in the terminal-location portion along a second direction perpendicular to the first direction. The metal frame is attached to the housing and includes a base portion located above the terminal-location portion to define a receiving slot between the terminal-location portion and the base portion for receiving a mating end of the card, the base portion is not beyond the terminal-location portion in the first direction and the receiving. The metal frame further includes a pair of locking portions adapted for pressing against a top face of the card to lock the card in the insulating housing and moving outwards in the second direction to release the card. | 2010-11-25 |
20100297866 | ELECTRICAL CONNECTOR - Disclosed is an electrical connector including a plurality of conductive terminals. The conductive terminal comprises a base and a pair of arms. Each arm includes a connection part extending forwardly from the base, a first bending part bent and extending upwardly from the connection part, a second bending part bent upwardly from the first bending part, a first elastic arm extending upwardly from the second bending part, and a contact section formed at a rear end of the first elastic arm. The first and second bending part are bent away from the other arm while the first elastic arm extends toward the other arm. The minimum distance between the two first elastic arms and that between the two second bending parts are larger than the minimum distance between the two connection parts and that between the two contact sections. | 2010-11-25 |
20100297867 | CO-AXIAL CONNECTOR - A coaxial connector having an outer conductor with first and second plug-side ends axially opposite, and an inner conductor with first and second plug-side ends axially opposite. The outer conductor has two separate outer conductor parts arranged and configured such that they are mobile relative to each other in the axial direction, the outer conductor being configured as an outer conductor bellows between the two outer conductor parts. An elastic spring element is provided on the outer conductor and acts upon the two outer conductor parts, driving them away from each other. A change in length of the outer conductor bellows changes capacitance of the outer conductor bellows and is compensated by a correspondingly changing opposite inductance such that the characteristic impedance of the coaxial connector remains substantially constant. | 2010-11-25 |
20100297868 | CONNECTOR FOR BIOMETRIC BELT - A biometric belt connector for electrically connecting an electrode belt to a biometric device to be carried on a human or animal body. The belt connector comprises a back element and a front element configured to engage with each other in a fixed and locked arrangement, fastening in between them an end of an electrode belt, the front element having a substantially circular hole, an electrically conducting wire which forms a loop, such that part of said wire loop is exposed through said hole when the back and front elements are engaged. The wire loop is connected to a conducting element extending from an end of an electrode belt, which conducting element forms part of or is connected to an electrode in the electrode belt. The hole is of suitable dimension to form a female snap button receiver for a male snap fastener on said biometric device. | 2010-11-25 |
20100297869 | ELECTRONIC APPARATUS HAVING A COVER WHICH SYNCHRONOUSLY DEFINED AS A WALL OF A MODULAR JACK DISPOSED THEREOF - An electronic apparatus includes a base portion including a first cover, a second cover perpendicular to the first cover and a receiving cavity running through the first and second covers to respectively provide a locking slot in the first cover and an opening in the second cover. The first cover defines locking portions oppositely extending from opposite faces of the locking slot. | 2010-11-25 |
20100297870 | RJ MODULAR CONNECTOR - An RJ modular connector is provided that has wire channels that slope downward and end at openings in the bottom of the connector through which the stripped wires extend. In use, the outer jacket insulation is removed from an end portion of the cable, leaving lengths of exposed wires. The length of the exposed wire is unimportant. The wires are arranged in an essentially flat configuration and inserted longitudinally into the connector and then directed downward by the downward slope of the channels, so that the distal ends of the respective wires extend through the bottom of the connector. The protruding wire ends are then compared with a standard to confirm the correct color identification pattern for them and corresponding wire position. After the comparison is made, the protruding wire ends are crimped/secured and sheared off. Conductive contact blades are inserted, and pierce the wires. | 2010-11-25 |
20100297871 | Click-Tight Coaxial Cable Continuity Connector - A click-tight coaxial cable continuity connector is provided comprising a connector body, a post engageable with connector body, the post including a flange having a plurality of spaced-apart surface features. A nut is rotatably movable with respect to the post, wherein the nut includes an internal lip having a plurality of spaced-apart surface features, wherein the plurality of spaced-apart surface features of the nut are dimensioned to oppositely correspond in size, number and location to the plurality of spaced-apart surface features of the post. A click-tight continuity member is structurally configured to operably correspond with the dimensions of the plurality of spaced-apart surface features of the nut and also the spaced apart surface features of the post, the click-tight continuity member residing between the nut and the post. When the nut is rotated with respect to the post, the click-tight continuity member affords intermittent rotational resistance upon the nut, via structurally-induced compression forces resultant when the plurality of spaced-apart surface features of the nut are not oppositely correspondingly aligned with the plurality of spaced-apart surface features of the post. | 2010-11-25 |
20100297872 | RELAY CONNECTOR FOR FPC USING ADHESIVE - A relay connector for connecting together two free ends of flat flexible cable (FFC) is provided with an insulative housing that has a body portion with two open ends that receive free ends of the FFC. The housing includes a terminal assembly disposed in its mid-section and this terminal assembly includes a base with terminals embedded therein. The terminals extend length-wise through the base and have their body portions held by the terminal assembly base so that free ends of the terminals are free to deflect under pressure. The terminals are formed so that their free ends extend at a slight upward angle. A sheet of a thermoplastic adhesive is interposed between the terminal assembly and the housing. Free ends of the FFC are pressed into alignment with the terminal ends under heat and pressure so that the adhesive becomes plastic and flows between the terminals into contact with the FFC. Once the adhesive cools and solidifies, the two free ends of the FFC are connected together. | 2010-11-25 |
20100297873 | USB cable and method for producing the same - A method and apparatus for producing a USB cable capable of being fed out of and returned to a cable reel is disclosed along with a cable reel that houses the cable and provides connectivity for the cable. | 2010-11-25 |
20100297874 | MULTI-PORT CABLING SYSTEM AND METHOD - A multi-port cabling system for use in installing cable to an equipment rack or enclosure or within an equipment room or data center includes a cabling assembly comprising at least one connector head having a plurality of ports and at least one cable operatively connected to the plurality of ports. The at least one cable terminates internally within the connector head to operatively couple the cable to the plurality of ports. The system further includes a mounting bracket. The mounting bracket and the connector head are each configured for tool-less attachment of one or more cabling assemblies to the bracket. The mounting bracket is further configured to removably mount to an equipment rack or enclosure, and/or to a wall, to thereby install one or more cables. The cabling assembly and the cabling system help to eliminate on-site cable termination and testing during installation of cables to rack-mounted equipment. | 2010-11-25 |
20100297875 | COAXIAL CABLE CONNECTOR HAVING ELECTRICAL CONTINUITY MEMBER - A coaxial cable connector comprising a connector body; a post engageable with connector body, wherein the post includes a flange; a nut, axially rotatable with respect to the post and the connector body, the nut having a first end and an opposing second end, wherein the nut includes an internal lip, and wherein a second end portion of the nut corresponds to the portion of the nut extending from the second end of the nut to the side of the lip of the nut facing the first end of the nut at a point nearest the second end of the nut, and a first end portion of the nut corresponds to the portion of the nut extending from the first end of the nut to the same point nearest the second end of the nut of the same side of the lip facing the first end of the nut; and a continuity member disposed within the second end portion of the nut and contacting the post and the nut, so that the continuity member extends electrical grounding continuity through the post and the nut is provided. | 2010-11-25 |
20100297876 | COAXIAL ELECTRICAL CONNECTOR - A coaxial connector includes an outer conductor having a tubular section and leg sections. A central conductor having a mating portion extends in an axial direction within the tubular section, and the mating portion is centrosymmetrical about a central axis thereof. A dielectric block holds said outer and central conductors. The mating portion has a contacting portion, a transitional portion and a guiding portion, the transitional portion joins the contacting portion and the guiding portion together, the transitional portion is larger than the guiding portion and smaller than the mating portion at diameters thereof; wherein an acute angle formed by the transitional portion and the central axis is larger than an acute angle formed by the guiding portion and the central axis. | 2010-11-25 |
20100297877 | COAXIAL CONNECTOR AND ASSEMBLING METHOD OF COAXIAL CONNECTOR - To provide a coaxial connector and an assembling method of the coaxial connector in which an operation efficiency can be enhanced, and also facilities related to the assembling can be simplified. The coaxial connector | 2010-11-25 |
20100297878 | CABLE CONNECTOR HAVING IMPROVED GOUNDING MEANS - A cable connector ( | 2010-11-25 |
20100297879 | Connector With Switch - A connector includes an insulating housing, a metal shell that covers the insulative housing, and a switch. The switch includes a fixed contact and a movable contact. The fixed contact is formed by partially bending a rear end of a top surface of a metal shell downward. The metal shell covers an insulating housing to be mated with a mating connector. The movable contact extends while having a fixed end held by the insulating housing, and bifurcates at an approximate midpoint of the movable contact. The movable contact has, at one free end, an attachment section that abuts a mating connector approaching in a mating direction and a contacting section, at an opposite free end, that contacts the fixed contact when the attachment section is pushed by the mating connector. | 2010-11-25 |
20100297880 | CONNECTOR - A connector to be connected to a counterpart connector includes a circuit board having a ground layer, an insulating layer, and a first conductive layer successively stacked, the first conductive layer including a signal circuit and a ground circuit; and a second conductive layer electrically connecting the ground circuit and the ground layer, the second conductive layer being provided on a side of the counterpart connector in the ground circuit. | 2010-11-25 |
20100297881 | Electric power supply connecting device for a parameterizable electrical apparatus - There is provided an electric power supply connecting device for a parameterizable electrical apparatus, comprising a first connector for an electric power source, a second connector to the electrical apparatus and a storage device for parameter data which can be read out by the electrical apparatus. | 2010-11-25 |
20100297882 | MODULAR JACK CONNECTOR HAVING IMPROVED MAGNETIC MODULE - A modular jack connector ( | 2010-11-25 |
20100297883 | TRAILER TOW PRESERVING BATTERY CHARGE CIRCUIT - A method and integrated circuit for preserving a battery's charge and protecting electrical devices is disclosed. A maximum and a minimum battery voltage value at the output port are stored in a memory. A steady state battery voltage at the output port is measured and stored in the memory. A processor compares the measured steady battery voltage value to the maximum and the minimum battery voltage values. If the measured steady state battery voltage value is greater than the maximum battery voltage value, an over voltage state is reported by the processor. If the measured steady state battery voltage value is less than the minimum battery voltage value, a low battery voltage state is reported by the processor. | 2010-11-25 |
20100297884 | ELECTRICAL CONNECTOR WITH IMPROVED CONTACT ARRANGEMENT - An electrical connector includes an insulative housing extending in a front-to-back direction and including a rear base portion and a front tongue portion, and first and second sets of contacts held in the insulative housing. The first set of contacts includes at least one pair of differential contacts for transmitting high-speed signals. Each first contact includes a nonelastic first mating portion occupying a front section of the tongue portion. Each of the second set of contacts includes an elastic second mating portion located behind the nonelastic first mating portion along the front-to-back direction. The first and second sets of contacts are assembled to the insulative housing along opposite directions. The first and second body portions are provided with interference sections thereon to interferentially engage with the insulative housing. The first mating portion of each first contact is provided with interference sections to engage with the tongue portion of the insulative housing. | 2010-11-25 |
20100297885 | ELECTRICAL CONNECTOR HAVING PASSAGEWAYS PROTECTED FROM CONTAMINATION - An electrical connector ( | 2010-11-25 |
20100297886 | Card connector capable of detecting card entry - A card connector is composed of a base, a cover, and a terminal set. The cover is made of a metal and covered onto the base in such a way that an entrance is formed at front sides of the base and the cover and a card space is formed between the base and the cover. The terminal set includes a plurality of terminals mounted to the base. One of the base and the cover includes a working spring strip located at one side of the card connector and the other includes a passive spring strip located at the same side of the card connector as the working spring strip. The working spring strip has a working portion interfering with the card space. When a card enters the card space, the card works on the working portion to force the working spring strip to contact the passive spring strip for perfect electric conduction. | 2010-11-25 |
20100297887 | POWER SUPPLY AND CONNECTOR ASSEMBLY THEREOF - A power supply includes a body, a number of cables, a first connector, and a second connector. The first and second connectors are connected to the body of the power supply via the cables. The first connector includes a first connecting portion. The second connector includes a second connecting portion, operable to engage with the first connecting portion. | 2010-11-25 |
20100297888 | CONNECTOR - A connector comprising an insulative housing that has a top, a bottom, a first side, a second side, all four sides connected to form a mating face and a board-mounting end; a plurality of terminals supported in the housing and terminating at the board-mounting end wherein each terminal further comprises a contact portion configured to establish electrical contact with a complementary mating connector, a solder tail that extends out of the housing at the board-mounting end, a body portion that is disposed intermediate the contact portion and the solder tail and which interconnect them together; a plurality of solder tabs engaged with the housing; and a plurality of engagement portions coupled to the housing to confine the solder tabs to a predetermined position with respect to the housing. | 2010-11-25 |
20100297889 | ELECTRIC CABLE DEVICE AND INFORMATION REPRODUCTION SYSTEM - An electric cable device includes an electric cable, and a plug component. The plug component includes a terminal body with a plurality of plug terminals, a hood component, and a plug body. The hood component is disposed around the terminal body. The hood component has a width measured in a first direction of the plug component. The width of the hood component is greater than a height of the hood component that is measured in a second direction of the plug component. The first direction is perpendicular to the second direction. The plug body is disposed around part of the hood component such that the hood component protrudes from the plug body in a third direction of the plug component with the third direction being perpendicular to the first and second direction. The plug body is asymmetrically formed relative to any of planes that are perpendicular to the second direction. | 2010-11-25 |
20100297890 | ELECTRICAL CONNECTOR INTEGRALLY FORMED WITH SCREW HOLES - An electrical connector includes a plurality of terminals and an insulating housing loading terminals and defining a pair of mounting portions. Each of mounting portions has a screw hole extending along an upper to lower direction in which the electrical connector is mounted. The hole is divided into at least a first segment and a second segment below the first segment. The first segment and the second segment are tapped with a plurality of threads thereinside and open in opposite directions along a front and rear direction respectively. | 2010-11-25 |
20100297891 | CONNECTOR FOR HIGH ELECTRICAL POWER APPLICATIONS - A connector assembly includes a preassembly frame to which the ends of a number of high-voltage transmission lines are connected, whereupon the preassembly frame is mounted in an open-ended chamber contained in a connector housing. The frame includes a first end wall having openings that receive intermediate portions of the transmission lines, which first end wall carries a grounding plate having projections for engaging exposed portions of braided shielding layers of the transmission lines. The free ends of the transmission lines are provided with contact members that are supported by insulation sleeves in wall openings contained in a second end wall of the preassembly frame. A coding arrangement prevents the connector assembly from being connected to an unauthorized companion electrical device. | 2010-11-25 |
20100297892 | DETACHABLE CONNECTOR - A connector includes a housing including a first housing unit and a second housing unit. The first housing unit is fitted to the second housing unit to form a fitting opening for receiving a plug connector. The first housing unit includes a rotatable section, and the second housing unit includes a support section for supporting the rotatable section to be rotatable to freely open the fitting opening. The support section is arranged to release the rotatable section so that the first housing unit is separated from the second housing unit when a force is applied to the support section. | 2010-11-25 |
20100297893 | CONNECTOR APPARATUS - A connector apparatus includes first and second connectors that can be engaged with each other. The first connector includes a first contact and a first main body that supports the first contact. The first connector is conductive. The first main body is insulative. The second connector includes a second contact and a second main body that supports the second contact. The second contact is conductive. The second main body is insulative. The first contact includes a first connection part that can contact the second contact. The second contact includes a second connection part that can contact the first connection part at plural portions of the first connection part. The first and second connection parts substantially have the same shape and size. | 2010-11-25 |
20100297894 | TERMINAL CONNECTOR AND WIRE HARNESS - A wire barrel to be crimped onto an end of an electric wire has a surface on a side to face the electric wire. The surface has a plurality of recesses that extend in a direction that is to cross the axial direction of the electric wire and are separated from each other in the direction that is to cross the axial direction of the electric wire. The wire barrel has a thickness in a range from 0.15 mm to 1 mm before being crimped to the electric wire. Each recess has a depth in a range from 30% to 60% of the thickness of the wire barrel before the wire barrel is crimped onto the electric wire. | 2010-11-25 |
20100297895 | Marine propulsion system - Illustrative marine propulsion systems are disclosed. In a non-limiting, illustrative embodiment, a marine propulsion system includes a pump housing that is configured to be disposed below a waterline of a marine vessel and a centrifugal pump assembly that is disposed in the pump housing. The centrifugal pump assembly includes an inlet pump stage configured to receive inlet water and to discharge impulse water. The centrifugal pump assembly also includes an outlet pump stage that includes an impulse turbine wheel configured to rotate about an axis responsive to the impulse water and an outlet pump stage impeller integral with the impulse turbine wheel. The outlet pump stage impeller is configured to rotate about the axis. | 2010-11-25 |
20100297896 | MARINE PROPULSION AND CONSTRUCTIONAL DETAILS THEREOF - A mount for supporting part of a marine drive system to a marine hull, the mount comprising a rigid outer housing ( | 2010-11-25 |
20100297897 | INFLATABLE LIFERAFT - The present invention relates to an inflatable liferaft comprising at least a first inflatable flotation tube layer, a second inflatable flotation tube layer, said first and second flotation tube layers being adapted to be arranged substantially above each other, said inflatable tube layers extending circumferentially for providing a substantially ring-shaped area, and a bottom element which is adapted to provide a bottom to the substantially ring-shaped area. Furthermore, each tube layer comprises at least two inflatable tubes, said inflatable tubes being connected to each other at their ends so that each tube layer extends continuously around the ring-shaped area. The present invention also relates to a method for assembling an inflatable liferaft as well as a method for manufacturing an inflatable tube for use in an inflatable liferaft. | 2010-11-25 |
20100297898 | HARDWARE-LESS WAKEBOARD BINDING COMPONENT AND ASSEMBLY AND METHOD OF MAKING ASSEMBLY - A wakeboard binding assembly includes a binding base and an outersole. The binding base is adapted to attach both to the wakeboard, and an upper of the binding. The outersole is designed to surround the periphery of the binding base and cover the area of attachment between the binding base and the binding upper. The attachment of the upper to the binding base eliminates the need to use hardware and fasteners for attachment of the upper to the wakeboard. | 2010-11-25 |