47th week of 2010 patent applcation highlights part 27 |
Patent application number | Title | Published |
20100296297 | LIGHT EMITTER - A light emitter is disclosed herein. The light emitter may have a lead frame and a plastic reflector cup. The lead frame may have a planar portion; a bond area having a light-emitting diode attached thereto; and at least two terminals configured for surface mount technology. The reflector cup may be proximate the bond area and may have an opening, wherein light emitted from the light-emitting diode passes through the opening; a side wall extending between the planar portion and the opening; and a clear lens located proximate the opening and attached to the reflector cup. The combination of the lens and the reflector cup causes a light beam originating from the light-emitting diode to be less than fifteen degrees. | 2010-11-25 |
20100296298 | REAR-BEVELED MIRROR WITH DAY/NIGHT ADJUSTABLE BACKLIGHTING - A rear-beveled mirror has backlighting located near the beveled areas. The beveled areas, having the backlighting, may be located in at least two opposite sides of the mirror. The angle of the bevel may be adjusted so that the backlighting may pass through the bevel and focus on a subject standing at a typical distance away from the mirror. This typical distance may vary with the type of mirror that includes the backlighting. For example, a make-up mirror may focus the light for use from about 1-2 feet away from the mirror; and a bathroom vanity mirror may focus the light for use from about 2-4 feet away from the mirror. | 2010-11-25 |
20100296299 | Demountable Lampshade - The present invention provides a demountable lampshade that comprises a frame and a semitransparent mask; the frame includes a support ring, a fixing plate, and support bars connecting the support ring and the fixing plate; a lamp installation seat is arranged on the fixing plate; the mask is formed by multiple non-light tight surfaces being connected, is provided with up and down two openings, and is demountable to be arranged to the frame by socket joint. The mask not only can be mounted to the frame to form a lampshade, but also can be folded up to be stored solely without the frame, thereby being more convenient for dismounting and transport. The mask and the frame are independent to each other, so, if either one is damaged, it can be directly replaced without the need to discard the whole lampshade. | 2010-11-25 |
20100296300 | LED lamp - An LED lamp includes a glass electric light bulb ( | 2010-11-25 |
20100296301 | Pull-down Self-supportive Lighting mounted on hand-reachable ceilings - Pull-down self-supportive lighting device mounted on hand-reachable ceilings, the lighting device comprising retracting unit ( | 2010-11-25 |
20100296302 | INTERIOR COMPONENTS HAVING ILLUMINATION FEATURES - An interior component having an illuminated portion comprises a trim cover positioned over a substrate. At least one light conductive element is in communication with an illumination source. A carrier engages the trim cover. The carrier further secures the light conductive element to the trim cover. The carrier has a plurality of windows formed therethrough such that the light conductive element is visible through the plurality of windows. The illuminated portion may further include an emblem in communication with the light source. The illuminated interior component may be formed by a method that includes the steps of forming a light conductive element that includes extruding an optical guide and a carrier having a mounting tab thereon. | 2010-11-25 |
20100296303 | Touchless Keyless Entry Keypad Integrated with Electroluminescence Backlight - The present invention is a dead front actuating assembly, including a first layer having at least one selectively illuminated area, and a second layer having a plurality of sensors used for activating the at least one selectively illuminated area such that the at least one selectively illuminated area becomes illuminated, and the first layer is adjacent to the second layer. | 2010-11-25 |
20100296304 | COMBINATION FOR A VEHICLE INCLUDING A SELF-CONTAINED LIGHT - A combination for a vehicle is set forth herein. The combination includes a compartment positioned in the vehicle. The compartment is defined by a plurality of surfaces generally facing one another to define an interior volume. The compartment is thereby operable to hold a stowable item. A first surface of the plurality of surfaces is substantially fixed relative to the vehicle and a second surface of the plurality of surfaces is movable relative to the first surface. The combination also includes at least one self-contained light mounted on the second surface. The at least one self-contained light includes at least one light emitting structure and at least one battery. | 2010-11-25 |
20100296305 | VEHICLE LIGHT - A vehicle light is provided which can prevent the accumulation of assembly errors during the assembling of separate optical components. The vehicle light can include a first heat sink having a first heat sink body and a first heat radiation fin, and a first optical system configured to form a part of a predetermined light distribution pattern. The first optical system can include a first LED light source, a first reflector configured to reflect light emitted from the first LED light source, and a projection lens configured to allow light reflected from the first reflector to pass therethrough. The first LED light source, the first reflector, and the projection lens can be secured to an upper surface of the first heat sink body. | 2010-11-25 |
20100296306 | VEHICLE LIGHT - A light can be configured by assembling an additional optical system in a lower optical system in a period of time that can be shorter than that of the conventional case. In addition to this, accumulation of assembly errors can be avoided during the assembling of these optical systems. The vehicle light can include a first optical system configured to form a part of a predetermined light distribution pattern, and a second optical system disposed adjacent to the first optical system and configured to form a part of the predetermined light distribution pattern. The second optical system can include a light source, and a reflector including a first reflecting surface, a second reflecting surface, and a third reflecting surface. The first reflecting surface can be disposed in the light emitting direction of the light source, and the first reflecting surface can reflect light emitted from the light source to a predefined illuminating direction, for forming a part of the predetermined light distribution pattern. The second reflecting surface can be disposed in the light emitting direction of the light source and extend from the lower end of the first reflecting surface, and can reflect light emitted from the light source towards the third reflecting surface. The third reflecting surface can be disposed at a position so that the light-emitting areas of the first optical system and the second optical system are observed as an integrated single light-emitting area of the optical systems, and can reflect light from the second reflecting surface to a predefined illuminating direction. The reflector can be integrally formed with the first reflecting surface, the second reflecting surface, and the third reflecting surface. | 2010-11-25 |
20100296307 | VEHICULAR LAMP - A vehicular lamp includes a lamp unit disposed inside a lamp chamber and an aiming mechanism. The lamp chamber is formed from a lamp body opening forward and a front cover attached to the front opening portion of the lamp body. The aiming mechanism is interposed between the lamp unit and the lamp body. The aiming mechanism performs an optical axis adjustment by tiltably supporting the lamp unit with respect to the lamp body. The aiming mechanism includes a rotational operation portion supported by a lamp body side fixing portion provided on the lamp body; a screw portion threadedly engaged with a lamp unit side fixing portion provided on the lamp unit; and a connection portion that joins the rotational operation portion and the screw portion. At least part of the connection portion has radial flexibility and no axial elasticity. Torque from the rotational operation portion is transmitted to the screw portion to move the lamp unit side fixing portion in the vehicle longitudinal direction. | 2010-11-25 |
20100296308 | VEHICLE HEADLAMP - A vehicle headlamp includes a light source section | 2010-11-25 |
20100296309 | ILLUMINATION DEVICE - An exemplary illumination device includes a light source and a light-pervious light guiding barrel. The light source is configured for emitting light along a given light path. The light-pervious light guiding barrel receives the light source therein, and the barrel includes light guiding regions with different light directing and/or reflecting capabilities. In addition, the barrel is rotatable relative to the light source such that each of the light guiding regions can be selectively placed on the light path to direct and/or reflect the light from the light source. | 2010-11-25 |
20100296310 | BACKLIGHT UNIT OF DISPLAY APPARATUS - A backlight unit of a display apparatus is provided. The backlight unit includes a display housing, a light source which is arranged along an inner circumference the display housing, a light guide plate through which light of the light source is transmitted, and which forms surface light, an optical sheet which is disposed on an upper side of the light guide plate to upwardly diffuse the light of the light source transmitted through the light guide plate, a plurality of first fixing units, each of which fix both the light guide plate and the optical sheet, a plurality of second fixing units which support only the light guide plate, and a support frame which is connected to the display housing to fix the optical sheet to the display housing provisionally, and has a window formed on a surface corresponding to the light guide plate to allow light to pass therethrough. | 2010-11-25 |
20100296311 | Moire reducing optical substrates with irregular prism structures - An optical substrate having a structured surface that enhances brightness and reduces moiré effect. The optical substrate has a three-dimensionally varying, structured light output surface that comprises an irregular prismatic structure. The irregular prismatic structure may be viewed as comprising longitudinal prism blocks or rows thereof, arranged laterally defining peaks and valleys. Adjacent peaks, adjacent valleys, and/or adjacent peak and valley may be parallel or non-parallel, in an orderly, semi-orderly, random, or quasi-random manner. The lateral adjacent peaks, adjacent valleys, and/or adjacent peak and valley are not parallel. The adjacent irregular prism blocks may be irregular longitudinal sections having the same length, or random or quasi-random irregular sections having different lengths. The facets of each prism block may be flat, or curved (convexly and/or concavely). | 2010-11-25 |
20100296312 | LIGHTING SYSTEM WITH DICHROMATIC SURFACES - A high efficiency lighting system ( | 2010-11-25 |
20100296313 | BACKLIGHT MODULE - A backlight module includes a housing, at least a light-mixing tube, a plurality of light emitting devices, and at least a reflector. The housing includes a bottom sheet and a frame, in which the bottom sheet and the frame define a chamber. The frame is a hollow structure, and inner walls of the frame define the light-mixing tube. The light emitting devices are disposed at a light entrance of the light-mixing tube. Lights generated by the light emitting devices enter the light-mixing tube from the light entrance, mix in the light-mixing tube, and emit from a light exit of the light-mixing tube. Lights emit from the light-mixing tube are reflected at the reflector and therefore are reflected into the chamber. | 2010-11-25 |
20100296314 | LIGHTING DEVICE AND DISPLAY DEVICE - A lighting device includes a plurality of light-transmitting guide plates | 2010-11-25 |
20100296315 | PIEZOELECTRIC POWER CONVERTER - Disclosed is a piezoelectric power supply converter, wherein, a piezoelectric element is utilized to replace a conventional capacitor, due to characteristic of mechanical resonance of said piezoelectric element, said piezoelectric element may contain higher capacitance than said conventional capacitor, and a parasitic resistance of said piezoelectric element is smaller that that of an ordinary capacitor. Through a resonance between an externally added inductive element and a piezoelectric-capacitor and said resonance of said piezoelectric element itself, said piezoelectric element is capable of transmitting electrical energy efficiently, thus achieving large output power. Therefore, said piezoelectric-capacitor is capable of improving shortcomings of said conventional capacitors of low voltage endurance, large leakage current, and small output power. | 2010-11-25 |
20100296316 | PIEZOELECTRIC CONVERTER WITH PRIMARY REGULATION AND ASSOCIATED PIEZOELECTRIC TRANSFORMER - The present invention relates to voltage transformers, comprising multi-layer structures of piezoelectric ceramics, so-called piezoelectric transformers. The present invention further relates to switched mode power supplies, comprising such a piezoelectric transformer as part of a piezoelectric converter. The piezoelectric transformer according to the invention comprises a primary-side electrode arrangement ( | 2010-11-25 |
20100296317 | EXTENSIBLE SWITCHING POWER CIRCUIT - An extensible switching power circuit includes a plurality of switching power modules and a plurality of synchronous signal generators. Every two adjacent switching power modules are connected through a synchronous signal generator. The switching power modules generate induction electric potentials. Each synchronous pulse generator measures relevant electric potentials of the previous switching power module connected thereto and generates corresponding synchronous signals sent to the subsequent switching power module connected thereto. The subsequent switching power module regulates the phase of its induction electric potential according to the synchronous signals, such that the induction electric potentials of the two adjacent switching power modules compensate each other's energy gaps. | 2010-11-25 |
20100296318 | System and Method for Ringing Suppression in a Switched Mode Power Supply - In one embodiment, a method of operating a switched-mode power supply having a switch coupled to a drive signal is disclosed. The method includes shutting off the switch with the drive signal at a first instance of time, and comparing a magnitude of a voltage of a power supply node to a threshold after shutting off the switch. If the magnitude of the voltage of the power supply node exceeds the threshold, the switch is inhibited from turning on for a first time interval. | 2010-11-25 |
20100296319 | POWER SOURCE MODULE WITH BROAD INPUT VOLTAGE RANGE - The present invention discloses a power source module with a broad input voltage range, which includes a first and a second power source input terminals, a rectification filter circuit, and a conversion circuit connected between the first and the second power source input terminals and the rectification filter circuit, and the conversion circuit is connected with the first and the second power source input terminals through a rectification circuit and includes a first converter and a second converter, both of which are connected in parallel for output in a low voltage operation mode and in series for output in a high voltage operation mode. The power source module with a broad input voltage range according to the invention can be implemented so that an input voltage to a single converter can be half of a high input voltage, thereby addressing the problem of a limitation upon the voltage of the power device. The connection in parallel at a low voltage can facilitate choosing an alternative transistor with relatively small current. The loss of power devices can be dispersed to facilitate a thermal design. The utilization ratio of an input direct current filter capacitor can be improved greatly in the broad voltage range. The voltage range can be altered with merely simple pre-use configuration. | 2010-11-25 |
20100296320 | Device and method for generating a stable high voltage - A device is disclosed for generating a stable high voltage, namely a high-voltage DC generator for a particle beam apparatus. A method is also disclosed for generating a stable high voltage for a particle beam apparatus. The high-voltage DC generator has a controllable voltage source, which is connected to an amplifier. The high-voltage DC generator ensures that fluctuations of the smoothed high voltage are detected by a capacitive divider and supplied to the amplifier. The amplifier controls the controllable voltage source in counterphase. The voltage of the controllable voltage source is superimposed on the smoothed high voltage. The sum of the voltage of the controllable voltage source and the smoothed high voltage forms the generated and stable high voltage, which is supplied to a particle beam apparatus. | 2010-11-25 |
20100296321 | DIRECT AC POWER CONVERTING APPARATUS - A control section controls a current-source converter while a switch is conducting, to render conducting a pair of a high-aim side transistor and a low-arm side transistor (for example, transistors) which are connected to any one of input lines, performs voltage doubler rectification on a voltage between a neutral phase input line on which a resistor is provided and any one of the input lines, to serve for charging of clamp capacitors. | 2010-11-25 |
20100296322 | Power Switching System to Increase Induction Heating to a Load From Available AC Mains Power - In one aspect, the invention provides a power system for providing power to a load. In some embodiment, the system comprises: a rectifier configured to rectify an AC main signal to produce a rectified AC main signal; a zero cross detector configured to receive the AC main signal and to detect when the AC main signal equals zero; a switching device having (i) a first terminal connected to a first node, wherein a first output terminal of the rectifier is also connected to the first node and (ii) a second terminal connected to a second node; a tank circuit having (i) a first terminal coupled to a third node, wherein a second output terminal of the rectifier is also coupled to the third node and (ii) a second terminal coupled to the second node; a current and/or voltage detector connected to the second node; and a controller in communication with the current detector and zero cross detector and configured to turn on and off the switching device based on, at least in part, information received from the zero cross detector and the current and/or voltage detector. | 2010-11-25 |
20100296323 | Integrated device with AC to DC conversion function and integrated circuit using same - The present invention discloses an integrated device with AC to DC conversion function, and an integrated circuit using the device. The integrated circuit comprises: a circuit operating under low DC voltage; and an integrated device with AC to DC conversion function, the device including first, second, third and fourth diodes, wherein the first diode has a cathode coupled to an anode of the second diode at a first node which receives an input of an AC voltage; the third diode has a cathode coupled to an anode of the fourth diode at a second node which receives another input of the AC voltage; the first diode has an anode coupled to an anode of the third diode at a third node which provides a low level of a DC voltage; and the second diode has a cathode coupled to a cathode of the fourth diode at a fourth node which provides a high level of the DC voltage. | 2010-11-25 |
20100296324 | ELECTRONIC DRIVER CIRCUIT AND METHOD - The present invention relates to an electronic driver circuit and a corresponding method for supplying an electronic load (LED | 2010-11-25 |
20100296325 | Power Converting Device - A power converting device converts a DC voltage input from an external power source into an AC voltage output across an output capacitor of an output circuit, and includes a coupling circuit having series first and second windings. A rectifying diode has a grounded anode coupled to an anode of a clamp diode, and a cathode coupled to the second winding. A cathode of the clamp diode is coupled to a clamp switch and the first winding. A full-bridge circuit includes a first series connection of first and second switches, and a second series connection of third and fourth switches. The first and second series connections are coupled in parallel between the first winding and ground. The output capacitor is coupled between a first common node between the first and second switches, and a second common node between the third and fourth switches. | 2010-11-25 |
20100296326 | Power Circuit With Passthrough - A power circuit device has a housing. A connection electrically couples AC power to an interior portion of the housing. A female electrical socket is coupled to the housing and is electrically coupled to and receives AC power from the connection. An AC to DC converter is electrically coupled to the connection to receive AC power therefrom and produce a DC output therefrom. A current sensor senses current drawn by one of the AC to DC converter and the female electrical socket. A switch, responsive to the current sensor, selectively removes power from the other one of the female electrical socket and the AC to DC converter when a drop in current is sensed by the current sensor. AC versions without DC conversion are also contemplated. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 2010-11-25 |
20100296327 | TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship. | 2010-11-25 |
20100296328 | BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY - An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.-doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.-doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.-doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed. | 2010-11-25 |
20100296329 | Differential Plate Line Screen Test for Ferroelectric Latch Circuits - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability. | 2010-11-25 |
20100296330 | SEMICONDUCTOR MEMORY DEVICE - There is provided a semiconductor memory device capable of suppressing writing disturbances without increasing the cell array area. A semiconductor memory device has a memory cell array where a number of memory cells having a two-terminal type memory element and a transistor for selection connected in series are aligned in a matrix shape, a first voltage applying circuit for applying a writing voltage pulse to a first bit line, and a second voltage applying circuit for applying a pre-charge voltage to a first and second bit line, such that at the time of the writing of a memory cell, the first voltage applying circuit pre-charges the two ends of the memory cell to the same voltage in advance, and after that, the second voltage applying circuit applies a writing voltage pulse via the first bit line directly connected to the transistor for selection. | 2010-11-25 |
20100296331 | SENSING RESISTANCE VARIABLE MEMORY - The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (R | 2010-11-25 |
20100296332 | SRAM Cell for Single Sided Write - A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage. | 2010-11-25 |
20100296333 | 8T SRAM Cell With One Word Line - An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. | 2010-11-25 |
20100296334 | 6T SRAM Cell with Single Sided Write - An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary drivers are biased. During write operations, the auxiliary drivers in half-addressed SRAM cells are biased and the auxiliary drivers in the addressed SRAM cells may be floated or biased. | 2010-11-25 |
20100296335 | Asymmetric SRAM Cell with Split Transistors on the Strong Side - An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. | 2010-11-25 |
20100296336 | 8T SRAM Cell with Two Single Sided Ports - A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write and read operations, the auxiliary driver transistors may be floated or biased. Auxiliary driver transistors in half-addressed SRAM cells may be biased. During standby modes, the auxiliary driver transistors may be floated. During sleep modes, the auxiliary driver transistors may be biased at reduced voltages. The auxiliary driver transistors in each cell may be independent or may have a common source node within each cell. Additional single sided write ports and read buffers may be added. A process of operating an integrated circuit that includes performing a single-sided write bit-side low, a single-sided write bit-side high, and a read bit-side operation. | 2010-11-25 |
20100296337 | 8T SRAM Cell with Four Load Transistors - An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of operating an integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The process includes biasing the auxiliary load transistors in addressed SRAM cells independently of half-addressed cells. | 2010-11-25 |
20100296338 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 2010-11-25 |
20100296339 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION FOR EACH MEMORY BLOCK - A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value. | 2010-11-25 |
20100296340 | NANOTUBE MEMORY CELL WITH FLOATING GATE BASED ON PASSIVATED NANOPARTICLES AND MANUFACTURING PROCESS THEREOF - A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by passivating conductive nanoparticles with passivation molecules and arranging a disposition of passivated conductive nanoparticles on the nanotube, the conductive nanoparticles being adapted to store the electric charges and being insulated by the passivation molecules from the nanotube, and forming a control gate coupled with the channel. | 2010-11-25 |
20100296341 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME - The disclosure of this application enhances the data writing speed of an electrically erasable and writable semiconductor memory. In a semiconductor storage device of this application, at a time of writing data, when a positive voltage lower than a voltage at control gate | 2010-11-25 |
20100296342 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When bit lines or sense amplifiers are checked whether they are defective during a test performed to check whether the bit lines are defectively open, an electrical current supplied from one sense amplifier is detected by another sense amplifier. Thus, if plural bit lines are defectively open, they can be detected simultaneously. Consequently, the test time can be shortened greatly. | 2010-11-25 |
20100296343 | Non-Volatile Memory and Semiconductor Device - There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. | 2010-11-25 |
20100296344 | Methods of operating nonvolatile memory devices - Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell. | 2010-11-25 |
20100296345 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line. | 2010-11-25 |
20100296346 | NAND MEMORY DEVICE COLUMN CHARGING - Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations. | 2010-11-25 |
20100296347 | Method of erasing device including complementary nonvolatile memory devices - Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous. | 2010-11-25 |
20100296348 | ERASE OPERATION CONTROL SEQUENCING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage. | 2010-11-25 |
20100296349 | NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT WITH IMPROVED RESISTANCE DISTRIBUTION - Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability is provided in response to a bias signal based on set or reset state of data. | 2010-11-25 |
20100296350 | METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS - A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states. | 2010-11-25 |
20100296351 | TIMING ADJUSTMENT CIRCUIT, TIMING ADJUSTMENT METHOD, AND CORRECTION VALUE COMPUTING METHOD - A timing adjustment circuit includes a determination unit for outputting delay information corresponding to a period of a first input signal, a storing unit for storing a plurality of correction values in accordance with a circuit included in the determination unit, a correction unit for correcting the delay information based on a correction value selected from the plurality of the correction values, in accordance with the delay information, and a first delay line for delaying a second input signal corresponding to the first input signal, in accordance with the delay information corrected by the correction unit. | 2010-11-25 |
20100296352 | MEMORY CONTROLLER FOR DETECTING READ LATENCY, MEMORY SYSTEM AND TEST SYSTEM HAVING THE SAME - A memory controller includes an I/O circuit, a read latency detector and a clock domain synchronizer. The I/O circuit transmits a first signal to a semiconductor memory device, receives a reflected signal returned from the semiconductor memory device, and delays the reflected signal in response to a delay selection signal to generate a second signal. The reflected signal is provided by reflection of the first signal from the semiconductor memory device. The read latency detector generates the first signal in response to a system clock signal, and generates a read latency signal in response to the system clock signal, a hold signal, and the second signal. The clock domain synchronizer generates the delay selection signal and the hold signal in response to the system clock signal and the second signal. | 2010-11-25 |
20100296353 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines. | 2010-11-25 |
20100296354 | SRAM AND METHOD FOR ACCESSING SRAM - A static random access memory includes: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit connected with the pair of bit lines and configured to precharge the pair of bit lines with a precharge voltage; and a voltage reducing circuit connected between the precharge circuit and the first power supply. The voltage reducing circuit includes: a control circuit comprising a differential amplifier circuit which is configured to amplify a difference input of a reference voltage generated through resistance division of the power supply voltage and the precharge voltage supplied to a node to output a control signal; and a voltage reduction control transistor connected between the node and the first power supply and configured to generate the precharge voltage in response to the control signal. The precharge circuit includes: precharge transistors connected between the bit lines and the node and configured to control supply of the precharge voltage to the bit lines in response to a first precharge control signal. | 2010-11-25 |
20100296355 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines. | 2010-11-25 |
20100296356 | CIRCUIT FOR GENERATING REFRESH PERIOD SIGNAL AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - Circuits for generating refresh period signals and semiconductor integrated circuits using the same are presented. The refresh period signal generation circuit can include an oscillator, a pulse generation unit, and a signal controller. The oscillator is configured to generate an oscillation signal in response to a refresh duration correction signal. The pulse generation unit is configured to generate a refresh period signal in response to the oscillation signal. The signal controller configured to generate the refresh duration correction signal, which corrects an active time of a refresh duration signal, in response to the oscillation signal. | 2010-11-25 |
20100296357 | Semiconductor Memory Device - A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses, a global line driving block configured to drive the global line by selectively inverting data on the positive local line and data on the negative local line according to the row addresses, a first cell region configured to allow a first internal data to be equalized with the data on the positive local line in response to the row addresses and column addresses, and a second cell region configured to allow a second internal data to be equalized with the data on the negative local line in response to the row addresses and the column addresses. | 2010-11-25 |
20100296358 | ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal. | 2010-11-25 |
20100296359 | System and Method for Facilitating Well Servicing Operations - A technique facilitates well servicing operations by utilizing a hopper system to introduce a dry additive into a mixing tank. The hopper system comprises a feeder and a hopper that delivers the dry additive into the feeder. The feeder, in turn, enables introduction of the dry additive into the cement mixing tank in a controlled manner. When the hopper system is used on a transportable cementing unit, the hopper system may be mounted on a cement mixing tank and also may incorporate a hopper that is both expandable to accommodate a greater amount of dry additive and contractible to facilitate transport. | 2010-11-25 |
20100296360 | MELTING KNEADING DEVOLATILIZING EXTRUDER - There is provided a melting kneading devolatilizing extruder in which the surface renewability of a molten raw material is improved. | 2010-11-25 |
20100296361 | EXTRUSION OF POLYURETHANE COMPOSITE MATERIALS - Methods of extruding polyurethane composite materials are described. One method includes introducing at least one polyol and inorganic filler to a first conveying section of the extruder, transferring the at least one polyol and inorganic filler to a first mixing section of an extruder, mixing the at least one polyol and the inorganic filler in the first mixing section, transferring the mixed at least one polyol and inorganic filler to a second conveying section of the extruder, introducing a di- or poly-isocyanate to the second conveying section, transferring the mixed at least one polyol and inorganic filler and the di- or poly-isocyanate to a second mixing section, mixing the mixed at least one polyol and inorganic filler with the di- or poly-isocyanate in the second mixing section of the extruder to provide a composite mixture, and transferring the composite mixture to an output end of the extruder. Other related methods are also described. | 2010-11-25 |
20100296362 | System for manufacture and delivery of an emulsion explosive - A method for manufacture and delivery of an emulsion explosive having a discontinuous oxidizer solution phase, a continuous fuel phase, and an emulsifier, the method comprising: (a) providing an emulsion manufacturing system; (b) conveying an oxidizer solution phase to the emulsion manufacturing system at a pre-determined pressure; (c) conveying a fuel phase to the emulsion manufacturing system at a pre-determined pressure; (d) forming an emulsion from the oxidizer solution and the fuel phases using only a portion of the pre-determined pressures so as to provide a usable residual pressure after the formation of the emulsion; and (e) utilizing the residual pressure to non-mechanically deliver the emulsion to a pre-determined location. | 2010-11-25 |
20100296363 | HOMOGENIZING VALVE - A homogenizer valve ( | 2010-11-25 |
20100296364 | Guiding Device for Submersible Motor Agitators - A guiding device for submersible motor agitators having a guiding tube and a sliding carriage for carrying a submersible motor agitator. The guiding tube is held in a pivotable lower mount and in an upper mount composed of a bracket and an adjusting lug, and the angular position of the guiding tube can be adjusted via the adjusting lug. The sliding carriage, the adjustment lug and any optional connecting lug are dimensioned in such a way that the sliding carriage carrying the submersible motor agitator can be removed from the guiding tube without disassembling the guiding device. | 2010-11-25 |
20100296365 | APPARATUS FOR TREATMENT OF LIQUIDS - An apparatus for treating a liquid is disclosed herein. The apparatus comprises a chamber defining an inlet and an outlet, a rotor located in the chamber; and at least one surface located in the chamber. The at least one surface is spaced apart and substantially parallel to the rotor. The rotor and the at least one surface define a reaction zone therebetween. The reaction zone is in fluid communication with the inlet and the outlet. The rotation of the rotor relative to the at least one surface is adapted to cause turbulence in the liquid passing through the reaction zone. At least one of the rotor and the at least one surface define a plurality of dimples thereon. | 2010-11-25 |
20100296366 | METHODS AND SYSTEMS FOR SEISMIC SIGNAL DETECTION - Methods and systems utilizing seismic sensors configured or designed for use in seismic signal detection. An electrical current is applied to a seismic sensor such that the moving coil is located at a neutral position relative to the magnetic field in the seismic sensor to compensate for gravitational acceleration. | 2010-11-25 |
20100296367 | METHOD OF IMAGING A TARGET AREA OF THE SUBSOIL FROM WALKAWAY TYPE DATA - A method of imaging a target area of the subsoil from “walkaway” data having application to development of oil reservoirs or monitoring of geologic storage sites is disclosed. After acquisition of seismic data of walkaway type and estimation of the rate of propagation of the seismic waves in the subsoil, p illumination angles are selected. The seismic measurements are then converted to data D | 2010-11-25 |
20100296368 | CHANNEL IMPULSE RESPONSE ESTIMATION - A method of estimating the impulse response of a channel is disclosed. The method includes transmitting an impulse signal to the channel, detecting a received signal from the channel at a receiver, and calculating an estimate of the impulse response of the channel by applying a calculated inverse matrix of the impulse signal to the received signal. | 2010-11-25 |
20100296369 | WEARABLE OBJECT SUCH AS A TIMEPIECE INCLUDING MEANS FOR TRIGGERING AN ELECTRONIC CONTROL FUNCTION - Portable object such as a timepiece including a dial ( | 2010-11-25 |
20100296370 | DEVICE - A time keeping device comprising (i) time keeping means, (ii) a display means, capable of displaying at least first and second images to differentiate between two different time periods, wherein the first image can alter to indicate the passage of time throughout a user-selected time period, and (iii) control means for causing the display means to display either its first or its second image dependent on the time of day and/or on timing information input by a user, and for causing alteration of the first image with the passage of time during the user-selected time period. | 2010-11-25 |
20100296371 | Rotative clock - In a rotative desk clock having in a main body of it a clock module, a driving module and a control module for sound controlling or touch controlling, wherein the driving module includes a rotary disk exposed downwardly out of the main body, when the control module is touched by a hand or senses the change of sound waves, it activates the driving module to rotate a rotary disk; thereby if the rotary disk is placed on the desk, the main body can rotate relatively to the rotary disk. Thus a dynamically rotating clock is formed. | 2010-11-25 |
20100296372 | RECORDING MEDIUM, METHOD AND APPARATUS FOR REPRODUCING DATA ON THE RECORDING MEDIUM, AND METHOD AND APPARATUS FOR RECORDING DATA ON THE RECORDING MEDIUM - A recording medium on which data is recorded in units of clusters, a method and apparatus for reproducing data on the recording medium, and a method and apparatus for recording data on the recording medium, wherein each of the clusters includes a plurality of address fields, each address field includes 32-bit address unit number (AUN) address information, and the AUN address information includes a reserved area recorded on 4 bits, layer information, recorded on 3 bits, indicating a layer on which data corresponding to the AUN address information is recorded, and location information, recorded on 25 bits, indicating a location of the data corresponding to the AUN address information. In the recording medium of the present invention, a space in which addresses are recorded is expanded, thereby securing an address area in which addresses of data can be recorded in a data structure. | 2010-11-25 |
20100296373 | DISC DEVICE - A disc device capable of achieving a slimming down of a tilt adjusting portion is provided. A tilt adjusting member | 2010-11-25 |
20100296374 | APPARATUS AND METHOD FOR INITIALIZING INFORMATION RECORDING MEDIUM, APPARATUS AND METHOD FOR RECORDING INFORMATION, AND INFORMATION RECORDING MEDIUM - An initialization apparatus that has a simplified configuration and that forms an initial hologram in an information recording medium is provided. An initialization apparatus ( | 2010-11-25 |
20100296375 | INFORMATION REPRODUCING APPARATUS - In a case where free space of a local storage becomes smaller than a predetermined threshold while additional contents are downloaded by executing a “BD-Live” function, a screen for deleting old contents is displayed on a display. When a user deletes the old contents and the free space of the local storage becomes equal to or larger than the threshold, the screen displayed on a display is automatically erased. By repeating the deletion of old contents until download of the additional contents is completed, the entire additional contents are completely acquired. | 2010-11-25 |
20100296376 | OPTICAL DISC DEVICE - An optical disc device including: a light source; an object lens to focus light emitted from the light source on an information recording surface of an optical disc; a movable lens that is arranged on an optical path between the light source and the objective lens and arranged such that position thereof is adjustable along a direction of a light axis; a lens moving portion to move the movable lens along the direction of the light axis; a tracking servo system which makes a beam spot that is formed of the light from the light source through focusing by the objective lens keep on track of the optical disc; and a control part which controls gain of a servo loop of the tracking servo system is made temporarily larger when the movable lens is moved by the lens moving portion in comparison with a case where moving of the movable lens by the lens moving portion is not performed. | 2010-11-25 |
20100296377 | METHOD OF EVALUATING CHARACTERISTICS OF MULTILAYER OPTICAL RECORDING MEDIUM - A multilayer optical recording medium having three or more information recording layers is irradiated with a laser beam, and a first signal obtained from the reflected laser beam is subjected to a frequency filter. A second signal obtained by filtration through a high-pass filter is used to evaluate the characteristics of the multilayer optical recording medium. In this manner, even in a multilayer optical recording medium having three or more information recording layers, the influence of the variation of the thickness and material of the information recording layers and the influence of the variation of the thickness of a spacer layer can be clearly determined and evaluated. | 2010-11-25 |
20100296378 | CALIBRATION CIRCUIT AND METHOD THEREOF FOR DATA RECOVERY - A calibration circuit and a calibration method thereof for data recovery are provided. The calibration circuit includes an amplitude detector, a period detector, and a compensation circuit. The amplitude detector samples amplitudes of a data signal according to a zero-crossing signal and outputs an amplitude signal accordingly. The period detector counts a clock signal according to the zero-crossing signal and outputs a period signal accordingly. The compensation circuit receives the amplitude signal, the period signal, and the data signal. The compensation circuit adjusts a phase of the data signal by calculating differences between a reference signal and the amplitude signal and between the reference signal and the period signal and outputs a calibrated data signal accordingly. Accordingly, a better recognition performance on the data signal is achieved by calibrating the data signal in real-time. | 2010-11-25 |
20100296379 | ERROR CORRECTING CIRCUIT AND DISK STORAGE DEVICE - According to one embodiment, an error correcting circuit includes: a marker decoder configured to sample 2-bit markers from a data string and, from a plurality of sample values of the 2-bit markers, determine whether there is an occurrence of an error on the 2-bit markers, of an insertion error, or of a deletion error; and an error correcting module configured to perform first error correction on the data string received from the marker decoder by using an error correcting code in the data string. When either one of the insertion error and the deletion error is determined to have occurred, the marker decoder is configured to perform second error correction on the either one of the insertion error and the deletion error, and output the data string from which the 2-bit markers are removed. | 2010-11-25 |
20100296380 | Spatial Light Modulators with Changeable Phase Masks for Use in Holographic Data Storage - A holographic data storage system that includes a write head that includes a pixellated spatial light modulator and a separate or integral phase mask that varies the phase depending on the location in the phase mask that light passes through. The phase variation can be changed over time in a random, pseudo-random, or predetermined fashion. The spatial light modulator and phase mask can be implemented in a liquid crystal SLM (nematic, ferroeleletric, or other), in a DMD SLM, in a magneto-optical SLM, or in any other suitable manner. | 2010-11-25 |
20100296381 | Apparatus and Method to Store Information in a Holographic Data Storage Medium - A method is disclosed to store information in a holographic data storage medium. The method provides a hologram comprising an alignment pattern, and disposes that hologram into a holographic data storage medium during manufacture. | 2010-11-25 |
20100296382 | DOUBLE-ELECTRODE CANTILEVER ACTUATION FOR SEEK-SCAN-PROBE DATA ACCESS - A seek-scan-probe memory device, utilizing a media electrode to allow active cantilevers to contact the storage media, and a pull electrode to pull up cantilevers away from the storage media when in an inactive mode. Other embodiments are described and claimed. | 2010-11-25 |
20100296383 | REDUCED ENERGY CONSUMPTION USING ACTIVE VIBRATION CONTROL - Embodiments of a computer system that includes a vibration-cancelling mode, and a related method and computer-program product (e.g., software) for use with the computer system, are described. During operation, a processor monitors operations in the computer system, and may select either the vibration-cancelling mode or an inactive mode based on the monitored operations. For example, the processor may select the vibration-cancelling mode when there are input/output-(I/O) intensive workloads to an array of one or more hard disk drives (HDDs) in the computer system. In this way, the processor may reduce the energy consumption associated with vibration-induced retries to the HDDs (and reduced I/O throughput) without increasing the energy consumption associated with active vibration damping at other times, such as when the computer system is idle or during processor-intensive workloads. | 2010-11-25 |
20100296384 | WIRELESS COMMUNICATION APPARATUS AND RESPONSE SIGNAL SPREADING METHOD - A wireless communication apparatus capable of minimizing the degradation in separation characteristic of a code multiplexed response signal. In this apparatus, a control part ( | 2010-11-25 |
20100296385 | USER SIGNAL TRANSMITTING AND RECEIVING METHOD, APPARATUS AND SYSTEM IN OFDMA SYSTEM - This invention provides a user signal transmitting method in an OFDMA system, where all the time-frequency grids of each timeslot are divided into sub-channels, each sub-channel comprises N | 2010-11-25 |
20100296386 | METHOD AND APPARATUS FOR WIDEBAND WIRELESS TRANSMISSION AND TRANSMISSION SYSTEM - A method of wideband radio transmission is disclosed, the method includes the following steps: obtaining the parallel data symbols; encoding the obtaining parallel data symbols respectively; superposing the encoded data symbols; performing the fast Fourier inverse transform for the superposed data symbols and transmitting them. Applying the solution, the transmission efficiency and the transmission dependability of the OFDM system is raised. An apparatus for wideband radio transmission and a transmission system are also disclosed. | 2010-11-25 |
20100296387 | SECURITY SYSTEM AND METHOD FOR WIRELESS COMMUNICATION WITHIN A VEHICLE - A method for providing wireless communications between nodes of a vehicle includes providing a plurality of frequency channels on which the nodes of a first vehicle may wirelessly communicate. Wireless communication with a second vehicle adjacent to the first vehicle includes assigning a first of the frequency channels to the first vehicle for intra-vehicle transmissions within the first vehicle, and a second of the frequency channels to the second vehicle for intra-vehicle transmissions within the second vehicle. The first vehicle is prohibited from using the second frequency channel and the second vehicle is prohibited from using the first frequency channel. | 2010-11-25 |
20100296388 | COMMUNICATION SYSTEM - A communication system includes: a base station; and a mobile terminal for sequentially sending a plurality of data packets at a designated data transfer rate and information of velocity of the mobile terminal to the base station; the base station including: a receiver for receiving the data packet and the velocity information; a transmitter for transmitting a request to the mobile terminal to resend a data packet upon detection of an error in the data packet previously received; and a reply controller for setting number of requests to be repetitively sent in accordance with the velocity information and, after the number of requests have been sent, sending command to change the designated data transfer rate to the mobile terminal. | 2010-11-25 |
20100296389 | FAILURE INDICATION FOR ONE OR MORE CARRIERS IN A MULTI-CARRIER COMMUNICATION ENVIRONMENT - Systems and methodologies are described that facilitate indicating a loss of channel quality on a component carrier of a plurality of component carriers. A UE can monitor configured component carriers to determine channel qualities associated therewith. The UE can transmit carrier quality information that includes the channel qualities of the plurality of component carriers. In addition, the UE can identify a component carrier experiencing a loss of channel quality and notify a base station of the component carrier with poor channel conditions. In one aspect, the UE can incorporate additional information into a scheduling request. In addition, the UE can generate a CQI report that contains the carrier quality information. Further, the base station, when a loss of channel quality occurs, can retry transmission on different carriers. Moreover, the base station can employ information provided by the UE when selecting a component carrier for a transmission. | 2010-11-25 |
20100296390 | FAULT TOLERANCE IN WIRELESS NETWORKS - A network includes a plurality of logical access entities. Each access entity includes two or more communication interfaces. The network further includes a plurality of logical node entities. Each logical node entity includes two or more communication interfaces that are configured to wirelessly communicate in a redundant manner with any of the logical access entities. In an embodiment, a communication degradation in the network is assessed, and the network is configured as a function of that assessment to provide fault tolerance within the network. | 2010-11-25 |
20100296391 | Method for Conducting Redundancy Checks in a Chain Network - The present invention relates to a method for conducting redundancy checks in a chain network, wherein the two ends of the chain network are equipped with a first switch and a second switch respectively, and a port of the first or second switch used for communicating with an external network is set to be blocked, so that when an link failure happens to any switch of the chain network, the two switches close to the link failure port sends control packets to the first and second switches respectively to forward the port that is originally blocking, thus making the network to return to normal state quickly. Besides, as the first and second switches are used to connect other chain networks, external network devices or external redundant network architectures, it allows more network nodes to be included in single network architecture and provides flexibility and compatibility in use by including different redundancy mechanisms. | 2010-11-25 |
20100296392 | DETERMINING LINK FAILURE WITHIN A NETWORK - Methods and systems for determining link failure in a network are provided. According to one embodiment, multiple paths are provided between each pair of multi-path load balancing (MPLB) components within a Layer 2 network by establishing overlapping loop-free topologies in which each MPLB component is reachable by any other via each loop-free topology. A first MPLB component sends latency requests to a second MPLB component via a particular path. Responsive thereto, the first MPLB component receives latency responses. Based on timestamp information in the latency responses, an estimated latency between the first and second MPLB components is determined. A link failure timeout period is derived based upon the estimated latency. An additional latency request is sent. If an additional latency response is not received by the first MPLB component prior to expiration of the link failure timeout period, then it is concluded that a link failure has occurred. | 2010-11-25 |
20100296393 | METHOD FOR ESTABLISHING AN MPLS DATA NETWORK PROTECTION PATHWAY - Recovery time upon the failure of a link or switching system in an asynchronous data network can be minimized if downstream data switches provide upstream messages indicating to upstream switching system that the downstream traffic arrived in tact and was properly handled. Upon this loss or failure of the upstream status message to an upstream switching system, an upstream switching system can reroute data traffic around a failed link or failed switch with a minimal amount of lost data. The upstream status message is conveyed from a downstream switching system to an upstream switching system via a reverse notification tree data pathway. The reverse notification pathway is established by using a messaging protocol between network switches by which the working and protection paths, among other things, are established. | 2010-11-25 |
20100296394 | AUTOMATIC PROTECTION SWITCHING OF VIRTUAL CONNECTIONS - A method and system provision a first virtual connection between a first device and a second device; and provision a second virtual connection between the first device and a third device. A first bridge function is configured to control switching associated with the first virtual connection. A second bridge function is configured to control switching associated with the second virtual connection. A parent bridge function is configured to control switching on the first bridge function and the second bridge function, wherein the first virtual connection comprises an active connection and the second virtual connection comprises a standby connection, and wherein the parent bridge function switches traffic to the second bridge device upon determining that the first virtual connection has failed. | 2010-11-25 |
20100296395 | PACKET TRANSMISSION SYSTEM, PACKET TRANSMISSION APPARATUS, AND PACKET TRANSMISSION METHOD - A first apparatus includes a sending unit which attaches a sequence number which is numbered for each priority of QoS set in a first packet, the sequence number is numbered for each priority of QoS set in the first packet, and sends the first packet with the sequence number. A second apparatus includes a storage unit which stores, for each priority, a history of sequence numbers attached to packets received, a determining unit which receives the first packet from the first apparatus, identifies the sequence number of the first packet, and determines whether the first packet has been previously received by comparing the identified sequence number with the history of sequence numbers according to the priority of QoS set in the first packet stored in the storage unit, and a unit which discards, when the determining unit determines the first packet has been previously received, the first packet. | 2010-11-25 |
20100296396 | Traffic Shaping Via Internal Loopback - A method for traffic shaping includes receiving traffic from one or more clients at one or more ingress ports of forwarding engine of a network node. The method also includes transmitting at least a portion of the traffic through the forwarding engine to one or more first egress ports of the forwarding engine and shaping the traffic transmitted to the egress ports. Furthermore, the method includes looping the shaped traffic internally within the network node back to one or more ingress ports of the forwarding engine. The method further includes transmitting the looped traffic through the forwarding engine to one or more second egress ports (the second egress ports different than the first egress ports) and outputting the shaped traffic from the network node. | 2010-11-25 |