47th week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110284932 | BODY CONTACT STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact. | 2011-11-24 |
20110284933 | ELECTRIC CONTACTING OF SEMICONDUCTOR COMPONENTS HAVING LOW CONTACT RESISTANCE - The present invention relates to a semiconductor component which comprises at least one electric contact surface for the electric contacting of a semiconductor region ( | 2011-11-24 |
20110284934 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There are provided a semiconductor device and a method of fabricating the same. The semiconductor device comprises: a semiconductor substrate of a first conductive type; a gate formed on the semiconductor substrate; and a heavily doped region of the first conductive type and a heavily doped region of a second conductive type formed respectively in the semiconductor substrate at either side of the gate, wherein the heavily doped region of the second conductive type is separated from the channel region under the gate and partially separated from the semiconductor substrate by a dielectric layer. By means of this semiconductor device, it is possible to provide excellent switching behavior. | 2011-11-24 |
20110284935 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; a side wall spacer formed on a side wall of the gate electrode; source/drain regions formed in opposing portions of the semiconductor substrate with the gate electrode and the side wall spacer interposed therebetween; and a stress-applying insulating film covering the gate electrode, the side wall spacer, and an upper surface of the semiconductor substrate. A gate-length-direction thickness of an upper portion of the side wall spacer is at least larger than a gate-length-direction thickness of a middle portion thereof. | 2011-11-24 |
20110284936 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer. | 2011-11-24 |
20110284937 | SPIN TRANSISTOR USING N-TYPE AND P-TYPE DOUBLE CARRIER SUPPLY LAYER STRUCTURE - A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer. | 2011-11-24 |
20110284938 | SPIN TRANSISTOR AND INTEGRATED CIRCUIT - A spin transistor according to an embodiment includes: a first magnetic region supplying a first polarized signal polarized in a first magnetization direction in accordance with a first input signal; a second magnetic region supplying a second polarized signal polarized in a second magnetization direction opposite from the first magnetization direction in accordance with a second input signal, the second input signal being different from the first input signal; and a third magnetic region outputting the first polarized signal supplied from the first magnetic region in accordance with a third input signal, and outputting the second polarized signal supplied from the second magnetic region in accordance with a fourth input signal different from the third input signal. | 2011-11-24 |
20110284939 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction. | 2011-11-24 |
20110284940 | Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory. | 2011-11-24 |
20110284941 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the dielectric film sandwiched therebetween. | 2011-11-24 |
20110284942 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction. | 2011-11-24 |
20110284943 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion. | 2011-11-24 |
20110284944 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al | 2011-11-24 |
20110284945 | Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells. | 2011-11-24 |
20110284946 | SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME - A semiconductor memory capable of increasing bit density by three-dimensional arrangement of cells and a method for manufacturing the same are provided. | 2011-11-24 |
20110284947 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state. | 2011-11-24 |
20110284948 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A semiconductor device and a fabrication method for the semiconductor device are provided in which an increase of a forward loss is suppressed and a reverse recovery loss is reduced. | 2011-11-24 |
20110284949 | VERTICAL TRANSISTOR AND A METHOD OF FABRICATING THE SAME - A vertical transistor and a method of fabricating the vertical transistor are provided. The vertical transistor has a substrate, a first electrode formed on the substrate, a first insulation layer formed on the first electrode, with a portion of the first electrode exposed from the first insulation layer and having a thickness greater than 50 nm and no more than 300 nm, a grid electrode formed on the first insulation layer, a semiconductor layer formed on the first electrode, and a second electrode formed on the semiconductor layer. | 2011-11-24 |
20110284950 | Method for fabricating a shallow and narrow trench FETand related structures - Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed. | 2011-11-24 |
20110284951 | Semiconductor device and method of manufacturing the semiconductor device - A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion. | 2011-11-24 |
20110284952 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a transistor having multiple trenches with the thickness thereof being intermittently changed in the lateral direction of a gate, a gate insulating film formed on the side walls and at the bottom of each of the trenches, a gate electrode formed over the gate insulating film, a source region formed in the surface of the substrate on one side in the longitudinal direction of the gate, and a drain region formed in the surface of the substrate on the other side in the longitudinal direction of the gate. The thickness of the gate insulating film in the lower portion of the side wall of the trench from an intermediate position directing from the surface of the substrate to the bottom of the trench to the bottom thereof is larger than the thickness of the gate insulating film in the upper portion on the side wall of the trench from the intermediate position directing from the surface of the substrate to the bottom of the trench and equal with or larger than the thickness of the gate insulating film at the bottom of the trench. | 2011-11-24 |
20110284953 | POWER TRENCH MOSFET RECTIFIER - A trench MOSFET rectifier includes oxide layers having different thicknesses formed in different regions of the devices. The rectifying device also includes a source region of first conductivity type at a surface of each mesa region and a body region of a second conductivity type beneath each source region. The rectifying device also includes a dielectric layer lining the bottom and sidewall surfaces of the trenches, the portion of the dielectric layer on the bottom surface being thicker than the portion on the sidewall surface. A doped region underlies each of the first plurality of trenches. A polycrystalline silicon region filling each of the first plurality of trenches to form a gate region in each trench. A conductive material fills a plurality of contact trenches and forms ohmic contacts with the source region, body region, and gate region. | 2011-11-24 |
20110284954 | LOW Qgd TRENCH MOSFET INTEGRATED WITH SCHOTTKY RECTIFIER - An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions. | 2011-11-24 |
20110284955 | FIELD EFFECT TRANSISTOR WITH TRENCH FILLED WITH INSULATING MATERIAL AND STRIPS OF SEMI-INSULATING MATERIAL ALONG TRENCH SIDEWALLS - In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material may be insulated from the first semiconductor region. | 2011-11-24 |
20110284956 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - The semiconductor device comprises a first impurity region having a second conductivity type and formed in a semiconductor layer having a first conductivity type; a body region adjacent to and in contact with the first impurity region and having the first conductivity type; a second impurity region formed in the first impurity region, having the second conductivity type, and having a depth smaller than the first impurity region; a source region formed in the body region and having the second conductivity type; a drain region formed in the second impurity region and having the second conductivity type; and a gate electrode formed via a gate insulating film. In a preferable mode of the semiconductor device, the second impurity region has a higher impurity concentration than the first impurity region and the first impurity region has a depth of 1 μm or smaller. | 2011-11-24 |
20110284957 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To fabricate a power MOSFET, etc. high in voltage-proofing (or breakdown voltage) and low in ON resistance (or On-state resistance) by a trench filling method, trial manufacture of power MOSFETs, etc. has been repeated with varying internal structures and layouts of super junction structures in a chip inner region located inside a guard ring. As a result, there occasionally occurred a source-drain voltage-proofing defect attributable to outer end portions of a supper junction structure. In one aspect of the present invention there is provided a semiconductor device having a power semiconductor element with a super junction structure introduced substantially throughout the whole surface of a drift region, the super junction structure being provided substantially throughout the whole surfaces of end portions of a semiconductor chip which configures the semiconductor device. | 2011-11-24 |
20110284958 | Semiconductor Component - A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed. | 2011-11-24 |
20110284959 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - One object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. Another object is to manufacture a highly reliable semiconductor device in a high yield. In a top-gate staggered transistor including an oxide semiconductor film, as a first gate insulating film in contact with the oxide semiconductor film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon fluoride and oxygen; and as a second gate insulating film stacked over the first gate insulating film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon hydride and oxygen. | 2011-11-24 |
20110284960 | NON-PLANAR THIN FIN TRANSISTOR - Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing. | 2011-11-24 |
20110284961 | SELF-ALIGNED SCHOTTKY DIODE - A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided. | 2011-11-24 |
20110284962 | High Performance Devices and High Density Devices on Single Chip - A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner. | 2011-11-24 |
20110284963 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts. | 2011-11-24 |
20110284964 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 2011-11-24 |
20110284965 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES - Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film. | 2011-11-24 |
20110284966 | Structure and Method for Alignment Marks - The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant. | 2011-11-24 |
20110284967 | Stressed Fin-FET Devices with Low Contact Resistance - A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 2011-11-24 |
20110284968 | SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a recessed portion including at least two oblique side surfaces and a first bottom surface therebetween, a gate insulating layer formed on the recessed portion, a gate electrode formed on the gate insulating layer, a channel region below the gate electrode in the semiconductor substrate, and gate spacers formed on side surfaces of the gate electrode, wherein both the bottom surface and the side surfaces of the recessed portion include flat surfaces. A method of manufacturing a semiconductor device comprising the steps of forming a recess portion including at least two oblique side surfaces and a bottom surface therebetween in a semiconductor substrate, forming a gate insulating layer formed on the recessed portion, forming a gate electrode formed on the gate insulating layer, forming a channel region below the gate electrode in the semiconductor substrate, and forming gate spacers formed on side surfaces of the gate electrode. | 2011-11-24 |
20110284969 | SEMICONDUCTOR DEVICE, METHOD OF FORMING SEMICONDUCTOR DEVICE, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region. | 2011-11-24 |
20110284970 | Transistor Device and Methods of Manufacture Thereof - Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor. | 2011-11-24 |
20110284971 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film. | 2011-11-24 |
20110284972 | Modifying Work Function in PMOS Devices by Counter-Doping - A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode. | 2011-11-24 |
20110284973 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - One object is to provide a semiconductor element in which leakage current between a gate electrode and a channel formation region is suppressed even when the gate electrode is miniaturized as a result of miniaturization of the semiconductor element. Another object is to provide a downsized and high-performance semiconductor device. A semiconductor element having the following structure is manufactured: an insulating film containing gallium oxide and having a relative permittivity of 10 or more is formed as a gate insulating film over a semiconductor layer having a function of a channel formation region; and a gate electrode is formed over the gallium oxide. Further, a semiconductor device is manufactured by using the semiconductor element. | 2011-11-24 |
20110284974 | SEMICONDUCTOR DEVICE - An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films. | 2011-11-24 |
20110284975 | MICROSTRUCTURE, METHOD FOR PRODUCING THE SAME, DEVICE FOR BONDING A MICROSTRUCTURE AND MICROSYSTEM - A microstructure has at least one bonding substrate and a reactive multilayer system. The reactive multilayer system has at least one surface layer of the bonding substrate with vertically oriented nanostructures spaced apart from one another. Regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures. A method for producing at least one bonding substrate and a reactive multilayer system, includes, for forming the reactive multilayer system, at least one surface layer of the bonding substrate is patterned or deposited in patterned fashion with the formation of vertically oriented nanostructures spaced apart from one another, and regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures. A device for bonding a microstructure, which has at least one bonding substrate and a reactive multilayer system, to a further structure, which has a bonding substrate. The device has a bonding chamber, which can be opened and closed and evacuated and in which the microstructure and the further structure can be introduced and aligned with one another, and also an activation mechanism, which is coupled to the bonding chamber and by means of which the reactive multilayer system of the microstructure, said reactive multilayer system being formed from reactive nanostructures with—situated therebetween—a material constituting a reaction partner with respect to the material of the nanostructures, can be activated mechanically, electrically, electromagnetically, optically and/or thermally in such a way that a self-propagating, exothermic reaction takes place between the nanostructures and the material constituting a reaction partner with respect to the material of the nanostructures. A microsystem is formed from two bonding substrates and a construction lying between the bonding substrates, the construction having a reacted reactive layer system, wherein the reacted reactive layer system is a reacted structure sequence composed of at least one surface layer—provided on the bonding substrate—with vertically oriented nanostructures spaced apart from one another, and regions filled between the nanostructures with at least one material constituting a reaction partner with respect to the material of the nanostructures. The microsystem is a sensor coated with biomaterial and/or has elements composed of polymeric material and/or at least one magnetic and/or piezoelectric and/or piezoresistive component. | 2011-11-24 |
20110284976 | SOLID-STATE IMAGE PICKUP APPARATUS, METHOD FOR MANUFACTURING SAME, AND ELECTRONIC DEVICE - A solid-state image pickup apparatus includes a substrate, a solid-state image pickup device, and a Micro Electro Mechanical Systems (MEMS) device. The solid-state image pickup device and the MEMS device are configured to be formed on the same substrate. | 2011-11-24 |
20110284977 | Array of magnetic tunneling junction film structures with process determined in-plane magnetic anisotropy - An MRAM array of MTJ memory cells is provided wherein each such cell is a layered MTJ structure located at an intersection of a word and bit line and has a small circular horizontal cross-section of 1.0 microns or less in diameter and wherein the ferromagnetic free layer of each such cell has a magnetic anisotropy produced by a magnetic coupling with a thin antiferromagnetic layer that is formed on the free layer. The array of MTJ memory cells so provided is far less sensitive to shape irregularities and edge defects of individual cells than arrays of the prior art. | 2011-11-24 |
20110284978 | RADIATION CONVERTER COMPRISING A DIRECTLY CONVERTING SEMICONDUCTOR LAYER AND METHOD FOR PRODUCING SUCH A RADIATION CONVERTER - A radiation converter includes a directly converting semiconductor layer, wherein the semiconductor layer includes grains whose interfaces at least predominantly run parallel to a drift direction—constrained by an electric field—of electrons liberated in the semiconductor layer. in at least one embodiment, the charge carriers liberated by incident radiation quanta are accelerated in the electric field in the direction of the radiation incidence direction and on account of the columnar or pillar-like texture of the semiconductor layer, in comparison with the known radiation detectors, cross significantly fewer interfaces of the grains that are occupied by defect sites. This increases the charge carrier lifetime/mobility product in the direction of charge carrier transport. Consequently, it is possible to realize significantly thicker semiconductor layers for the counting and/or energy-selective detection of radiation quanta. This increases the absorptivity of the radiation converter which in turn makes it possible to reduce a radiation dose applied to the patient. at least one embodiment of the invention additionally relates to a method for producing such a radiation converter. | 2011-11-24 |
20110284979 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING SAME - A solid-state imaging device according to an aspect of the present invention includes: a semiconductor substrate; and a plurality of light-receiving units formed in a matrix in the semiconductor substrate and converting incident light into signal charges, and each of the convex parts is positioned corresponding to one of the light-receiving units and formed integrally with the semiconductor substrate. | 2011-11-24 |
20110284980 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device according to an aspect of the present invention includes: a first photodiode and a second photodiode; a first optical waveguide formed above the first photodiode; a second optical waveguide formed above the second photodiode; a first color filter which is formed above the first optical waveguide and transmits mainly light having a first wavelength; a second color filter which is formed above the second optical waveguide and transmits mainly light having a second wavelength; a first microlens formed above the first color filter; and a second microlens formed above the second color filter, wherein the first wavelength is longer than the second wavelength, and the first optical waveguide has a first width smaller than a second width of the second optical waveguide, the first and second widths being in a direction parallel to the semiconductor substrate. | 2011-11-24 |
20110284981 | IMAGE SENSOR COMPRISING MICROLENS ARRAY, AND MANUFACTURING METHOD THEREOF - The present invention relates to an image sensor comprising a microlens array, and to a manufacturing method thereof. The method of the present invention includes gradually increasing the aluminum composition ratio of a compound semiconductor as the latter gradually gets farther from a substrate, to enable a microlens-forming layer to grow, and making the oxidation rate of the region adjacent to the substrate slower and the oxidation rate of the region farther from the substrate faster, making the interface between the oxidized region and the unoxidized region into a lens shape after the completion of oxidation. The thus-made lens is integrated into an image sensor. The present invention reduces costs for manufacturing image sensors in which a microlens is integrated, increases the signal-to-noise ratio and resolution of the image sensor, and achieves improved sensitivity. | 2011-11-24 |
20110284982 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH BACKSIDE DIFFUSION DOPING - Embodiments of a process comprising forming a pixel on a front side of a substrate, thinning the substrate, depositing a doped silicon layer on a backside of the thinned substrate, and diffusing a dopant from the doped silicon layer into the substrate. Embodiments of an apparatus comprising a pixel formed on a front side of a thinned substrate, a doped silicon layer formed on a backside of the thinned substrate, and a region in the thinned substrate, and near the backside, where a dopant has diffused from the doped silicon layer into the thinned substrate. Other embodiments are disclosed and claimed. | 2011-11-24 |
20110284983 | PHOTODIODE DEVICE AND MANUFACTURING METHOD THEREOF - A photodiode device and the manufacturing method of the same are provided. The photodiode device includes a substrate; an epitaxy layer on the substrate, the epitaxy layer including a window layer and a cap layer on the window layer, the cap layer covering a portion of the window layer; and a patterned conductive layer on the cap layer, the patterned conductive layer being formed with a bottom area and a top area wherein the bottom area is greater than the top area. | 2011-11-24 |
20110284984 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - The present invention provides an image sensor and a fabricating method thereof capable of approaching higher quantum efficiency and reducing cost. The method comprises: providing a substrate; forming a pixel region on a top surface of the substrate; forming an interlayer insulating layer and at least a metal line on the pixel region; forming an isolation carrier layer having a hole array therein on the interlayer insulating layer; grinding a lower surface of the substrate to reduce the thickness of the substrate; placing a plurality of conductors into the hole array to form a plurality of bumps on the isolation carrier layer. | 2011-11-24 |
20110284985 | SHALLOW TRENCH ISOLATION EXTENSION - A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects. | 2011-11-24 |
20110284986 | BYPASS DIODE FOR A SOLAR CELL - Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate, the first conductive region of a first conductivity type. A second conductive region is disposed on the first conductive region, the second conductive region of a second conductivity type opposite the first conductivity type. | 2011-11-24 |
20110284987 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region. | 2011-11-24 |
20110284988 | ELECTRICAL FUSE DEVICE - The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link. | 2011-11-24 |
20110284989 | SEMICONDUCTOR APPARATUS AND POWER SUPPLY CIRCUIT - A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals. | 2011-11-24 |
20110284990 | Process for making an alignment structure in the fabrication of a semiconductor device - A process for making an alignment structure in manufacturing a semiconductor device, comprising copper interconnect (Cu-interconnect) fabrication involving chemical-mechanical planarization (CMP) is disclosed. The process comprises tailoring said CMP process to produce a sufficiently high dishing on a designated alignment key area during bulk removal of Cu. The additional dishing step would have sufficient step height for optical pickup to produce alignment signal. Subsequent photolithographic processes specifically for making conventional alignment structure may thus be omitted. Preferably, the additional dishing is achieved by control over any one or combination of pressuring, vacuuming and/or venting of a CMP head's membrane, inner tube and retaining ring chambers, and selection of any one or combination of pads, slurry, pad conditioner and recipe, and may only need to achieve a removal of up to 100 {dot over (A)}. Our process may be adapted for fabricating a MIM top and MIM bottom layers via 2 masking processes, wherein the additional dishing is created as a narrow metal line. It may also be adapted for fabricating an MIM capacitor wherein the underlying Cu layer is used as the bottom plate of the MIM. The additional dishing does not appear to affect electrical properties of the underlying Cu layer. | 2011-11-24 |
20110284991 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane. | 2011-11-24 |
20110284992 | 3D INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME - The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit. | 2011-11-24 |
20110284993 | COMPOSITE GROWTH SUBSTRATE FOR GROWING SIMICONDUCTOR DEVICE - A method according to embodiments of the invention includes providing an epitaxial structure comprising a donor layer and a strained layer. The epitaxial structure is treated to cause the strained layer to relax. Relaxation of the strained layer causes an in-plane lattice constant of the donor layer to change. | 2011-11-24 |
20110284994 | Electrically Broken, but Mechanically Continuous Die Seal for Integrated Circuits - A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die. | 2011-11-24 |
20110284995 | MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS - Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in a substrate, and in some instances may be oxidized to provide desired mechanical properties. Mechanical resonating structures may be formed from the membrane and oxide structures. | 2011-11-24 |
20110284996 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2 | 2011-11-24 |
20110284997 | Chip-Exposed Semiconductor Device and Its Packaging Method - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chi on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices. | 2011-11-24 |
20110284998 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 2011-11-24 |
20110284999 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated. | 2011-11-24 |
20110285000 | SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF - A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate. | 2011-11-24 |
20110285001 | LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate. | 2011-11-24 |
20110285002 | LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS - A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer. | 2011-11-24 |
20110285003 | OPTICAL DEVICE AND METHOD FOR MANUFACTURING OPTICAL DEVICE, AND CAMERA MODULE AND ENDOSCOPE MODULE EQUIPPED WITH OPTICAL DEVICE - An optical device is equipped with a light receiving region | 2011-11-24 |
20110285004 | DEVICES INCLUDING, METHODS USING, AND COMPOSITIONS OF REFLOWABLE GETTERS - Methods for protecting circuit device materials, optoelectronic devices, and caps using a reflowable getter are described. The methods, devices and caps provide advantages because they enable modification of the shape and activity of the getter after sealing of the device. Some embodiments of the invention provide a solid composition comprising a reactive material and a phase changing material. The combination of the reactive material and phase changing material is placed in the cavity of an electronic device. After sealing the device by conventional means (epoxy seal for example), the device is subjected to thermal or electromagnetic energy so that the phase changing material becomes liquid, and consequently: exposes the reactive material to the atmosphere of the cavity, distributes the getter more equally within the cavity, and provides enhanced protection of sensitive parts of the device by flowing onto and covering these parts, with a thin layer of material. | 2011-11-24 |
20110285005 | PACKAGE SYSTEMS HAVING INTERPOSERS - A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. | 2011-11-24 |
20110285006 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip. | 2011-11-24 |
20110285007 | Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP - A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die. | 2011-11-24 |
20110285008 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS UNIT - A semiconductor apparatus including: a substrate | 2011-11-24 |
20110285009 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first terminal; connecting an integrated circuit to the first terminal; forming a second terminal connected over the first terminal and the integrated circuit by a vertical conductive post integral with the first terminal or the second terminal; and encapsulating the integrated circuit and the vertical conductive post leaving portions of the first terminal and the second terminal exposed. | 2011-11-24 |
20110285010 | Electric power converter - An electric power converter includes: a heat sink having a heat receiving surface; a semiconductor module including a metal plate having a heat radiation surface, a switching element on the metal plate opposite to the heat radiation surface, and a resin member covering a part of the metal plate and the switching element; a heat radiation member between the heat receiving surface and the semiconductor module for transmitting heat of the switching element to the heat receiving surface via the metal plate. The heat receiving surface includes a concavity, and the heat radiation surface includes a convexity. The heat radiation member has a predetermined area sandwiched between the concavity and the convexity. | 2011-11-24 |
20110285011 | CU PILLAR BUMP WITH L-SHAPED NON-METAL SIDEWALL PROTECTION STRUCTURE - An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof. | 2011-11-24 |
20110285012 | Substrate Contact Opening - An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die. | 2011-11-24 |
20110285013 | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists - A device includes a first work piece bonded to a second work piece. The first work piece includes a solder resist at a surface of the first work piece, wherein the solder resist includes a solder resist opening, and a bond pad in the solder resist opening. The second work piece includes a non-reflowable metal bump at a surface of the second work piece. A solder bump bonds the non-reflowable metal bump to the bond pad, with at least a portion of the solder bump located in the solder resist opening and adjoining the non-reflowable metal bump and the bond pad. A thickness of the solder resist is greater than about 50 percent a height of the solder bump, wherein the height equals a distance between the non-reflowable metal bump and the bond pad. | 2011-11-24 |
20110285014 | PACKAGING STRUCTURE AND PACKAGE PROCESS - A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip. | 2011-11-24 |
20110285015 | BUMP STRUCTURE AND FABRICATION METHOD THEREOF - There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps. | 2011-11-24 |
20110285016 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate and a stress generating film. A first surface of the substrate includes a protruding part at each of two end portions. The substrate includes a semiconductor element. The stress generating film is formed so as to come into contact with a second surface of the substrate that is opposite to the first surface of the substrate. The stress generating film is in a shape which causes a second stress that offsets at least a part of a first stress occurring as a result of bonding between an external substrate and the protruding part. | 2011-11-24 |
20110285017 | METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE AND OPTOELECTRONIC DEVICE - A method for producing an optoelectronic device includes providing a carrier, applying at least one first metal layer on the carrier, providing at least one optical component, applying at least one second metal layer on the at least one optical component, and mechanically connecting the carrier to the at least one optical component by the at least one first and the at least one second metal layer, wherein the connecting includes friction welding or is friction welding. | 2011-11-24 |
20110285018 | MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE - An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions arc selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module. The second level module substrate has connector pins to provide physical and electrical connections between the external circuitry and the wiring connections on the second level substrate. | 2011-11-24 |
20110285019 | TRANSPARENT CONDUCTORS COMPRISING METAL NANOWIRES - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 2011-11-24 |
20110285020 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 2011-11-24 |
20110285021 | NOBLE METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface. | 2011-11-24 |
20110285022 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5 μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride. | 2011-11-24 |
20110285023 | Substrate Interconnections having Different Sizes - A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like. | 2011-11-24 |
20110285024 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer. | 2011-11-24 |
20110285025 | Wafer Level Chip Scale Package Method Using Clip Array - A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface. | 2011-11-24 |
20110285026 | Process For Improving Package Warpage and Connection Reliability Through Use Of A Backside Mold Configuration (BSMC) - A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection. | 2011-11-24 |
20110285027 | SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME USING A CAPPING LAYER - A semiconductor structure includes an interconnect region, and a material transfer region coupled to the interconnect region through a bonding interface. The semiconductor structure includes a capping layer sidewall portion which extends annularly around the material transfer region and covers the bonding interface. The capping layer sidewall portion restricts the flow of debris from the bonding interface. | 2011-11-24 |
20110285028 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an insulating film, serving as low-porosity regions low in porosity, formed on a substrate and high-porosity regions higher in porosity than the low-porosity regions, and also includes copper interconnects formed to fill interconnect grooves in the insulating film. The insulating film is present under the interconnect grooves, and present in portions neighboring the sidewalls of the interconnect grooves. | 2011-11-24 |
20110285029 | SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS - Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines. | 2011-11-24 |
20110285030 | METHOD FOR PRODUCING CHIP PACKAGES, AND CHIP PACKAGE PRODUCED IN THIS WAY - A method for producing chip packages is disclosed. In one embodiment, a plurality of chips is provided. The chips each have first pads. Second connection pads are applied on the wafer, wherein each second pad is electrically connected to a first pad. | 2011-11-24 |
20110285031 | Interconnect Structure to Reduce Stress Induced Voiding Effect - An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via. | 2011-11-24 |