47th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120292573 | GASIFICATION REACTOR AND PROCESS - A gasification reactor ( | 2012-11-22 |
20120292574 | Process For The Production Of Hydrogen And Carbon Dioxide - This present invention provides a method to more efficiently recover hydrogen and carbon dioxide, preferably at least 50%, even more preferably at least 75%, and most preferably at least 90% of the carbon dioxide. The present invention further provides the design for capture of at least 80%, carbon dioxide from syngas that allows for the simultaneous production of medium to high amounts of hydrogen in the syngas as a part of the production of hydrogen in a hydrogen generation plant. By using the process of the present invention, especially in terms of a hydrogen generation plant, it is possible to increase recovery of hydrogen and capture of the carbon dioxide in the syngas stream by balancing the recycle of the hydrogen rich permeate from the hydrogen membrane separation units to the process unit and/or the water gas shift as capacity allows when a carbon dioxide separation unit, a carbon dioxide membrane separation unit and two hydrogen membrane separation units are utilized. | 2012-11-22 |
20120292575 | NANOCOMPOSITE THERMOELECTRIC CONVERSION MATERIAL AND PROCESS FOR PRODUCING SAME - The invention provides a nanocomposite thermoelectric conversion material ( | 2012-11-22 |
20120292576 | COMPOUNDS FOR ELECTRONIC DEVICES - The present invention relates to compounds of the formula (I) and to the use thereof in organic electronic devices, and to organic electronic devices which comprise compounds of the formula (I), preferably as hole-transport materials and/or as matrix materials, in particular in combination with a further matrix material. | 2012-11-22 |
20120292577 | REGIOREGULAR POLYTHIOPHENE AND PROCESS FOR PRODUCTION THEREOF - Disclosed is a polythiophenes having high electrical conductivity, excellent solubility, long-term stability, excellent processability and high regioregularity. Specifically disclosed is regioregular polythiophene represented by chemical formula (1) | 2012-11-22 |
20120292578 | METHOD FOR PRODUCING COMPOSITE MATERIALS BASED ON POLYMERS AND CARBON NANOTUBES (CNTs), COMPOSITE MATERIALS PRODUCED IN THIS WAY AND USE THEREOF - The invention relates to a method for producing composite materials based on at least one polymer and carbon nanotubes (CNTs), and to composite materials obtained in this manner and the use thereof. | 2012-11-22 |
20120292579 | NANOPARTICLE ARRAY COMPRISING DISTRIBUTED NANOPARTICLES - There is set forth herein a method for providing a nanoparticle array. A nanoparticle network can be provided by nanoparticles combined with surfactant micelle chains. The nanoparticle network can be provided by distributing metal nanoparticles in a surfactant solution and agitating the surfactant solution comprising the nanoparticles to form a gel comprising the nanoparticle network which can be characterized by a distributed array of nanoparticles combined with surfactant micelle chains within a fluid. The gel can comprise a fluid in a continuous phase and the nanoparticles in a discontinuous phase. Apparatus having arrays of nanoparticles are also set forth herein. | 2012-11-22 |
20120292580 | OPTICAL FILM - Provided is an optical film which exhibits low internal haze, low internal scattering, and excellent moisture resistance though the film contains diacetylcellulose having excellent retardation-inducing properties. An optical film characterized by comprising: a cellulose acetate α which has a 6% viscosity of 70 to 250 mPas and a degree of acetyl substitution of 2.0 to less than 2.5; another cellulose acetate β which has a 6% viscosity lower than that of the cellulose acetate α and a degree of acetyl substitution of 2.0 to less than 2.5; ester compound C which has 1 to 12 pyranose or furanose structures of at least one kind and in which all or a part of the OH groups of the structures are esterified; and polyester D represented by Formula (1). B-(G-A)n-G-B (1). | 2012-11-22 |
20120292581 | LIGAND EXCHANGE THERMOCHROMIC SYSTEMS AND HIGH E LIGANDS FOR SAME - Ligand exchange of thermochromic, LETC, systems exhibiting a reversible change in absorbance of electromagnetic radiation as the temperature of the system is reversibly changed are described. The described LETC systems include one or more than one transition metal ion, which experiences thermally induced changes in the nature of the complexation or coordination around the transition metal ion(s) and, thereby, the system changes its ability to absorb electromagnetic radiation as the temperature changes. | 2012-11-22 |
20120292582 | AMMONIUM SALTS OF 9,10-DIHYDRO-10-HYDROXY-9-OXA-10-PHOSPHA-PHENANTHRENE-10-ONE - The invention relates to ammonium salts of 9,10-dihydro-10-hydroxy-9-oxa-10-phosphaphenanthrene-10-one or -10-oxide (DOPO-OH) of formula I: | 2012-11-22 |
20120292583 | BLOCK - A block including first and second generally identical side plates that engage one another and rotatably capture a sheave between them. The side plates may includes interlocking tabs to secure the engagement between the side plates or a separate clip may be used to engage elements of the side plates to secure the plates to each other. | 2012-11-22 |
20120292584 | RESISTIVE MEMORY CELL - Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions. | 2012-11-22 |
20120292585 | CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-POINT MEMORY - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 2012-11-22 |
20120292586 | NONVOLATILE VARIABLE RESISTANCE ELEMENT - According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element. | 2012-11-22 |
20120292587 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell includes a stacked film structure. The stacked film structure is capable of maintaining a first state or a second state. The first state includes a lower electrode film, a first memory element film provided on the lower electrode film and containing a first oxide and an upper electrode film provided on the first memory element film. The second state includes the lower electrode film, the first memory element film provided on the lower electrode film, a second memory element film provided on the first memory element film and containing a second oxide and the upper electrode film provided on the second memory element film. | 2012-11-22 |
20120292588 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device including: a strip-shaped first electrode line ( | 2012-11-22 |
20120292589 | NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element according to the present disclosure includes: a variable resistance element including a first electrode layer, a second electrode layer, and a variable resistance layer which is located between the first electrode layer and the second electrode layer and has a resistance value that reversibly changes based on an electrical signal applied between the first electrode layer and the second electrode layer; and a fixed resistance layer having a predetermined resistance value and stacked together with the variable resistance element. The variable resistance layer includes (i) a first transition metal oxide layer which is oxygen deficient and (ii) a second transition metal oxide layer which has a higher oxygen content atomic percentage than the first transition metal oxide layer. The predetermined resistance value ranges from 70Ω to 1000Ω inclusive. | 2012-11-22 |
20120292590 | OPTICAL COMPONENT - An optical component comprising an emitter and a solid reflector, said reflector having a convex outer surface, said emitter being located within the solid reflector, the emitter being configured to emit radiation via an electric dipole transition, the dipole having a dipole axis being orientated at an angle of 45 degrees or less to the surface normal at the apex of the reflector. | 2012-11-22 |
20120292591 | High-Voltage Electronic Device - A high-voltage electronic device comprising high-voltage electrodes, located in a dielectric envelope with an internal surface coated with a material having a conductivity which is greater than the conductivity of the envelope, characterized in that the areas subject to high field strength are coated with composite material, based on a polycrystalline material with a bulk conductivity of particles 10 | 2012-11-22 |
20120292592 | SEMICONDUCTOR LIGHT EMITTING DEVICE, NITRIDE SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a semiconductor light emitting device includes: first and second semiconductor layers, a light emitting part, and an In-containing layer. The first semiconductor layer is formed on a silicon substrate via a foundation layer. The light emitting part is provided on the first semiconductor layer, and includes barrier layers and a well layer provided between the barrier layers including Ga | 2012-11-22 |
20120292593 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes: a stacked foundation layer, and a functional layer. The stacked foundation layer is formed on an AlN buffer layer formed on a silicon substrate. The stacked foundation layer includes AlN foundation layers and GaN foundation layers being alternately stacked. The functional layer includes a low-concentration part, and a high-concentration part provided on the low-concentration part. A substrate-side GaN foundation layer closest to the silicon substrate among the plurality of GaN foundation layers includes first and second portions, and a third portion provided between the first and second portions. The third portion has a Si concentration not less than 5×10 | 2012-11-22 |
20120292594 | DEVICE INCLUDING QUANTUM DOTS AND METHOD FOR MAKING SAME - A device comprises an anode; a cathode; a layer therebetween comprising quantum dots; and a first layer comprising a material capable of transporting and injecting electrons in, or forming, contact with the cathode, the material comprising nanoparticles of an inorganic semiconductor material. In one embodiment of the device, quantum dots comprise a core comprising a first semiconductor material that confines holes better than electrons in the core and an outer shell comprising a second semiconductor material that is permeable to electrons. In another embodiment of the device, the nanoparticles comprise n-doped inorganic semiconductor material, and a second layer comprising a material capable of transporting electrons is disposed between the layer including quantum dots and the first layer, wherein the second layer has a lower electron conductivity than the first. In a further embodiment of the device, the first layer is UV treated. A method and other embodiments are also disclosed. | 2012-11-22 |
20120292595 | LIGHT EMITTING DEVICE INCLUDING SEMICONDUCTOR NANOCRYSTALS - A light emitting device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor. | 2012-11-22 |
20120292596 | Graphene Base Transistor Having Compositionally-Graded Collector Barrier Layer - A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer. | 2012-11-22 |
20120292597 | Self-Aligned Contacts in Carbon Devices - A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity. | 2012-11-22 |
20120292598 | EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS - A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks. | 2012-11-22 |
20120292599 | CHARGE TRANSPORT MOLECULE GRADIENT - The present embodiments are generally directed to layers that are useful in imaging apparatus members and components, for use in electrophotographic, including digital, apparatuses. More particularly, the embodiments pertain to an electrophotographic imaging member having a charge transport layer in which a charge transport molecule (CTM) concentration gradient is formed through a single coating pass using only a single charge transport layer solution, and time-of-flight based methods of measuring the CTM gradient through the thickness of the charge transport layer. | 2012-11-22 |
20120292600 | PHOSPHORESCENT HETEROLEPTIC PHENYLBENZIMIDAZOLE DOPANTS - Novel phosphorescent heteroleptic iridium complexes with benzimidazole and phenylpyridine ligands are provided. These iridium complexes can improve OLED properties, and are useful in white light applications. | 2012-11-22 |
20120292601 | PHOSPHORESCENT HETEROLEPTIC PHENYLBENZIMIDAZOLE DOPANTS AND NEW SYNTHETIC METHODOLOGY - Novel heteroleptic iridium complexes are provided. These iridium complexes are useful compounds in OLED devices. The ligands for these novel complexes may be obtained using a new synthetic methodology that utilizes manganese dioxide. | 2012-11-22 |
20120292602 | SELF-ALIGNED CARBON ELECTRONICS WITH EMBEDDED GATE ELECTRODE - A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack comprising a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions. | 2012-11-22 |
20120292603 | Heterocyclic compound, organic light-emitting device including the heterocyclic compound, and flat display device including the organic light-emitting device - A heterocyclic compound includes compounds represented by Formula 1 or Formula 2 below: | 2012-11-22 |
20120292604 | ORGANIC LIGHT EMITTING DEVICE - An organic light emitting device is provided. The organic light emitting device includes a substrate, at least one organic scattering layer, a first electrode layer, an organic light emitting layer, and a second electrode layer. The organic scattering layer is disposed on a surface of the substrate, and a glass transition temperature Tg of a material of the organic scattering layer is lower than | 2012-11-22 |
20120292605 | ORGANIC LIGHT EMITTING DIODE DEVICE - In one aspect, an organic light emitting diode device that includes a first electrode, a second electrode facing the first electrode, an emission layer interposed between the first electrode and the second electrode and an auxiliary layer interposed between either one of the first electrode and the second electrode and the emission layer, wherein the auxiliary layer includes a substituted or unsubstituted pyrene-based compound having at least one appended phenyl group is provided. | 2012-11-22 |
20120292606 | AROMATIC AMINE DERIVATIVE, AND ORGANIC ELECTROLUMINESCENT ELEMENT - An aromatic amine derivative including a substituent A and a substituent B each represented by the formula (1) or (2) and having an arylene group bound to a carbazole structure, in which the substituent A and the substituent B include groups different from each other in the position at which the arylene group is bonded to the carbazole structure, and the substituent A and the substituent B are bonded to the same nitrogen atom or different nitrogen atoms in the molecule; an organic electroluminescent device including an organic thin-film layer formed of one or more layers including at least a light emitting layer, the organic thin-film layer being interposed between a cathode and a anode, in which at least one layer of the organic thin-film layer contains the aromatic amine derivative, and the molecules are rarely crystallized. | 2012-11-22 |
20120292607 | ORGANIC ELECTROLUMINESCENCE DEVICE - As an organic electroluminescence device that exhibits superior external quantum efficiency and durability during driving at high temperature, and small variation in chromaticity and small increase in voltage after high-temperature driving, it is provided that the organic electroluminescence device including on a substrate a pair of electrodes and at least one layer of an organic layer including a light emitting layer disposed between the electrodes, wherein the light emitting layer contains at least one specific blue phosphorescent iridium complex and any layer of the at least one layer of an organic layer contains at least one compound represented by Formula (1): | 2012-11-22 |
20120292608 | ORGANIC ELECTROLUMINESCENCE ELEMENT - A light emitting organic thin film including at least one compound represented by Formula (PQ-1) and at least one compound represented by Formula (BN-1). | 2012-11-22 |
20120292609 | COMPOUND HAVING TRIPHENYLAMINE STRUCTURE, AND ORGANIC ELECTROLUMINESCENT DEVICE - There is provided an organic compound of excellent characteristics that exhibits excellent hole-injecting/transporting performance and has an electron blocking ability and a highly stable thin-film state with excellent heat resistance. The compound of the present invention is an arylamine compound having a triphenylamine structure. The arylamine compound is used as a constituent material of at least one organic layer in an organic electroluminescent device that includes a pair of electrodes, and one or more organic layers sandwiched between the pair of electrodes. | 2012-11-22 |
20120292610 | OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING OXIDE SEMICONDUCTOR DEVICES, DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES - An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure. | 2012-11-22 |
20120292611 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus including: a substrate; a thin-film transistor (TFT) formed on the substrate and including a gate electrode, a source electrode, a drain electrode, and an active layer; a first electrode formed on the substrate and electrically connected to the drain electrode; an intermediate layer formed on the first electrode and including an organic light-emitting layer; a second electrode formed on the intermediate layer; and an insertion layer formed between the first electrode and the intermediate layer and including an oxide. | 2012-11-22 |
20120292612 | BACKPLANE FOR FLAT PANEL DISPLAY APPARATUS, FLAT PANEL DISPLAY APPARATUS, AND METHOD OF MANUFACTURING THE BACKPLANE - A backplane includes: a substrate, a pixel electrode, which includes a transparent conductive material, on the substrate, a capacitor first electrode formed on the same layer as the pixel electrode, a first protection layer covering the capacitor first electrode and an upper edge of the pixel electrode, a gate electrode of a thin film transistor (TFT) formed on the first protection layer, a capacitor second electrode formed on the same layer as the gate electrode, a first insulating layer that covers the gate electrode and the capacitor second electrode, a semiconductor layer that is formed on the first insulating layer and includes a transparent conductive material, a second insulating layer covering the semiconductor layer, source and drain electrodes of the TFT that are formed on the second insulating layer, and a third insulating layer that covers the source and drain electrodes and exposes the pixel electrode. | 2012-11-22 |
20120292613 | SEMICONDUCTOR DEVICE - The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor. | 2012-11-22 |
20120292614 | SEMICONDUCTOR DEVICE - A content addressable memory has many elements in one memory cell; thus, the area of one memory cell tends to be large. In view of the above, it is an object of an embodiment of the present invention to reduce the area of one memory cell. Charge can be held with the use of a channel capacitance in a reading transistor (capacitance between a gate electrode and a channel formation region). In other words, the reading transistor also serves as a charge storage transistor. One of a source and a drain of a charge supply transistor is electrically connected to a gate of the reading and charge storage transistor. | 2012-11-22 |
20120292615 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes. | 2012-11-22 |
20120292616 | SEMICONDUCTOR DEVICE - A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor. | 2012-11-22 |
20120292617 | In-Ga-O OXIDE SINTERED BODY, TARGET, OXIDE SEMICONDUCTOR THIN FILM, AND MANUFACTURING METHODS THEREFOR - An oxide sintered body including indium oxide of which the crystal structure substantially includes a bixbyite structure, wherein gallium atoms are solid-saluted in the indium oxide, and an atomic ratio Ga/(Ga+In) is 0.10 to 0.15. | 2012-11-22 |
20120292618 | OPTICAL SEMICONDUCTOR, OPTICAL SEMICONDUCTOR ELECTRODE USING SAME, PHOTOELECTROCHEMICAL CELL, AND ENERGY SYSTEM - The optical semiconductor of the present invention is an optical semiconductor containing In, Ga, Zn, O and N, and has a composition in which a part of oxygen (O) is substituted by nitrogen (N) in a general formula: In | 2012-11-22 |
20120292619 | BACKSIDE TEXTURING BY CUSPS TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing comprises a plurality of cusped features providing diffusive scattering. Constructing the solar cell with a smooth front surface results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 2012-11-22 |
20120292620 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of pixel structure includes: sequentially forming a gate, a gate insulation layer, a semiconductor layer and a conductive layer on a substrate; forming a first patterned photoresist layer including multiple first photoresist blocks and multiple second photoresist blocks on the conductive layer; reducing the thickness of the first patterned photoresist layer until the second photoresist blocks are completely removed; forming a pixel electrode layer and a second photoresist layer on a partial pixel electrode layer; removing a part of the pixel electrode layer exposed by the second photoresist layer, a partial conductive layer and a partial semiconductor layer both under the removed pixel electrode layer to define a first electrode block, a second electrode block and a channel region; removing the remained first patterned photoresist layer and second photoresist layer and forming a protective layer and a common electrode layer on a part of the protective layer. | 2012-11-22 |
20120292621 | Organic Light-Emitting Display Apparatus and Method of Manufacturing the Same - An organic light-emitting display apparatus may include: a planarization layer disposed on a substrate and covering a plurality of thin film transistors; pixel electrodes, each comprising a light emission portion and anon-light emission portion, the light emission portion being arranged on the planarization layer in a first grid pattern; via-holes, each connecting one thin film transistor and one pixel electrode through the planarization layer, and arranged in a second grid pattern offset from the first grid pattern; dummy via-holes spaced apart from the via-holes; a pixel-defining layer (PDL) disposed on the planarization layer and covering the via-holes, the dummy via-holes, and the non-light emission portion of the pixel electrodes; an organic layer disposed on the light emission portion and comprising an emissive layer; and an opposite electrode disposed on the organic layer. | 2012-11-22 |
20120292622 | PIXEL STRUCTURE AND ELECTRICAL BRIDGING STRUCTURE - A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole. | 2012-11-22 |
20120292623 | Thin-Film Semiconductor Device And Display Equipped With Same - The invention provides a thin-film semiconductor device, which is equipped with a gate electrode, a source electrode, a drain electrode, an oxide semiconductor film, and an oxygen release insulator film. The oxygen release insulator film is in contact with at least a part of the oxide semiconductor film. | 2012-11-22 |
20120292624 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND LIQUID CRYSTAL DISPLAY DEVICE - The disclosed technology is directed to an array substrate, a method for fabricating the same and a liquid crystal display device. The array substrate comprises an electro-static discharge (ESD) circuit region and a pixel region. The method comprises: adjusting the amount of light for exposing so that the amount of light for exposing corresponding to the pixel region is identical to that corresponding to the ESD circuit region; and forming a channel of a thin film transistor (TFT) in the ESD circuit region and a channel of a TFT in the pixel region by a pattering process, wherein the channel of the TFT in the ESD circuit region comprises a plurality of sub-channels arranged in parallel, and each of the sub-channels of the TFT in the ESD circuit region has the same length as the length of the channel of the TFT in the pixel region. | 2012-11-22 |
20120292625 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An embodiment of the disclosed technology provides a method of manufacturing an array substrate, comprising: a first mask process of forming an inorganic material protrusion on a base substrate; a second mask process of forming a reflective region pattern, a gate line, a gate electrode branched from the gate line, and a common electrode; a third mask process of forming an active island and a data line formed and forming a source electrode connected to the data line and a drain electrode on the active island and a channel; a fourth mask process of forming an insulation material layer, treating the insulation material layer to form a planarization layer, and forming a through hole above the drain electrode; and a fifth mask process of forming a pixel electrode and connected to the drain electrode via the through hole in a reflective region. | 2012-11-22 |
20120292626 | OPTICAL AND THERMAL ENERGY CROSS-LINKABLE INSULATING LAYER MATERIAL FOR ORGANIC THIN FILM TRANSISTOR - The problem of the present invention is to provide an organic thin film transistor insulating layer material capable of producing an organic thin film transistor having a small absolute value of threshold voltage and small hysteresis. The means for solving the problem is an organic thin film transistor insulating layer material comprising a macromolecular compound (A) containing repeating units having a fluorine atom-containing group, repeating units having a photodimerizable group and repeating units having a first functional group that generates a second functional group which reacts with active hydrogen by the action of electromagnetic waves or heat, and an active hydrogen compound (B). | 2012-11-22 |
20120292627 | PHOTOSENSOR ELEMENT, PHOTOSENSOR CIRCUIT, THIN-FILM TRANSISTOR SUBSTRATE, AND DISPLAY PANEL - Disclosed is a photosensor element that is provided with a gate electrode ( | 2012-11-22 |
20120292628 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND PREPARATION METHOD THEREOF - One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner. | 2012-11-22 |
20120292629 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process. | 2012-11-22 |
20120292630 | LED SUBSTRATE AND LED - A light emitting diode (LED) substrate including a sapphire substrate is provided. The sapphire substrate has a surface consisting of a plurality of upper trigonal and lower hexagonal tapers, wherein each of the upper trigonal and lower hexagonal tapers is consisted of a hexagonal taper and a trigonal taper on the hexagonal taper, and a pitch of the upper trigonal and lower hexagonal tapers is less than 10 μm. This LED substrate has high light-emitting efficiency. | 2012-11-22 |
20120292631 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part. | 2012-11-22 |
20120292632 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type. | 2012-11-22 |
20120292633 | LIGHT EMITTING DIODE ARRAY AND METHOD FOR MANUFACTURING THE SAME - An LED array includes a substrate and a plurality of LEDs formed on the substrate. The LEDs are electrically connected with each other. Each of the LEDs includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the n-type GaN layer which connects the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. A method for manufacturing the LED array is also provided. | 2012-11-22 |
20120292634 | GALIUM-NITRIDE LIGHT EMITTING DEVICE OF MICROARRAY TYPE STRUCTURE AND MANUFACTURING THEREOF - Disclosed are a microarray type nitride light emitting device and a method of manufacturing the same. More particularly, a uniform current distribution property is ensured by dividing a fine light emitting region by using a first transparent contact layer according to a resistance change property in heat treatment of a material of a transparent conducting oxide used as a transparent contact layer, and connecting the divided light emitting regions by using a second transparent contact layer. | 2012-11-22 |
20120292635 | COMPOSITE SEMICONDUCTOR DEVICE - This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor. | 2012-11-22 |
20120292636 | SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL - A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode. | 2012-11-22 |
20120292637 | Dual Cavity Etch for Embedded Stressor Regions - Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process. | 2012-11-22 |
20120292638 | PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE - A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface. | 2012-11-22 |
20120292639 | STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer. | 2012-11-22 |
20120292640 | Solid State Device - A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device. In another embodiment, the solid state energy conversion device operates as a photovoltaic device. | 2012-11-22 |
20120292641 | SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT, AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE HAVING AT LEAST ONE CONTACT - A semiconductor device having a substrate, and at least one contact, situated on and/or above a surface of the substrate, having at least one layer made of a conductive material, the conductive material including at least one metal. The layer made of the conductive material is sputtered on, and has tear-off marks on at least one outer side area between an outer base area facing the surface and an outer contact area facing away from the surface. A manufacturing method for a semiconductor device having at least one contact is also described. | 2012-11-22 |
20120292642 | FUNCTIONAL ELEMENT AND MANUFACTURING METHOD OF SAME - Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [ | 2012-11-22 |
20120292643 | LED MODULE AND IMAGE SENSOR MODULE - An LED module includes first through third LED chips and two Zener diodes for preventing excessive voltage application to the first and the second LED chips. A first lead includes a mount portion on which the first through third LED chips and the two Zener diodes are mounted. A resin package covers part of the first lead and includes an opening for exposing the three LED chips and two Zener diodes. A single insulating layer bonds the first and second LED chips to the first lead. A single conductive layer bonds the third LED chip and two Zener diodes to the first lead. The Zener diodes are arranged between the first, second LED chips and the third LED chip. | 2012-11-22 |
20120292644 | LED PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a Light Emitting Diode (LED) package, comprising a Printed Circuit Board (PCB), an LED mounted on the PCB, a pillar placed higher than the LED around the LED on the PCB, a transparent plate disposed on the pillar, spaced apart from the LED, and configured to transmit light emitted from the LED, and a fluorescent layer formed on a surface of the transparent plate, facing the LED, and conformably coated with a substance for converting the light emitted from the LED into white light by changing a wavelength of the light, wherein an electrical pad of the LED and an electrical pad of the PCB are electrically connected to each other, and the LED and the fluorescent layer are spaced apart from each other. | 2012-11-22 |
20120292645 | ORGANIC ELECTROLUMINESCENCE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic electroluminescence display including: a gate line disposed on a substrate; a data line crossing the gate line; a TFT connected to the gate and data lines; a capacitor connected to the TFT; and an OLED connected to the TFT. A gate electrode of the TFT and a lower electrode of the capacitor are patterned from a first layer. A gate insulating layer disposed on the gate electrode and an insulating island disposed on the gate line are patterned from a second layer. A semiconductor island disposed on the insulating island and an active layer disposed on the gate insulating layer are patterned from a third layer. An insulating layer is disposed on the TFTs, the capacitor, and between the semiconductor island and the data line. An upper electrode of the capacitor, source/drain electrodes of the TFT, and the data line are patterned from a fourth layer. | 2012-11-22 |
20120292646 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND LIGHTING APPARATUS AND DISPLAY APPARATUS USING THE SAME - The present invention aims to provide a semiconductor light emitting device that may be firmly attached to a substrate with maintaining excellent light emitting efficiency, and a manufacturing method of the same, and a lighting apparatus and a display apparatus using the same. | 2012-11-22 |
20120292647 | ORGANIC ELECTROLUMINESCENT LIGHT SOURCE - An organic electroluminescent light source including a first organic electroluminescent device and a second organic electroluminescent device is provided. The first organic electroluminescent device is coupled to a first bias voltage to emit a first color light having a color temperature ranging from 2800K to 3500K. The second organic electroluminescent device is coupled to a second bias voltage to emit a second color light. The first color light and the second color light mix to generate a third color light having a color temperature ranging from 3500K to 6500K. | 2012-11-22 |
20120292648 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and the functional layer. The foundation layer is formed on an amorphous layer and includes aluminum nitride. The functional layer is formed on the foundation layer and includes a nitride semiconductor. | 2012-11-22 |
20120292649 | SEMICONDUCTOR LIGHT EMITTING DEVICE, WAFER, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL LAYER - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer. | 2012-11-22 |
20120292650 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes an n-type layer, a light emitting layer, a p-type layer, and a transparent electrode. The n-type layer includes a nitride semiconductor and has a thickness not more than 500 nm. The light emitting layer is provided on the n-type layer. The p-type layer is provided on the light emitting layer and includes a nitride semiconductor. The transparent electrode contacts the n-type layer. The n-type layer is disposed between the transparent electrode and the light emitting layer. | 2012-11-22 |
20120292651 | LIGHT EMITTING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - There is provided a light emitting device package including: a substrate having a cavity formed therein; a heat sink provided on a bottom surface of the cavity to be adjacent to an inner wall of the cavity; a light emitting device mounted on the heat sink; and a phosphor layer provided within the cavity and covering the heat sink and the light emitting device. | 2012-11-22 |
20120292652 | SURFACE LIGHT EMITTING DEVICE - The surface light emitting device includes an organic EL element, a protection substrate, a protection part, and a light extraction structure part. The element has a first face and a second face opposite to the first face, and emits light from the first face. The substrate has transparency for light emitted from the element, and is placed facing the first face, and has a primary surface facing the first face of the element. The protection part is placed facing the second face of the element, and constitutes a housing in combination with the substrate and accommodates the element so as to protect the element from water. The structure part is interposed between the first face of the element and the substrate, and suppresses reflection of light emitted from the element on at least one of the first face of the element and the primary surface of the substrate. | 2012-11-22 |
20120292653 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting device. The semiconductor light emitting device includes: a light emitting structure; an electrode layer under the light emitting structure; a light transmitting layer under of the light emitting structure; a reflective electrode layer connected to the electrode layer; and a conductive supporting member under the reflective electrode layer and electrically connected to the reflective electrode layer, wherein the reflective electrode layer includes a first part in contact with an under surface of the electrode layer and a second part spaced apart from the electrode layer. | 2012-11-22 |
20120292654 | LIGHT EMITTING DEVICE - A light emitting device includes an active layer; at least a portion of the active layer constitutes a gain region. The gain region is continuous from a first end surface and a second end surface. The gain region includes a first portion extending from the first end surface to a first reflective surface in a direction tilted with respect to a normal to the first side surface as viewed two-dimensionally; a second portion extending from the second end surface to the second reflective surface in a direction tilted with respect to a normal to the first side surface as viewed two-dimensionally; and a third portion extending from the first reflective surface to the second reflective surface in a direction tilted with respect to a normal to the first reflective surface as viewed two-dimensionally. | 2012-11-22 |
20120292655 | LIGHT EMITTING DIODE CARRIER - A light emitting diode (LED) carrier assembly includes an LED die mounted on a silicon submount, a middle layer that is thermally conductive and electrically isolating disposed below the silicon submount, and a printed circuit board (PCB) disposed below the middle layer. The middle layer is bonded with the silicon submount and the PCB. | 2012-11-22 |
20120292656 | ORGANIC LIGHT EMITTING DEVICE - An organic light emitting device includes a first electrode formed over a substrate, an intermediate layer that is formed over the first electrode and includes an organic light emitting layer, and a second electrode that includes a central electrode unit disposed in a central region and a peripheral electrode unit separated from the central electrode unit and disposed in a peripheral region. The intermediate layer is disposed between the first and second electrodes. The organic light emitting device can readily secure a uniform brightness characteristic. | 2012-11-22 |
20120292657 | SEMICONDUCTOR LIGHT-EMITTING STRUCTURE - A semiconductor light-emitting structure is provided, which includes a first doped type semiconductor layer, a light-emitting layer, a second doped type semiconductor layer, a first electrical transmission layer and at least one first conductor. The light-emitting layer is disposed on the first doped type semiconductor layer and the second doped type semiconductor layer is disposed on the light-emitting layer. The first electrical transmission layer is disposed on the first doped type semiconductor layer, in which a first interface is formed between the first electrical transmission layer and the first doped type semiconductor layer. The first conductor is disposed on the first doped type semiconductor layer. The first electrical transmission layer connects the first conductor. A second interface is formed between each of the first conductor and the first doped type semiconductor layer, and the resistance of the second interface is less than the resistance of the first interface. | 2012-11-22 |
20120292658 | SEMICONDUCTOR OPTOELECTRONIC CONVERTING SYSTEM AND THE FABRICATING METHOD THEREOF - The present invention discloses a semiconductor optoelectronic converting system and the fabricating method thereof, the system comprises a supporting module, a heat pipe, a power converting module and a heat-dissipating plate module. The main features of the present invention are that the supporting module has an accommodating space for disposing the heat pipe, and wherein the supporting module and the heat pipe have a common surface for disposing the power converting module thereon. Furthermore, the present invention further decreases the heat resistant therebetween and improves the heat conducting rate and further capable of becoming a rechargeable self-sufficiency lighting system. | 2012-11-22 |
20120292659 | ORGANIC OPTOELECTRONIC DEVICE AND METHOD - An organic optoelectronic device, such as an organic light emitting device, includes an anode, a cathode and an active organic layer between the anode and the cathode. The cathode includes a layer including a strontium compound, a first conductive layer over the layer including a strontium compound, and a second conductive layer over the first conductive layer, and provides a stable device. | 2012-11-22 |
20120292660 | LED DEVICE, METHOD OF MANUFACTURING THE SAME, AND LIGHT-EMITTING APPARATUS - The LED device ( | 2012-11-22 |
20120292661 | FLUORINATED CURABLE RESIN COMPOSITION - To provide a fluorinated curable resin composition which is excellent in thermal stability and thermal adhesive property. A fluorinated curable resin composition comprising a fluoropolymer (P) having a polymerizable double bond and a thiol compound (S), wherein the fluoropolymer (P) is a copolymer having repeating units derived from a fluoromonoene (a) and a fluorodiene (b) having a residual unsaturated side chain, and the content of the thiol compound (S) is from 0.01 to 1 part by mass per 100 parts by mass of the fluoropolymer (P). | 2012-11-22 |
20120292662 | IE-TYPE TRENCH GATE IGBT - The invention of the present application provides an IE-type trench IGBT. In the IE-type trench IGBT, each of linear unit cell areas that configure a cell area is comprised principally of linear active and inactive cell areas. The linear active cell area is divided into an active section having an emitter region and an inactive section as seen in its longitudinal direction. | 2012-11-22 |
20120292663 | Structure and Method for Monolithically Fabrication Sb-Based E/D Mode MISFETs - The invention provides two Sb-based n- or p-channel layer structures as a template for MISFET and complementary MISFET development. Four types of MISFET devices and two types of complementary MISFET circuit devices can be developed based on the invented layer structures. Also, the layer structures can accommodate more than one complementary MISFETs and more than one single active MISFETs to be integrated on the same substrate monolithically. | 2012-11-22 |
20120292664 | Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs. | 2012-11-22 |
20120292665 | High performance multigate transistor - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a FET structure, where multiple channels and multiple gate regions are formed in order to achieve a lower specific on-resistance, and a higher control on the transport properties of the device. No dielectric layer is present between gate electrodes and device channels, decreasing the parasitic capacitance associated with the gate terminal. The fabrication of the device does not require Silicon On Insulator techniques and it is not limited to Silicon semiconductor materials. It can be fabricated as an enhancement or depletion device with much more control on the threshold voltage of the device, and with superior RF performance. | 2012-11-22 |
20120292666 | SEMICONDUCTOR DEVICE - In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is. | 2012-11-22 |
20120292667 | CROSSBAR STRUCTURE WITH MECHANISM FOR GENERATING CONSTANT OUTPUTS - Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed. | 2012-11-22 |
20120292668 | CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS - The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer. | 2012-11-22 |
20120292669 | FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME - The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region. | 2012-11-22 |
20120292670 | Post-Silicide Process and Structure For Stressed Liner Integration - A method of fabricating a semiconductor device and a corresponding semiconductor device are provided. The method can include implanting a species into a silicide region, the silicide region contacting a semiconductor region of a substrate. A stressed liner may then be formed overlying the silicide region having the implanted species therein. In a particular example, prior to forming the stressed liner, a step of annealing can be performed within an interval less than one second to elevate at least a portion of the silicide region to a peak temperature ranging from 800 to 950° C. The method may reduce the chance of deterioration in the silicide region, e.g., the risk of void formation, due to processing used to form the stressed liner. | 2012-11-22 |
20120292671 | Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer. | 2012-11-22 |
20120292672 | FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION - FINFET ICs and methods for their fabrication are provided. In accordance with one embodiment a FINFET IC is fabricated by forming in a substrate a region doped with an impurity of a first doping type. The substrate region is etched to form a recess defining a fin having a height and sidewalls and the recess adjacent the fin is filled with an insulator having a thickness less than the height. Spacers are formed on the sidewalls and a portion of the insulator is etched to expose a portion of the sidewalls. The exposed portion of the sidewalls is doped with an impurity of the first doping type, the exposed sidewalls are oxidized, and the sidewall spacers are removed. A gate insulator and gate electrode are formed overlying the fin, and end portions of the fin are doped with an impurity of a second doping type to form source and drain regions. | 2012-11-22 |