47th week of 2013 patent applcation highlights part 45 |
Patent application number | Title | Published |
20130309828 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device manufacturing method, comprising forming a first sacrificial layer that contacts at least a portion of a first semiconductor layer and has a higher solid solubility for impurities included in the first semiconductor layer than the first semiconductor layer; annealing the first sacrificial layer and the first semiconductor layer; removing the first sacrificial layer through a wet process; after removing the first sacrificial layer, performing at least one of forming an insulating layer that covers at least a portion of the first semiconductor layer and etching a portion of the first semiconductor layer; and forming an electrode layer that is electrically connected to the first semiconductor layer. | 2013-11-21 |
20130309829 | Method of Forming a Semiconductor Device - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 2013-11-21 |
20130309830 | Self-Aligned III-V MOSFET Fabrication with In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed. | 2013-11-21 |
20130309831 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench. The present invention prevents the Halo implanted ions from entering into the source/drain regions, thus reducing the source/drain junction capacitance; and the asymmetric Halo implantation region can reduce the static power dissipation of the semiconductor device. | 2013-11-21 |
20130309832 | MOS CAPACITORS WITH A FINFET PROCESS - Methods for capacitor fabrication include doping a capacitor region of a semiconductor layer in a semiconductor-on-insulator substrate; partially etching the semiconductor layer to produce a first terminal layer comprising doped semiconductor fins on a remaining base of doped semiconductor; forming a dielectric layer over the first terminal layer; and forming a second terminal layer over the dielectric layer in a finFET process. | 2013-11-21 |
20130309833 | Decoupling Composite Capacitor in a Semiconductor Wafer - According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode. | 2013-11-21 |
20130309834 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch. | 2013-11-21 |
20130309835 | RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS - A method for forming a semiconductor device includes forming a deep trench in a substrate having a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth. A region around the deep trench is doped to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion. A deep trench capacitor is formed in the deep trench using the buried plate as one electrode of the capacitor. An access transistor is formed to charge or discharge the deep trench capacitor. A well is formed in the first doped portion. | 2013-11-21 |
20130309836 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line. | 2013-11-21 |
20130309837 | PREVENTING SHORTING OF ADJACENT DEVICES - Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins. | 2013-11-21 |
20130309838 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS ON BULK SEMICONDUCTOR SUBSTRATES - Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins. | 2013-11-21 |
20130309839 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING RECESSES - Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 2013-11-21 |
20130309840 | COMBINATION OF A SUBSTRATE AND A WAFER - The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer. | 2013-11-21 |
20130309841 | METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES - The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates. | 2013-11-21 |
20130309842 | METHOD FOR MANUFACTURING SOI WAFER - The object of the present invention is to provide a method for reducing defects, which are incurred on a surface of and inside a single-crystal silicon layer by a bonding method, by a treatment at a relatively low temperature over a relatively short duration. More specifically, the present invention relates to a method for manufacturing an SOI wafer, the method comprising the steps of forming a single-crystal silicon layer by a bonding method on a handle substrate selected from a material having a heat-resistant temperature of 800° C. or above to obtain a bonded substrate; depositing amorphous silicon on the single-crystal silicon layer of the bonded substrate; and heating the bonded substrate after the depositing at 800° C. or above. | 2013-11-21 |
20130309843 | SOS SUBSTRATE HAVING LOW DEFECT DENSITY IN VICINITY OF INTERFACE - A bonded SOS substrate having a semiconductor film on or above a surface of a sapphire substrate is obtained by a method with the steps of implanting ions from a surface of a semiconductor substrate to form an ion-implanted layer; activating at least a surface from which the ions have been implanted; bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at a temperature of 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to form a bonded body; and irradiating visible light from a sapphire substrate side or a semiconductor substrate side to the ion-implanted layer of the semiconductor substrate for embrittling an interface of the ion-implanted layer, while keeping the bonded body at a temperature higher than the temperature at which the surfaces of the semiconductor substrate and the sapphire substrate were bonded. | 2013-11-21 |
20130309844 | LASER BEAM PROCESSING METHOD FOR WAFER - A laser beam processing method for a wafer includes a first processed groove forming step in which a laser beam is radiated along a planned dividing line so that the overlapping rate of condensed beam spots is equal to or less than 95%, to thereby form a first laser beam processed groove. The laser beam processing method for a wafer further includes a second processed groove forming step in which a laser beam is radiated along the first laser beam processed groove in such a manner that the overlapping rate of condensed beam spots is equal to or more than 97%, to thereby form a second laser beam processed groove at a bottom portion of the first laser beam processed groove. | 2013-11-21 |
20130309845 | METHOD OF PROCESSING SUBSTRATE - A method of processing a substrate is provided. The method includes providing a substrate, performing a device forming process on the substrate, and cleaning the substrate. The step of cleaning the substrate includes cleaning the substrate with an atomic spray and rinsing the substrate with deionized water. | 2013-11-21 |
20130309846 | METHODS OF FORMING A SILICON SEED LAYER AND LAYERS OF SILICON AND SILICON-CONTAINING MATERIAL THEREFROM - Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon. | 2013-11-21 |
20130309847 | METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS - One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin. | 2013-11-21 |
20130309848 | HIGH THROUGHPUT SEMICONDUCTOR DEPOSITION SYSTEM - A reactor for growing or depositing semiconductor films or devices. The reactor may be designed for inline production of III-V materials grown by hydride vapor phase epitaxy (HVPE). The operating principles of the HVPE reactor can be used to provide a completely or partially inline reactor for many different materials. An exemplary design of the reactor is shown in the attached drawings. In some instances, all or many of the pieces of the reactor formed of quartz, such as welded quartz tubing, while other reactors are made from metal with appropriate corrosion resistant coatings such as quartz or other materials, e.g., corrosion resistant material, or stainless steel tubing or pipes may be used with a corrosion resistant material useful with HVPE-type reactants and gases. Using HVPE in the reactor allows use of lower-cost precursors at higher deposition rates such as in the range of 1 to 5 μm/minute. | 2013-11-21 |
20130309849 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole. | 2013-11-21 |
20130309850 | METHOD OF FABRICATING HIGH EFFICIENCY CIGS SOLAR CELLS - A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25−0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency. | 2013-11-21 |
20130309851 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak. | 2013-11-21 |
20130309852 | BORDERLESS CONTACT FOR AN ALUMINUM-CONTAINING GATE - An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions. | 2013-11-21 |
20130309853 | Methods for Forming a Semiconductor Device Using Masks with Non-Metallic Portions - A method of forming a semiconductor device can be provided by forming a mask pattern including non-metallic first spaced-apart portions that extend in a first direction on a lower target layer and non-metallic second spaced-apart portions that extend in a second direction on the lower target layer to cross-over the non-metallic first spaced-apart portions at locations. The lower target layer can be etched using the mask pattern. | 2013-11-21 |
20130309854 | METHOD FOR MANUFACTURING A SUBSTRATE PROVIDED WITH DIFFERENT ACTIVE AREAS AND WITH PLANAR AND THREE-DIMENSIONAL TRANSISTORS - A substrate is successively provided with a support, an electrically insulating layer, and a semi-conductor material layer. A first protective mask completely covers a second area of the semi-conductor material layer and leaves a first area of the semi-conductor material layer uncovered. A second etching mask partially covers the first area and at least partially covers the second area, so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask so as to form a third etching mask. The semi-conductor material layer is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area, the first etching mask protecting the second area. | 2013-11-21 |
20130309855 | METHODS FOR REOXIDIZING AN OXIDE AND FOR FABRICATING SEMICONDUCTOR DEVICES - Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure. | 2013-11-21 |
20130309856 | ETCH RESISTANT BARRIER FOR REPLACEMENT GATE INTEGRATION - Semiconductor devices and methods of their fabrication are disclosed. One method includes forming a semiconductor device structure including a plurality of dummy gates and a dielectric gap filling material with a pre-determined aspect ratio that is between the dummy gates. An etch resistant nitride layer is applied above the dielectric gap filling material to maintain the aspect ratio of the gap filling material. In addition, the dummy gates are removed by implementing an etching process. Further, replacement gates are formed in regions of the device structure previously occupied by the dummy gates. | 2013-11-21 |
20130309857 | MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES - In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics. | 2013-11-21 |
20130309858 | Method of Forming a Plurality of Spaced Features - A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed. | 2013-11-21 |
20130309859 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A silicon carbide semiconductor device ( | 2013-11-21 |
20130309860 | SEMICONDUCTOR WAFER PLATING BUS AND METHOD FOR FORMING - A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal. | 2013-11-21 |
20130309861 | Semiconductor Constructions and Methods of Planarizing Across a Plurality of Electrically Conductive Posts - Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts. | 2013-11-21 |
20130309862 | METHOD FOR MANUFACTURING Sn ALLOY BUMP - Provided is a method for manufacturing an Sn alloy bump, wherein composition of the Sn alloy bump can be readily controlled. The method for manufacturing an Sn alloy bump formed of an alloy composed of Sn and other one or more types of metals has a step of forming an Sn layer on an electrode pad in a resist opening formed on a substrate by electrolytic plating; a step of laminating Sn and an alloy layer on the Sn layer by electrolytic plating; and a step of forming an Sn alloy bump by melting the Sn layer and the laminated alloy layer after removal of a resist. | 2013-11-21 |
20130309863 | METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION - Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material. | 2013-11-21 |
20130309864 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer. | 2013-11-21 |
20130309865 | METHOD OF MANUFACTURING SUBSTRATE FOR MOUNTING ELECTRONIC DEVICE - There is provided a method of manufacturing a substrate for mounting an electronic device. The method includes disposing a protective layer on a surface of the substrate except for an edge portion thereof . An oxide film is disposed on the entirety of the surface of the substrate except for where the protective layer is disposed The oxide film is grown. A through hole is formed in a thickness direction of the substrate by selectively etching the protective layer. The oxide film is removed. In the manufacturing method, defects in the substrate for mounting an electronic device may be reduced and manufacturing costs can be reduced. | 2013-11-21 |
20130309866 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed. | 2013-11-21 |
20130309867 | LATERAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer. | 2013-11-21 |
20130309868 | METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE - Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened. | 2013-11-21 |
20130309869 | LITHOGRAPHY MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lithography mask is disclosed. The lithography mask is for use with an exposure apparatus which forms an unpatterned first region and a patterned second region that includes groups of desired patterns in a photosensitive layer. The lithography mask includes a transparent substrate; and a patterned light blocking layer that is formed above the transparent substrate and that is configured to block or partially transmit incident light. The patterned light blocking layer includes a first mask pattern that exposes the first region. The first mask pattern includes a periodic pattern having a sub-resolution pitch that is given by an exposure condition of the exposure apparatus. | 2013-11-21 |
20130309870 | METHODS OF REDUCING SUBSTRATE DISLOCATION DURING GAPFILL PROCESSING - Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them. | 2013-11-21 |
20130309871 | METHODS OF FORMING A MASKING PATTERN FOR INTEGRATED CIRCUITS - In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes. | 2013-11-21 |
20130309872 | GAS CLUSTER ION BEAM ETCHING PROCESS FOR ACHIEVING TARGET ETCH PROCESS METRICS FOR MULTIPLE MATERIALS - A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics. | 2013-11-21 |
20130309873 | METHOD OF SELECTIVELY ETCHING A THREE-DIMENSIONAL STRUCTURE - A method of selectively etching a three-dimensional (3-D) structure includes generating a plasma in contact with the 3-D structure, and illuminating a designated portion of the 3-D structure with a laser beam while the plasma is being generated. Nonilluminated portions of the 3-D structure are etched at a first etch rate, and the designated portion of the 3-D structure is etched at a second etch rate, where the second etch rate is different from the first etch rate. | 2013-11-21 |
20130309874 | METHOD AND APPARATUS FOR LIQUID TREATMENT OF WAFER-SHAPED ARTICLES - An apparatus for treating a wafer-shaped article, comprises a spin chuck for holding a wafer-shaped article in a predetermined orientation, a liquid dispenser for dispensing a treatment liquid onto a downwardly facing surface of a wafer-shaped article when positioned on the spin chuck, and a gas dispenser for dispensing a gas within a gap defined between the downwardly-facing surface of the wafer-shaped article and an upper surface of the spin chuck. | 2013-11-21 |
20130309875 | INTERFACE TREATMENT METHOD FOR GERMANIUM-BASED DEVICE - Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on ther surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device. | 2013-11-21 |
20130309876 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber. | 2013-11-21 |
20130309877 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A silicon carbide semiconductor device ( | 2013-11-21 |
20130309878 | PLUG EXTRACTION TEST APPARATUS - A plug extraction test apparatus is disclosed. The plug extraction test apparatus is used for electrically connecting a device to be tested that has an adapter to a testing host, wherein the plug extraction test apparatus includes a first circuit board and a second circuit board. The first circuit board includes at least one connection port and at least one first slot, wherein the at least one connection port allows the adapter to be plugged into it. The second circuit board includes a plurality of conductive contacts used for being electrically connected to the testing host, such that an electrical signal in the second circuit board is transmitted to the testing host. The second circuit board is electrically connected to the first circuit board via the first slot so that an electrical signal in the first circuit board is transmitted to the second circuit. | 2013-11-21 |
20130309879 | UNIVERSAL CIRCUIT BOARD MODULE AND ELECTRIC CONNECTOR USING THE SAME - The present invention discloses a universal circuit board module and an electric connector using the same. The electric connector includes a housing and a universal circuit board module. The housing includes an electric connecter with a plurality of connecting ports and a recess. The recess is used for assembling the universal circuit board module. The electric connector is expanded by increasing the universal circuit board module having electric connecting head with demanded standard or particular function, such that the expansibility can be enhanced. | 2013-11-21 |
20130309880 | CONNECTOR WITH SENSING COMPONENT - A connector with a sensing component comprises an insulated base, a conductive terminal set, a printed circuit board, an insulated bottom plate, and a metal al case. The printed circuit board electrically connects with a sensing component that has a triaxial accelerator, a gyroscope or a motion sensor into a connector. While an electronic device or electrical equipment electrically connecting with the connector is rotating or is tilting, the connector may output a triaxial variation signal in order to change the displaying orientation of the screen of the electronic device or cut off the power of the electrical equipment. | 2013-11-21 |
20130309881 | ELECTRICAL CONNECTOR FOR USE WITH A CIRCUIT BOARD - An electrical connector for use with a circuit board including an insulating housing used to be fixed to a circuit board, a plurality of signal contacts arranged on the insulating housing along a longitudinal direction of the same, at least one ground contact provided in an arrangement of the signal contacts on the insulating housing, and a conductive shell member provided for covering partially a portion of the insulating housing and to be connected with a grounding portion of the circuit board, wherein the conductive shell member has a ground connecting reed-like portion formed thereon so as to correspond to the ground contact and both of the ground connecting reed-like portion of the conductive shell member and the ground contact are connected by means of soldering with the grounding portion of the circuit board. | 2013-11-21 |
20130309882 | ELECTRONIC DEVICE AND CONNECTING COMPONENT - An electronic device includes a first housing, a second housing disposed on the first housing, and a connecting component. The connecting component includes a connecting body and an elastic conductive element. The connecting component is located between the first housing and the second housing. The elastic conductive element with an elastic restoring force is movably disposed in the connecting component. When a part of the elastic conductive element protrudes beyond the connecting body, the elastic conductive element is connected to the second housing and the connecting body. | 2013-11-21 |
20130309883 | Protective Lockable Female Electrical Outlet - An improved electrical outlet providing a lockable electrical connection between a male plug and the outlet to securely retain the plug. The method to secure and retain the plug imparts minimal stress to the outlet and to the male plug so as to not substantially decrease the durability of either. The outlet decreases the shocking potential to a user or unwitting child by remaining un-energized when idle, and prohibits movement from its idle position until the outlet has received the plug terminal prongs. The shape of the movable receptacle assembly and its corresponding cavity blocks a child from contacting the outlets power source with a metallic object, while making the power source available to the receptacle assembly when initiated by the user. The outlets locking action steps secure and energize the plug simultaneously during the locking action steps in a user friendly manner. The modularized design of the receptacle module can provide an easily adaptable means to fit and form various arrangements such as a wall outlet or an extension cord outlet. | 2013-11-21 |
20130309884 | ELECTRICAL CONNECTOR FOR A SAFETY RESTRAINT SYSTEM HAVING A GROUND CONTACT - The present invention relates to an electrical connector for a plug-in connection, comprising a connector housing having a mating part defining a receiving section adapted for receiving a mating section of a counter-connector, at least two contact elements that are placed in the receiving section, and a ground contact assembly comprising a ground contact having a contacting portion adapted for being electrically connected with a grounding element of a retainer. For providing an electrical connector, which can be coupled with standard counter-connectors, the ground contact assembly of the electrical connector according to the present invention is arranged outside the receiving section with the contacting portion extending at least section-wise into the receiving section. | 2013-11-21 |
20130309885 | HOLDER FOR SURFACE CONTACT CARD FOR ELECTRONIC DEVICE - A holder for a surface contact card includes a housing, a tray for receiving the surface contact card, and an ejecting mechanism including a locking block and a first elastic member. The housing includes a base defining a receiving recess. The tray is slidably received in the receiving recess. The locking block releasably locks the tray in the receiving recess. The first elastic member flexibly resists the insertion of the tray into the housing. When the locking block is pushed by an outside force to release the locking by the locking block, the tray is ejected out of the receiving recess under the restoring force of the first elastic member. | 2013-11-21 |
20130309886 | CONNECTOR ASSEMBLY AND CORRESPONDING ASSEMBLY - This connector assembly ( | 2013-11-21 |
20130309887 | CONNECTOR - A connector includes a housing having an insertion portion an upper part of which is opened so as to insert a connection end portion of a connection target having a plurality of contact portions, and at least one confirmation groove for viewing a tip end position of the connection end portion of the connection target inserted into the insertion portion from above, an actuator rotatably attached to the housing between an open position where the upper part of the insertion portion is opened and a closed position where the upper part of the insertion portion is covered, and a portion of the actuator which is located right above the confirmation groove of the housing when the actuator is located at the open position is cut out, and a plurality of contacts fixed to the housing. | 2013-11-21 |
20130309888 | METAL ENCASED CABLE POWER DELIVERY SYSTEM FOR DOWNHOLE PUMPING OR HEATING SYSTEMS - An assembly can include a housing that includes an opening, a bore extending from the opening along an axis and a sealable port; and a cable feed-through body that includes a first axial end, a second axial end, a bore extending between the axial ends, a tapered bore surface and a sealable port, the cable feed-through body being partially disposed within the bore of the housing to locate the second axial end at an axial distance from the opening of the housing that exceeds an axial distance of the sealable port of the housing to at least in part form a gland seal between the cable feed-through body and the bore of the housing. Various other apparatuses, systems, methods, etc., are also disclosed. | 2013-11-21 |
20130309889 | CONNECTOR MODULE ASSEMBLIES, METHODS, AND COMPONENTS FOR IMPLANTABLE MEDICAL ELECTRICAL DEVICES - A contact component of an implantable medical device connector module assembly includes a threaded bore in fluid communication with a connector bore thereof, and a flanged bore in fluid communication with the threaded bore. A perimeter surface of the flanged bore creates a shutoff with a pin during injection molding to form an insulative body of the assembly, and a perimeter surface of an insulative bore formed around the pin is preferably flush with that of the flanged bore of the contact component. A centerline axis of the flanged bore is preferably aligned with that of the threaded bore, for example, so that the molded insulative bore has a centerline axis aligned with that of the threaded bore of the contact component. | 2013-11-21 |
20130309890 | CONNECTOR HOLDING STRUCTURE - A connector holding structure includes a pair of holders each shaped substantially like a U and having a base and a pair of arms extending from both ends of the base; and levers. The pair of arms includes a connector support portion in which the distance between their inner side surfaces is narrower at positions adjacent to the base than the width of the connector opening, and notched portions for getting rid of interference with the claw tabs. The holders are placed respectively at both ends along a longitudinal direction of the connector opening and housed in the faceplate. The lever causes the faceplate to support the holder in one of a position for a holder locked state and a position for a holder released state. | 2013-11-21 |
20130309891 | ELECTRICAL CONNECTOR - An engagement amount of a latch lock part with respect to a signal transmission medium is sufficiently and constantly ensured by a simple configuration. A reference abutting surface having a stepped shape projecting toward an upper surface of the signal transmission medium compared with other part of an inner wall surface of a medium insertion path is formed at part of the inner wall surface of the medium insertion path facing the upper surface of the signal transmission medium, the upper surface of the signal transmission medium is caused to abut at least the reference abutting surface of the medium insertion path, and the position of the upper surface of the signal transmission medium is determined in the thickness direction while using the reference abutting surface as a reference. As a result, the engagement amount and the canceling amount of a latch lock part can be constantly maintained regardless of variations in the thickness of the signal transmission medium, the force of retaining the signal transmission medium is stabilized, and this electrical connector can be downsized. | 2013-11-21 |
20130309892 | Card Edge Connector with Improved Locking Arm - A card edge connector includes an insulative housing, a number of contacts and a pair of locking arms for holding a card. Each locking arm includes a retaining portion fixed to the insulative housing and a resilient arm extending forwardly from the retaining portion. The resilient arm is deformable outwardly so as to lock or unlock with the card. The resilient arm includes an engaging portion extending inwardly and a hook at a front of the engaging portion. The engaging portion includes a downwardly inclined surface for guiding installation of the card. The hook protrudes upwardly beyond the engaging portion so that when the card is not so inserted along a card-insertion direction, even if the card is downwardly pressed, a top edge of the hook resists against the card so as to prevent the card from further downward movement. | 2013-11-21 |
20130309893 | CARD EDGE CONNECTOR ASSEMBLY AND POSITIONING MRTHOD OF THE SAME - A card edge connector assembly comprising a first card edge connector comprising a first insulative housing, a pair of first latching arms disposed on opposite ends of the first insulative housing and a plurality of first conductive terminals retained in the first insulative housing; a second card edge connector including a second insulative housing, a pair of second latching arms located on the opposite ends of the second insulative housing and a plurality of second conductive terminals retained in the second insulative housing. The first and second terminals define pin-shaped solder portions respectively, wherein the first and second insulative housings define protruding portions and recessed portions mutually engaged with each other when the first and second insulative housings are disposed in a head to head arrangement. It can shorten distance between the first and second card edge connectors, which is conducive to miniaturization of connector assembly. | 2013-11-21 |
20130309894 | I/O MOUDLE OF ELECTRONIC DEVICE - An electronic device input and output (I/O) assembly includes a bracket, a first I/O module, and a second I/O module. The first I/O module includes a first connector. The second I/O module is detachably mounted to the first I/O module. The second I/O module includes a second connector. The second connector has a different type with the first connector. The bracket can mount both the first I/O module and the second I/O module to a bezel of an electronic device. | 2013-11-21 |
20130309895 | CONNECTOR - Provided is a connector having a locking mechanism that can ensure both the joining strength between a housing and a locking portion and the locking strength and that can cope with pitch narrowing and miniaturization. A plug connector comprises a plug-side housing, plug-side contacts provided to the plug-side housing and adapted to be electrically connected to a receptacle connector, and plug-side locking portions provided to the plug-side housing and adapted to maintain a connected state of the plug connector and the receptacle connector. The plug-side locking portions each comprise a locking plate having a flat plate-like shape and provided so that the normal direction of the plane of the flat plate is oriented in a locking direction with the receptacle connector, and retaining portions provided to the locking plate and formed so as to be integrated with the plug-side housing. | 2013-11-21 |
20130309896 | Underwater Electrical Connection And Termination Assemblies - An underwater electrical connection assembly may include a contact pin including an axially extending conductive core and an axially extending annular insulation portion around said conductive core, a front end portion of the conductive core having an electrical contact surface, a rear end portion of the conductive core having an electrical contact surface, and an intermediate portion of the conductive core extending axially at an intermediate location between the front and rear end portions, wherein the rear end portion of the conductive core of the pin has a diameter larger than the diameter of the intermediate portion thereof, and wherein the annular insulation portion includes an inner insulating layer around the intermediate portion of the conductive core and an insulating sleeve around the inner insulating layer. | 2013-11-21 |
20130309897 | PLUG-CONNECTOR WITH CAP-HOLDING MECHANISM - The present invention relates to an electrical plug-element for an electrical plug-in connector, comprising a conductor receiving section adapted to take up at least one electrical conductor, and a cap which in a fitted position (R) at least partly covers the conductor receiving section and/or the conductor. In order to securely hold the cap on the plug-element, the present invention provides a blocking member, which in a blocking position (B) blocks the cap in the fitted position (R). | 2013-11-21 |
20130309898 | CHARGING APPARATUS - When a power supply plug | 2013-11-21 |
20130309899 | CONNECTOR AND SYSTEM FOR COOLING ELECTRONIC DEVICES - An electrical connector ( | 2013-11-21 |
20130309900 | Multi-Socketed Electrical Conduit Apparatus - A multi-socketed electrical conduit apparatus for providing power to the outside of a building when there is not an outdoor power socket available. The conduit apparatus includes a prewired conduit that passes through a wall. The conduit is rugged, flexible, and may include numerous elbows and extensions to navigate through studs, wires, and piping. A first socket of the conduit faces outside the building, while a second socket faces inside the building. Both sockets rest flush against both walls, giving the appearance of permanent fixtures. A cable operably joins an indoor power source with the second socket. The subsequent power transmits through the conduit, and becomes available to the first socket. The conduit may also be operable to transfer power wirelessly. In this manner, the outdoor socket may receive power from numerous indoor power sources rather than depending on an extension power cord. | 2013-11-21 |
20130309901 | MULTIPURPOSE ULTRA-PORTABLE ELECTRONICS CABLE - A configurable cable for supporting an/or coupling a portable media device includes a main body with a first electrical connector on a terminal end thereof, a trunk extending from an opposing terminal end of the main body, and a second electrical connector formed on a terminal end of the trunk, wherein the second electrical connector is electrically coupled to the first electrical connector via wires running through a core of the trunk. Left and right legs extend from the opposing terminal end of the main body and on either side and substantially parallel to the trunk such that the body, trunk, and legs are disposed substantially in a plane in a first position of the configurable cable. The trunk and left and right legs are bendable from the first position into at least one of a plurality retained positions out of the plane. | 2013-11-21 |
20130309902 | CONNECTOR HAVING A COUPLING MEMBER FOR LOCKING ONTO A PORT AND MAINTAINING ELECTRICAL CONTINUITY - A jumper comprising a first connector, wherein the first connector includes a post configured to receive a center conductor surrounded by a dielectric of a coaxial cable, a connector body attached to the post, and a coupling member attached to the post, the coupling member having one or more resilient contacts, wherein the resilient contacts are configured to pass over the external threads in a first axial direction, and physically engage the external threads in a second axial direction, and a second connector, wherein the first connector is operably affixed to a first end of the coaxial cable, and the second connector is operably affixed to a second end of the coaxial cable is provided. | 2013-11-21 |
20130309903 | CRIMP TERMINAL - A crimp terminal ( | 2013-11-21 |
20130309904 | COAXIAL CONNECTOR ASSEMBLY - A coaxial connector assembly includes a housing having a mating end and a mounting end having anvils. The housing has a cavity. A center contact is received in the cavity that includes a mating end and a terminating end. An outer contact is received in the cavity. The outer contact has a mating cylinder surrounding the center contact. The outer contact has mounting legs extending from the mating cylinder that extend through the housing to the mounting end of the housing. The mounting legs are formed against the anvils for termination to a circuit board. | 2013-11-21 |
20130309905 | CONNECTOR - The present invention provides a connector, which may comprise a terminal fitting, a connector housing having a terminal receiving chamber in which the terminal fitting is at least partly disposed, and a waterproof body formed of thermoplastic elastomer composition. The thermoplastic elastomer composition may comprise (A) styrene-based elastomer component and (B) syndiotactic polystyrene-based polymer component. (A) Styrene-based elastomer component may comprise (A1) acid-modified styrene-based elastomer and (A2) unmodified styrene-based elastomer. The mass ratio of (A1) acid-modified styrene-based elastomer to the sum of (A1) acid-modified styrene-based elastomer, and (A2) unmodified styrene-based elastomer (A1/(A1+A2)) may be from 0.9 to 0.1. The mass ratio of the (A) styrene-based elastomer component to (B) syndiotactic polystyrene-based polymer component may be from 60:40 to 90:10. | 2013-11-21 |
20130309906 | High Speed Edge Card Connector - A connector for connection between a circuit board and a further electronic component is disclosed. The connector includes an insulating housing having a board slot open towards a mating direction for accommodating the circuit board, and a plurality of terminals. The terminals have a rear portion, an intermediate portion and a tip portion, the intermediate portion including a contact portion for contacting a surface portion of the circuit board when accommodated in the board slot. The housing includes a window such that for a number of adjacent terminals housing material is absent between the intermediate portions. A shield member may be arranged in between the rear portions of the terminals. Improved circuit boards are also disclosed. | 2013-11-21 |
20130309907 | ELECTRICAL CONNECTOR - An electrical connector includes a base board having a plurality of first contact pads and second contact pads exposed on one end of the base board, a plurality of first terminals each having one end thereof connected with the corresponding first contact pad of the base board, a plurality of second terminals each having one end thereof arranged alternately with the first terminals and connected with the corresponding second contact pad of the base board, and an insulating housing having a window. The other end of the first terminal is slanted downward at an angle and then curved upward back to form a barb-like contact portion. The other end of the second terminal defines a contact protrusion. The base board together with the first terminals and the second terminals are disposed in the insulating housing. The contact portions and the contact protrusions are exposed outside through the window. | 2013-11-21 |
20130309908 | CONSOLIDATED POWER TIPS - Consolidated power tips allow a power adaptor to be connected to disparately sized input ports of electronic devices. The consolidated power tips may be sized to balance insertion and pull-out forces for the disparately sized input ports. Deformable members may be added to the consolidated power tips for more desirable insertion and pull-out forces and improved electrical contact. For input ports with different electrical requirements, a mode selector may be added to the consolidated power tip to select between the electrical requirements of the different input ports. | 2013-11-21 |
20130309909 | STACKED ELECTRIC CONNECTOR HAVING BUILT-IN HUB INTEGRATED CIRCUIT - A stacked electric connector includes an insulating body, multiple electrically conductive terminals, a circuit board, a hub integrated circuit, and multiple outputting terminals. Multiple tongues portions extend forwards from the insulating body. Multiple terminal slots are disposed within the tongue portions. The electrically conductive terminals are disposed within the terminal slots. One end of each electrically conductive terminal extends out of the insulating body and is electrically connected to the circuit board. The electrically conductive terminals and the tongue portions together construct multiple connecting ports having the same interface. The hub IC is disposed on the circuit board and electrically connected to the electrically conductive terminals. The outputting terminals are disposed on the circuit board and electrically connected to the hub IC. An amount of the outputting terminals is equal to an amount of the electrically conductive terminals of each connecting port. | 2013-11-21 |
20130309910 | ELECTRICAL CONNECTOR ASSEMBLY - Electrical connectors for interconnecting circuit boards. One such connector includes an integral flange for mounting a guidance pin in any of multiple orientations. A corresponding keying block may have a polarization component that can be mounted in a corresponding number of positions. The connector can accept conductive elements with different shapes for signals and grounds, but the housing may be adapted to receive either type of contact in any contact location. Protection of contact elements from excessive yield is provided within the insulative housing of the backplane connector. On the daughter card connector, height difference between ground and signal contacts in wafer assemblies protects components from electrostatic discharge. | 2013-11-21 |
20130309911 | Mobile High-Definition Link Converter - A Mobile High-Definition Link converters for connecting with a MHL line with a HDTV or with a USB female socket of any electronic device, comprising a zinc alloy press molded shell, located in said shell by injection molding a rubber core and a press formed terminal assembly. The shell comprises of a High Definition Multimedia Interface (HDMI) female socket casing and a USB male socket casing connecting to each other. It is characterized in that, the rubber core and terminal assembly are fixed in a channel formed in the shell and are adapted for the HDMI female socket casing and the USB male socket casing. | 2013-11-21 |
20130309912 | SOCKET CONNECTOR WITH SIGNAL CONTACTS - A socket connector includes an insulative housing, at least one power contact received in the insulative housing, at least one ground contact received in the insulative housing and at least one signal contact received in the insulative housing. The insulative housing includes an upper wall, a lower wall opposite to the upper wall and a pair of lateral walls connecting the upper wall and the lower wall. The insulative housing includes a first receiving recess defined cooperatively by the upper wall, the lower wall and the lateral walls, a complementary section formed in the first receiving recess with a second receiving recess defined therein. | 2013-11-21 |
20130309913 | Connector and Assembly Jig for Connector - A joint connector includes connector housing | 2013-11-21 |
20130309914 | MULTI-ACCESS RJ45 ADAPTOR - A multi-access RJ45 adaptor is provided, which includes an RJ45 plug, at least two RJ45 sockets, and a mobile piece that can move between the at least two RJ45 sockets. The mobile piece is configured to allow insertion of an RJ45 plug into any of the RJ45 sockets and simultaneously to prevent the insertion of another RJ45 plug into the other of the RJ45 sockets. | 2013-11-21 |
20130309915 | ELECTRICAL CONNECTOR WITH SEPARABLE CONTACTS - A contact sub-assembly is provided for an electrical connector. The contact sub-assembly includes a printed circuit and an array of mating contacts. Each mating contact includes a terminating end portion and a mating interface. The contact sub-assembly also includes an array of circuit contacts that is discrete from the array of mating contacts. Each circuit contact is engaged with and electrically connected to the printed circuit. Each circuit contact is separably engaged with and electrically connected to the terminating end portion of a corresponding one of the mating contacts such that the array of circuit contacts electrically connects the array of mating contacts to the printed circuit. | 2013-11-21 |
20130309916 | ELECTRICAL CONNECTORS HAVING OPEN-ENDED CONDUCTORS - Electrical connector including a plurality of mating conductors. Each of the mating conductors extends between an engagement portion and an interior portion. The engagement portions of the mating conductors are configured to engage contacts of the mating connector. The engagement portions are located proximate to one another at a first nodal region. The interior portions are located proximate to one another at a second nodal region. The electrical connector also includes a first open-ended conductor electrically connected to the engagement portion of a first mating conductor of the plurality of mating conductors and extending from the first nodal region. The electrical connector also includes a second open-ended conductor electrically connected to the interior portion of a second mating conductor of the plurality of mating conductors and extending from the second nodal region. The first open-ended conductor is capacitively coupled to the second open-ended conductor. | 2013-11-21 |
20130309917 | WIRE-GRASPING STRUCTURE FOR TERMINAL BLOCK - A wire-grasping structure for a terminal block includes a seat part, a fixing piece, a cover part, a fastening piece, a screw and a spring. The seat part has a transverse opening. The fixing piece is received in a lower accommodating recess of the seat part to slide in the seat part vertically. The cover part covers the seat part. The fastening piece is sandwiched between the cover part and the seat part. The screw is vertically received in an upper accommodating recess of the cover part and aligned with the through hole of the fastening piece and the threaded hole of the fixing piece. The spring is vertically received in the upper accommodating recess of the cover part and has two ends abutting against the fastening piece and the screw. The wire-grasping structure has good wire-grasping reliability and good applicability and is convenient to use. | 2013-11-21 |
20130309918 | CONDUCTIVE TERMINAL - A conductive terminal includes a connecting portion in which a plurality of wires each having a rectangular cross section are to be arranged in parallel and to which the wires are to be electrically connected. The connecting portion has a structure to cover the wires. The connecting portion includes a position regulation member to regulate positions of the wires in an arrangement direction in which the wires are arranged. The position regulation member is provided to face at least one side surface of a wire located at an end of the wires in the arrangement direction. | 2013-11-21 |
20130309919 | CONNECTION PLATE FOR BATTERY TERMINALS AND METHOD FOR MANUFACTURING CONNECTION PLATE FOR BATTERY TERMINALS - A connection plate for battery terminals capable of inhibiting a first member and a second member from being detached from each other is provided. This bus bar | 2013-11-21 |
20130309920 | SYSTEMS AND METHODS FOR MOUNTING OF PLUG-IN ELECTONICS DONGLES - Systems and methods for mounting of plug-in electronic dongles are provided. In one embodiment, an electronics mounting adapter device comprises: a base member that includes a cavity and at least one cable stabilizing element configured to secure a cable connector of a cable within the cavity, wherein the cable is routed though an opening in the base member into the cavity; a cover coupled to the base member by at least one fastener; one or more mounting provisions for securing the base member to a mounting surface; and at least one clamping element configured to clamp a dongle within the cavity, wherein the dongle is coupled to the cable connector. | 2013-11-21 |
20130309921 | INLET GRATE FOR A WATER JET PROPULSION SYSTEM - An inlet grate for a water jet propulsion system to be used in a watercraft has a water passage having an inlet defined by a forward and a rearward area with respect to the watercraft. The inlet grate comprises a first end portion adapted to be connected to the forward area of the inlet and a second end portion adapted to be connected to the rearward area of the inlet as well as at least one elongated member extending from the first end portion toward the second end portion. The inlet grate also comprises at least one deflector having a forward end and a rearward end, the forward end being adjacent to the first end portion of the inlet grate. | 2013-11-21 |
20130309922 | SWIMMING PADDLE AND CUSTOM FITTING METHOD - A swimming paddle with an upper rounded swimcap-shaped edge terminating in side indentations that define cap-securing temples, and a central goggle-securing notch cooperating with a concave region in the lower edge to store goggles vertically on the paddle. The paddle may further include fingerpad-indexing holes extending through the body of the paddle from the inner face to the outer face, the holes sized to allow only the fingerpads of a swimmer's extended fingers to partially protrude from the inner face. A method for custom fitting a swimming paddle to a particular swimmer's hand includes generating a side-by-side image of the swimmer's hand and a commonly-carried object such as a mobile phone in a common plane. The image is compared to stored dimensional data for the object to remotely determine the dimensions of the swimmer's hand and manufacture a custom paddle. | 2013-11-21 |
20130309923 | PERSONAL EMERGENCY VESSEL/SHELTER - The invention is both a functional piece of furniture, but also claims to serve as an emergency haven that can be used as a tornado shelter or as a floating device. | 2013-11-21 |
20130309924 | REINFORCED PULTRUDED POLYURETHANE AND PRODUCTION THEREOF - The invention relates to reinforced pultruded polyurethane and to a method for the production thereof by pultrusion. | 2013-11-21 |
20130309925 | CARBON FIBER FABRIC - A carbon fiber fabric is made of a carbon fiber, which is coated with a sizing being formed of a heat resistant polymer or a precursor of the heat resistant polymer. | 2013-11-21 |
20130309926 | THERMOSETTING RESIN-CONTAINING SOLUTION IN WHICH FINE CARBON FIBERS ARE DISPERSED AND THERMOSETTING RESIN FORMED ARTICLES THEREOF - In dispersing a fine carbon fiber in a thermosetting resin, the invention disperses and disentangles the fine carbon fiber being aggregates form in the thermosetting resin solution, maintains the stable dispersed state, lowers the viscosity of the thermosetting resin solution in which the fine carbon fiber is dispersed, and provides a thermosetting resin formed article containing the fine carbon fiber by curing the fine carbon fiber dispersion solution and a production method thereof. | 2013-11-21 |
20130309927 | Composite Porous Fibrous Dehumidifying Material - A composite porous fibrous dehumidifying material comprised of a plurality of fibers whose surface has immobilized thereon a reversible hydrogel material. The composite porous fibrous structure can be used as a dehumidifying material for reducing energy consumption in air conditioning/climate control units. Preferred fibrous materials are electrically conductive materials, such a graphitic fibers. | 2013-11-21 |