47th week of 2014 patent applcation highlights part 21 |
Patent application number | Title | Published |
20140340089 | MAGNETIC SENSING APPARATUS, SYSTEMS, AND METHODS - In some embodiments, an apparatus and a system, as well as a method and an article, may operate to acquire a first signal from a first magnetometer at least partially disposed within a Helmholtz coil, to acquire a second signal from a second magnetometer having a sensitivity at least one thousand times less than the first magnetometer, to process the second signal to determine a N drive signal, to drive the Helmholtz coil using the drive signal so as to null an ambient Earth magnetic field surrounding the first magnetometer, and to process the first signal as one of a down hole location signal or a down hole telemetry signal, the location signal to determine a range to a sub-surface object, and the telemetry signal to provide data from down hole drilling operations. Additional apparatus, systems, and methods are disclosed. | 2014-11-20 |
20140340090 | METHOD FOR SENSING WELDED CONTACTS ON A SWITCHING DEVICE - A method for sensing a welded relay contact when breaking both sides of a power line on a HVAC device including the steps: applying a first signal to one of a pair of switching devices; electronically sensing a second signal, with a sensing device, whether the other of said two switching devices is welded closed; and sending a third signal from the sensing device indicative of whether the other of said two switching devices is welded closed. | 2014-11-20 |
20140340091 | METHOD FOR MEASURING ELECTRIC CHARGE OF A BATTERY - A method for measuring electric charge of a battery is provided. The method includes the following steps. A lookup table is provided that stores a plurality of preset measurement confirmation voltages and a plurality of set electric charge. A first voltage of the battery is measured as a start point. An end point is calculated according to the lookup table and the start point. A voltage and a current of the battery are measured until a measured voltage reaches a preset measurement confirmation voltage corresponding to the end point. A set electric charge is calculated according to the lookup table from the start point to the end point. An actual electric charge is calculated from the start point to the end point. The set electric charge is corrected according to a difference between the actual electric charge and the set electric charge. | 2014-11-20 |
20140340092 | MONITORING APPARATUS AND METHOD OF BATTERY CONTACT POINT IN CHARGE/DISCHARGE SYSTEM WITH BATTERIES CONNECTED IN SERIES - A monitoring apparatus and method of a battery contact point that autonomously measures contact resistances of a contact terminal for directly connecting a battery for charging/discharging and a circuit in a charge/discharge apparatus for charging/discharging a single secondary battery or a plurality of secondary batteries in series. | 2014-11-20 |
20140340093 | LIQUID ION DETECTOR - A system and method comprising a liquid interface with an electrode. The electrode may be coupled to a MEMS-based electrometer for sensing small amounts of charge imposed on the electrode. In some embodiments ion exchangers may be employed to provide for specific selectivity for certain ions or molecules. The electrometer may include a comb drive actuator coupled to a moving shuttle supported on flexures. | 2014-11-20 |
20140340094 | CURRENT TESTER - A current tester includes: a probe, a computing device for converting a voltage drop across a component to a current, and an output device for signaling a presence or non-presence of current. The computing device stores a pre-determined voltage drop/current relationship for the component. A method for detecting current in a circuit includes: connecting a current tester to the component, measuring a voltage drop across the component, converting the voltage drop to a current via the current tester, and producing a signal by the current tester indicating a presence or non-presence of current in the circuit. A method for detecting current in a circuit may also comprises: connecting probes of a testing device to a component in the circuit; determining via whether the probes are properly connected to the component; and determining a voltage drop across the component to determine the presence or non-presence of current. | 2014-11-20 |
20140340095 | HIGH VOLTAGE CABLE DETECTION USING ROTATING MACHINE IN HYBRID VEHICLES - A system and method described herein detects the presence of an unconnected condition in high voltage component cables in an electric or hybrid-electric vehicle having a high voltage battery or energy storage system. The system includes a mechanical motive device, such as a combustion engine, which is used to rotate an electrical machine (E-machine). The rotation of the E-machine induces a sufficient, yet safe, test voltage on the main high voltage cabling of the vehicle. Measurements are taken at various points near the individual high voltage components to determine if a high voltage cable has become disconnected. | 2014-11-20 |
20140340096 | Method for Identifying One or More Simultaneously Occurring Partial Discharge Sources - A method for identifying one or more simultaneously occurring partial discharge sources from partial discharge measurement signals of an electrical device to which an AC voltage is applied. A method according to the invention for identifying one or more simultaneously occurring partial discharge sources from partial discharge measurement signals of an electrical device to which an AC voltage is applied, in particular a gas-insulated system, a high-voltage generator, a transformer, an electrical high-voltage power line or an electrical cable, comprises the following steps:
| 2014-11-20 |
20140340097 | METHOD OF DETECTING STATE OF POWER CABLE IN INVERTER SYSTEM - Provided is a method of detecting a state of a power cable in an inverter system. The method includes detecting a direct current (DC)-link voltage value of a DC-link capacitor included in an inverter, detecting a battery voltage value of a battery supplying a DC power to the inverter, comparing the DC-link voltage value with the battery voltage value, and determining the state of the power cable connecting the inverter to the battery to be abnormal when a difference between the DC-link voltage value and the battery voltage value is out of a preset range. | 2014-11-20 |
20140340098 | COMBINED CRYSTAL RETAINER AND CONTACT SYSTEM FOR DEPOSITION MONITOR SENSORS - A combination retainer and electrical contact mechanism for a deposition monitor sensor includes a sensor body and a removable flexible electrical contact spanning between a fixed electrical (contact) element in the sensor's body and one face of an associated monitor crystal. A retainer insulates or insures electrical isolation of the spanning electrical contact from unwanted contact to electrically grounded components in which at least one of the retainer and crystal holder include features that maintain the electrical contact with the retainer in order to provide a single mechanism. | 2014-11-20 |
20140340099 | METAL DETECTOR FOR PRODUCTION AND PACKAGING LINES - A metal detector ( | 2014-11-20 |
20140340100 | TECHNIQUES FOR DETERMINING A RESISTANCE VALUE - Some embodiments relate to an integrated circuit (IC). The IC determines a time-variant resistance of an sensing resistor, wherein a resistance of the sensing resistor reflects an ambient environmental condition. The IC includes first and second conditioning circuits, an analog to digital conversion (ADC) element, and a logic circuit. The first conditioning circuit provides a first voltage based on the resistance of the sensing resistor, while the second conditioning circuit provides a second voltage based on a resistance of an on-chip reference resistor. The ADC element provides a multi-bit digital value based on a ratio of the first and second voltages. The multi-bit digital value is indicative of the ambient environmental condition measured by the off-chip sensor. A logic circuit selectively adjusts the first and second voltages based on the multi-bit digital value to limit or avoid saturation of the ADC element. Other embodiments are also disclosed. | 2014-11-20 |
20140340101 | METHOD AND APPARATUS FOR DETERMINING WIRE RESISTANCE - A method and apparatus qualifies a conductor for service and determines imbalance resistance of a conductor. The method and apparatus comprises feeding signals from a controller to termination ends of at least three wires of a conductor. In the controller a resistance difference is determined between first and second wires of the conductor using a measured resistance of one of the three conductor wires as a reference value. The conductor is qualified for services when the resistance difference between the first and second wires is below a threshold. | 2014-11-20 |
20140340102 | Monitoring Voltage Stability of a Transmission Corridor - A voltage stability monitoring apparatus monitors the voltage stability of a transmission corridor through which power flows between different parts of a power system. The apparatus monitors an equivalent load impedance at an interface between the transmission corridor and a part of the power system designated as generating the power. This equivalent load impedance at the interface comprises a ratio of a voltage phasor at the interface to a current phasor at the interface. The apparatus tracks a Thevenin equivalent voltage and impedance of the designated part by separately updating that voltage and impedance. Notably, the apparatus updates the Thevenin equivalent voltage to reflect the magnitude of any changes in the voltage phasor that are associated with large variations in the magnitude of the equivalent load impedance at the interface. The apparatus computes an index indicating the voltage stability as a function of this tracked Thevenin equivalent voltage and impedance. | 2014-11-20 |
20140340103 | Automated Attaching And Detaching Of An Interchangeable Probe Head - A probe card apparatus can comprise a tester interface to a test controller, probes for contacting terminals of electronic devices to be tested, and electrical connections there between. The probe card apparatus can comprise a primary sub-assembly, which can include the tester interface. The probe card apparatus can also comprise an interchangeable probe head, which can include the probes. The interchangeable probe head can be attached to and detached from the primary sub-assembly while the primary sub-assembly is secured to or in a housing of a test system. Different probe heads each having probes disposed in different patterns to test different types of electronic devices can thus be interchanged while the primary sub-assembly is secured to or in a housing of the test system. | 2014-11-20 |
20140340104 | Assembly and Method for Testing an Electronic Circuit Test Fixture - A method provides testing of an electronic circuit test system that includes a test fixture having headed and headless test probes, a shorting plate and a test probe verification plate with apertures. A probe verification test includes: moving the test probe verification plate and the shorting plate into position, where the shorting plate engages any test probe that extends through an aperture of the verification plate; and transmitting an electrical signal to each of the test probes. The electricity flow associated with each of the test probes is analyzed to determine if any of the headless test probes have an open circuit. In response to detecting an open circuit: one or more of the headless test probes are indicated as (a) defective in the test fixture or (b) missing from the test fixture; and the specific locations in the test fixture of the defective or missing test probes are identified. | 2014-11-20 |
20140340105 | TEST ASSEMBLY - A test assembly adapted to test a semiconductor device is provided. The test assembly includes a main circuit board, an intermediate dielectric board, an intermediate circuit board, a plurality of intermediate conductive elements and a plurality of test probes. The main circuit board includes a surface and a plurality of pads disposed on the surface. The intermediate dielectric board is detachably disposed on the surface of the main circuit board and includes a plurality of through holes. The intermediate circuit board is disposed on the intermediated dielectric board and includes a plurality of first pads, a plurality of second pads, a first surface and a second surface opposite to the first surface. The intermediate conductive elements are disposed in the through holes, respectively. Each of the intermediate conductive elements electrically connects one of the pads of the main circuit board and one of the first pads of the intermediate circuit board. The test probes are disposed on the second surface of the intermediate circuit board and respectively electrically connected to the second pads of the intermediate circuit board. Each of the test probes is electrically connected to the main circuit board through the intermediate circuit board and one of the intermediated conductive elements. | 2014-11-20 |
20140340106 | PROBE MEMBER FOR POGO PIN - Provided is probe member for a pogo pin used for testing a semiconductor device, at least a portion of the probe member being inserted into a cylindrical body and supported by an elastic member and an upper end of the probe member contacting a terminal of the semiconductor device. | 2014-11-20 |
20140340107 | BGA TEST SOCKET - For testing a high density BGA package, a central pressure block is designed to press against the chip of the package during test in a test socket. High density socket probe causes high pressure against the package, especially the area under the chip. With the central pressure block of the present invention, the high density BGA package is prevented from deformation because the central pressure block pressing downward against the chip, which balances the pressure coming upward from the high density socket probes under the circuit board in the area under the chip. | 2014-11-20 |
20140340108 | TEST ASSEMBLY - A test assembly adapted to test a semiconductor device is provided. The test assembly includes a main circuit board, a space transformer, a plurality of electrical connection elements, an intermediary stiffener, and a plurality of test probes. The space transformer is disposed on the main circuit board and has a first surface and a second surface opposite to the first surface. The first surface of the space transformer faces the main circuit board. The electrical connection elements are disposed between the main circuit board and the first surface of the space transformer. The space transformer is electrically connected to the main circuit board through the electrical connection elements. The intermediary stiffener is disposed between the main circuit and the first surface of the space transformer. The intermediary stiffener has a plurality of accommodating through holes. Each of the electrical connection elements is disposed in one of the accommodating through holes. The test probes are disposed on the second surface of the space transformer and electrically connected to the space transformer. | 2014-11-20 |
20140340109 | TEST PROBE CARD STRUCTURE - A test probe card structure includes a probe card and a connection circuit common plate. The probe card includes a probe substrate, A test circuit board is disposed between the probe substrate and the connection circuit common plate, The test circuit board has a lest circuit connection section attached to and electrically connected with a common circuit adaptation section of the connection circuit common plate. A circuit extension section is formed around the connection circuit common plate, which is all-channel electrically connectable between a tester and the teat circuit connection section. The connection circuit common plate serves to provide an all-channel test circuit convergence connection ability for the test circuit board so as to greatly minify the size of the test circuit board and lower the manufacturing cost of the probe card. | 2014-11-20 |
20140340110 | Device and Method for Detecting Ability of Anti PID Effect of Solar Cell - A device and a method for detecting the ability of anti PID effect of a solar cell are disclosed according to embodiments of the invention. The device includes a static generator including a high voltage power supply and an ion stick connected to the high voltage power supply; and a metal tray under the ion stick. It is judged whether the solar cell has the ability of anti PID effect by detecting the solar cell directly by the device, so for determining whether the solar cell has the ability of anti PID effect, there is no need for a solar cell assembly manufactured by the solar cell. | 2014-11-20 |
20140340111 | SYSTEM AND METHOD OF MAKING AN INTEGRITY TEST ON AN ELECTRICITY NETWORK IN AN AIRCRAFT - A system and method to test integrity of an electricity power supply network in an aircraft is disclosed. The system comprises: a current injector for connection to an output point of one or more phase line forming a test circuit with an electricity generator, the current injector configured to inject a test signal through the electricity generator in the test circuit; a current measurement test probe for installation in the test circuit to measure intensity of the injected test signal current; and a processing unit to connect to the current measurement test probe and to a set of input and output current measurement probes associated with the phase line to acquire current intensity measurement signals output by the current measurement test probe and by the set of input and output current measurement probes, and to determine electricity indicators representative of the integrity of the electricity power supply network. | 2014-11-20 |
20140340112 | METHODS AND SYSTEMS FOR HARDWARE PIRACY PREVENTION - Provided are methods, systems, and devices for preventing hardware piracy. | 2014-11-20 |
20140340113 | THROUGH SILICON VIA REPAIR CIRCUIT OF SEMICONDUCTOR DEVICE - TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate. | 2014-11-20 |
20140340114 | FAULT DETECTION FOR A DISTRIBUTED SIGNAL LINE - An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal. | 2014-11-20 |
20140340115 | SIGNAL PROCESSING DEVICE - A signal processing device is provided. In a programmable switch in which one of a source and a drain of a first transistor is connected to a gate of a second transistor to control continuity between a source and a drain of the second transistor, a capacitance connected to the gate of the second transistor (which is indicated by C | 2014-11-20 |
20140340116 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device having low power consumption with operation speed maintained is provided. The programmable logic device includes a first circuit; a second circuit; a first transistor making electrical connection between the first circuit and the second circuit depending on a potential of a gate of the first transistor; a first switch configured to control supply of a signal to a first node; a second switch configured to control supply of the signal to a second node; a second transistor having a gate and one of a source and a drain that are electrically connected to the first node and having the other of the source and the drain that is electrically connected to the second node; and a capacitor that holds a potential of the signal supplied to the first node. | 2014-11-20 |
20140340117 | SIGNAL PROCESSING DEVICE - A signal processing device is produced. The signal processing device including a first transistor with high off-state resistance, a second transistor which controls conduction between two different nodes, a capacitor which holds electric charge, and a current control element such as a transistor or a resistor. The first node to which a gate of the second transistor and a second electrode of the current control element are connected, and the second node to which one of a source and a drain of the first transistor, a first electrode of the capacitor, and a first electrode of the current control element are connected. The capacitance (including a parasitic capacitance) of the second node is greater than ten times the capacitance (including a parasitic capacitance) of the first node. The capacitance does not affect the first node; thus, a boosting effect is large and charge retention characteristics are favorable. | 2014-11-20 |
20140340118 | TRISTATE GATE - The present invention relates to a tristate gate ( | 2014-11-20 |
20140340119 | VOLTAGE LEVEL SHIFTER AND SYSTEMS IMPLEMENTING THE SAME - According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain. A lower-voltage control circuit can control a supply of the lower-voltage level to a boundary node arranged at a boundary between the first and second domains. A higher-voltage control circuit can also be provided to control a supply of the higher-voltage level to the boundary node. The lower-voltage control circuit can cut off the lower-voltage supply to the boundary node when the higher-voltage control circuit supplies the higher-voltage level to the boundary node. The higher-voltage control circuit can, for instance, include logic circuitry that enables and disables a connection to the higher-voltage supply. Alternatively, the higher-voltage control circuit can include a boost capacitor coupled between the output node and the boundary node. | 2014-11-20 |
20140340120 | Techniques for Phase Detection - A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase. | 2014-11-20 |
20140340121 | PHASE-DETECTOR CIRCUIT AND CLOCK-DATA RECOVERY CIRCUIT - A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time. | 2014-11-20 |
20140340122 | CONTROLLING VOLTAGE GENERATION AND VOLTAGE COMPARISON - An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage. | 2014-11-20 |
20140340123 | KEY PRESS DETECTING CIRCUIT AND METHOD FOR DETECTING THE STATUS OF MULTIPLE KEYS THROUGH A SINGLE PIN - A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys. | 2014-11-20 |
20140340124 | Circuit with a Plurality of Bipolar Transistors and Method for Controlling Such a Circuit - A circuit includes a bipolar transistor circuit including a first node, a second node, and a plurality of bipolar transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of bipolar transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the bipolar transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period. | 2014-11-20 |
20140340125 | PROGRAMMABLE HIGH-SPEED I/O INTERFACE - Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application. | 2014-11-20 |
20140340126 | DRIVING UNIT AND GATE DRIVER CIRCUIT - The present invention discloses a gate driver circuit. The gate driver circuit includes a plurality of driving units electrically connected in series, wherein the gate driver circuit receives a plurality of frequency signals and the driving units transmit a plurality of output signals sequentially. Furthermore, each driving unit includes a primary circuit, a first voltage regulator circuit and a second voltage regulator circuit. | 2014-11-20 |
20140340127 | SEMICONDUCTOR DEVICE - A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film. | 2014-11-20 |
20140340128 | Organic Zener Diode, Electronic Circuit, and Method for Operating an Organic Zener Diode - This disclosure relates to an organic zener diode having one electrode and one counter electrode, and an organic layer arrangement formed between the electrode and the counter electrode, wherein the organic layer arrangement includes the following organic layers: an electrically n-doped charge carrier injection layer on the electrode side, made from a mixture of an organic matrix material and an n-dopant, an electrically p-doped charge carrier injection layer on the counter electrode side, made from a mixture of another organic matrix material and a p-dopant, and an electrically undoped organic intermediate layer that is arranged between the electrically n-doped charge carrier injection layer on the electrode side and the electrically p-doped charge carrier injection layer on the counter electrode side. An electronic circuit arrangement with an organic zener diode and method for operating an organic zener diode are also provided. | 2014-11-20 |
20140340129 | FREQUENCY CONTROL SYSTEM WITH DUAL-INPUT BIAS GENERATOR TO SEPARATELY RECEIVE MANAGEMENT AND OPERATIONAL CONTROLS - Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes a first bias generator circuit to generate a bias control based on a difference between the management control and a bias feedback reference during a first mode of operation, a second bias generator circuit to generate the bias control based on a difference between the operational control and the bias feedback reference during a second mode of operation, and a bias feedback reference circuit to generate the bias feedback reference based on the bias control. The first mode may include a characterization and/or a start-up mode. The second mode may include an operational mode, such as a feedback-controlled mode. | 2014-11-20 |
20140340130 | Clock Generation Using Fixed Dividers and Multiplex Circuits - Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block. | 2014-11-20 |
20140340131 | REDUCING SETTLING TIME IN PHASE-LOCKED LOOPS - A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled. | 2014-11-20 |
20140340132 | METHOD AND APPARATUS FOR GENERATING A REFERENCE SIGNAL FOR A FRACTIONAL-N FREQUENCY SYNTHESIZER - A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal. | 2014-11-20 |
20140340133 | RADIATION HARDENED CIRCUIT - A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal. | 2014-11-20 |
20140340134 | SEMICONDUCTOR DEVICE - To reduce power consumption of a circuit (TEDC) which detects timing errors in a main flip-flop by determining whether or not output data signals of the main flip-flop and a shadow flip-flop correspond. The TEDC includes a power gating circuit (PGC) which performs power gating of the shadow FF and a reset circuit (RSTC) which resets an output signal of the shadow FF. The PGC makes the shadow FF in an active mode only when error detection needs to be performed; other than that, the PGC makes the shadow FF in a power saving mode. The RSTC supplies a certain voltage to an output terminal of the shadow FF in the power saving mode to suppress malfunction of the TEDC. A transistor using an oxide semiconductor is used to supply the voltage to the output terminal. | 2014-11-20 |
20140340135 | CONTROLLING CLOCK INPUT BUFFERS - An integrated circuit may have a clock input pin coupled to a buffer ( | 2014-11-20 |
20140340136 | Dynamic Level Shifter Circuit - A level shifter does not require any DC (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors. The input-output power voltages domains are unrestricted and flexible. DC isolation is deployed between power domains. Symmetrical rise/fall times are without duty cycle distortion. Over voltage stress is reduced by using metal capacitors. Finally the level shifter does not use high-voltage devices for level shifting purpose. Embodiments of level shifters provide one-way level shifting and bi-directional level shifting. | 2014-11-20 |
20140340137 | RADIO FREQUENCY SWITCH WITH IMPROVED SWITCHING TIME - A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load. | 2014-11-20 |
20140340138 | LOW VOLTAGE METAL GATE ANTIFUSE WITH DEPLETION MODE MOSFET - An antifuse according to an embodiment of the invention herein can include a depletion mode metal oxide semiconductor field effect transistor (“MOSFET”) having a conduction channel and a metal gate overlying the conduction channel. A cathode and an anode of the antifuse can be electrically coupled to the gate, such that the antifuse is programmable by driving a programming current between the cathode and the anode to cause material of the metal gate to migrate away. Under appropriate biasing conditions, when the antifuse is unprogrammed, the conduction channel is turned on unless a voltage above a first threshold voltage is applied to the gate to turn off the conduction channel. The gate can be configured such that when the antifuse has been programmed, the conduction channel remains turned on even if a voltage above the first threshold voltage is applied between the gate and a source region of the MOSFET. | 2014-11-20 |
20140340139 | CIRCUIT WITH A PLURALITY OF DIODES AND METHOD FOR CONTROLLING SUCH A CIRCUIT - A circuit includes a diode circuit and a deactivation circuit. The diode circuit includes a first terminal, a second terminal, and a plurality of diodes coupled in parallel between the first terminal and the second terminal. The diode circuit is configured to be forward biased in an on-time and reverse biased in an off-time. The deactivation circuit is configured to switch a first group of the diodes into a deactivation state at a time instant before the end of the on-time, the first group of diodes including one or more but less than all of the diodes included in the diode circuit. | 2014-11-20 |
20140340140 | PHASED-ARRAY CHARGE PUMP SUPPLY - A charge pump system and method that may provide large supply voltages and currents with reduced ripple voltage at reduced ripple frequency. The charge pump system may include an array of charge pumps and a delay pipeline. The array of charge pumps may include a plurality of charge pumps. The delay pipeline may include a plurality of delay elements. The delay elements may respond to a global trigger signal to output a trigger signal to the array of charge pumps. Respective charge pumps may fire in response to the trigger signal. | 2014-11-20 |
20140340141 | MINIMIZING VOLTAGE DROPS ON PRINTED CIRCUIT BOARDS (PCBs) BY USING CURRENT INJECTORS - A device determines a first voltage measurement of an output of a first brick. The device further determines a second voltage measurement associated with a second brick. The first brick is larger in size than the second brick. The device ramps up an output voltage of the second brick when the second voltage measurement is less than the first voltage measurement. | 2014-11-20 |
20140340142 | MULTI-LEVEL STACK VOLTAGE SYSTEM FOR INTEGRATED CIRCUITS - An integrated circuit supplied by a rail-to-rail power supply voltage includes a multi-level stack voltage generator configured to partition the rail-to-rail power supply voltage into one or more reduced supply voltages each having a voltage value between positive and negative power supply voltages of the rail-to-rail power supply. The reduced supply voltages and the positive and negative power supply voltages being configured in series to form a stack of circuit layers. The integrated circuit further includes a core circuit including core circuit units coupled in a circuit layer or coupled between two or more circuit layers. Each core circuit unit is coupled to at least one of the reduced supply voltages. The core circuit units are coupled in the stack of circuit layers to form a serial connection of core circuit units between the positive power supply voltage and the negative power supply voltage. | 2014-11-20 |
20140340143 | All-CMOS, Low-voltage, Wide-temperature Range, Voltage Reference Circuit - A CMOS voltage reference is disclosed. The CMOS voltage reference may include a PTAT current bias circuit including a start-up circuit, a core module implementing high order non-linear curvature compensation and an output stage supplying the reference voltage. The CMOS voltage reference may include a PTAT current bias circuit having a start-up and a CTAT feedback loop and a PTAT feedback loop and a compensating circuit summing the current from the CTAT feedback loop and the PTAT feedback loop. | 2014-11-20 |
20140340144 | COMMON MODE NOISE REDUCTION CIRCUIT, DIFFERENTIAL SIGNAL TRANSMITTING APPARATUS, DIFFERENTIAL SIGNAL TRANSMITTING SYSTEM AND CAR ELECTRONICS DEVICE - A common mode noise reduction circuit works with a transmission signal output circuit that has a first and a second output terminals and transmits differential signals from the first and second output terminals. The common mode noise reduction circuit includes: a first generating circuit to generate electric current to input to or receive electric current from the first output terminal; a second generating circuit to generate electric current to input to or output receive electric current from the second output terminal; and a control circuit to control the first and second generating circuits so that in synchronism with a drive control clock of the transmission signal output circuit, the first and second generating circuits generate current pulses to reduce common mode noise of the differential signals to be transmitted. | 2014-11-20 |
20140340145 | SIGNAL PROCESSING CIRCUIT, RESOLVER DIGITAL CONVERTER, AND MULTIPATH NESTED MIRROR AMPLIFIER - A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period. | 2014-11-20 |
20140340146 | VARIABLE-GAIN DUAL-OUTPUT TRANSCONDUCTANCE AMPLIFIER-BASED INSTRUMENTATION AMPLIFIERS - A variable-gain current conveyor-based instrumentation amplifier without introducing distortion. An exemplary variable-gain instrumentation amplifier includes a first dual-output transconductance amplifier (DOTA) (i.e., current conveyor) that receives a first input voltage, a second DOTA that receives a second input voltage, a first resistive element connected between the first and second DOTA, an amplifier connected to the second DOTA at an inverting input, and a second resistive element that connects the second DOTA and the inverting input to an output of the amplifier. At least one of the resistive elements is a variable resistive element. | 2014-11-20 |
20140340147 | AMPLIFIER CIRCUIT AND AMPLIFICATION METHOD - A true ground amplifier circuit in which a voltage sensor senses the output voltage and generates a binary output which indicates whether the output is above or below a threshold. A variable gain feedback system generates a feedback signal for combination with the digital input, thereby to provide offset cancellation. The variable gain is reduced over time to provide offset cancellation during an initial period of time of operation of the amplifier circuit. This provides offset cancellation during a start-up period, for example. | 2014-11-20 |
20140340148 | Variable Gain Amplifier - A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor. | 2014-11-20 |
20140340149 | METHOD FOR LOW POWER LOW NOISE INPUT BIAS CURRENT COMPENSATION - Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation. | 2014-11-20 |
20140340150 | TRANSCONDUCTANCE CIRCUIT AND A CURRENT DIGITAL TO ANALOG CONVERTER USING SUCH TRANSCONDUCTANCE CIRCUITS - An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor. | 2014-11-20 |
20140340151 | Transconductance Amplifier - A transconductance amplifier comprises a set of amplifier stages. The last stage of the amplifier is split with a certain ratio whereby one part is used to deliver output current and other part to deliver feedback current to the input. | 2014-11-20 |
20140340152 | ADAPTIVE POWER AMPLIFIER AND METHODS OF MAKING SAME - An exemplary embodiment of the present invention provides an adaptive power amplifier comprising a transistor, a resistive load, and a tuning circuit. The transistor has a drain, a source, and a gate. The resistive load can be electrically coupled to the drain. The tuning circuit can be electrically coupled to the drain in parallel with the transistor. The tuning circuit can comprise an inductor and a capacitive element. The inductor and capacitive element can be in series connection. | 2014-11-20 |
20140340153 | Automatic Gain Control of a Received Signal using a Power Target - The present invention relates to a method and device for performing automatic gain control of a received signal. The method comprises the steps of receiving (S | 2014-11-20 |
20140340154 | SYSTEMS AND METHODS FOR IMAGE LAG MITIGATION FOR BUFFERED DIRECT INJECTION READOUT WITH CURRENT MIRROR - Embodiments relate to systems and methods for image lag mitigation for a buffered direct injection readout circuit with current mirror. A photo detector device is coupled to a buffered direct injection (BDI) circuit, in which an operational amplifier and other elements communicate the output signal from the detector to subsequent stages. The BDI output is transmitted to a first current mirror, which can be implemented as a Säckinger current mirror. The first current mirror is coupled to a second current mirror, one of whose outputs is a fixed bias current. Image lag can be controlled by the fixed bias current, rather than the photocurrent produced directly by the optical detector. In aspects, the negative feedback provided by the first current mirror can increase the modulation of the second current mirror. This gain factor can reduce image lag to a significantly lower point than the lag experienced by known BDI-current-modulated readout circuitry without Säckinger current mirror. | 2014-11-20 |
20140340155 | LINEARIZATION OF HETEROGENEOUS POWER AMPLIFIER SYSTEMS - Systems and methods are provided for adaptive linearization of an amplifier system having a plurality of heterogeneous amplifier paths. An amplifier system includes a plurality of amplifier paths, each configured to provide an amplified output signal from an input signal, and a signal combiner configured to combine the amplified output signals from the plurality of amplifier paths to provide a system output, such that the system output is a non-linear function of the amplified output signals. A monitoring system is configured to sample the system output and normalize the sampled output to a signal level associated with the input signal. A signal processing component is configured to characterize the amplifier paths via an iterative adaptive linearization process, such that the system output is linear with respect to the input signal. | 2014-11-20 |
20140340156 | AMPLIFIER - An amplifier comprises a power amplifier for amplifying an unmodulated high-frequency input signal, a first branching device which is provided at an input terminal side of the power amplifier and extracts a signal, a second branching device which is provided at an output terminal side of the power amplifier and extracts a signal, a mixer for mixing a signal from the first branching device and a signal from the second branching device, a low-pass filter for removing a frequency band component of the input signal from an output signal of the mixer, a high-pass filter for removing a DC component from an output signal of the low-pass filter, and a wave detector for extracting a signal. | 2014-11-20 |
20140340157 | POWER AMPLIFIER - A power amplifier comprising a plurality of primary amplifying channels arranged to each receive an input signal from one or more signal sources for generating a primary amplified output in each of the plurality of primary amplifying channels, a secondary amplifying channel in communication with the one or more signal sources wherein the secondary amplifying channel is arranged to receive one or more signal components each associated with the input signal received by each of the plurality of primary amplifying channels to form a merged input signal for generating a secondary amplified output, and an electric junction arrangement being in electrical communication with the primary amplified output of each of the primary amplifying channels and the secondary amplified output of the secondary amplifying channel. | 2014-11-20 |
20140340158 | REDUCING KICKBACK CURRENT TO POWER SUPPLY DURING CHARGE PUMP MODE TRANSITIONS - Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition. | 2014-11-20 |
20140340159 | Circuit Layout and Method for Frequency-Dependent Matching of a High-Frequency Amplifier Stage - A circuit for frequency-dependent matching of a high-frequency amplifier stage includes high-frequency stage with an output to a total high-frequency path that divides a total frequency band into a plurality of partial frequency paths for respectively preset partial frequency bands. The outputs of the plurality of partial frequency paths are reunited again into the total high-frequency path, following the processing of the partial frequency bands of these partial frequency paths. The partial frequency paths include a matching network surrounded by a first and second pass filter. At least one partial frequency path is switchable, when a control signal is supplied thereto. | 2014-11-20 |
20140340160 | SEMICONDUCTOR POWER AMPLIFIER - A semiconductor power amplifier comprises an input-side amplifier for inputting and amplifying an input signal, a balanced amplifier which is connected to an output terminal of the input-side amplifier, comprises two hybrid couplers and a plurality of power amplifiers, passes the input signal, and converts a reflective wave into thermal energy, and an output-side amplifier which is connected to an output terminal of the balanced amplifier and amplifies an output signal. | 2014-11-20 |
20140340161 | DIGITAL PHASE-LOCKED LOOP DEVICE WITH AUTOMATIC FREQUENCY RANGE SELECTION - A digital phase-locked loop (PLL) device includes a digital loop filter which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed. | 2014-11-20 |
20140340162 | OSCILLATOR - An oscillator includes: a piezoelectric material to vibrate; a first inverting amplifier; a second inverting amplifier; a first output electrode to apply an output signal of the first inverting amplifier to the piezoelectric material; a second output electrode to apply an output signal of the second inverting amplifier to the piezoelectric material; a first input electrode to receive a voltage signal generated by the piezoelectric material and output the voltage signal to the first inverting amplifier; and a second input electrode to receive the voltage signal and output the voltage signal to the second inverting amplifier, wherein the first and second output electrodes are coupled to the piezoelectric material so that faces of the piezoelectric material move in opposite directions, and the first and second input electrodes are coupled to the piezoelectric material so that the voltage signals are input to the first and second input electrodes. | 2014-11-20 |
20140340163 | OSCILLATOR DEVICE AND METHOD OF MOUNTING OSCILLATOR DEVICE - A oscillator device includes: a first substrate that has a first surface, a second surface, and a through hole extending between the first surface and the second surface; a crystal oscillator that is disposed on the first surface of the first substrate, the crystal oscillator including an electrode; a second substrate that is disposed on the crystal oscillator; a through electrode that is disposed in the through hole, that has a diameter smaller than a diameter of the through hole, that is electrically coupled to the electrode, and that extends between the first surface and the second surface; and a filling member with which an area between an inner wall of the through hole and the through electrode is filled. | 2014-11-20 |
20140340164 | CR OSCILLATION CIRCUIT - In a CR oscillation circuit, resistance elements forming a series circuit include a first resistance element having a large temperature coefficient of resistance and a second resistance element having a smaller temperature coefficient of resistance than the first resistance element. At least one of a capacitor and an oscillation resistance element is trimmable. A first switching circuit connected between the series circuit and a non-inverting input terminal of a comparator is turned on when an output signal of the comparator is at a high level, and a second switching circuit is turned on when the output signal is at a low level. | 2014-11-20 |
20140340165 | FERRITE CIRCULATOR WITH INTEGRATED E-PLANE TRANSITION - A waveguide circulator system for an E-plane-layer transition includes a first waveguide including: at least N waveguide arms, and a first-interface aperture spanning a first X-Y plane on a bottom surface of a first waveguide arm, a ferrite element having N segments protruding into the N respective waveguide arms of the first waveguide; an E-plane-transition waveguide having a first open-end and a second opposing open-end; and a second waveguide including a second-interface aperture spanning a second X-Y. The first-interface aperture is arranged to proximally overlap the first open-end. The second second-interface aperture of the second waveguide and the second-interface aperture is arranged to proximally overlap the second open-end. At least a portion of the first segment of the ferrite element protrudes into a volume extending between the first-interface aperture on the bottom surface of the first waveguide arm and an opposing top surface of the first waveguide arm. | 2014-11-20 |
20140340166 | NON-RECIPROCAL CIRCUIT ELEMENT - A non-reciprocal circuit element includes a ferrite, a first central electrode and a second central electrode that are arranged on the ferrite so as to cross each other in an insulated state, and a permanent magnet configured to apply a DC magnetic field to a portion where the first and second central electrodes cross each other. One end of the first central electrode defines an input port and the other end thereof defines an output port. One end of the second central electrode defines the input port and the other end thereof defines a ground port. A resistance element and a capacitance element which are connected in parallel with each other are connected in series between the input port and the output port. A switching capacitance unit configured to switch a capacitance is connected in parallel with the resistance element between the input port and the output port. | 2014-11-20 |
20140340167 | DIFFERNTIAL TRANSMISSION CIRCUIT - A low pass filter | 2014-11-20 |
20140340168 | FILTER CIRCUIT AND MODULE - A filter circuit includes: a first band-pass filter, a second band-pass filter, a third band-pass filter and a fourth band-pass filter each having input and output terminals; a first terminal to which one of input and output terminals of first band-pass filter and one of input and output terminals of second band-pass filter are connected; a second terminal to which one of input and output terminals of third band-pass filter and one of input and output terminals of fourth band-pass filter are connected; a third terminal to which another one of input and output terminals of first band-pass filter and another one of input and output terminals of fourth band-pass filter are connected; and a fourth terminal to which another one of input and output terminals of second band-pass filter and another one of input and output terminals of third band-pass filter are connected. | 2014-11-20 |
20140340169 | REDUCED SIZE CAVITY FILTER FOR PICO BASE STATIONS - An improved microwave cavity filter used in cellular communication systems such as base stations is disclosed. The cavity filter has a conductive housing forming a cavity therein and a hollow conductive resonator configured in the cavity with a folded hat shaped upper portion. A tuning screw extends from the top cover of the housing into the top folded hat portion of the hollow resonator to fine tune the resonator. The resonator also may preferably include two different diameter sections providing a first high impedance section with smaller diameter and a second lower impedance section with a larger diameter configured at an upper end of the resonator. This configuration provides a significantly smaller cavity height for a given power handling capability. The resonator is preferably of constant thickness allowing low cost stamping or other forming techniques to be used in forming the resonator. | 2014-11-20 |
20140340170 | GFCI Compatible System and Method for Activating Relay Controlled Lines Having a Filter Circuit Between Neutral and Ground - A GFCI compatible system and method for activating relay controlled lines having a filter circuit between neutral and ground is described herein. Specifically the disclosure teaches a GFCI compatible system for reducing CMN. A CMN Suppressor can comprise a hot line, a neutral line, and a ground line. The first ends of the hot line, the neutral line, and the ground line can be connected to a GFCI protected hot node, a GFCI protected neutral node, and an electrical ground. The second ends of the hotline, the neutral line, and the ground line can be connected to a CMN sensitive device hot line, a CMN sensitive device neutral line, and a CMN sensitive device ground line. The system can further comprise a high pass filter, a hot line relay contact, a neutral line relay contact, a hot line relay, and a neutral line power relay. | 2014-11-20 |
20140340171 | GFCI Compatible System and Method for Reducing Common Mode Noise - A GFCI Compatible System and Method for Reducing Common Mode Noise is described herein. Specifically the disclosure teaches a GFCI compatible system for reducing common mode noise (CMN). A CMN suppressor can comprise a hot line, neutral line and ground line. The first ends of the hot line, neutral line and ground line can be connected to a GFCI protected hot node, neutral node and ground node. The second ends of the hot line, neutral line and ground line can be connected to a common mode noise (CMN) sensitive device's hot line, neutral line, and ground line. The system can further comprise a toroidal coil inductor located on the ground line and a high pass filter connected between the neutral line and the ground line. The high pass filter can be located downstream from the toroidal coil inductor. | 2014-11-20 |
20140340172 | BULK ACOUSTIC WAVE RESONATOR COMPRISING A BORON NITRIDE PIEZOELECTRIC LAYER - A bulk acoustic wave (BAW) resonator structure comprises: a first electrode disposed over a substrate; a piezoelectric layer disposed over the first electrode, the piezoelectric layer comprising boron nitride (BN); and a second electrode disposed over the first piezoelectric layer. | 2014-11-20 |
20140340173 | Method, System, and Apparatus for Resonator Circuits and Modulating Resonators - Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed. | 2014-11-20 |
20140340174 | ACTIVE FILTER WITH DUAL RESPONSE - Based on an active low-pass filter structure comprising a main conductor line between an input port and an output port, consisting of an input conductor section, an output conductor section, and an inductance network in series between the input and output sections, the inductance network being coupled to the LC resonators, an LC resonator connected to each junction point between two network inductances, and at least one negative resistance in series with one of the resonators, a dual response filter is formed by providing an auxiliary conductor line, wherein an input end of the filter is connected to an electrical ground, forming a resonator with its own resonant frequency less than the cut-off frequency f | 2014-11-20 |
20140340175 | SIGNAL TRANSMISSION DEVICE, FILTER, AND INTER-SUBSTRATE COMMUNICATION DEVICE - A signal transmission device includes substrates and resonance sections resonating at the predetermined resonance frequency. At least one of the substrates is formed with two or more resonators in the second direction, and the remaining one or two or more of the substrates are each formed with one or more resonators in the second direction, and at least one of the resonance sections is configured by a plurality of resonators opposing one another in the first direction between the substrates, the opposing resonators form a coupled resonator resonating as a whole at the predetermined resonance frequency through electromagnetic coupling in a hybrid resonance mode, and in a state that the substrates are separated away from one another to fail to establish electromagnetic coupling thereamong, the resonators forming the coupled resonator resonate at any other resonance frequency different from the predetermined resonance frequency on the substrate basis. | 2014-11-20 |
20140340176 | COMBLINE FILTER - A microstrip combline bandpass filter includes an input port, an output port, and a plurality of resonators each including a microstrip line having a first end and a second end. One of the plurality of resonators is connected to the input port, and another of the plurality of resonators is connected to the output port. The filter also includes a plurality of pairs of series coupled varactors. The first end of each microstrip line is coupled to one of the pairs of varactors, and the second end of each microstrip line is coupled to ground. | 2014-11-20 |
20140340177 | RESONANT CIRCUIT, DISTRIBUTED AMPLIFIER, AND OSCILLATOR - In order to provide a resonant circuit in which the variation in the coupling coefficient with the process fluctuation of the capacitance value is suppressed in a resonant circuit composed of a transmission line and a capacitance, a resonant circuit according to an exemplary aspect of the invention includes a stub; a first capacitance whose one to be connected to the stub and whose another end to be grounded; and a second capacitance whose one end to be connected to a connection between the stub and the first capacitance. | 2014-11-20 |
20140340178 | MULTI-STEP DEEP REACTIVE ION ETCHING FABRICATION PROCESS FOR SILICON-BASED TERAHERTZ COMPONENTS - A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range. | 2014-11-20 |
20140340179 | COMMUNICATION SHEET, SMART SHELF - The communication sheet according to the present invention includes a dielectric layer including a dielectric substrate, a first conductor layer that is a conductor layer including a mesh sheet-like mesh conductor disposed on one surface of the dielectric substrate, wherein an opening region from where the mesh conductor is removed is formed, and a second conductor layer that is a conductor layer including a sheet-like sheet conductor disposed on another surface of the dielectric substrate opposite to the first conductor layer, wherein the sheet conductor in a region opposite to the opening region from where the mesh conductor is removed is not removed. | 2014-11-20 |
20140340180 | IMPEDANCE MATCHING SWITCH CIRCUIT, IMPEDANCE MATCHING SWITCH CIRCUIT MODULE, AND IMPEDANCE MATCHING CIRCUIT MODULE - An impedance matching switch circuit module includes a first switch device connected to first and second high-frequency input/output terminals, a second switch device connected between the first high-frequency input/output terminal and a first matching terminal, and a third switch device connected between the second high-frequency input/output terminal and a second matching terminal. Impedance matching elements having appropriately set element values (inductances or capacitances) are connected to the first and second high-frequency input/output terminals and the first and second matching terminals, and on/off control is performed for the first, second, and third switch devices. | 2014-11-20 |
20140340181 | System and Method for a Switchable Capacitance - In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each has a first semiconductor switching circuit and a capacitance circuit having a first terminal coupled to the first semiconductor switching circuit. A resistance of the first semiconductor switching circuit of a first switch-capacitance cell of the plurality of capacitance-switch cells is within a first tolerance of a resistance of the first semiconductor switching circuit of a second capacitance-switch cell of the plurality of capacitance-switch cells, and a capacitance of the capacitance circuit of the first capacitance-switch cell is within a second tolerance of a capacitance of the capacitance circuit of the second capacitance-switch cell. | 2014-11-20 |
20140340182 | Electromagnetic Actuator Comprising Permanent Magnets and Mechanical Load Interrupter Actuated By Such An Actuator - The invention relates to a novel permanent magnet electromagnetic actuator with triggering speed and drive torque improved relative to those of the prior art. The main target application is actuating an electromechanical switch-disconnector specifically for performing the operations to disconnect a mechatronic circuit-breaker for breaking high-voltage direct currents. | 2014-11-20 |
20140340183 | THIN FILM MAGNETIC ELEMENT - A magnetoresistive effect element includes a pair of first soft magnetic layers that are arranged opposite to each other so as to sandwich a magnetoresistive effect film; a second soft magnetic layer; and a coil that is windingly formed about the second soft magnetic layer. When a rear end region cross-sectional area of the first soft magnetic layers is defined as S1r and a tip end region cross-sectional area of the second soft magnetic layer is defined as S2f, S2f>S1r is established, and when a tip end width of the first soft magnetic layers is defined as W1f and a rear end width of the first soft magnetic layers is defined as W1r, W1r>W1f is established. | 2014-11-20 |
20140340184 | TRANSFORMER DEVICE AND MANUFACTURING METHOD THEREOF - A transformer device includes: a transformer that includes a magnetic body core and a winding; a case that houses the transformer; an external terminal that is provided in the case; a relay section that is provided in the case and to which an end portion of the winding of the transformer is connected; and a conducting wire of which one end is wound around the external terminal and bonded thereto, and another end is connected to the relay section. | 2014-11-20 |
20140340185 | Rotary Connection for Electric Power Transmission - A rotor is rotatable on an axis within a stator. The rotor and stator each have facing coupled magnetic fields formed by electric coils positioned to produce axial force and radial magnetic filed. Stacked laminations are positioned to extend along the length of the rotor axis and the planes of the laminations lie parallel to the axis. There are several lamination packs arranged around both the rotor and the stator so as to shape the inter-engaging magnetic fields for maximum coupling across the rotor/stator airgap with minimum eddy current losses in the laminations. In this way, electric power is transmitted across a rotating coupling without rubbing or other wear contact to provide a long life. | 2014-11-20 |
20140340186 | INTERLEAVED PLANAR INDUCTIVE DEVICE AND METHODS OF MANUFACTURE AND USE - A low cost, high performance electronic device for use in electronic circuits and methods. In one exemplary embodiment, the device includes an interleaved flat coil arrangement that ensures low leakage inductance while using a smaller number of flat coil windings compared to prior art devices. The flat coil windings further include features that are configured to mate with the header assembly terminal pins which substantially simplify the manufacturing process. Methods for manufacturing the device are also disclosed. | 2014-11-20 |
20140340187 | POWER TRANSMISSION COIL - A power transmission coil is unsusceptible to a dimensional error between individual coils or a displacement between primary and secondary coils. The power transmission coil includes a first planar coil having an inner diameter (Di) and a second planar coil having an outer diameter (Do) and being disposed opposite to the first planar coil. The quotient of the outer diameter (Do) of the second planar coil and the inner diameter (Di) of the first planar coil is defined as an inner/outer diameter ratio (Do/Di). The rate of change in the coupling coefficient between the first planar coil and the second planar coil is defined as a coupling coefficient change rate (Δk). The inner diameter (Di) of the first planar coil and the outer diameter (Do) of the second planar coil are determined in accordance with the correlation between the inner/outer diameter ratio (Do/Di) and the coupling coefficient change rate (Δk) so that the inner/outer diameter ratio (Do/Di) has a value not more than the value at which the slope of the correlation begins to rise steeply. | 2014-11-20 |
20140340188 | PLANAR CORE WITH HIGH MAGNETIC VOLUME UTILIZATION - A structure is disclosed, comprising: a first magnetic core portion comprising: a first plurality of leg posts that are to be surrounded by a first set of windings; and a first plurality of center portions that are not to be surrounded by windings; and a second magnetic core portion comprising: a second plurality of leg posts that are to be surrounded by a second set of windings; and a second plurality of center portions that are not to be surrounded by the second set of windings, wherein the first set of center portions and the second set of center portions are configured to provide a plurality of physically separate magnetic flux paths. | 2014-11-20 |