47th week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140339589 | METHOD FOR PRODUCING A POLYCHROMATIZING LAYER AND SUBSTRATE AND ALSO LIGHT-EMITTING DIODE HAVING A POLYCHROMATIZING LAYER - The invention relates to a method for applying a polychromatizing layer which contains at least one luminescent means on a semiconductor substrate, which layer is suitable for producing a monochromatic light. The polychromatizing layer is applied with a printing process, especially with a micro-contact printing process. Preferably the polychromatizing layer is applied structured. | 2014-11-20 |
20140339590 | LIGHT EMITTING APPARATUS - A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer. | 2014-11-20 |
20140339591 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD OF PRODUCTION THEREOF - An optoelectronic semiconductor chip includes a semiconductor layer stack including a nitride compound semiconductor material on a carrier substrate, wherein the semiconductor layer stack includes an active layer that emits an electromagnetic radiation, the semiconductor layer stack being arranged between a layer of a first conductivity and a layer of a second conductivity, the layer of the first conductivity is adjacent a front of the semiconductor layer stack, the layer of the first conductivity electrically connects to a first electrical connection layer covering at least a portion of a back of the semiconductor layer stack, and the layer of the second conductivity type electrically connects to a second electrical connection layer arranged at the back. | 2014-11-20 |
20140339592 | LIGHT EMITTING DIODE - A light emitting diode includes a patterned carbon nanotube layer, a first semiconductor layer, a second semiconductor layer, an active layer stacked on an epitaxial growth surface of a substrate in that sequence. A first portion of the patterned carbon nanotube layer is covered by the first semiconductor layer and a second portion of the patterned carbon nanotube layer is exposed. A first electrode is electrically connected with the second semiconductor layer. A second electrode electrically is electrically connected with the second portion of the patterned carbon nanotube layer. | 2014-11-20 |
20140339593 | LIGHT EMITTING DIODE (LED) COMPONENT COMPRISING A PHOSPHOR WITH IMPROVED EXCITATION PROPERTIES - A light emitting diode (LED) component comprises an LED having a dominant wavelength in a range of from about 425 nm to less than 460 nm and a phosphor in optical communication with the LED. The phosphor includes a host lattice comprising yttrium aluminum garnet (YAG), and may include an activator comprising Ce and a substitutional dopant comprising Ga incorporated in the host lattice. An emission spectrum of the phosphor has a maximum intensity in a wavelength range of from about 540 nm to about 570 nm, and an excitation spectrum of the phosphor comprises an intensity at 440 nm equivalent to at least about 85% of a maximum intensity of the excitation spectrum. | 2014-11-20 |
20140339594 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same. | 2014-11-20 |
20140339595 | LED MODULE - An LED module is provided with a lead, an LED chip mounted on the obverse surface of the lead, and a case covering at least a part of the lead. The case has a side wall surrounding the LED chip. The lead includes a thin extension whose bottom surface is spaced apart upward from the reverse surface of the lead in the thickness direction of the lead. The case is provided with a holding portion that covers at least a part of each of the top surface and the bottom surface of the first thin extension | 2014-11-20 |
20140339596 | CLAD MATERIAL FOR LED LIGHT-EMITTING ELEMENT HOLDING SUBSTRATE, AND METHOD FOR MANUFACTURING SAME - Disclosed is a clad material for an LED light-emitting element holding substrate in which a plurality of layers composed of different materials are stacked and bonded via a metal layer to a III-V group semiconductor crystal surface, the linear expansion coefficient being 14×10 | 2014-11-20 |
20140339597 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH THICK METAL LAYERS - A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature. | 2014-11-20 |
20140339598 | NITRIDE-BASED LIGHT-EMITTING ELEMENT COMPRISING A CARBON-DOPED P-TYPE NITRIDE LAYER - The present invention relates to a nitride-semiconductor light-emitting element in which a p-type nitride layer is doped with carbon, and to a production method therefor. More specifically, the present invention relates to a nitride-semiconductor light-emitting element comprising a p-type nitride layer formed from a nitride having a high concentration of free holes as the carbon is auto-doped in accordance with adjustment of the rate of flow of a nitrogen source. The nitride-semiconductor light-emitting element of the present invention can provide a high free-hole concentration, which is difficult to achieve with conventional single p-type dopants, and can therefore lower the resistance and increase the light efficiency of the light-emitting element. | 2014-11-20 |
20140339599 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first gate electrode that is provided on a first insulating film along one side wall of a first trench and is provided in a second trench, a shield electrode that is provided on a second insulating film along the other side wall of the first trench and is provided in a third trench, a gate runner that is an extended portion of the second trench, has a portion which is provided on the first gate electrode, and is connected to the first gate electrode, and an emitter polysilicon layer that is an extended portion of the third trench, has a portion which is provided on the shield electrode, and is connected to the shield electrode. The semiconductor device has improved turn-on characteristics with a slight increase in the number of process steps, while preventing increase in costs and reduction in yield. | 2014-11-20 |
20140339600 | SEMICONDUCTOR DEVICE - A trench gate MOS structure is provided on one main surface of a semiconductor substrate which will be an n | 2014-11-20 |
20140339601 | DUAL-TUB JUNCTION-ISOLATED VOLTAGE CLAMP DEVICES FOR PROTECTING LOW VOLTAGE CIRCUITRY CONNECTED BETWEEN HIGH VOLTAGE INTERFACE PINS AND METHODS OF FORMING THE SAME - Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin. | 2014-11-20 |
20140339602 | SEMICONDUCTOR DEVICE - In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches. | 2014-11-20 |
20140339603 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region. | 2014-11-20 |
20140339604 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE - A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy. | 2014-11-20 |
20140339605 | Group III-V Device with a Selectively Reduced Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 2014-11-20 |
20140339606 | BSI CMOS IMAGE SENSOR - A back surface illuminated image sensor is provided. The back surface illuminated image sensor includes: a first passivation layer disposed on the photodiode array; an oxide grid disposed on the first passivation layer and forming a plurality of holes exposing the first passivation layer; a color filter array including a plurality of color filters filled into the holes, wherein the oxide grid has a refractive index smaller than that of plurality of color filters; and a metal grid aligned to the oxide grid, wherein the metal grid has an extinction coefficient greater than zero. | 2014-11-20 |
20140339607 | FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES - A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes. | 2014-11-20 |
20140339608 | JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS - An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type ( | 2014-11-20 |
20140339609 | TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation. | 2014-11-20 |
20140339610 | FINFET DEVICE AND METHOD OF FABRICATION - Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency. | 2014-11-20 |
20140339611 | STACKED SEMICONDUCTOR NANOWIRES WITH TUNNEL SPACERS - A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material. | 2014-11-20 |
20140339612 | USING SACRIFICIAL OXIDE LAYER FOR GATE LENGTH TUNING AND RESULTING DEVICE - Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity. | 2014-11-20 |
20140339613 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged on the gate electrode to penetrate the metal layer, and having a bottom surface at a level lower than an upper surface of the semiconductor layer. | 2014-11-20 |
20140339614 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - The present invention provides an image sensor and a method of fabricating the same. The image sensor comprises a semiconductor substrate, a photosensitive component, and a pixel-readout circuit, characterized in that, the semiconductor substrate comprises a supporting substrate, a first insulating buried layer, a first semiconductor layer, a second insulating buried layer, and a second semiconductor layer covered on the semiconductor substrate in sequence; the first semiconductor layer and the second semiconductor layer have different thicknesses, such that the photosensitive component is in the thicker semiconductor layer, and the pixel-readout circuit is in the thinner semiconductor layer. To realize the image sensor mentioned above, two different methods are provided. Ion implantation and bonding method are used respectively to provide the first and second insulating buried layers, and the first and second semiconductor layer substrates, and then the image sensor is fabricated. The image sensor in the present invention has a well anti-radiation character and a well semiconductor character, and a photosensitive zone that has higher light absorption rate. | 2014-11-20 |
20140339615 | BSI CMOS IMAGE SENSOR - A back surface illuminated image sensor is provided. The back surface illuminated image sensor includes: a first passivation layer disposed on the photodiode array; an oxide grid disposed on the first passivation layer and forming a plurality of holes exposing the first passivation layer; a color filter array including a plurality of color filters filled into the holes, wherein the oxide grid has a refractive index smaller than that of plurality of color filters; and a metal grid aligned to the oxide grid, wherein the metal grid has an extinction coefficient greater than zero. | 2014-11-20 |
20140339616 | NON-VOLATILE MEMORY, WRITING METHOD FOR THE SAME, AND READING METHOD FOR THE SAME - A non-volatile memory of an embodiment includes a plurality of memory cells, each of the memory cells including a plurality of transistors including a first to fourth transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the first and second transistors being connected in series with the first non-volatile element, the third and fourth transistors being connected in series with the second non-volatile element, the first node being disposed between the first and second transistors, the second node being disposed between the third and fourth transistors, gates of the first and third transistors being connected to one of first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of second wiring lines and the first node. | 2014-11-20 |
20140339617 | MAGNETIC FIELD EFFECT TRANSISTOR - A magnetic field effect transistor is presented. A magnetic field effect transistor comprises a current control part and a magnetic field applying part. A current control part comprises multiple electrodes and a current flowing material region located between multiple electrodes and in which the amount of current flowing between the electrodes is changed, and a magnetic field applying part applying a magnetic field generating from a magnetization state, which changes according to external input, of a pre-set material. By controlling current by using magnetic fields, high speed operation is possible as charging time is not required, and calculation results may be stored without external power supply because magnetic field is supplied by altering magnetization state of a material according to external input. | 2014-11-20 |
20140339618 | CIRCUIT HAVING CAPACITOR COUPLED WITH MEMORY ELEMENT - A circuit includes a capacitor and a memory element. The capacitor includes a first conductive layer, a first terminal, and a second terminal. The first conductive layer includes a first plurality of bars extending along a first direction and parallel to one another, where two adjacent bars of the first plurality of bars have a first capacitance therebetween. The first terminal is coupled with a first bar of the two adjacent bars, and the second terminal is coupled with a second bar of the two adjacent bars. The memory element has an input coupled with the first terminal and an output coupled with the second terminal. The capacitor is configured to inhibit changing a logic state at the input of the memory element. | 2014-11-20 |
20140339619 | SEMICONDUCTOR DEVICE - Problem: To prevent an excess charge from accumulating in a channel region of a transistor. | 2014-11-20 |
20140339620 | Integrated Circuitry and Methods of Forming Transistors - Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped. | 2014-11-20 |
20140339621 | METHODS FOR FORMING A STRING OF MEMORY CELLS AND APPARATUSES HAVING A VERTICAL STRING OF MEMORY CELLS INCLUDING METAL - Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material. | 2014-11-20 |
20140339622 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells arranged along a first direction that is transverse to a second direction in which word lines for the memory cells extend, each memory cell including a charge accumulation layer provided over the semiconductor substrate, a control gate electrode provided over the charge accumulation layer, and an inter insulating film provided between the charge accumulation layer and the control gate electrode. The inter insulating film is wider along the first direction than the charge accumulation layer and covers opposing side surfaces of an upper portion of the charge accumulation layer in the first direction. In addition, the control gate electrode may be wider along the first direction than the charge accumulation layer. | 2014-11-20 |
20140339623 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 2014-11-20 |
20140339624 | Charge-Retaining Transistor, Array Of Memory Cells, and Methods Of Forming A Charge-Retaining Transistor - A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed. | 2014-11-20 |
20140339625 | PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE - A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET. | 2014-11-20 |
20140339626 | MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F+hu 2 +l MEMORY CELLS - A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts. | 2014-11-20 |
20140339627 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. | 2014-11-20 |
20140339628 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A gate electrode and gate insulating film surround the pillar-shaped silicon layer and a gate line is connected to the gate electrode and extends in a direction orthogonally intersecting the fin-shaped silicon layer. A first diffusion layer resides in an upper portion of the pillar-shaped silicon layer and a second diffusion layer resides in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer. A first silicide resides in an upper portion of the first diffusion layer and a second silicide resides in an upper portion of the second diffusion layer. A contact and metal wire are on the second silicide, and a metal wire is on the first contact. | 2014-11-20 |
20140339629 | CONTACT FORMATION FOR ULTRA-SCALED DEVICES - Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling. | 2014-11-20 |
20140339630 | DEVICE STRUCTURE AND METHODS OF MAKING HIGH DENSITY MOSFETS FOR LOAD SWITCH AND DC-DC APPLICATIONS - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-11-20 |
20140339631 | Innovative Approach of 4F2 Driver Formation for High-Density RRAM and MRAM - Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array. | 2014-11-20 |
20140339632 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other. | 2014-11-20 |
20140339633 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode adjacent to the body region. The body region, the drift zone, the source region and the drain region are disposed in a first semiconductor layer having a first main surface. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. Trenches are disposed in the first semiconductor layer, the trenches extending in the first direction. The transistor further includes a drift control region arranged adjacent to the drift zone. The drift control region and the gate electrode are disposed in the trenches. | 2014-11-20 |
20140339634 | Lateral Transistor Component and Method for Producing Same - A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone. | 2014-11-20 |
20140339635 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region. | 2014-11-20 |
20140339636 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. | 2014-11-20 |
20140339637 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor substrate, a first conductive type well and a second conductive type drift region in the semiconductor substrate, the drift region including a first drift doping region and a second drift doping region, the second drift doping region vertically overlapping the well, and a first conductive type body region in the well, the body region being in contact with a side of the first drift doping region. The first drift doping region and the second doping region may include a first conductive type dopant and a second conductive type dopant, and an average density of the first conductive type dopant in the first drift doping region may be less than an average density of the first conductive type dopant in the second drift doping region. | 2014-11-20 |
20140339638 | INTEGRATING CHANNEL SIGE INTO PFET STRUCTURES - A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer. | 2014-11-20 |
20140339639 | MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES - A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions. | 2014-11-20 |
20140339640 | FINFET WITH VERTICAL SILICIDE STRUCTURE - FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls. | 2014-11-20 |
20140339641 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region. | 2014-11-20 |
20140339642 | REDUCTION OF OXIDE RECESSES FOR GATE HEIGHT CONTROL - An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height. | 2014-11-20 |
20140339643 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS - A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region. | 2014-11-20 |
20140339644 | SEMICONDUCTOR UNIT AND ELECTRONIC APPARATUS - A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal. | 2014-11-20 |
20140339645 | METHODS OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENT INSULATION THICKNESSES ON THE SAME SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICES - One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material. | 2014-11-20 |
20140339646 | NON-PLANAR TRANSITOR FIN FABRICATION - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the doping of fins within non-planar transistors, wherein a conformal blocking material layer, such as a dielectric material, may be used to achieve a substantially uniform doping throughout the non-planar transistor fins. | 2014-11-20 |
20140339647 | DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME - One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively | 2014-11-20 |
20140339648 | TRANSISTORS WITH AN EXTENSION REGION HAVING STRIPS OF DIFFERING CONDUCTIVITY TYPE - A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions. | 2014-11-20 |
20140339649 | FINFET TYPE DEVICE USING LDMOS - The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate. | 2014-11-20 |
20140339650 | TRANSISTORS HAVING FEATURES WHICH PRECLUDE STRAIGHT-LINE LATERAL CONDUCTIVE PATHS FROM A CHANNEL REQION TO A SOURCE/DRAIN REQION - Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations. | 2014-11-20 |
20140339651 | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness. | 2014-11-20 |
20140339652 | SEMICONDUCTOR DEVICE WITH OXYGEN-CONTAINING METAL GATES - A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer. | 2014-11-20 |
20140339653 | SENSOR CHIP HAVING A MICRO INDUCTOR STRUCTURE - A sensor chip has a supporting structure layer and a micro-inductor layer formed on the supporting structure layer and having an inductance. The micro-inductor layer comprises an insulating layer, at least one magnetic layer, and a micro-coil layer. When an external physical quantity is applied on sensor chip, the micro-inductor layer can deform correspondingly to generate a variation of the inductance. The variation of the inductance can be measured by an inductance measurement circuit. The inductance measurement circuit can be an external circuit or be integrated into the sensor chip. | 2014-11-20 |
20140339654 | MICROPATTERNED COMPONENT AND METHOD FOR MANUFACTURING A MICROPATTERNED COMPONENT - A micropatterned component, for measuring accelerations and/or yaw rates, including a substrate having a principal plane of extension of the substrate, an electrode, and a further electrode; the electrode having a principal plane of extension of the electrode, and the further electrode having a principal plane of extension of the further electrode; the principal plane of extension of the electrode being set parallelly to a normal direction perpendicular to the principal plane of extension of the substrate; the principal plane of extension of the further electrode being set parallelly to the normal direction; the electrode having an electrode height extending in the normal direction; the electrode having a flow channel extending completely through the electrode in a direction parallel to the principal plane of extension of the substrate; the flow channel having a channel depth extending parallelly to the normal direction; the channel depth being less than the electrode height. | 2014-11-20 |
20140339655 | MEMS PACKAGE STRUCTURE - A MEMS package structure, including a substrate, an interconnecting structure, an upper metallic layer, a deposition element and a packaging element is provided. The interconnecting structure is disposed on the substrate. The MEMS structure is disposed on the substrate and within a first cavity. The upper metallic layer is disposed above the MEMS structure and the interconnecting structure, so as to form a second cavity located between the upper metallic layer and the interconnecting structure and communicates with the first cavity. The upper metallic layer has at least a first opening located above the interconnecting structure and at least a second opening located above the MEMS structure. Area of the first opening is greater than that of the second opening. The deposition element is disposed above the upper metallic layer to seal the second opening. The packaging element is disposed above the upper metallic layer to seal the first opening. | 2014-11-20 |
20140339656 | MEMS PRESSURE TRANSDUCER ASSEMBLY - An assembly ( | 2014-11-20 |
20140339657 | PIEZOELECTRIC MEMS MICROPHONE - A piezoelectric MEMS microphone comprising a multi-layer sensor that includes at least one piezoelectric layer between two electrode layers, with the sensor being dimensioned such that it provides a near maximized ratio of output energy to sensor area, as determined by an optimization parameter that accounts for input pressure, bandwidth, and characteristics of the piezoelectric and electrode materials. The sensor can be formed from single or stacked cantilevered beams separated from each other by a small gap, or can be a stress-relieved diaphragm that is formed by deposition onto a silicon substrate, with the diaphragm then being stress relieved by substantial detachment of the diaphragm from the substrate, and then followed by reattachment of the now stress relieved diaphragm. | 2014-11-20 |
20140339658 | DEVICE COMPRISING A SPRING AND AN ELEMENT SUSPENDED THEREON, AND METHOD FOR MANUFACTURING SAME - The invention relates to an MEMS structure with a stack made of different layers and a spring-and-mass system varying in its thickness which is formed of the stack, and wherein, starting from a back side of the stack and the substrate, at laterally different positions, the substrate while leaving the first semiconductor layer, or the substrate, the first etch-stop layer and the first semiconductor layer are removed, and to a method for manufacturing such a structure. | 2014-11-20 |
20140339659 | Method of Manufacturing A Semiconductor Integrated Circuit Device Having A MEMS Element - In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer. | 2014-11-20 |
20140339660 | MAGNETORESISTIVE ELEMENT AND MEMORY DEVICE INCLUDING THE SAME - Provided are magnetoresistive elements, memory devices including the same, and an operation methods thereof. A magnetoresistive element may include a free layer, and the free layer may include a plurality of regions (layers) having different properties. The free layer may include a plurality of regions (layers) having different Curie temperatures. The Curie temperature of the free layer may change regionally or gradually away from the pinned layer. The free layer may include a first region having ferromagnetic characteristics at a first temperature and a second region having paramagnetic characteristics at the first temperature. The first region and the second region both may have ferromagnetic characteristics at a second temperature lower than the first temperature. The effective thickness of the free layer may change with temperature. | 2014-11-20 |
20140339661 | METHOD TO MAKE MRAM USING OXYGEN ION IMPLANTATION - A method to make magnetic random access memory (MRAM), in particular, perpendicular spin transfer torque MRAM or p-STT-MRAM is provided. Electrically isolated memory cell is formed by ion implantation instead of etching and dielectric refill. Oxygen ion implantation is used to convert the photolithography exposed areas into metal oxide dielectric matrix. An ultra thin single-layer or multiple-layer of oxygen-getter, selected from Mg, Zr, Y, Th, Ti, Al, Ba is inserted into the active magnetic memory layer in addition to putting a thicker such material above and below the memory layer to effectively capture the impinged oxygen ions. Oxygen is further confined within the core device layer by adding oxygen stopping layer below the bottom oxygen-getter. After a high temperature anneal, a uniformly distributed and electrically insulated metal oxide dielectric is formed across the middle device layer outside the photolithography protected device area, thus forming MRAM cell without any physical deformation and damage at the device boundary. | 2014-11-20 |
20140339662 | OPTICAL COMMUNICATION DEVICE - An optical communication device includes a planar optical waveguide, a substrate and an optical-electric element. The planar optical waveguide includes a first side surface and a light guide portion formed in the planar optical waveguide. The substrate includes a first sidewall and a second sidewall facing away from the first sidewall. The first sidewall is substantially parallel with the second sidewall. The substrate defines a light guide hole running through both the first sidewall and the second sidewall. The first sidewall is connected to the first side surface, with the light guide hole aligning with the light guide portion. The optical-electric element includes an optical surface. The optical-electric element is assembled to the second sidewall, with the optical surface aligning with the light guide hole and the light guide portion. | 2014-11-20 |
20140339663 | Sensor Arrangement with a Silicon-Based Optical Sensor and a Substrate for Functional Layer Systems - A sensor arrangement with a silicon-based optical sensor, particularly color sensors for colorimetric applications is disclosed. The invention aims to find a novel possibility for suppressing interference ripples occurring in optical sensors when adding substrates with optically functional coatings which permits a simple production without complicated adaptation layers. The sensor passivation is composed of a combination of thin SiO | 2014-11-20 |
20140339664 | Optical Devices and Opto-electronic Modules and Methods for Manufacturing The Same - The optical device comprises a first substrate (SI) comprising at least one optical structure ( | 2014-11-20 |
20140339665 | IMAGE SENSOR - An image sensor having a plurality of photoelectric conversion elements that receive light and convert the light to electric charges, color filter layers having different spectral characteristics, each being provided corresponding to each of the photoelectric conversion elements, and a partition wall having a lower refractive index than that of the color filter layers provided at the boundary of each color filter layer. The image sensor is formed such that a space of the partition wall on the light exit side is narrower than a space of the partition wall on the light incident side. | 2014-11-20 |
20140339666 | POLARIZED LIGHT DETECTING DEVICE AND FABRICATION METHODS OF THE SAME - Described herein is a device operable to detect polarized light comprising: a substrate; a first subpixel; a second subpixel adjacent to the first subpixel; a first plurality of features in the first subpixel and a second plurality of features in the second subpixel, wherein the first plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a first direction parallel to the substrate and the second plurality of features extend essentially perpendicularly from the substrate and extend essentially in parallel in a second direction parallel to the substrate; wherein the first direction and the second direction are different; the first plurality of features and the second plurality of features react differently to the polarized light. | 2014-11-20 |
20140339667 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer. | 2014-11-20 |
20140339668 | IMAGING UNIT AND IMAGING APPARATUS - An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. | 2014-11-20 |
20140339669 | Semiconductor Device with a Field Plate Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as a power MOSFET, and methods for fabricating same. The device includes a field plate trench. The device further includes first and second trench dielectrics inside the field plate trench. The device also includes a field plate situated over the first trench dielectric and within the second trench dielectric. A combined thickness of the first and second trench dielectrics at a bottom of the field plate trench is greater than a sidewall thickness of the second trench dielectric. | 2014-11-20 |
20140339670 | Semiconductor Device with a Thick Bottom Field Plate Trench Having a Single Dielectric and Angled Sidewalls - Disclosed is a power device, such as a power MOSFET device and a method for fabricating same. The device includes a field plate trench. The field plate trench has a predetermined width and a predetermined sidewall angle. The device further includes a single trench dielectric on sidewalls of the field plate trench and at a bottom of the field plate trench. The single trench dielectric has a bottom thickness that is greater than a sidewall thickness. The device also includes a field plate situated within the single trench dielectric. | 2014-11-20 |
20140339671 | METHOD TO FORM STEPPED DIELECTRIC FOR FIELD PLATE FORMATION - A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate. | 2014-11-20 |
20140339672 | WAFER DIE SEPARATION - A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet. | 2014-11-20 |
20140339673 | WAFER PROCESSING - A method of separating dies of a singulated wafer is disclosed. The method may include supporting the singulated wafer on a supporting portion of a sheet of dicing tape that has a first ring attached to a first annular portion of the sheet that encompasses the supporting portion. The method may further include radially expanding the supporting portion by relative axial displacement of the supporting portion with respect to the first ring. The method may also include further expanding the supporting portion by radially outward displacement of a support surface that supports at least an annular portion of the sheet. The method may also include attaching a second ring to a second annular portion of the sheet. | 2014-11-20 |
20140339674 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a lower wiring on the substrate; an inter-layer insulating film covering the lower wiring; first and second upper wirings on the inter-layer insulating film and separated from each other; and a semi-insulating protective film covering the first and second upper wirings, wherein the protective film is not provided in a region right above the lower wiring and between the first upper wiring and the second upper wiring. | 2014-11-20 |
20140339675 | POLYSILICON FUSE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE INCLUDING POLYSILICON FUSE - A polysilicon fuse is disclosed that is capable of securing good insulation after being cut into small areas. A manufacturing method for the fuse and a small-size and highly-reliable semiconductor device including a polysilicon fuse also are disclosed. By forming a cavity inside a polysilicon portion serving as a melting portion by setting the melting portion of the polysilicon fuse to be a vertical type, a gap is formed between an upper part electrode and the surface of melted polysilicon when the polysilicon fuse is cut off. Because of this gap, good insulation can be secured. By using this polysilicon fuse, a semiconductor device that has a small size and high reliability is provided. | 2014-11-20 |
20140339676 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material. | 2014-11-20 |
20140339677 | HYBRID PLASMA-SEMICONDUCTOR TRANSISTORS, LOGIC DEVICES AND ARRAYS - A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction. An insulator layer is upon one side the base layer and emitter region. Base and emitter electrodes are isolated from each other by the insulator layer and electrically contact the base layer and emitter region through the insulator layer. A thin and flexible collector layer is upon an opposite side of the base layer. A microcavity is formed in the collector layer and is aligned with the emitter region. Collector electrodes are arranged to sustain a microplasma within the microcavity with application of voltage to the collector electrodes. A depth of the emitter region and a thickness of the base layer are set to define a predetermined thin portion of the base layer as a base region between the emitter region and the microcavity. Microplasma generated in the microcavity serves as a collector. Logic devices are provided in multiple sub collector and sub emitter microplasma devices formed in thin and flexible or not flexible semiconductor materials. | 2014-11-20 |
20140339678 | Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing - An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·10 | 2014-11-20 |
20140339679 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of Al or Ga are repeatedly deposited a plurality of times on an initial layer of Al | 2014-11-20 |
20140339680 | III-V Device and Method for Manufacturing Thereof - The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor. | 2014-11-20 |
20140339681 | METHOD FOR FABRICATING A COMPOSITE STRUCTURE TO BE SEPARATED BY EXFOLIATION - The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing:
| 2014-11-20 |
20140339682 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of −5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device. | 2014-11-20 |
20140339683 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 2014-11-20 |
20140339684 | SYNTHETIC DIAMOND COATED COMPOUND SEMICONDUCTOR SUBSTRATES - A method of fabricating a synthetic diamond coated compound semiconductor substrate, the method comprising: loading a composite substrate into a chemical vapour deposition (CVD) reactor, the composite substrate comprising a single crystal carrier wafer, a layer of single crystal compound semiconductor epitaxially grown on the carrier wafer, and an interface layer disposed on the layer of compound semiconductor, the interface layer forming a growth surface suitable for growth of synthetic diamond material thereon via a CVD technique; and growing a layer of CVD diamond material on the growth surface of the interface layer, wherein during growth of CVD diamond material a temperature difference at the growth surface between an edge and a centre point thereof is maintained to be no more than 80° C., and wherein the carrier wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100. | 2014-11-20 |
20140339685 | GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A glass composition for protecting a semiconductor junction contains at least SiO | 2014-11-20 |
20140339686 | Group III-V Device with a Selectively Modified Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 2014-11-20 |
20140339687 | POWER PLANE FOR MULTI-LAYERED SUBSTRATE - A semiconductor device includes a ground plane and a power plane that lie in spaced, parallel planes. The power plane includes a number of openings formed around its outer edge. A ground ring surrounds the power plane and has fingers that extend towards and are received within corresponding ones of the openings of the power plane. The ground ring is electrically connected to the ground plane with vias. | 2014-11-20 |
20140339688 | TECHNIQUES FOR THE CANCELLATION OF CHIP SCALE PACKAGING PARASITIC LOSSES - The present invention generally relates to techniques and structures that cancel or mitigate RF coupling from the RF circuit to the silicon die. To cancel or mitigate the RF coupling, a conductive coating may be formed over the RF-MEMS device. The conductive coating may be coupled to the die. Alternatively, the conductive coating may be coupled to the die through the RF-MEMS by having a through silicon via. Another manner for cancelling or mitigating RF coupling is to have no conductive traces located on the front side of the PCB. | 2014-11-20 |