47th week of 2008 patent applcation highlights part 64 |
Patent application number | Title | Published |
20080288750 | Small barrier with local spinning - A barrier with local spinning. The barrier is described as a barrier object having a bit vector embedded as a pointer. If the vector bit is zero, the object functions as a counter; if the vector bit is one, the object operates as a pointer to a stack. The object includes the total number of threads required to rendezvous at the barrier to trigger release of the threads. The object points to a stack block list that describes each thread that has arrived at the barrier. Arriving at the barrier involves reading the top stack block, pushing onto the list a stack block for the thread that just arrived, decrementing the thread count, and spinning on corresponding local memory locations or timing out and blocking. When the last thread arrives at the barrier, the barrier is reset and all threads at the barrier are awakened for the start of the next process. | 2008-11-20 |
20080288751 | TECHNIQUE FOR PREFETCHING DATA BASED ON A STRIDE PATTERN - A processor system ( | 2008-11-20 |
20080288752 | DESIGN STRUCTURE FOR FORWARDING STORE DATA TO LOADS IN A PIPELINED PROCESSOR - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis. | 2008-11-20 |
20080288753 | Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call - An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction. | 2008-11-20 |
20080288754 | GENERATING STOP INDICATORS DURING VECTOR PROCESSING - A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more stop indicators corresponding to any detected conflict between the memory addresses, where a given stop indicator indicates a memory hazard. Next, the processor executes the instructions for detecting the conflict between the memory addresses and generating the one or more stop indicators. | 2008-11-20 |
20080288755 | CLOCK DRIVEN DYNAMIC DATAPATH CHAINING - A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations. | 2008-11-20 |
20080288756 | "OR" BIT MATRIX MULTIPLY VECTOR INSTRUCTION - A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system. | 2008-11-20 |
20080288757 | Communicating Instructions and Data Between a Processor and External Devices - A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 2008-11-20 |
20080288758 | Method and Device for Switching Over in a Computer System Having at Least Two Execution Units - A method and device for switching over in a computer system having at least two execution units, switching being carried out between at least two operating modes, and the operating modes corresponding to states of the computer system, a first state corresponding to a comparison mode and a second state corresponding to a performance mode, so that events may occur by which the computer system can attain an otherwise undefined state, in which, in response to the occurrence of any such event, the second state is assumed, which corresponds to a performance mode. | 2008-11-20 |
20080288759 | Memory-hazard detection and avoidance instructions for vector processing - A processor that is configured to perform parallel operations in a computer system where one or more memory hazards may be present is described. An instruction fetch unit within the processor is configured to fetch instructions for detecting one or more critical memory hazards between memory addresses if memory operations are performed in parallel on multiple addresses corresponding to at least a partial vector of addresses. Note that critical memory hazards include memory hazards that lead to different results when the memory addresses are processed in parallel than when the memory addresses are processed sequentially. Furthermore, an execution unit within the processor is configured to execute the instructions for detecting the one or more critical memory hazards. | 2008-11-20 |
20080288760 | BRANCH TARGET PREDICTION FOR MULTI-TARGET BRANCHES BY IDENTIFYING A REPEATED PATTERN - An information processing system for branch target prediction includes: a first memory for storing entries for multi-target branch, wherein each entry includes a plurality of target addresses representing a history of target addresses for each single branch in the multi-target branch, and wherein said first memory stores an entry for the branch only if the branch is a multi-target branch; hardware logic for reading the memory and identifying a repeated pattern in each of the plurality of target addresses for the multi-target branch; logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified, using a pattern matching algorithm; and a second memory for storing information regarding whether a branch is a multi-target branch; wherein the logic for reading and the logic for predicting are executed only if the branch is the multi-target branch. | 2008-11-20 |
20080288761 | METHOD AND SYSTEM FOR EFFICIENT TENTATIVE TRACING OF SOFTWARE IN MULTIPROCESSORS - A method of tentative tracing execution events in a multiprocessor system. Each processor stores tentative events in a corresponding buffer. The processor sets pointers in an array to a head and tail of a thread. When a condition triggers a tentative thread to be committed, the processor marks the first event as committed and sets the pointers to a null value. When a condition triggers the thread to be discarded, the processor marks the first event as discarded and sets the pointers to a null value. The processor makes the buffer available to a consumer process, which extracts the first event. If the first event is marked as committed, the consumer process follows a link to a second event of the thread and marks the second event as committed. If the first event is marked as discarded, the second event is marked as discarded and the first event is skipped. | 2008-11-20 |
20080288762 | Firmware Interface Runtime Environment Protection Field - Method and apparatus for protecting a firmware runtime environment are described herein. In one embodiment, a process example is provided to retrieve a first key from a secure store of a firmware within a platform, the firmware including an initialization table for initializing the platform, and verify the initialization table using the first key retrieved from the secure store during an initialization of the platform. Other methods and apparatuses are also described. | 2008-11-20 |
20080288763 | Method For Controlling the Operation of a Display Screen In A Computing Device - In a computing device such as a mobile phone which includes a splash-screen displayed while the operating system is booting up, the portion of the operating system which is responsible for the display after booting up is provided with all the information about the state of the splashscreen, so that a smooth transition is provided between the splashscreen and the initial screen under the control of the operating system when control of the screen is passed from the boot-up process to the operating system. | 2008-11-20 |
20080288764 | BOOT-SWITCHING APPARATUS AND METHOD FOR MULTIPROCESSOR AND MULTI-MEMORY SYSTEM - A boot-switching apparatus suitable for a system having a plurality of processors and a plurality of memories and a method thereof are provided. While booting the system, a single timer is used for counting down a time-out and it is determined whether a disabling signal sent by a Basic Input/Output System (BIOS) is received during the countdown. If the disabling signal is not received and the time-out is up, whether the processors operate normally is further detected and a plurality of detection signals is obtained. Next, whether each of the detection signals matches its corresponding enabling signal is determined. If the two do not match, the corresponding processor is disabled. If all of them match, the memories are switched. Accordingly, the problem of misjudgment in the prior art can be resolved and the system can be led to select normal processor and memory for executing its booting. | 2008-11-20 |
20080288765 | Computer system capable of reducing booting time and method thereof - The present invention discloses a method for reducing booting time of a computer system, and the method is applied in a computer booting process. If a computer receives an easy booting signal, the computer will read an easy booting data built in a basic input output system (BIOS) of the computer, start an operating system (OS) of the computer and enable at least one terminate-and-stay-resident (TSR) program of the operating system, such that the whole booting process can be completed quickly without wasting unnecessary time on self-testing all hardware devices for the booting process or loading all terminate-and-stay-resident programs. | 2008-11-20 |
20080288766 | INFORMATION PROCESSING APPARATUS AND METHOD FOR ABORTTING LEGACY EMULATION PROCESS - An information processing apparatus includes: a non-volatile memory that stores a BIOS program that performs legacy emulation process for enabling a device not supported by an operating system to be accessed from the operating system; a controller that controls the device; a boot process unit that performs a boot sequence for booting the operating system stored in the device by controlling the controller through the legacy emulation process of the BIOS program; and a legacy emulation process control unit that performs a stop control process including: monitoring write access by software to a predetermined register, in which a value for designating an operation environment for controlling the device to the controller is set; and aborting execution of the legacy emulation process by the BIOS program when the write access is detected. | 2008-11-20 |
20080288767 | Computer system - The invention provides a computer system, which includes a motherboard, a nonvolatile memory and a chipset provided on the motherboard. The nonvolatile memory stores a first BIOS and a second BIOS. The chipset has an external flag having a first state and a second state corresponding to the first BIOS and second BIOS, respectively. When the external flag is in the first state, the motherboard is booted by the first BIOS. When the external flag is in the second state, the motherboard is booted by the second BIOS. When one BIOS is booted according to the state of the external flag, if the BIOS is damaged, the other complete BIOS is booted and is used to update the damaged BIOS program. | 2008-11-20 |
20080288768 | Arrangement and method for reprogramming control devices - In an arrangement for reprogramming at least two control devices connected to one another via a data bus, each of the at least two control devices includes a reprogramming module for effecting reprogramming of the each of the at least two control devices with new program data according to a first reprogramming protocol. A conversion module connected to the data bus receives the new program data using a second reprogramming protocol, and transmits the new program data onto the data bus using the first reprogramming protocol. | 2008-11-20 |
20080288769 | METHOD FOR ADJUSTING SET-UP DEFAULT VALUE OF BIOS AND MAINBOARD USING THE SAME METHOD - A method for adjusting a set-up default value of a BIOS and a mainboard using the method are provided. The adjusting method used by the mainboard includes providing an original set-up default value and an adjusting table. The original set-up default value is adjusted according to the adjusting table, so as to obtain a customized set-up value, and to store the set-up value in a set-up value memory. | 2008-11-20 |
20080288770 | SYSTEM AND METHOD FOR A COMMERCIAL MULTIMEDIA RENTAL AND DISTRIBUTION SYSTEM - A system and method for securing intellectual property rights in distributed intellectual property. Rights are granted and policed in electronically distributed intellectual property. Use limitations are established by agreement by the content provider and the client. The use limitations are reflected in time-based, usage-based and player based component codes that are used to determine if the client is entitled to use the intellectual property. Intellectual property is protected from unauthorized use by encrypting the intellectual property with a key created from some or all of the component codes. As the component codes are known to both the client and the content provider, no key exchange is required. | 2008-11-20 |
20080288771 | SYSTEM AND METHOD FOR DEFINING PROGRAMMABLE PROCESSING STEPS APPLIED WHEN PROTECTING THE DATA - Systems and methods for protecting data being sent between a client and a server include the capability of defining programmable processing steps that are applied by the server when protecting the data and the same steps are applied by the client when unprotecting the data. The programmable processing steps can be defined uniquely for each client, and the programmable processing steps are selected from a number of functions using sequencing data that defines the processing steps. The programmable processing steps allow for each client to process encrypted data in a different manner and the programmable processing steps are defined by what is called a digital rights management (DRM) Sequencing Key, and as such the system and method introduces a key-able DRM whereby each DRM message can be processed in a unique (or pseudo unique) manner. | 2008-11-20 |
20080288772 | SYSTEM FOR STORING ENCRYPTED DATA BY SUB-ADDRESS - A system and method for storing encrypted electronic data using a transmission Control Protocol (TCP), requires leaving both the header and the first 48 bytes of the “0” data packet in the data area of the TCP format in clear text. Consequently, the data can be routed to a main address (storage facility), and then to a sub-address (storage device) for storage. A single compression/encryption operation can be accomplished, before storage, at the host (server), the network switch, or the final storage device. | 2008-11-20 |
20080288773 | SYSTEM AND METHOD FOR AUTHENTICATION OF A COMMUNICATION DEVICE - A system and method for authentication of a communication device is disclosed. A system that incorporates teachings of the present disclosure may include, for example, a communication device having a controller element to compute a shared secret key based at least in part on a communication device (CD) private key and a cryptography algorithm, wherein the CD private key is stored in an identity module of the communication device and is unknown to an authentication center, and wherein the communication device is authenticated by the authentication center based at least in part on the shared secret key. Additional embodiments are disclosed. | 2008-11-20 |
20080288774 | Contact Information Retrieval System and Communication System Using the Same - There is described a communication system allowing communication over one or more communication networks. The communication system includes a domain name server storing a zone data file for a domain associated with a first party, the zone data file including contact information associated with the first party, the contact information including a plurality of electronic communication identifiers associated with the first party with each electronic communication identifier being associated with a corresponding communication protocol. An access granting system enables the first party to grant a second party access to one or more of the plurality of electronic communication identifiers. In particular, the access granting system encrypts one or more electronic communication identifiers to generate encrypted contact information, stores the encrypted contact information in the zone data file in association with a sub-domain of the domain associated with the first party, and provides the second party with access to the identity of said sub-domain. | 2008-11-20 |
20080288775 | EMBEDDED HISTORIANS WITH DATA AGGREGATOR - Systems and methods that aggregate history data collected via embedded historians with additional data that is supplied by third parties. Triggering events can be defined for initiating aggregation of such history data with additional data, which enable a process/application to retrieve the operational metric data of the industrial unit/entity from any of a plurality of systems operatively coupled to such industrial unit/entity. | 2008-11-20 |
20080288776 | Security method using virtual keyboard - The present invention relates to a security method using a virtual keyboard, and more specifically, to a security method using a virtual keyboard, in which a user may input information through the virtual keyboard using a mouse when the user logs into a web server by inputting an identification (ID) and a password, and the inputted password is transmitted to the web server after being encrypted, so that personal information is prevented from being leaked by a hacking program and a safe connection is established. According to the present invention, risk of personal information leakage that can be occurred when an ID and a password are inputted through a keyboard may be greatly reduced, and it is effective in that even when a symmetric key is leaked, which is least expected, decipher of data is prevented by maintaining security of a private key. | 2008-11-20 |
20080288777 | A Peer-to-Peer Access Control Method Based on Ports - A port based peer access control method, comprises the steps of: 1) enabling the authentication control entity; 2) two authentication control entities authenticating each other; 3) setting the status of the controlled port. The method may further comprise the steps of enabling the authentication server entity, two authentication subsystems negotiating the key. By modifying the asymmetry of background technique, the invention has advantages of peer control, distinguishable authentication control entity, good scalability, good security, simple key negotiation process, relatively complete system, high flexibility, thus the invention can satisfy the requirements of central management as well as resolve the technical issues of the prior network access control method, including complex process, poor security, poor scalability, so it provides essential guarantee for secure network access. | 2008-11-20 |
20080288778 | Method for Generating and Verifying an Electronic Signature - The present invention provides a secure, efficient, simple and operator-independent method for generating an electronic signature, for execution by a processing unit in a mobile terminal. The method comprises the steps of receiving an electronic message, fetching a basic key from a memory area, inputting a credential from a user, generating a dynamic key based on the basic key and the credential, and generating an electronic signature for the message using the dynamic key. The invention further comprises a corresponding method for verifying the electronic signature, for execution by a verification server. | 2008-11-20 |
20080288779 | Generating and verifying trusted digital time stamp - Methods, apparatus and systems for generating a trusted digital time stamp as well as a public time source. It includes, an apparatus for receiving and recording public time information and a method for verifying a digital time stamp. A method for generating a trusted digital time stamp includes: obtaining a first time information and a corresponding random code from a public time source; and generating a digital time stamp using a first time information and random code. A method for verifying a digital time stamp includes: recording time information and corresponding random codes transmitted by a public time source; retrieving time information and a random code contained in the time stamp; and comparing a retrieved random code from the time stamp with one of the recorded random codes that corresponds to a time information in the time stamp, if they are consistent, the time stamp is determined to be trusted, otherwise the time stamp is determined to be not trusted. | 2008-11-20 |
20080288780 | LOW-LATENCY DATA DECRYPTION INTERFACE - Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations. | 2008-11-20 |
20080288781 | SYSTEMS AND METHODS FOR SECURE PASSWORD CHANGE - Systems and methods for changing a user password are described. In one embodiment, the method includes determining at least one password equivalent value, determining a safe-to-transmit password value, determining a password change authentication value, transmitting, from a remote device to a controller, the password change authentication value and the safe-to-transmit password value, confirming the data integrity of the password change authentication value sent from the remote device to the controller, and storing a new password equivalent value. | 2008-11-20 |
20080288782 | Method and Apparatus of Providing Security to an External Attachment Device - Systems and methods of providing security to an external Serial Advanced Technology Attachment (SATA) device are described herein. One embodiment includes presenting to a computing device, a first partition of an external Serial Advanced Technology Attachment storage device, as a Read Only Memory; restricting the computing device from accessing a secured second partition of the external Serial Advanced Technology Attachment storage device; and in response to receiving a valid identity authentication, unrestricting access to the second partition of the external Serial Advanced Technology Attachment storage device. In one embodiment, in response to receiving a logon request from the computing device, an identity authentication process is initiated, wherein the process is stored on the first partition. Furthermore, in one embodiment, a process stored on a disk controller receives an encryption key from the process stored on the first partition of the Serial Advanced Technology Attachment storage device, and the process stored on the disk controller uses the encryption key to decrypt the second partition of the Serial Advanced Technology Attachment storage device. | 2008-11-20 |
20080288783 | METHOD AND SYSTEM TO AUTHENTICATE AN APPLICATION IN A COMPUTING PLATFORM OPERATING IN TRUSTED COMPUTING GROUP (TCG) DOMAIN - A method and system for verifying authenticity of an application in a computing-platform operating in a Trusted Computing Group (TCG) domain is provided. The method includes computing one or more integrity measurements corresponding to one or more of the application, a plurality of precedent-applications, and an output file. The output file includes an output of the application, the application is executing on the computing-platform. Each precedent-application is executed before the application. The method further includes comparing one or more integrity measurements with re-computed integrity measurements. The re-computed integrity measurements are determined corresponding to one or more of the application, the plurality of precedent-applications, and the computing-platform. | 2008-11-20 |
20080288784 | METHOD OF INSTALLING SOFTWARE FOR USING DIGITAL CONTENT AND APPARATUS FOR PLAYING DIGITAL CONTENT - A method of and apparatus for installing software for using digital content and are provided. The method of installing software for using digital content includes: transmitting a request for the software; transmitting security information indicating a security status of a device in which the software is to be installed; and receiving the software from an external apparatus that received the request and security information. According to the method and apparatus, the software can be dynamically securely installed, thereby allowing a variety of digital contents to be used and enhancing the utilization of the device. | 2008-11-20 |
20080288785 | Data Security and Digital Rights Management System - A system and method is described for enhancing data security in a broad range of electronic systems through encryption and decryption of addresses in physical memory to which data is written and from which data is read. It can be implemented through software, hardware, firmware or any combination thereof. Implementation in Digital Rights Management execution using the invention reduces cost, enhances performance, and provides additional transactional security. | 2008-11-20 |
20080288786 | System with access keys - In an embodiment, a secure module is provided that provides access keys to an unsecured system. In an embodiment, the secure module may generate passcodes and supply the passcodes to the unsecured system. In an embodiment, the access keys are sent to the unsecured system after the receiving the passcode from the unsecured system. In an embodiment, after authenticating the passcode, the secure module does not store the passcode in its memory. In an embodiment, the unsecured module requires the access key to execute a set of instructions or another entity. In an embodiment, the unsecured system does not store access keys. In an embodiment, the unsecured system erases the access key once the unsecured system no longer requires the access key. In an embodiment, the unsecured system receives a new passcode to replace the stored passcode after using the stored passcode. Each of these embodiments may be used separately. | 2008-11-20 |
20080288787 | Export control for a GNSS receiver - Embodiments of the present invention recite a method and system for implementing export control for a Global Navigation Satellite System (GNSS) receiver. In one embodiment, a GNSS receiver is used to determine the geographic position of an electronic device. It is then determined that the geographic region corresponds to an exclusion zone. In response to determining that the geographic region corresponds to the exclusion zone, accessing data from the electronic device is prevented. | 2008-11-20 |
20080288788 | Digital Rights Management Metafile, Management Protocol and Applications Thereof - Methods, systems and computer program products to create and manage encapsulated Digital Rights Management (DRM) metafiles, also referred to as objects, are provided herein. Each object comprises a file header section, an encrypted webpage metadata section, an encrypted preferences section, an encrypted tracking section, an encrypted license section, a media file section and an encrypted file trailer section. Each section comprises multiple attributes. A metabase is provided herein to catalog objects, sections and attributes. Instructions are provided herein to allow for setting a current object, section or attribute; retrieving an object, section or attribute; and enumerating objects, sections and attributes in a device memory. | 2008-11-20 |
20080288789 | Reducing information leakage between processes sharing a cache - A method of impeding leakage of cache access behavioural information of a section of a sensitive process to an untrusted process, said sensitive and untrusted processes being performed by a processor within a data processing apparatus, said data processing apparatus further comprising at least one cache operable to store information required by said processor while performing said sensitive and untrusted processes, the method comprising the steps of: prior to commencing processing of a section of said sensitive process by said processor, evicting information stored in locations of said at least one cache which may otherwise be evicted by said sensitive process loading information that may be required by said section of said sensitive process in said at least one cache; commencing processing of said section of said sensitive process by said processor; switching said processor during processing of said section of said sensitive process to said untrusted process in response to a switching request; on switching back to said section of said sensitive process from said untrusted process, evicting information stored in locations of said at least one cache which may otherwise be evicted by said sensitive process loading information that may be required by said section of said sensitive process in said at least one cache prior to recommencing processing of said section of said sensitive process. | 2008-11-20 |
20080288790 | Means and Method of Using Cryptographic Device to Combat Online Institution Identity Theft - Whereas smartcards and similar cryptographic devices may customarily be used to protect against personal identity theft, this invention stores Public Keys of an institution in cryptographic devices issued by the institution to its customers, in order to protect the institution's identity from being stolen. The invention improves the security of electronic business applications using Secure Sockets Layer, Secure E-mail, Object Signing and similar low level electronic business security functions by storing various Public Keys of the institution within the cryptographic device. The invention thereby helps to reduce the likelihood of “ghosting” an institution's web site (where an illegitimate web site seeks to mimic a genuine web site in order to defraud customers), and provides a means to overcome the problem of “phishing” (where illegitimate e-mails purporting to be from the institution are sent to customers in order to elicit personal information). | 2008-11-20 |
20080288791 | Computer Power Measurement Device - The present invention provides a computer power measurement device, which comprises: a first inductor connected power supply, and the first inductor is provided with a first DC equivalent resistance; a second inductor connected power consumption components, and the second inductor is provided with a second DC equivalent resistance; an input measurement module, which is connected to the first inductor, and measures the input power based on the first DC equivalent resistance; and, an output measurement module, which is connected to the second inductor, and measures the output power based on the second DC equivalent resistance. | 2008-11-20 |
20080288792 | METHOD AND APPARATUS OF ADAPTIVE INTEGRATION ACTIVITY MANAGEMENT FOR BUSINESS APPLICATION INTEGRATION - An adaptive integration activity management framework for on demand business process integration provides a mechanism to enable easy integration of legacy and new applications. The framework minimizes the effort need to integrate a new application into an existing business process environment such that the new activity is a “plug-in” into an action manager by implementing a standard adaptation layer. Activity integration is implemented in the principle of “on-demand” because it is invoked as required, so the communication and collaboration between partners become much more flexible. | 2008-11-20 |
20080288793 | Laptop Computer Recharging Using Ethernet Connection - One embodiment disclosed relates to a laptop computer system including a display casing, having display circuitry and a display screen, and a main computer casing coupled to the display casing. The main computer casing includes a battery power source, a charging regulator, and an Ethernet-type connector. The battery power source is coupled to a motherboard switching regulator. The charging regulator is coupled to the battery power source and configured to recharge the battery power source. The Ethernet-type connector coupled to the charging regulator and configured to provide power thereto. | 2008-11-20 |
20080288794 | METHOD AND SYSTEM FOR MANAGING POWER DELIVERY FOR POWER OVER ETHERNET SYSTEMS - A method for managing the delivery of power for a plurality of devices includes allocating a power limit for each of the plurality of devices and providing power to at least one of the plurality of devices. The method also includes, in response to the providing of power, measuring the amount of power utilized by each of at least one of the at least one of the plurality of devices and determining that the amount of power exceeds the power limit for the device. | 2008-11-20 |
20080288795 | METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION OF STORAGE SYSTEM SERVING AS TARGET DURING REMOTE COPYING EMPLOYING JOURNAL - A second storage system comprises a restore control unit for controlling restoration processing, in which a data element in a journal stored in a journal storage area is written into a secondary logical volume, and a storage device control unit for controlling a storage device in the second storage system. The restore control unit is provided with a function for suspending the restoration processing. A first value indicating the usage condition of the journal storage area in the second storage system is obtained, and the restore control unit suspends the restoration processing in accordance with the obtained first value. The storage device control unit then executes power saving on a storage device relating to the secondary logical volume. | 2008-11-20 |
20080288796 | MULTI-PROCESSOR CONTROL DEVICE AND METHOD - A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit. | 2008-11-20 |
20080288797 | Method and apparatus for power reduction on a processor bus - Power consumption of an address bus interface is reduced by reducing drive duration of address signals on the address bus. The address bus interface may operate in normal or power saving mode. In power saving mode, address signals are driven for a quarter of a clock period instead of half a clock period and address strobe edges are moved so that they are aligned with valid address signals. | 2008-11-20 |
20080288798 | Power management of low power link states - A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described. | 2008-11-20 |
20080288799 | DYNAMIC PROCESSOR POWER MANAGEMENT DEVICE AND METHOD THEREOF - A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power. | 2008-11-20 |
20080288800 | SEMICONDUCTOR DEVICE WITH A POWER DOWN MODE - includes a power down detecting block for generating a power down mode signal by detecting if the power down mode is activated, a power source control block for producing a power control signal whose ratio of an enable period to a disable period is determined by the power down mode signal, a current saving block whose driving current requirement is reduced in the power down mode, a power switching block for controlling the power supply to the current saving block in response to the power control signal, and a current non-saving block whose driving current requirement in the power down mode is identical to that in a normal operation mode. The semiconductor device can prevent the current consumption due to off-leakage components and static current components generated at internal analog circuits in the power down mode. | 2008-11-20 |
20080288801 | Information Processing Apparatus and Power Supply Control Method for Information Processing Apparatus - An information storage device ( | 2008-11-20 |
20080288802 | METHOD AND APPARATUS FOR OPERATING AN ELECTRONIC DEVICE IN A LOW POWER MODE - An electronic device, such as a hand-held portable computer, is provided with capability to operate an application during a low power mode. During the low power mode, portions of hardware, software, services, and/or other components of the portable computer that are not necessary to the operation of the application is suspended or otherwise deactivated. As each task is performed by the application, the components that are no longer needed for subsequent tasks to be performed by the application are also deactivated and reactivated as needed. The deactivation can be performed in sequence from the highest-level components to the lowest-level components to ensure that components that are needed by other components are not prematurely deactivated. A specific set of events transitions the portable computer out of the low power mode. | 2008-11-20 |
20080288803 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING ELECTRONIC DEVICE - An electronic device includes a power supply unit that generates plural output voltages from an input voltage and outputs the various output voltages from respective plural power supply channels, a voltage detecting unit that monitors voltages of two power supply channels among plural power supply channels which are different in decreases of the output voltage in the case that the input voltage is cut off, outputs a first detecting signal upon detecting a decrease in voltage of a first power supply channel having a fast decrease to a first threshold and outputs a second detecting signal upon detecting a decrease in voltage of a second power supply channel having a slow decrease to a second threshold, and a control unit that saves data upon receiving the first detecting signal and stops an operation of the electronic device upon receiving the second detecting signal. | 2008-11-20 |
20080288804 | Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test - An integrated circuit ( | 2008-11-20 |
20080288805 | SYNCHRONIZATION DEVICE AND METHODS THEREOF - A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced. | 2008-11-20 |
20080288806 | Clock generation circuit and semiconductor memory apparatus having the same - A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal. | 2008-11-20 |
20080288807 | SYSTEM, METHOD, AND COMPUTER PROGRAM FOR PRESENTING AND UTILIZING FOOTPRINT DATA AS A DIAGNOSTIC TOOL - A data processing system for storing and identifying footprint data in a data processing system enabling automated collection, identification and formatting recovery of footprint data executing on a mainline routine. A footprint area is allocated onto a failure recovery routine stack for use by the mainline routine for storing footprint data. The mainline routine stores footprint data within the first footprint area. The data processing system can then receive a request from a diagnostic tool, where the request includes at least one search parameter. The data processing system can output any footprint data to a diagnostic tool corresponding to the search parameters in the request. | 2008-11-20 |
20080288808 | DEBUGGING A PROCESSOR THROUGH A RESET EVENT - A method for operating a processor in data processing system comprises: asserting a debug control signal to cause the processor to enter a debug operating mode; initializing a plurality of shared processor resources with debug configuration information, wherein the plurality of shared processor resources are shared between a normal operating mode and the debug operating mode; executing instructions with the processor while in the debug operating mode; re-initializing the processor in response to a reset event; and preventing the reset event from re-initializing a predetermined portion of the debug configuration information in the plurality of shared processor resources. This allows processor debugging through reset events without losing the debug information. | 2008-11-20 |
20080288809 | MEMORY CONTROLLER FOR WRITING DATA INTO AND READING DATA FROM A MEMORY - According to an aspect of an embodiment, a memory controller for writing data into and reading data from a memory, comprises an error detector for detecting an error of data stored in the memory when reading the data, a time stamper for generating first time information indicative of the time when data is written into the memory, the first time information being written together with the data into an address location of the memory where the error has been detected, a timer for measuring a time period from the time indicated by the first time information until the time of subsequent occurrence of an error of data stored in said address location and a counter for counting a number of accesses to the address location over the time period. | 2008-11-20 |
20080288810 | METHOD AND SYSTEM FOR MANAGING RESOURCES DURING SYSTEM INITIALIZATION AND STARTUP - A method for managing a system's computer resources, includes: detecting an error condition in a computer resource; labeling the computer resource as not usable based on the error condition detected; reconfiguring the remaining computer resources to compensate for the detected error condition based on a failure mode policy; and wherein the failure mode policy manages the computer resources by one of: maximizing the amount of the remaining computer resources (mode 1), and maximizing the speed of the remaining computer resources (mode 2). | 2008-11-20 |
20080288811 | Multi-node replication systems, devices and methods - Replication techniques are presented. According to an embodiment of a method, a node of a replicated storage network is assigned to be an owner of a data block to issue write memory block commands. The network includes at least two nodes including the node assigned to be the owner. If a read memory block command is received to read the data block, a read_lock is issued for the data block, the data block is read, and the read_lock for the data block is released. If a write memory block command is received to write new data to the data block, a write_lock is issued for the data block, the data block is written and a version associated with the data block is incremented, and the write_lock for the data block is released. | 2008-11-20 |
20080288812 | CLUSTER SYSTEM AND AN ERROR RECOVERY METHOD THEREOF - A cluster system including: a transmission side server cluster consisting of a plurality of computers; a receiving side server cluster consisting of a plurality of computers; and a network that interconnects both the transmission side server cluster and the receiving side server cluster, wherein an active-transmission computer which is included in the transmission side server cluster selects a standby-transmission computer from the computers in the transmission side server cluster, based on load information, and transmits a backup-copy of a message to the standby-transmission computer when the active-transmission computer transmits the message to a computer in the receiving side server, the stand-by transmission computer for back-up handling of the message in the event of occurrence of a fault in the active-transmission computer. | 2008-11-20 |
20080288813 | Method for repairing a neighborhood of rows in a memory array using a patch table - A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N-1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N-1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N-1, N, and N+1. | 2008-11-20 |
20080288814 | APPARATUS FOR DETECTING AND RECOVERING FROM DATA DESTRUCTION CAUSED IN AN UNACCESSED MEMORY CELL BY READ, AND METHOD THEREFOR - Read disturb in a flash memory destroys data that is not requested to be read, and an efficient read disturb check method is therefore needed. In addition, data may be destroyed beyond repair by error correction before a read disturb check is run. Thus, this invention provides a non-volatile data storage apparatus including a plurality of memory cells and a memory controller, in which the memory controller is configured to: count how many times data read processing has been executed in memory cells within the management area; read, when the data read processing count that is counted for a first management area exceeds a first threshold, data and an error correction code that are stored in the memory cells within the first management area; decode the read error correction code; and write the data corrected by decoding the error correction code in other management areas than the first management area. | 2008-11-20 |
20080288815 | Firmware assisted error handling scheme - A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system. | 2008-11-20 |
20080288816 | System module and data relay method - A system module includes a plurality of processors, and a system controller that is connected to the processors via a first transmission line and relays a packet from each of the processors to another system module via a second transmission line in a multiprocessor system. The system controller includes a data transmission controller that, when part of packets constituting a series of data is not received normally from a processor due to a fault in the processor or the first transmission line, generates a supplement packet for a packet that has not been received normally and outputs the supplement packet to the second transmission line. | 2008-11-20 |
20080288817 | Gorbadey's Method for Ensuring the Reliable Operation of the Program Computing Means - The invention relates to the computer engineering, and its usage ensures the possibility to recognize in due time the failures being occurred during operation of the program computing means, and to response respectively for the failure of each type. The method is realized in a program computing means (PCM) comprising a processor operating under the control of a predetermined operating system and intended for processing data under the control of at least one program being executed; a core memory intended for storing said at least one program being executed and data being processed; time interval sequence generators. The technical result is achieved owing to performing steps of: defining in advance the states of the program being executed different from the start and end states thereof, hereinafter referred to as the restart points, for resuming the operation of the program being executed after a failure during execution thereof; in the case of failure occurrence, determining the following failures in the PCM operation: a) an error in storing the core memory content, determined by checking a respective part of the core memory content; b) a control transfer to a wrong command, determined by monitoring the correctness of every control transfer in the processor; and c) various time interruptions determined by monitoring a run duration of a respective part of the program being executed and predetermined operating system; while processing a respective interruption and upon occurrence of anyone of the failures being recognizable, in the case of allowable conditions for continuing the operation, restarting the execution of said program being executed beginning with the nearest restart point preceding to this interruption. | 2008-11-20 |
20080288818 | Method and System for Protecting Information between a Master Terminal and a Slave Terminal - In an application system of a liquid crystal display, for protecting transmissions between a master terminal and a slave terminal, effects caused by an unstable power source of the slave terminal have to be reduced to a lowest degree. When the application system is reset or under normal operations with the power source having a suddenly-decreased or suddenly-unstable voltage level, the transmission between the master terminal and the slave terminal have to be terminated, and related data of the terminated transmission is temporarily stored. When the voltage of the slave terminal is confirmed to reach to a stable voltage over a predetermined duration, the transmission may be restored by the stored data. | 2008-11-20 |
20080288819 | Computing System with Transactional Memory Using Millicode Assists - A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. Program millicode provides transactional memory functions including creating and updating transaction tables, committing transactions and controlling the rollback of transactions which fail. | 2008-11-20 |
20080288820 | MULTI-DIRECTIONAL FAULT DETECTION SYSTEM - An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection. | 2008-11-20 |
20080288821 | Automated Diagnosis for Electronic Systems - Systems for providing automated diagnosis of problems for an electronic network include a central diagnosis engine configured to include modules that rank identified policy/configuration changes into potential causes, verify the ranked potential causes and determine whether any of the ranked potential causes is a likely cause or contributor to the problem. An estimator module is configured to calculate distances associated with the ranked potential causes such that a list of potential causes of the problem can be presented in order of likelihood. Other systems and methods are also provided. | 2008-11-20 |
20080288822 | EXHAUSTIVE SECURITY FUZZING FOR TRANSACT STRUCTURED QUERY LANGUAGE - Systems and methods that incorporate fuzzing capabilities within an SQL server to facilitate penetration testing. A fuzzing component associated with the SQL server provides an entry point for accessing the fuzzing system to update explicit user specified parameters associated with SQL, wherein the server's in depth knowledge regarding semantics of the language code (e.g., manner of parsing) can be employed to determine vulnerabilities thereof. | 2008-11-20 |
20080288823 | JTAG Interface - Implementations are presented herein that relate to improved Joint Test Action Group (JTAG) compatible devices. | 2008-11-20 |
20080288824 | POWER-ON SELF TEST PROGRAM MANAGEMENT APPARATUS AND ITS MANAGEMENT METHOD AND PROGRAM - A POST management apparatus for managing a POST of an SB in a partition which operates in units of an OS using the CPU of the SB as a resource accesses the storage area storing the POST of the SB so as to perform read/write operation and to acquire/recognize the individual information on the SB and the version number information of the POST, transmits the POST of a predetermined version number according to at least one of the individual information and the version number information, and manages the version number of the POST so that the version numbers of the POSTs used in the SBs in units of a partition coincide with each other. | 2008-11-20 |
20080288825 | STORAGE SUBSYSTEM, STORAGE SYSTEM, AND COMMUNICATION CONTROL METHOD - In a storage subsystem which is connected to an IP network, by excluding an improper packet, security is heightened, and a performance of communication to a logical unit of storage subsystem is maintained and secured. In the storage subsystem, a function which carries out filtering of a packet other than an iSCSI packet is provided. With respect to only the packet passed through the function, its accessibility to the logical unit is filtered. Also, traffic of all received packets, and a traffic lob of a packet judged to be discarded by the above filtering is recorded. By using this information, controlling such as a cut-off process of improper communication, QoS securement for normal communication and so on, are carried out. | 2008-11-20 |
20080288826 | TRACE INFORMATION COLLECTING SYSTEM AND PROGRAM - Occurrence of a failure in a computer system is appropriately detected, and information required for removing the failure is automatically collected. A trace information collecting system of the present invention which collects trace information indicating the course of processing of a program comprises a history recording section for recording a history of run and stop of a target program for which the trace information is to be produced, a similarity calculating section for calculating a degree of similarity between a first operation pattern in which the target program ran and stopped at the last time and a second operation pattern in which the target program ran and stopped at the time before last when the target program, which once stopped, starts to run, a failure occurrence determining section for determining that a failure occurred when the target program ran at the last time on condition that the similarity calculated by the similarity calculating section is lower than a reference similarity, and a trace information collecting section for collecting the trace information from the target program in response to the determination that the failure occurred, wherein the trace information is not collected if it is determined that the failure did not occur. | 2008-11-20 |
20080288827 | METHOD FOR VISUALIZING RESULTS OF ROOT CAUSE ANALYSIS ON TRANSACTION PERFORMANCE DATA - Mechanisms for graph manipulation of transactional performance data are provided in order to identify and emphasize root causes of electronic business system transaction processing performance problems. A system transaction monitoring system, such as IBM Tivoli Monitoring for Transaction Performance™ (ITMTP) system, is utilized to obtain transaction performance data for a system. This transaction performance data is stored in a database and is utilized to present a graph of a given transaction or transactions. Having generated a graph of the transaction, and having identified problem conditions in the processing of the transaction(s), the present invention provides mechanisms for performing graph manipulation operations to best depict the root cause of the problems. | 2008-11-20 |
20080288828 | STRUCTURES FOR INTERRUPT MANAGEMENT IN A PROCESSING ENVIRONMENT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for managing interrupts in a processing system are disclosed. The design structure can determine an indication of an interrupt request from a peripheral entity, identify the peripheral entity associated with the indication, count occurrences of the indications; and flag the peripheral entity in response to the counted occurrences. When the counted occurrences reach a predetermined number in the predetermined time interval, interrupts from the peripheral entity can be ignored or the entity can be identified as having possible operational problems. | 2008-11-20 |
20080288829 | METHOD AND APPARATUS FOR VERIFYING DATA IN A STORAGE SYSTEM - A method for verifying data in a storage system is disclosed. A host computer transmits area management data to a storage controller. The area management data specifies a range of a storage area in a storage device to be used by an application program having a mechanism for verifying data suitability. Upon receipt of an input/output request transmitted from the host computer, the storage controller performs verification, which is usually performed by the application program, of the data that is to be processed according to the data input/output request and to be input/output to/from the storage area, which is specified in accordance with the received area management data. | 2008-11-20 |
20080288830 | METHOD, SYSTEM AND COMPUTER PROGRAM FOR FACILITATING THE ANALYSIS OF ERROR MESSAGES - A solution is proposed for managing a software application. A corresponding method ( | 2008-11-20 |
20080288831 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 2008-11-20 |
20080288832 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 2008-11-20 |
20080288833 | Method of Recording/Reproducing Digital Data and Apparatus for Same - A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another. | 2008-11-20 |
20080288834 | VERIFICATION OF MEMORY CONSISTENCY AND TRANSACTIONAL MEMORY - A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model. | 2008-11-20 |
20080288835 | Test method, integrated circuit and test system - The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of address pins, a second number of command pins and an address generation circuit which receives at least one encoded address information item using a third number of the address pins, which is smaller than the first number, and provides the other address pins as a fourth number of free address pins, where at least one first command is transferred using the command pins and at least one second command is transferred using at least one portion of the fourth number of the address pins from a test apparatus to the integrated circuit using a test clock which has a lower rate than the internal operating clock. | 2008-11-20 |
20080288836 | Semiconductor integrated circuit capable of testing with small scale circuit configuration - In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference. | 2008-11-20 |
20080288837 | Testing of a Circuit That has an Asynchronous Timing Circuit - Special test measures are required to test an asynchronous timing circuit. The asynchronous timing circuit ( | 2008-11-20 |
20080288838 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, an electrical package includes: an external input portion; an external output portion; a plurality of integrated circuits that is compatible with a compressed deterministic pattern test, each of the integrated circuits including: an input portion; a decompressor that is connected to the input portion; scan chains that are connected to the decompressor; a compactor that is connected to the scan chains; a selector that is connected to the compactor and the input portion to selectively output an output of the compactor or an output of the input portion; and an output portion that is connected to the selector. | 2008-11-20 |
20080288839 | Jtag Test Architecture For Multi-Chip Pack - A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip. | 2008-11-20 |
20080288840 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 2008-11-20 |
20080288841 | SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALANCED-LENGTH SCAN CHAINS INTO HIERARCHICALLY DESIGNED INTEGRATED CIRCUITS. - A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L. | 2008-11-20 |
20080288842 | Ic Testing Methods and Apparatus - A testing circuit has scan chain segments ( | 2008-11-20 |
20080288843 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 2008-11-20 |
20080288844 | Data Communication Module Providing Fault Tolerance and Increased Stability - A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted. | 2008-11-20 |
20080288845 | Range Extension and Noise Mitigation For Wireless Communication Links Utilizing a CRC Based Single and Multiple Bit Error Correction Mechanism - A novel and useful range extension and in-band noise mitigation mechanism that uses conventional CRC error detection codes to correct single and multiple bit errors in packets received over a communications link. The CRC error correction mechanism of the invention is particularly suitable for use with communication protocols with weak error correction capabilities. The mechanism uses the linearity property of the CRC calculation to detect the existence of errors in the received packet. The entire received packet is searched for single bit errors and are corrected in a single cycle. If no single bit errors are found, the mechanism then searches for multiple bit errors. Packet retransmissions are used to detect and mark the location of multiple bit errors. Multiple bit errors are corrected by trying a plurality of hypotheses of single bit error corrections. Each hypotheses pattern is investigated to find matching CRC patterns for correction using the single bit, single cycle CRC error correction method. | 2008-11-20 |
20080288846 | APPARATUS AND METHOD FOR ENCODING AND DECODING BLOCK LOW DENSITY PARITY CHECK CODES WITH A VARIABLE CODING RATE - An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code. | 2008-11-20 |
20080288847 | WIRELESS TRANSMIT/RECEIVE UNIT HAVING A TURBO DECODER WITH CIRCULAR REDUNDANCY CODE SIGNATURE COMPARISON AND METHOD - An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same. | 2008-11-20 |
20080288848 | Latency by offsetting cyclic redundancy code lanes from data lanes - Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving latency by offsetting cyclic redundancy check lanes from data. In some embodiments, a memory device includes a memory array to provide read data bits and a cyclic redundancy code (CRC) generator to generate CRC bits corresponding to the read data bits. In addition, the memory device may include a transmit framing unit to transmit the read data bits and the CRC bits to a host, wherein the transmit framing unit includes logic to offset the transmission of the CRC bits from the transmission of the read data bits based, at least in part, on an offset value. Other embodiments are described and claimed. | 2008-11-20 |
20080288849 | Apparatus for generating soft decision values and method thereof - According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value. | 2008-11-20 |