47th week of 2008 patent applcation highlights part 45 |
Patent application number | Title | Published |
20080286845 | FERMENTATION PROCESS - The present invention relates to processes of fermenting plant derived material into a desired fermentation product. The invention also relates to an antifoaming system for use in a fermentation process. | 2008-11-20 |
20080286846 | Method and equipment for treating microcystin-containing water - The method for treating microcystin-containing water which detoxifies microcystin in the microcystin-containing water, the method comprises the step of: bringing the microcystin-containing water into contact with a | 2008-11-20 |
20080286847 | ALTERNATE MORPHEEINS OF ALLOSTERIC PROTEINS AS A TARGET FOR THE DEVELOPMENT OF BIOACTIVE MOLECULES - A composition having an agent adapted to affect a multimeric protein by binding to a binding site of the multimeric protein and thereby affecting an equilibrium of units, wherein the multimeric protein has an assembly having a plurality of said units, wherein each of the units has a first complementary surface and a second complementary surface and wherein the first complementary surface of one unit is associated with the second complementary surface of another unit, provided that the assembly is at least one of different quaternary isoforms on a condition that in the multimeric protein (1) a structure of each of the units determines a structure of the different quaternary isoforms, (2) the units are in the equilibrium and (3) the structure of the different quaternary isoforms influences a function of the multimeric protein. | 2008-11-20 |
20080286848 | RECOVERY OF RECOMBINANT HUMAN PARAINFLUENZA VIRUS TYPE 2 (HPIV2) FROM cDNA AND USE OF RECOMBINANT HPIV2 IN IMMUNOGENIC COMPOSITIONS AND AS VECTORS TO ELICIT IMMUNE RESPONSES AGAINST PIV AND OTHER HUMAN PATHOGENS - Recombinant human parainfluenza virus type 2 (HPIV2) viruses and related immunogenic compositions and methods are provided. The recombinant HPIV2 viruses, including HPIV2 chimeric and chimeric vector viruses, provided according to the invention are infectious and attenuated in permissive mammalian subjects, including humans, and are useful in immunogenic compositions for eliciting an immune responses against one or more PIVs, against one or more non-PIV pathogens, or against a PIV and a non-PIV pathogen. Also provided are isolated polynucleotide molecules and vectors incorporating a recombinant HPIV2 genome or antigenome. | 2008-11-20 |
20080286849 | Herbal extract having anti-virus activity and preparation of same - The invention relates to the herbal extract having anti-viral activity. More specifically, it relates to the herbal extract produced by extracting the comminuted Fructus Ligustri Lucidi (privet fruit), Rhizoma Polygonati (sealwort), Herba Agrimoniae (agrimonia), Radix Rehmanniae Glutinosae Conquitae (steamed glutinous rehmannia) or the mixture thereof, with a low polar solvent, and to the method for in vitro antagonizing virus by contacting the herbal extract with viruses. | 2008-11-20 |
20080286850 | MDCK CELL LINES SUPPORTING VIRAL GROWTH TO HIGH TITERS AND BIOREACTOR PROCESS USING THE SAME - The present invention relates to novel MDCK cells which can be to grow viruses, e.g., influenza viruses, in cell culture to higher titer than previously possible. The MDCK cells can be adapted to serum-free culture medium. The present invention further relates to cell culture compositions comprising the MDCK cells and cultivation methods for growing the MDCK cells. The present invention further relates to methods for producing influenza viruses in cell culture using the MDCK cells of the invention. | 2008-11-20 |
20080286851 | Large-scale photo-bioreactor using flexible materials, large bubble generator, and unfurling site set up method - A closed photo-bioreactor, which in at least one example comprises a plurality of flexible, repeating, substantially enclosed, parallel chambers flexibly connected along their lengths, where a liquid growth media is substantially still without the need for turbulent mixing of the bulk liquid. In many examples, each is connected into integrated, flexible pipelines that serve to supply gas to the chambers, to vent gas from the chambers, and to fill and drain the individual photo-bioreactor chambers of their liquid contents. In some installations, a bioreactor will be rolled up using, for example, a long rod as a spool, for storage and transportation. Some examples will be manually unfurled and positioned on an angled site including, for example, an earthen berm. In many embodiments, a photo-bioreactor will be manufactured from thin plastics using low cost manufacturing techniques. In at least one example, a photo bioreactor is described in which bubbles with a substantially non-convex shape are introduced to mix the liquid contents. | 2008-11-20 |
20080286852 | Electroporation of Mycobacterium and Overexpression of Antigens in Mycobacteria - Recombinant | 2008-11-20 |
20080286853 | Process for Producing a Bio-Pesticide Composition Containing Trichoderma Harzianum and Pseudomonas Fluorescens - A process for the production of organic and combination formulation of bio-pesticide containing | 2008-11-20 |
20080286854 | Method for Enriching Lignocellulose Residues With Yeast Protein - The invention relates to the use of sugar cane molasses and distillery slop for carrying out a method for enriching lignocellulose residue, especially bagasse or straw, with yeast protein. The invention also relates to said lignocellulose residue enrichment method, and to the product thus obtained. | 2008-11-20 |
20080286855 | THERMACETOGENIUM PHAEUM CONSORTIUM FOR THE PRODUCTION OF MATERIALS WITH ENHANCED HYDROGEN CONTENT - An isolated microbial consortium is described that includes a first microbial consortium having | 2008-11-20 |
20080286856 | Nanostructure Enhanced Luminescent Devices - The present invention relates to nanostructures for use in luminescent devices. | 2008-11-20 |
20080286857 | Multi-functional Polymer-Entrapped-Cell-Bead airlift bioreactor for odor or gaseous emission treatment - The invention provides a multi-functional polymer-entrapped-cell-bead airlift bioreactor for odor or gaseous emission treatment. Especially, it refers to a reactor that mainly treats a low-and-medium gas flow rate and concentration of volatile organic emission or odorous substances. Particularly, it utilizes synthetic material (PAA beads) and microbial entrapment technology as the microbial source and startup mechanism for gaseous emission and odor treatment. Besides, plastic decomposing | 2008-11-20 |
20080286858 | Reaction vessel with integrated optical and fluid control elements - The present invention provides disposable, semi-reusable, or single use reaction vessels with integrated optical elements for use with diffraction based assay systems. The vessel for assaying liquids for analytes includes a housing having at least one chamber or well for receiving a liquid therein and an optical element integrally formed with the housing for directing an incident light beam towards the well or chamber and directing a light beam away from the reaction chamber after the light beam has interacted with analytes present in the liquid. | 2008-11-20 |
20080286859 | Apparatus For Producing Thin Sections - An apparatus for producing flat thin sections of a specimen ( | 2008-11-20 |
20080286860 | CANCER SPECIFIC PROMOTERS - The present invention regards cancer-specific control sequences that direct expression of a polynucleotide encoding a therapeutic gene product for treatment of the cancer. Specifically, the invention encompasses breast cancer-, prostate cancer-, and pancreatic cancer-specific control sequences. Two breast cancer-specific sequences utilize specific regions of topoisomerase IIα and transferrin receptor promoters, particularly in combination with an enhancer. The prostate cancer-specific and pancreatic cancer-specific control sequences utilize composites of tissue-specific control sequences, a two-step transcription amplification sequence, and a post-transcriptional control sequence. In more particular embodiments, these polynucleotides are administered in combination with liposomes. | 2008-11-20 |
20080286861 | Compositions and Methods for the Treatment of Immune Related Diseases - The present invention relates to compositions containing novel proteins and methods of using those compositions for the diagnosis and treatment of immune related diseases. | 2008-11-20 |
20080286862 | Physiochemical Culture Conditions for Embryonic Stem Cells - Physiochemical parameters to improve the culturing and sub-culturing (here called cloning) of human embryonic stem cells have been investigated. Low levels of oxygen and higher than expected levels of osmolarity in the culture medium have both been found to contribute to the improved culture of human stem cells. | 2008-11-20 |
20080286863 | METHOD AND SOLUTIONS FOR CRYOPRESERVING OOCYTES, ESPECIALLY FRESH HUMAN OOCYTES - In a method for cryopreserving fresh human oocytes, freezing and thawing solutions are used, which solutions include | 2008-11-20 |
20080286864 | Choroid Plexus Preparation and Uses Thereof - The present invention is directed to the use of choroid plexus cells and/or choroid plexus conditioned media for enhancing the growth, survival and/or maintenance of function of non-choroid plexus cells grown in long term or short term culture. | 2008-11-20 |
20080286865 | Methods for the Preservation of Platelet Efficacy During Storage - Invented is a method for the preservation of human platelet lifespan and/or efficacy during storage which comprises the addition of an effective amount of a non-peptide TPO receptor agonists to a storage solution containing human platelets. | 2008-11-20 |
20080286866 | NUCLEIC ACID COMPOUNDS FOR INHIBITING VEGF GENE EXPRESSION AND USES THEREOF - The present disclosure provides meroduplex ribonucleic acid molecules (mdRNA) capable of decreasing or silencing VEGFA, VEGFB, VEGFC, FIGF, or PGF gene expression. An mdRNA of this disclosure comprises at least three strands that combine to form at least two non-overlapping double-stranded regions separated by a nick or gap wherein one strand is complementary to a VEGF mRNA. In addition, the meroduplex may have at least one 5-methyluridine, locked nucleic acid, 2′-O-methyl, or optionally other modifications, and any combination thereof. Also provided are methods of decreasing expression of a VEGF gene in a cell or in a subject to treat a VEGF-related disease. | 2008-11-20 |
20080286867 | Method of Inducing Embryonic Stem Cells Into Pancreatic Cells - The present invention provided a simple three-step approach based on the combinational induction with activin A, all-trans retinoic acid and, optionally, other maturation factors which are able to induce embryonic stem cells to differentiate into insulin-producing cells. A kit used to induce embryonic stem cells to differentiate into insulin-producing cells was also provided. | 2008-11-20 |
20080286868 | METAL BINDING COMPOUNDS AND THEIR USE IN CELL CULTURE MEDIUM COMPOSITIONS - The present invention is directed generally to metal binding compounds which may be added to cell culture media to replace factors required for cultivation of the cells (e.g. transferrin) which are of animal or human origin. More specifically, the invention is directed to metal binding compounds or complexes thereof comprising one or more transition element cations (such as ferrous or ferric ions), which are added to cell and tissue culture medium compositions. The metal binding compounds may be added to the media alone or may be first complexed with a transition metal ion. The invention is also directed to methods of use of such compositions, including, for example, methods for the cultivation of eukaryotic cells, particularly animal cells, in vitro. The invention also relates to compositions comprising such culture media and one or more cells, and to kits comprising one or more of the above-described compositions. The compositions of the present invention obviate the need for naturally derived metal-binding proteins, such as transferrin and ceruloplasmin, which may contain blood-borne pathogens. | 2008-11-20 |
20080286869 | Retroviral Vector - Provided herein is a retroviral vector comprising, and capable of expressing, a nucleotide of interest (NOI), wherein the NOI encodes an RNA or protein which is harmful to a cell. | 2008-11-20 |
20080286870 | XYLITOL SYNTHESIS MUTANT OF XYLOSE-UTILIZING ZYMOMONAS FOR ETHANOL PRODUCTION - A strain of xylose-utilizing | 2008-11-20 |
20080286871 | Modular genomes for synthetic biology and metabolic engineering - The invention provides methods and compositions for assembling a modular replacement genome in a host microorganism. After such assembly, the host organism's genome is inactivated or ablated to permit full control of host cellular functions by the replacement genome. A modular replacement genome comprises an assembly of nucleic acid fragments, or segments, derived from one or more natural organisms or from synthetic polynucleotides or from a combination of both. Such an assembly, or set, of segments making up a replacement genome comprises a substantially complete set of genes and regulatory elements for carrying out minimal life functions under predefined culture conditions. The invention provides modular genomes having modules that are amenable to facile replacement, deletion, and/or additions. Such modules may be synthetic polynucleotides and may be designed for controlling gene content, excluding of genes that encode inhibitors or otherwise undesirable competing enzymes that divert a host cell from desired metabolic/synthetic processes; modifying codon usage to maximize or minimize protein production; modifying regulatory elements, including promoters, enhancers, repressors, activator, or the like, to modulate gene expression; balancing enzymatic and transport activities to optimize fluxes of substrates, intermediates, and products in metabolic pathways, and like objectives. | 2008-11-20 |
20080286872 | AUTOMATIC ANALYZER - An automatic analyzer analyzes a measurement item by making a sample and reagent react with each other and measuring the reaction result. This apparatus allows parameters associated with reagent dispensing executed by a reagent dispensing mechanism to be set as a dispensing condition for each measurement item or each type of reagent, and controls the reagent dispensing mechanism on the basis of the dispensing condition. | 2008-11-20 |
20080286873 | Method and device for reducing positron emitting isotope labeled carbon dioxide to positron emitter isotope labeled carbon monoxide via metal oxide - A method and device for reducing positron emitter isotope labeled CO | 2008-11-20 |
20080286874 | REDUCING OR AVOIDING MUSCLE CRAMPS - Muscle cramps can be reduced or avoided by monitoring the concentration of salt in perspiration to indicate the degree of salt depletion. Based on the degree of salt depletion, a sufficient amount of rehydration beverage is consumed to normalize the salt level. | 2008-11-20 |
20080286875 | RYR2 MUTATIONS - This document provides methods and materials related to assessing a mammal for the presence or absence of a genetic mutation. For example, methods for determining whether or not a mammal contains a genetic mutation in an RyR2 sequence are provided. In addition, isolated nucleic acid molecules containing an RyR2 sequence and encoding a mutation are provided herein. | 2008-11-20 |
20080286876 | GENES ASSOCIATED WITH ALZHEIMER'S DISEASE - Hltdip - A method of screening a small molecule compound for use in treating Alzheimers Disease, comprising screening a test compound against a target or targets selected from the gene products encoded by a group of specified genes, where activity against said target indicates the test compound has potential use in treating Alzheimers Disease. | 2008-11-20 |
20080286877 | Displacement assay for detection of small molecules - Complex of an anti-cocaine aptamer and the dye diethylthiotricarbocyanine behaves as a calorimetric sensor with attenuation in absorbance at 760 nm for cocaine in the concentration range of 2-5000 μM. Mechanistic studies indicate an intermolecular displacement of the dye as the mechanism of action of the sensor. As the dye is insoluble in buffer, cocaine binding can be detected as displaced dye precipitates and supernatant decolorizes. | 2008-11-20 |
20080286878 | Systems, Compositions And Methods For Nucleic Acid Detection - The invention relates to stretch measurements of nucleic acids and correlating those measurements to the extent of double- and single-stranded content of a nucleic acid of interest, and to compositions, systems, and devices related thereto. In preferred embodiments, one performs the stretch or elasticity measurements under conditions such that one can determine a nucleic acid sequence or the presence of an oligonucleotide in a sample. | 2008-11-20 |
20080286879 | Test device, and related methods - Test device for detection and visual indication of a specific analyte in a liquid sample such as a body fluid. The device includes a biodegradable housing, a test strip and a lid. The device is configured for placement in concentrate or dilute test liquid that is for example contained in a vessel. One end of the test strip wicks the liquid being tested into the housing and across a control site and test site which provide visual indication that the device is working correctly and whether the analyte being tested is present in the test liquid. An antibody specific to the antigen being tested may be provided on the test strip. The test device for example detects specific antigens in dilute urine, such that the device may be placed in a toilet bowl after urination. | 2008-11-20 |
20080286880 | Methods and Systems for Nanoparticle Enhancement of Signals - Methods and systems for utilizing metal nanoparticles to enhance optical (UV, visible, and IR, as appropriate) signals from a reporting entity are presented. The methods and systems of this invention do not require the nanoparticles to be attached or adhered to a surface, assembled in a matrix or coated with a spacer coating. | 2008-11-20 |
20080286881 | COMPOSITIONS AND METHODS FOR COMBINING REPORT ANTIBODIES - Compositions are disclosed. One embodiment of a composition comprises a first antibody having an affinity for an antigen and a second antibody having an affinity for the first antibody, wherein at least one antibody is conjugated to a marker, and wherein the antigen is not present in the composition. Further disclosed are methods of using compositions according to the invention for analyzing a biological sample by antibody profiling for identifying forensic samples or detecting the presence of an analyte. In embodiments of the invention, the analyte is a drug, such as marijuana, cocaine, methamphetamine, methyltestosterone, or mesterolone. Forensic samples are identified by comparing a sample from an unknown source with a sample from a known source. Further, an assay, such as a test for illegal drug use, may be coupled to a test for identity such that the results of the assay may be positively correlated to the subject's identity. | 2008-11-20 |
20080286882 | Method and Apparatus for Measuring the Concentration of a Ligand Contained in a Sample That Is To Be Tested - In a method for measuring the concentration of a ligand contained in a sample that is to be tested, at a plurality of test sites that are located on the surface of at least one substrate, in each case at least one receptor that is suitable upon contact with the ligand for specifically binding to said ligand, is immobilized. The sample is brought into contact for a predetermined time with the test sites in such a way that in the sample differently sized diffusion volumes are adjacent to the receptors from which at least one ligand can diffuse to the respective receptor during the predetermined time. After the predetermined time has passed, for each test site a measured signal for the number or density of the binding events at the test site is acquired. | 2008-11-20 |
20080286883 | Dry etching method and production method of magnetic memory device - Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction. | 2008-11-20 |
20080286884 | METHOD FOR IN-SITU REPAIRING PLASMA DAMAGE AND METHOD FOR FABRICATING TRANSISTOR DEVICE - A method for in-situ repairing plasma damage, suitable for a substrate, is provided. A component is formed on the substrate. The formation steps of the component include a main etching process containing plasma. The method involves performing a soft plasma etching process in the apparatus of the main etching process containing plasma to remove a portion of the substrate. The soft plasma etching process is less than 30% of the power used in the main etching process. | 2008-11-20 |
20080286885 | METHODS AND SYSTEMS FOR CREATING OR PERFORMING A DYNAMIC SAMPLING SCHEME FOR A PROCESS DURING WHICH MEASUREMENTS ARE PERFORMED ON WAFERS - Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process. | 2008-11-20 |
20080286886 | Monitoring Cool-Down Stress in a Flip Chip Process Using Monitor Solder Bump Structures - A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip. | 2008-11-20 |
20080286887 | Method for adjusting a transistor model for increased circuit simulation accuracy - According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model. | 2008-11-20 |
20080286888 | TEST STRUCTURES AND METHODOLOGY FOR DETECTING HOT DEFECTS - Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone shaped test structure, tower shaped test structure, and inside-hole shaped. A method for detecting HOT defects involves measuring defect size and location in terms of device leakage, such as gate leakage, junction leakage, and sub-threshold leakage. HOT edge defect density and edge defect size distribution may be calculated, and the resulting defect information may be used to calibrate a defect yield model. | 2008-11-20 |
20080286889 | Manufacturing method of liquid crystal display - A method of manufacturing a liquid crystal display at a reduced cost is presented. The method entails: preparing an insulating substrate; forming a gate line and a data line on the insulating substrate to define a pixel area; forming a thin film transistor at an intersection of the gate line and the data line; forming A passivation layer on the thin film transistor; positioning a mold having a concavo-convex pattern on the organic passivation layer, pressing the mold, and forming the concavo-convex pattern on the surface of the organic passivation layer. A pixel electrode on the organic passivation layer is formed. | 2008-11-20 |
20080286890 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device including a first substrate, a second substrate facing and spaced away from the first substrate, a liquid crystal layer sandwiched between the first and second substrates, a switching device formed on the first substrate, a first electrically insulating film randomly patterned on the first substrate, a second electrically insulating film covering the first electrically insulating film therewith, and having a wavy surface, and a reflection electrode formed on the second electrically insulating film, and electrically connected to an electrode of the switching device, wherein a light passing through the second substrate and the liquid crystal layer is reflected at the reflection electrode, and the second electrically insulating film extends outwardly from the first electrically insulating film by a certain length at an end of a display region in which images are to be displayed, such that a step formed by the first and second electrically insulating films in the vicinity of the end of the display region is smoothed. | 2008-11-20 |
20080286891 | Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method - A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed. | 2008-11-20 |
20080286892 | METHOD FOR FABRICATING THREE-DIMENSIONAL PHOTONIC CRYSTAL - A method for fabricating a three-dimensional photonic crystal comprises the steps of: forming a dielectric thin film; injecting ions selectively into the dielectric thin film by using a focus ion beam to form a mask on the dielectric thin film; forming a pattern by selectively removing an exposed part of the dielectric thin film at which the mask is not formed on the dielectric thin film; forming a sacrificial layer on the dielectric thin film having the pattern formed therein; and flattening the sacrificial layer formed on the dielectric thin film until the pattern comes to the surface. | 2008-11-20 |
20080286893 | Light emitting device having protrusion and recess structure and method of manufacturing the same - The semiconductor light emitting device having a protrusion and recess structure includes: a lower clad layer disposed on a substrate; an active layer formed on one portion of a top surface of the lower clad layer; an upper clad layer formed on the active layer; a first electrode formed on the upper clad layer; and a second electrode that is formed on a protrusion and recess structural pattern region formed on a portion of the top surface of the lower clad layer not occupied by the active layer. | 2008-11-20 |
20080286894 | GALLIUM NITRIDE BASED SEMICONDUCTOR LIGHT EMITTING DIODE AND PROCESS FOR PREPARING THE SAME - A process for preparing a gallium nitride based semiconductor light emitting diode includes the step of: providing a substrate for growing a gallium nitride based semiconductor material; forming a lower clad layer on the substrate using a first conductive gallium nitride based semiconductor material; forming an active layer on the lower conductive clad layer using an undoped gallium nitride based semiconductor material; forming an upper clad layer on the active layer using a second conductive gallium nitride based semiconductor material; removing at least a portion of the upper clad layer and active layer at a predetermined region so as to expose the corresponding portion of the lower clad layer; and forming, on the upper surface of the upper clad layer, an ohmic contact forming layer made of In | 2008-11-20 |
20080286895 | Method of manufacturing an organic device - A method of manufacturing an organic device includes the following steps. The first step is a step of forming a plurality of organic elements in the form of a matrix on a brittle substrate. Each of the organic elements is provided with an electrically connecting portion which electrically connects the organic element to an external circuit. The second step is a step of forming a sealing film on each organic element by a wet process with at least a part of the connecting portion covered with an adhesive masking material. The third step is a step of removing an adhesive deposit after peeling off the adhesive masking material. The fourth step is a step of forming a plurality of scribe lines on the brittle substrate. The fifth step is a step of breaking the brittle substrate along the scribe lines. | 2008-11-20 |
20080286896 | METHOD FOR MANUFACTURING IMAGE SENSOR - A method for manufacturing an image sensor including forming an interlayer dielectric layer on a substrate including a photo diode; forming a color filter layer on the interlayer dielectric layer; forming an oxide film on the color filter layer; forming a plurality of micro lens patterns spaced apart on the oxide film; forming an oxide-based micro lens having a predetermined curvature by etching the oxide film using the micro lens pattern as a mask; and cleaning the micro lens patterns with a peroxosulfuric acid mixing solution. | 2008-11-20 |
20080286897 | Method for Manufacturing Image Sensor - Provided is a method for manufacturing an image sensor. In the method, a microlens is formed from an oxide layer. The oxide layer used for the microlenses can be formed using a nitrogen gas as dopant. A plurality of photoresist patterns can be formed on the oxide layer, and the oxide layer can be etched using the photoresist patterns as a mask to form-oxide layer microlenses having a constant curvature. In a further embodiment, a plasma treatment can be applied to the photoresist patterns during forming of the oxide layer microlenses. | 2008-11-20 |
20080286898 | Material composition having core-shell microstructure used for varistor - A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties of the varistors during low temperature of sintering process can be decided and designated by precisely controlling the size of the grain of the cored-structure and the thickness and insulation resistance of the insulating layer of the shelled-structure of material composition. | 2008-11-20 |
20080286899 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SYSTEM-IN-PACKAGE USING THE SAME - A method for manufacturing a semiconductor device and a method for manufacturing a system-in-package using the same, which are capable of enhancing reliability and the step coverage for a trench having a high aspect ratio. The semiconductor manufacturing method includes forming a first insulating film over a substrate; and then forming first and second metal patterns over the first insulating film; and then forming a second insulating film over the first insulating film including the first and second metal patterns; and then forming a trench extending through the first and second insulating films and into the substrate thereby exposing the substrate; and then sequentially forming first and second oxide films over the second insulating film and in the trench; and then forming a via hole exposing the first metal pattern; and then sequentially forming first and second barrier metal films over a resultant surface of the substrate including the second oxide film; and then forming a copper layer over the second barrier metal film and in the trench and the via hole; and then planarizing the copper layer exposing a portion of the second barrier metal film; and then forming a copper pad by recessing predetermined portions of the second barrier metal film, the first barrier metal film, the second oxide film and the first oxide film exposing the second insulating film at opposite sides of the copper pad. | 2008-11-20 |
20080286900 | METHOD FOR ADHERING SEMICONDUCTOR DEVICES - A method for adhering semiconductor devices is provided. The method includes forming a first semiconductor device including a first metal pad, forming a second semiconductor device including a second metal pad, adhering the first semiconductor device to the second semiconductor device, the first metal pad electrically connecting the second metal pad, and forming a heat sink via in the second semiconductor device. | 2008-11-20 |
20080286901 | Method of Making Integrated Circuit Package with Transparent Encapsulant - A method for making an IC package with transparent encapsulant includes providing a leadframe, where the leadframe includes a first die pad and a second die pad, disposing a first die on the first die pad and a second die on the second die pad, forming a cavity on the leadframe, where the cavity includes the first die pad and the second die pad, injecting an encapsulant material into the cavity and cutting the injected encapsulant material and the leadframe to form a first IC package and a second IC package. The encapsulant material is transparent for visible wavelengths. The injection of the encapsulant material is performed at an encapsulant temperature ranging from 140° C. to 160° C. | 2008-11-20 |
20080286902 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate. | 2008-11-20 |
20080286903 | Semiconductor device packaged into chip size and manufacturing method thereof - A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm. | 2008-11-20 |
20080286904 | Method for manufacturing semiconductor package - Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line. | 2008-11-20 |
20080286905 | Fin-Type Antifuse - A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process. | 2008-11-20 |
20080286906 | STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 2008-11-20 |
20080286907 | SEMICONDUCTOR LAYER FOR THIN FILM TRANSISTORS - A method for making a zinc oxide semiconductor layer for a thin film transistor using solution processing at low temperatures is disclosed. The method comprises making a solution comprising a zinc salt and a complexing agent; applying the solution to a substrate; and heating the solution to form a semiconductor layer on the substrate. A thin film transistor using this zinc oxide semiconductor layer has good mobility and on/off ratio. | 2008-11-20 |
20080286908 | Method of Producing a Semiconductor Element in a Substrate - A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms. | 2008-11-20 |
20080286909 | SIDEWALL SEMICONDUCTOR TRANSISTORS - A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region. | 2008-11-20 |
20080286910 | Method for manufacturing SOI substrate and method for manufacturing semiconductor device - A method for manufacturing an SOI substrate with favorable adherence without high-temperature heat treatment being performed in bonding, and a semiconductor device using the SOI substrate and a manufacturing method thereof are proposed. An SOI substrate and a semiconductor device can be manufactured by forming a single-crystalline silicon substrate with a thickness of 50 μm or less in which a brittle layer is formed; forming a supporting substrate having an insulating layer over a surface; activating at least one of the surfaces of the single-crystalline silicon substrate and the insulating layer by exposure to a plasma atmosphere or an ion atmosphere; and bonding the single-crystalline silicon substrate and the supporting substrate with the insulating layer interposed therebetween. | 2008-11-20 |
20080286911 | Method for manufacturing semiconductor device - To provide a low-cost high performance semiconductor device and a method for manufacturing the semiconductor device, a separate single-crystal semiconductor layer having a first region and a non-single-crystal semiconductor layer having a second region are provided over a substrate. Further, it is preferable that a cap film is formed over either the separate single-crystal semiconductor layer or the non-single-crystal semiconductor layer, and the first region and the second region are irradiated with a laser beam by applying the laser beam from above the cap film. | 2008-11-20 |
20080286912 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device in which a semiconductor layer of a thin film transistor and a first electrode of a capacitor are formed of amorphous silicon and the whole or a part of source/drain regions of the semiconductor layer and the first electrode of the capacitor are crystallized by a metal induced crystallization method, and a channel region of the semiconductor layer is crystallized by a metal induced lateral crystallization method. | 2008-11-20 |
20080286913 | FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS - Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures. | 2008-11-20 |
20080286914 | Display device, method of production of the same, and projection type display device - A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film | 2008-11-20 |
20080286915 | Metal-Oxide-Semiconductor High Electron Mobility Transistors and Methods of Fabrication - A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described. | 2008-11-20 |
20080286916 | METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE - Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric. | 2008-11-20 |
20080286917 | LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS - The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt. | 2008-11-20 |
20080286918 | Methods for Fabricating Semiconductor Structures With Backside Stress Layers - Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region. | 2008-11-20 |
20080286919 | TUNNEL AND GATE OXIDE COMPRISING NITROGEN FOR USE WITH A SEMICONDUCTOR DEVICE AND A PROCESS FOR FORMING THE DEVICE - A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient which, due to their differences in sizing, results in nitridizing the tunnel oxide in its entirely but only partially nitridizing the gate oxide. Various process embodiments and completed structures are disclosed. | 2008-11-20 |
20080286920 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes forming a negative photoresist layer on a semiconductor substrate, forming a photoresist pattern on the negative photoresist layer, forming a well region in the semiconductor substrate, implanting ions into the semiconductor substrate, using the photoresist pattern as a mask, such that the ions are implanted into the well region, removing the photoresist pattern, and forming a gate region and a source/drain region on the semiconductor substrate. | 2008-11-20 |
20080286921 | METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES - The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness. | 2008-11-20 |
20080286922 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one example embodiment, a method of fabricating a semiconductor device includes various steps. First, an isolation film is formed on a semiconductor substrate to define a field region and an active region. Then, a stack gate structure is formed. Next, a first photoresist and a second photoresist are sequentially formed on the stack gate structure. Then, a patterning process is performed to remove the second photoresist in a source line region. Next, a patterning process is performed to remove the first photoresist in the source line region, to thereby expose the isolation film. Then, the exposed isolation film is removed to expose the semiconductor substrate in the source line region. Finally, a cell source ion implantation process is performed using the patterned second photoresist as an ion injection mask to form a source line having impurity ions implanted thereto in the semiconductor substrate of the source line region. | 2008-11-20 |
20080286923 | METHOD FOR FABRICATING FLASH MEMORY - A method for fabricating a flash memory device is disclosed that can improve the reliability of the device by counteracting against the generation of charge traps induced by interfacial damage of an oxide film during the formation of spacers. The method may comprise forming spacers comprised of an oxide film and a nitride film, nitriding an interface of the oxide film after removal of the nitride film; and forming a salicide film after formation of an insulating film on a sidewall of the nitrided oxide film. | 2008-11-20 |
20080286924 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer. | 2008-11-20 |
20080286925 | NONVOLATILE MEMORY WITH BACKPLATE - The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors. | 2008-11-20 |
20080286926 | BIT LINE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same. | 2008-11-20 |
20080286927 | NON-VOLATILE MEMORY DEVICE WITH BURIED CONTROL GATE AND METHOD OF FABRICATING THE SAME - In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation. | 2008-11-20 |
20080286928 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the chip with which a plurality of MISFET from which threshold value voltage differs is intermingled, leakage current, such as GIDL current and BTBT current, is suppressed, inhibiting the short channel effect of MISFET. The concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively low threshold value voltage is formed is made lower than the concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively high threshold value voltage is formed. Implantation amount of the impurity at the time of forming n | 2008-11-20 |
20080286929 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The method for manufacturing a semiconductor device according to the invention includes the first doping step of doping source/drain regions including source/drain extension regions adjacent to a channel region of a MOS transistor, the second doping step of doping pocket implant regions disposed from the bottom of the source/drain extension regions in the depth direction, the step of forming an amorphous surface layer at the surface of a semiconductor crystal substrate so as to overlap the source/drain extension regions and the pocket implant regions, and the recrystallization step of recrystallizing the amorphous surface layer by a solid-phase epitaxy technique. | 2008-11-20 |
20080286930 | NITRIDE-ENCAPSULATED FET (NNCFET) - A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further. | 2008-11-20 |
20080286931 | SEMICONDUCTOR DEVICE INCLUDING FIELD-EFFECT TRANSISTOR USING SALICIDE (SELF-ALIGNED SILICIDE) STRUCTURE AND METHOD OF FABRICATING THE SAME - An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region. | 2008-11-20 |
20080286932 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device may include the steps of: forming a doped polysilicon film by implanting or incorporating dopant ions simultaneously with forming a silicon film; forming a doped polysilicon pattern by patterning the doped polysilicon film; forming a spacer on sides of the doped polysilicon pattern; and forming source and drain regions using the polysilicon pattern and the spacer as a mask. | 2008-11-20 |
20080286933 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 2008-11-20 |
20080286934 | METHOD OF FORMING A TRENCH CAPACITOR - A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench. | 2008-11-20 |
20080286935 | METHOD OF FABRICATING AN ISOLATION SHALLOW TRENCH - A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench. | 2008-11-20 |
20080286936 | METHOD FOR PREPARING A SHALLOW TRENCH ISOLATION - A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench. | 2008-11-20 |
20080286937 | Manufacturing Method for Bonded Wafer - In a first ion implantation step (a1), a delamination-intended ion implantation layer | 2008-11-20 |
20080286938 | Semiconductor device and fabrication methods thereof - A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings. | 2008-11-20 |
20080286939 | Method for manufacturing SOI substrate - An object is to provide a method for manufacturing an SOI substrate, by which defective bonding can be prevented. An embrittled layer is formed in a region of a semiconductor substrate at a predetermined depth; an insulating layer is formed over the semiconductor substrate; the outer edge of the semiconductor substrate is selectively etched on the insulating layer side to a region at a greater depth than the embrittled layer; and the semiconductor substrate and a substrate having an insulating surface are superposed on each other and bonded to each other with the insulating layer interposed therebetween. The semiconductor substrate is heated to be separated at the embrittled layer while a semiconductor layer is left remaining over the substrate having an insulating surface. | 2008-11-20 |
20080286940 | PROCESS FOR PRODUCTION OF SOI SUBSTRATE AND PROCESS FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands. | 2008-11-20 |
20080286941 | Method of manufacturing a semiconductor device - There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained. | 2008-11-20 |
20080286942 | Method of manufacturing a semiconductor device - There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained. | 2008-11-20 |
20080286943 | Motherboard Cutting Method, Motherboard Scribing Apparatus, Program and Recording Medium - A mother substrate cutting method for cutting a plurality of unit substrates out of a mother substrate, comprises the steps of: (a) forming scribe lines on the mother substrate by scribe forming means; and (b) breaking the mother substrate along the scribe lines, wherein the step (a) includes a step of forming a first scribe line for cutting a first unit substrate out of the mother substrate and a second scribe line for cutting a second unit substrate out of the mother substrate by moving a pressure position to the mother substrate without a pressure to the mother substrate by the scribe forming means being interrupted. | 2008-11-20 |
20080286944 | Method to Manufacture a Silicon Wafer Electronic Component Protected Against the Attacks and Such a Component - In general, the invention relates to manufacturing a wafer. The method includes manufacturing a wafer that includes a front side and a back side, thinning the wafer down to a thickness suitable for an intended operation of the wafer, polarizing the substrate wafer from the back side, and cutting the wafer. The wafer is polarized such that an attempt to thin the wafer from the backside results in at least one selected from a group consisting of destruction of the wafer and damage to the wafer. | 2008-11-20 |