47th week of 2009 patent applcation highlights part 25 |
Patent application number | Title | Published |
20090284998 | Method and system for providing maximum power point tracking in an energy generating system - A method for providing a maximum power point tracking (MPPT) process for an energy generating device is provided. The method includes coupling a local converter to the energy generating device. A determination is made regarding whether the local converter is operating at or below a maximum acceptable temperature. A determination is made regarding whether at least one current associated with the local converter is acceptable. When the local converter is determined to be operating at or below the maximum acceptable temperature and when the at least one current associated with the local converter is determined to be acceptable, the MPPT process is enabled within the local converter. | 2009-11-19 |
20090284999 | VOLTAGE SOURCE INVERTER AND MEDIUM VOLTAGE PRE-CHARGE CIRCUIT THEREFOR - A medium voltage adjustable frequency drive includes an input isolation transformer having a three-phase input and a three-phase output, a converter having a three-phase input electrically connected to the three-phase output of the input isolation transformer and an output providing a direct current bus, an inverter having an input electrically connected to the output of the converter and a three-phase output, and a pre-charge circuit. The pre-charge circuit includes a ferro-resonant transformer circuit having a primary winding structured to input a low voltage and a secondary winding structured to output a medium voltage and provide a constant current source. The pre-charge circuit also includes a medium voltage diode bridge having an input receiving the medium voltage from the secondary winding of the ferro-resonant transformer circuit and an output structured to provide the constant current source to the direct current bus. | 2009-11-19 |
20090285000 | ADAPTER WITH TRANSFORMATIVE COMPONENT - An adapter for removably coupling a consumer electronic device to a host, with the adapter supplying a first service between the host and the consumer electronic device when the adapter is coupled to the host and the consumer electronic device is coupled to the adapter, and the adapter further supplying a second service to the consumer electronic device when the adapter and the consumer electronic device are removed from the host. The adapter can further include a power source including a transformative component that transforms power supplied by the host. | 2009-11-19 |
20090285001 | CONTROL CIRCUITS AND METHODS FOR CONTROLLING SWITCHING DEVICES - A control circuit for controlling a switching device having a first terminal, a second terminal, and a control terminal is disclosed. The control circuit includes a first diode for coupling to the first terminal of the switching device, a second diode for coupling to the second terminal of the switching device, a first transistor for coupling to the control terminal of the switching device, and a second transistor coupled to the second diode. The first transistor is coupled to the first diode. The control circuit is configured to allow current flow in only one direction between the first and second terminals of the switching device. | 2009-11-19 |
20090285002 | MAINS CONVERTER FOR SWITCHING, WITHOUT ANY INTERRUPTION, BETWEEN CLOCKED VOLTAGE-REGULATED OPERATION AND FUNDAMENTAL-FREQUENCY UNREGULATED OPERATION, AND METHOD FOR SWITCHING A CONVERTER SUCH AS THIS WITHOUT ANY INTERRUPTION - A current source inverter is disclosed, comprising: means for operating the inverter in fundamental frequency unregulated operation, means for operating the inverter in clocked voltage regulated operation, means for recording parameters from which conclusions can be drawn at an instantaneous operating point and/or at an instantaneous network condition, means for determining an appropriate operating condition from the recorded parameters and means for uninterrupted switching of the operation of the inverter to the operating condition as determined from the recorded parameters and a method for uninterrupted switching of such a current source inverter. | 2009-11-19 |
20090285003 | BOOST CONVERTER - In a boost converter including an input transistor receiving an input voltage, an inductor and a main switch serially connected to the input transistor, rectifying means connected to a node between the inductor and the main switch and smoothing means for smoothing the output of the rectifying means to generate an output voltage, a current detection circuit generates a current detection signal corresponding to the current flowing through the input transistor. A voltage detection circuit generates a voltage detection signal corresponding to the output voltage. A startup circuit adjusts the current at the input transistor until the output voltage reaches a first voltage when being lower than the first voltage, and turns ON the input transistor when being higher than the first voltage. A control circuit controls ON/OFF of the main switch based on the current and voltage detection signals so that the output voltage becomes a predetermined value. | 2009-11-19 |
20090285004 | INVERTER MODULE WITH THERMALLY SEPARATED SEMICONDUCTOR DEVICES - Systems and apparatus are provided for an inverter module for use in a vehicle. The inverter module comprises a first electrical base and a second electrical base each having an electrically conductive mounting surface, wherein the electrical bases are physically distinct and electrically coupled. A first semiconductor switch has a surface terminal that is coupled to the electrically conductive mounting surface of the first electrical base. A second semiconductor switch has a surface terminal that is coupled to the electrically conductive mounting surface of the first electrical base. A first semiconductor diode and a second semiconductor diode each have a surface terminal, the surface terminals are coupled to the electrically conductive mounting surface of the second electrical base. The first semiconductor switch and first semiconductor diode are antiparallel, and the second semiconductor switch and second semiconductor diode are antiparallel. | 2009-11-19 |
20090285005 | SPACE-SAVING INVERTER WITH REDUCED SWITCHING LOSSES AND INCREASED LIFE - The invention relates to an inverter, and in particular a solar inverter. According to the invention, the inverter has a step-up converter ( | 2009-11-19 |
20090285006 | Semiconductor Memory and Method for Operating a Semiconductor Memory - A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier. | 2009-11-19 |
20090285007 | INTEGRATED CIRCUIT WITH AN ARRAY OF RESISTANCE CHANGING MEMORY CELLS - An integrated circuit includes an array of resistance changing memory cells, and a circuit configured to apply an initialization signal to a first one of the memory cells that is in a virgin resistance state. The initialization signal is configured to modify the first memory cell without switching an operation state of the first memory cell. | 2009-11-19 |
20090285008 | MEMORY DEVICES WITH SELECTIVE PRE-WRITE VERIFICATION AND METHODS OF OPERATION THEREOF - A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles | 2009-11-19 |
20090285009 | Nonvolatile memory devices using variable resistive elements - A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines. | 2009-11-19 |
20090285010 | Write Assist Circuit for Improving Write Margins of SRAM Cells - A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines. | 2009-11-19 |
20090285011 | STATIC RANDOM ACCESS MEMORY - A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground. | 2009-11-19 |
20090285012 | Integrated Circuit, Cell Arrangement, Method of Manufacturing an Integrated Circuit, Method of Operating an Integrated Circuit, and Memory Module - According to one embodiment of the present invention, an integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing the memory cell, such that the bias condition increases the stability of the set reference memory cell state. | 2009-11-19 |
20090285013 | MAGNETO-RESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY DEVICE - The invention relates to a magneto-resistance effect element and a magnetic memory device. Lowering the magnetic domain wall movement current and drive at room temperature in a current induction single magnetic domain wall movement phenomenon are achieved. A magneto-resistance effect element is formed by including at least: a magnet wire | 2009-11-19 |
20090285014 | INTEGRATED CIRCUIT AND METHOD FOR SWITCHING A RESISTIVELY SWITCHING MEMORY CELL - An integrated circuit and method for switching a resistively switching memory cell. One embodiment provides an initial pulse and at least one escalated pulse in case the memory cell did not switch. | 2009-11-19 |
20090285015 | PHASE-CHANGE MEMORY DEVICE INCLUDING BIASING CIRCUIT - A memory cell device is provided which includes a substrate, a plurality of unit memory cells connected between a word line and respective bit lines, where each memory cell including a resistance variable element, such a phase-change element, and a diode connected in series between the word line and the respective bit line, and a biasing circuit which applies a biasing voltage to the substrate to decrease a current flow in the word line. | 2009-11-19 |
20090285016 | Circuit for Reading Memory Cells - A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value. | 2009-11-19 |
20090285017 | MEMORY DEVICE AND MEMORY - A memory device is provided. The memory device includes a memory layer and a fixed-magnetization layer. The memory layer retains information based on a magnetization state of a magnetic material. The fixed-magnetization layer is formed on the memory layer through an intermediate layer made of an insulating material. The information is recorded on the memory layer with a change in a magnetization direction of the memory layer caused by injecting a spin-polarized electron in a stacked direction. A level of effective demagnetizing field, which is received by the memory layer, is smaller than a saturation-magnetization level of magnetization of the memory layer. | 2009-11-19 |
20090285018 | Gated Diode Memory Cells - A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”). | 2009-11-19 |
20090285019 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit ( | 2009-11-19 |
20090285020 | METHOD OF PROGRAMMING A MULTI LEVEL CELL IN A NON-VOLATILE MEMORY DEVICE - In a method of programming a multi level cell, program speed increases as a program operation/erase operation is repeatedly performed. Particularly, in an ISPP method of reducing a program start voltage, much time may be required to finish a first verifying operation in an initial step where a few program operations/erase operations are performed. Accordingly, a blind verifying method may be applied in accordance with the number of the program operation/erase operations. | 2009-11-19 |
20090285021 | NON-VOLATILE MEMORY DEVICE AND METHOD OF VERIFYING A PROGRAM OPERATION IN THE SAME - A page buffer in a non-volatile memory device for performing a program operation for a multi level cell having m bits includes first register to mth registers, a first data transmitting circuit configured to transmit data stored in a first node or a second node of the first register to a sensing node in accordance with a first data transmitting signal or a second data transmitting signal, and (m-1) sensing node discharging circuits configured to couple the sensing node to ground in accordance with data stored in a first node or a second node of each of the second to mth registers, and a first sensing node discharge signal or a second sensing node discharge signal. | 2009-11-19 |
20090285022 | Memory programming method - A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage. | 2009-11-19 |
20090285023 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page. | 2009-11-19 |
20090285024 | FLASH MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A verify voltage may be changed into a plurality of voltage levels based upon a logic state of each of the memory cells and characteristics or logic states of other memory cells (e.g., adjacent) to each of the memory cells. | 2009-11-19 |
20090285025 | Method of Controlling a Program Control of a Flash Memory Device - A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis. | 2009-11-19 |
20090285026 | PROGRAM AND VERIFY METHOD OF NONVOLATILE MEMORY DEVICE - A program and verify method of a nonvolatile memory device, which can minimize the time taken for program and verify operations. The program and verify method includes precharging an output terminal of a block selector to a second level, making the output terminal of the block selector float, and, in the state where the output terminal floats, sequentially applying a program voltage and a verify voltage through a global word line. | 2009-11-19 |
20090285027 | Non-volatile memory devices and methods of operating non-volatile memory devices - A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line. | 2009-11-19 |
20090285028 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - The present invention relates to a method of programming a nonvolatile memory device. A method of programming a nonvolatile memory device in accordance with an aspect of the present invention can include performing a program operation on a first page, counting a program pulse application number until the program operation on the first page is completed, comparing the counted program pulse application number and a critical value and resetting a program start voltage based on the comparison result, and performing a program operation on a second page using the reset program start voltage. | 2009-11-19 |
20090285029 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 2009-11-19 |
20090285030 | MULTI-BIT NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME - A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node. | 2009-11-19 |
20090285031 | SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT - A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface. | 2009-11-19 |
20090285032 | Self pre-charging and equalizing bit line sense amplifier - A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors. | 2009-11-19 |
20090285033 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is constituted of a plurality of fuses (or anti-fuses) used for internal voltage adjustment or timing adjustment after manufacturing, a selector for sequentially selecting the fuses, and a single-direction latch circuit for latching a fuse breakdown determination result which is produced by determining whether or not each fuse selected by the selector is broken down and which is varied in a single direction from the low level to the high level or in a single direction from the high level to the low level. The semiconductor memory device allows the fuse breakdown determination to progress with a high reliability by use of a relatively small chip area and to cope with a failure in which one or more fuses are accidentally short-circuited to an unwanted potential. | 2009-11-19 |
20090285034 | LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that combines outputs of first latch circuits; a second wired-OR circuit that combines outputs of second latch circuits; a gate circuit that combines outputs of the first and second wired-OR circuits; and reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit. According to the present invention, as compared to a case that outputs of all the latch circuits are wired-OR connected, output loads are more reduced. Thus, a high signal quality can be obtained. | 2009-11-19 |
20090285035 | Pipelined wordline memory architecture - A method is provided for reducing semiconductor memory wordline propagation delays of long wordlines by inserting pipeline registers in the wordlines between groups of memory cells. | 2009-11-19 |
20090285036 | Fuse data read circuit having control circuit between fuse and current mirror circuit - A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided between the current mirror circuit and the fuse data holding unit. The bias voltage generating circuit applies the bias voltage to the control circuit. | 2009-11-19 |
20090285037 | INTERLEAVING CHARGE PUMPS FOR PROGRAMMABLE MEMORIES - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 2009-11-19 |
20090285038 | INTERLEAVING CHARGE PUMPS FOR PROGRAMMABLE MEMORIES - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 2009-11-19 |
20090285039 | METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WRITE ASSIST ON COLUMN SELECTED SRAM CELLS - A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read. | 2009-11-19 |
20090285040 | Semiconductor Memory Device - A semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of sub arrays. Each sub array includes a plurality of memory cells. The memory cell includes a pair of storage nodes that are complementary to each other. One storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a global bit-line. The other storage node constituting the pair of storage nodes in each of the memory cells in each of the sub arrays is connected to a local bit-line. The global bit-line is a bit-line connected in common to the plurality of the sub arrays. The local bit-line is provided for each of the sub arrays. | 2009-11-19 |
20090285041 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF WRITING DATA THERETO - A non-volatile semiconductor storage device includes: a plurality of memory cells storing information based on a change in resistance value; and a plurality of first and second wirings connected to the plurality of memory cells and activated in reading data from and writing data to a certain one of the memory cells. Each of the memory cells includes: an irreversible storage element storing information based on a change in resistance value associated with breakdown of an insulation film; and a voltage booster circuit receiving an input of a voltage-boost clock performing clock operation in writing data to a certain one of the memory cells and applying a voltage-boosted signal boosted based on the voltage-boost clock to one end of the irreversible storage element. | 2009-11-19 |
20090285042 | Memory interface circuit and memory system including the same - The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal. | 2009-11-19 |
20090285043 | Block Repair Scheme - Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows. | 2009-11-19 |
20090285044 | TESTING A MEMORY DEVICE HAVING FIELD EFFECT TRANSISTORS SUBJECT TO THRESHOLD VOLTAGE SHIFTS CAUSED BY BIAS TEMPERATURE INSTABILITY - A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level. | 2009-11-19 |
20090285045 | Area Efficient First-In First-Out circuit - A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a size of N/X by M. Control logic receives the data from the write port, writes the data into at least one of the X memories in a serial write manner, reads the data from at least one of the X memories in a serial read manner, and provides the data to the read port. The control logic also disables power to selected ones of the X memories when they are not being written to or read from. The FIFO memory is configured to both read and write the data at a given time to a given one of the X memories. | 2009-11-19 |
20090285046 | METHOD TO REDUCE LEAKAGE OF A SRAM-ARRAY - A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode. | 2009-11-19 |
20090285047 | ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE - A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals. | 2009-11-19 |
20090285048 | COUNTER CIRCUIT, LATENCY COUNTER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM - To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate. | 2009-11-19 |
20090285049 | FIXING OF SCREENING MEDIA - An adapter system for fixing different screening media to a vibrating screen. By way of the adapter system, different side hold downs used for different screening media may be fixed to a wall of the vibrating screen without any modifications of the wall. The adapter system includes an insert to be placed in an opening of the wall. An adapter is attached to the insert at a desired height in relation to the insert. The insert has a number of parallel grooves co-operating with parallel ribs on the adapter in order to attach the adapter to the insert. | 2009-11-19 |
20090285050 | MIXING MACHINE FOR AGITATING AND MINGLING MATERIALS - A mixing machine for agitating and mingling materials is disclosed. The mixing machine comprises a base and a driving device disposed on the base, and the driving device is connected to a rotary bracket and has a fixing portion with a container for receiving a mixture of materials mounted thereon, such that the mixture of materials may be agitated and mingled while the driving device drives the rotary bracket. A transmission device is disposed between the driving device and the rotary bracket, and the transmission device comprises a first spur gear, a second spur gear, and a bevel gear intermeshed which are successively intermeshed, wherein the first spur gear and the second spur gear are meshed together and fitted to parallel axles, the second spur gear and the bevel gear are meshed together, and the bevel gear connects to the fixing portion. | 2009-11-19 |
20090285051 | SENSING AND ACTUATING IN MARINE DEPLOYED CABLE AND STREAMER APPLICATIONS - Methods and related systems are described for use with hydraulic fracturing and other oilfield applications. A tool body is positioned in a wellbore at a location near a subterranean rock formation being fractured. The tool body contains a plurality of deployable continuous fibers. At least some of the deployable continuous fibers are deployed into fractures within a subterranean rock formation. Each deployed fiber is continuous from the tool body to the rock formation. The number of deployable continuous fibers provides sufficient redundancy to make at least a target measurement relating to the fracturing process. | 2009-11-19 |
20090285052 | Methods of enhancing separation of primary reflection signals and noise in seismic data using radon transformations - Improved methods of processing seismic data which comprise amplitude data assembled in the offset-time domain in which primary reflection signals and noise overlap are provided for. The methods include the step of enhancing the separation between primary reflection signals and coherent noise by transforming the assembled data from the offset-time domain to the time-slowness domain. More specifically, the assembled amplitude data are transformed from the offset-time domain to the time-slowness domain using a Radon transformation according to an index j of the slowness set and a sampling variable Δp; wherein | 2009-11-19 |
20090285053 | VELOCITY ANALYSIS FOR VSP DATA - A method for providing a velocity profile for a subsurface region that includes the reflective interfaces, the method comprising the steps of: providing a set of data comprising signals transmitted by a transmitter and collected at a receiver, wherein the data include a primary signal that has been reflected off of one of the reflective interfaces and a multiply-reflected signal that has been reflected off of at least two of the reflective interfaces, providing a velocity model for the subsurface region, using the velocity model and the primary signal to construct a first image of the subsurface region, using the velocity model and the multiply-reflected signal to construct a second image of the subsurface region, determining a measure of match between the first and second images, adjusting the velocity model based on this measure, and repeating the steps until the measure of match attains a desired level. | 2009-11-19 |
20090285054 | Downhole Telemetry System and Method - A downhole telemetry system for use in a wellbore including borehole fluid. The system includes a stator including flow channels though the stator and a rotor including flow channels though the rotor. The rotor is rotatable on a drive shaft by the force of the borehole fluid flowing through the rotor. The rotation of the rotor creates pressure variations in the borehole fluid related to the movement of the rotor channels relative to the stator channels, thus forming a carrier wave. A regulating system adjusts the amount of fluid force on the rotor for a given flow rate of borehole fluid to maintain the frequency of the carrier wave within a range of a target frequency. Also, an alternator drivable by the rotation of the drive shaft provides power to the system. The system also includes an encoder capable of adjusting the rotation of the rotor to modulate the carrier wave. | 2009-11-19 |
20090285055 | SENSOR FOR AIRBORNE SHOOTER LOCALIZATION SYSTEM - A sensor assembly suitable for use in an airborne shooter localization system. The sensor assembly has a pressure sensor subassembly with a pressure transducer positioned to detect pressure variations associated with a shock wave from a passing projectile or the muzzle blast following the shock wave. To substantially increase the signal to noise ratio for measurements of the shock wave, the pressure sensor subassembly attenuates pressure fluctuations triggered by turbulent airflow over the surface of the subassembly more than it attenuates the shock wave. This preferential attenuation is provided by separating the pressure transducer from the surface of the sensor assembly by a cavity large enough that the pressure fluctuations are substantially attenuated as they propagate across the cavity. Additionally, features of a housing that holds the pressure sensor subassembly facilitate use on an aircraft. Those features include flexibility that allows the sensor assembly to conform to curved surfaces, a skin that provides resistance to environmental conditions and allows the sensor assembly to be attached with an adhesive, and a body region that provides high vibrational impedance to prevent low frequency mechanical vibrations from being coupled to the pressure transducer. | 2009-11-19 |
20090285056 | ELECTRONIC DEVICE AND METHOD PROVIDING IMPROVED WORLD CLOCK FEATURE - An improved electronic device and method provide an improved clock feature that includes an improved world clock function. | 2009-11-19 |
20090285057 | Stepping motor drive circuit and analog electronic clock - The present invention aims to generate a proper drive pulse in accordance with a motor. A plurality of duty generating circuits each generates a signal at a duty ratio different from one another. A main drive pulse generating circuit uses an output signal of the plurality of the duty generating circuits to generate a drive pulse, and a motor driver circuit rotates and drives a stepping motor. The stepping motor drives the hands of a display unit. When a rotation detecting circuit detects that the stepping motor is not rotated, a correction drive pulse generating circuit uses a signal from one of the duty generating circuits to output a correction drive pulse, and the motor driver circuit forcedly rotates and drives the motor by the correction drive pulse. | 2009-11-19 |
20090285058 | MASTERING DEVICE, DISC MANUFACTURING METHOD, DISC-SHAPED RECORDING MEDIUM, DISC REPRODUCTION DEVICE, AND DISC REPRODUCTION METHOD - Second digital information serving as copyright protection information can be stably and reliably read without any effect of a defect or pit missing on a disk-shaped recording medium. | 2009-11-19 |
20090285059 | APPARATUS FOR INITIALIZING AND METHOD OF MANUFACTURING OPTICAL DISC, AND INITIALIZATION REFERENCE PLATE - An embodiment of the present invention includes rotating an integrated disc formed by temporarily fixing an initialization reference plate to an uninitialized optical disc that is an optical disc to be irradiated with a light beam of light having a predetermined or higher intensity to record information as a recording mark. The initialization reference plate has a reference part that reflects at least a part of a servo light beam of servo light intended for servo control. The reference part contains information that indicates the position of a track of the optical disc for the recording mark to be formed on, in the form of a track of pit-and-projection pattern. | 2009-11-19 |
20090285060 | METHOD OF ADJUSTING GAIN BALANCE OF OPTICAL TRANSDUCER - A method of adjusting gain balance of an optical transducer includes the following steps. First, two external gains are predetermined. Next, the projection position of a reflection spot is adjusted toward one side of the optical transducer, and the current output values of the optical transducer each corresponding to one of the external gains are measured, respectively, Next, the projection position of the reflection spot is adjusted toward the other side of the optical transducer, and the current output values of the optical transducer each corresponding to one of the external gains are measured, respectively. Then, a gain balance value of the optical transducer is adjusted, and is set as the external gain. Next, the projection position of the reflection spot is adjusted. Finally, the projection position of the reflection spot, where the current output value of the transducer is equal to 0, is locked to complete the adjustment rapidly. | 2009-11-19 |
20090285061 | DEVICE AND METHOD FOR REPRODUCING DIGITAL SIGNAL AND DEVICE AND METHOD FOR RECORDING DIGITAL SIGNAL - A technique capable of realizing a power saving in a device for reproducing/recording digital signals by properly controlling a frequency of a clock. The device for reproducing/recording digital signals (device for reproducing an optical disk) includes: a difference comparing circuit for comparing a first parameter (demodulating block counter) updated each time a process for one correcting block is done in a demodulating circuit with a second parameter (error correcting block counter) updated each time a process of one correcting block is done in an error correcting circuit; and a circuit (clock controlling circuit etc.) for switching a frequency of a master clock (MCLK) depending on a comparison result of the difference comparing circuit. Thereby, the frequency of the clock can be switched both of when the demodulation for one correcting block is ended and when the correcting process for one correcting block is ended by using the switched master clock. | 2009-11-19 |
20090285062 | Method for Rearranging Back-Up Data - The invention discloses a method for rearranging back-up data, which first starts rearranging a back-up area when a rewritable optical disc is loaded, reads all available replacing blocks on the back-up area, rearranges the order of the replacing blocks based on the order of addresses of corresponding data blocks on the user data area, writes the rearranged replacing blocks into a planned area of the back-up area, and registers the corresponding information to finish the operation of rearrangement for rapidly reading data. | 2009-11-19 |
20090285063 | DEFECT AREA MANAGEMENT - A multi-layer optical writable disc (D) comprises at least two layers (L | 2009-11-19 |
20090285064 | WRITE ONCE OPTICAL DISC, AND METHOD AND APPARATUS FOR RECOVERING DISC MANAGEMENT INFORMATION FROM THE WRITE ONCE OPTICAL DISC - A write once optical recording medium and a method and apparatus for storing and recovering defect management information to and from the write once optical recording medium are provided. The recording medium includes at least one recording layer, and a data area on the recording layer. The data area includes at least one spare area and a user data area. The spare area contains at least one replacement cluster, each of the replacement clusters storing therein address information of a corresponding defective cluster. | 2009-11-19 |
20090285065 | INFORMATION RECORDING MEDIUM, INFORMATION RECORDING DEVICE AND METHOD, AND COMPUTER PROGRAM - An information recording medium ( | 2009-11-19 |
20090285066 | INFORMATION RECORDING APPARATUS AND METHOD, AND COMPUTER PROGRAM - An information recording apparatus ( | 2009-11-19 |
20090285067 | BACK-UP METHOD FOR DEFECTIVE DATA - A back-up method for defective data includes: first writing a batch of data clusters on a user data area; reading the data clusters to check for defects; planning back-up positions on the back-up area; writing the correct data for the defective data clusters to form a batch of corresponding replacing blocks; reading the replacing blocks to check defects; planning back-up positions on the back-up area; and writing the correct data for the batch of replacing blocks in order until the rewritten replacing blocks do not contain defects. | 2009-11-19 |
20090285068 | DISK OPERATION PROTECTION METHOD AND DISK CONTROLLER - A disk operation protection method and a disk controller are disclosed herein. The method includes: receiving a request for a disk operation; obtaining, by a disk controller, operation control parameters corresponding to the current disk area to be operated, and determining whether to allow operation of the current disk area according to the operation control parameters; if determining that the current disk area is allowed to be operated according to the operation control parameters, performing the disk operation. By implementing the embodiments of the present disclosure, the operation of the data stored in a disk is protected, illegal disk operations such as maliciously intended modification are prevented, the disk is protected in the process of generating data, and the defects of the disk protection mechanism in the prior art are overcome. | 2009-11-19 |
20090285069 | FILE PROTECTION METHOD USED IN SOLID STATE DISC ARRAY SYSTEM - A file protection method is used for preventing files stored in a solid state disc array system from being reproduced unauthorizedly. After a file is produced completely, it is stored in a solid state disc array system connected to an external computer. When the external computer is to execute the files stored in the solid state disc array system, it checks the files and parameters (e.g. key password or serial number) set in the solid state disc array system step by step. Only when all of the parameters are correct and correspond to one another, the files can be executed normally. In this way, the files can be protected from being copied unauthorizedly. | 2009-11-19 |
20090285070 | COPY-PROTECTED OPTICAL STORAGE MEDIA AND METHOD FOR PRODUCING THE SAME - A method is provided for protecting and authenticating data (software programs, games etc) and media (video, audio) from an optical storage media from copyright infringement via a computing system or dedicated hardware while allow said content (especially media and audio) to perform as is on multimedia capable devices (dvd-players) without alteration or modification to the above-said multimedia devices. This method involves control of the layout of the optical disk structure, controlling access to the said layout and allowing for accurate identification of protected disks. It relies on the use of the optical media's lead-in area, program area and lead-out area all for storing certain portions of the system. An access control program is configured to determine access rights, the program area is encoded with data mapped in accordance to the layout scheme and for proper use on a computing system, a software application (layout control logic) is used to provide access to the data of the program area mapped in accordance with the layout scheme. During production of the optical media, the layout of the disc image is manipulated in accordance the layout scheme. | 2009-11-19 |
20090285071 | RECORDING METHOD, RECORDING MEDIUM, AND RECORDING SYSTEM - An information recording medium and an optical recording system allow target information (such as an ad) to be displayed without requiring changes in hardware or physical specifications. The recording medium comprises a recording-limited area in which recording is made possible by canceling the limit after an instruction is issued for displaying the target information. | 2009-11-19 |
20090285072 | METHOD FOR MONITORING AN OPTICAL DISK DRIVE PERFORMANCE QUALITY, OPTICAL DISK DRIVE, OPTICAL DISK DUPLICATOR SYSTEM AND COMPUTER PROGRAM PRODUCT - The invention relates to a method for monitoring an optical disk drive performance quality by determining a laser diode quality indicator for a laser diode arranged in an optical disk drive for scanning an optical disk. The determining includes measuring ( | 2009-11-19 |
20090285073 | PATTERN TRANSFER APPARATUS AND PATTERN TRANSFER METHOD - A pattern transfer apparatus includes a storage-medium-surface detecting unit that detects a foreign substance or defect on a surface of a storage medium and specifies a position and a size of the foreign substance or defect; a relative-position adjusting unit that adjusts a relative position on a contact surface between the surface of the storage medium and a transfer pattern surface of a transfer master, and a relative-position-adjustment instructing unit that calculates an adjusted value of the relative position according to a detection result, and instructs the relative-position adjusting unit to adjust the relative position based on the adjusted value. | 2009-11-19 |
20090285074 | ENHANCED SECURITY OF OPTICAL ARTICLE - An optical article comprising a first file encoded on the optical article comprising data structure information; a second file encoded on the optical article comprising a backup of the first file; wherein at least one of the first file or the second file must be fully readable for the player to read the data on the optical article; and a mark disposed on at least a portion of the optical article where the first file is encoded and at least a portion of the optical article where the second file is encoded; wherein the mark comprises an optical state change material; wherein the optical state change material undergoes a change in its optical state when exposed to an activation signal selected from one or more of a laser, thermal energy, infrared rays, X-rays, gamma rays, microwaves, visible light, ultraviolet light, ultrasound waves, radio frequency waves, electrical energy, chemical energy, magnetic energy, and mechanical energy; wherein the optical article is transformed from a pre-activated state to an activated state when an authorized activation method is used; and wherein the optical article is transformed from a pre-activated state to an incorrectly activated state when an unauthorized activation method is used. | 2009-11-19 |
20090285075 | ENHANCED SECURITY OF OPTICAL ARTICLE - An optical article comprising a mark disposed on the optical article; wherein the mark comprises an optical state change material; wherein the optical state change material undergoes a change in its optical state when exposed to an activation signal selected from one or more of a laser, thermal energy, infrared rays, X-rays, gamma rays, microwaves, visible light, ultraviolet light, ultrasound waves, radio frequency waves, electrical energy, chemical energy, magnetic energy, and mechanical energy; wherein the optical article is transformed from a pre-activated state to an activated state when an authorized activation method is used; and wherein the optical article is transformed from a pre-activated state to an incorrectly activated state when an unauthorized activation method is used. A method and a system for changing the functionality of the optical article are also provided. | 2009-11-19 |
20090285076 | Diffractive optical element and method of designing the same - A transmissive or reflective diffractive optical element, comprising: a substrate having a top surface, the top surface being etched into a pattern, the pattern including a periodic surface pattern of grooves formed such that when an incoming light beam is shone onto the top surface, the incoming light beam will be split into a plurality of diffracted light beams, the plurality of diffracted light beams including a plurality of primary diffracted order beams and a plurality of secondary diffracted order beams, wherein the primary diffracted order beams have a primary aggregate efficiency above ninety percent, wherein the plurality of secondary diffracted order beams have a secondary aggregate efficiency of lower than ten percent, and wherein a maximum power of the primary diffracted order beams and a minimum power of the primary diffracted order beams differ by at least ten percent of an average power of the primary diffracted order beams. | 2009-11-19 |
20090285077 | OPTICAL PICKUP DEVICE AND OPTICAL RECORDING MEDIUM INFORMATION REPRODUCTION DEVICE - The present invention provides an optical pickup device and optical recording medium information reproduction device that are capable of reproducing information that is recorded on a plurality of kinds of optical discs having different track pitches. With the present invention, an optical pickup device generates a main beam and sub beams that are made up from pairs of semi sub beams, such that the distance in the radial direction between center positions of a pair of semi sub spots on an optical disc where a pair of semi sub beams are formed is an odd multiple of half the track pitch of the optical disc, and the distance in the radial direction between center positions of semi sub spots that correspond to another pair of sub semi sub beams is an odd multiple of half the track pitch of another optical disc. | 2009-11-19 |
20090285078 | OBJECTIVE LENS, OPTICAL PICKUP DEVICE, AND OPTICAL RECORDING/REPRODUCING APPARATUS - An objective lens for converging light emitted from a light source onto an optical recording medium to record and reproduce information consists of a single lens that has at least one aspheric surface. The following conditional expressions (1) and (2) are satisfied: | 2009-11-19 |
20090285079 | OBJECTIVE LENS, OPTICAL PICKUP DEVICE, AND OPTICAL RECORDING/REPRODUCING APPARATUS - An objective lens for converging light emitted from a light source on an optical recording medium to record and reproduce information consists of a single lens having at least one aspheric surface. The following conditional expressions ( | 2009-11-19 |
20090285080 | PICKUP LENS WITH PHASE COMPENSATOR AND OPTICAL PICKUP APPARATUS USING THE SAME - A pickup lens with a phase compensator is composed of a condenser lens and a phase compensator. At least one surface of the condenser lens has a step-like annular zone structure to compensate wavefront aberration generated when recording and reproducing data on an information recording medium having a substrate thickness of t | 2009-11-19 |
20090285081 | APPARATUS AND METHOD FOR RECORDING INFORMATION IN OPTICAL STORAGE MEDIUM - To record information in an optical storage medium, a pulsed laser beam produced by a laser light source is split into first and second pulsed laser beams by a beam splitter. The first pulsed laser beam to be concentrated in the optical storage medium supported by a medium support part is interrupted and resumed by a shutter. The second pulsed laser beam is received by a photosensor which produces a detection signal. A controller includes a sync-generator configured to receive the detection signal from the photosensor and to generate a synchronizing signal based upon the received detection signal, and a shutter driver configured to drive the shutter in synchronization with timing represented by the synchronizing signal generated by the sync-generator. | 2009-11-19 |
20090285082 | ELECTRIC FIELD READ/WRITE HEAD, METHOD OF MANUFACTURING THE ELECTRIC FIELD READ/WRITE HEAD, AND INFORMATION STORAGE DEVICE INCLUDING THE ELECTRIC FIELD READ/WRITE HEAD - An electric field head includes a body portion and a read head having a channel layer provided on an air bearing surface (ABS) of the body portion facing a recording medium and a source and a drain contacting both ends of the channel layer. The electric field head is manufactured by defining a head forming portion of a substrate, separating the head forming portion from the substrate, forming an ABS pattern on a side surface of the separated head forming portion, and forming a channel layer for a read head on a surface of the head forming portion where the ABS pattern is formed. An information storage device includes a ferroelectric recording medium and the electric field head. | 2009-11-19 |
20090285083 | ACTIVATION SYSTEM AND METHOD FOR ACTIVATING AN OPTICAL ARTICLE - An optical article comprising a plurality of optically detectable marks disposed on a surface of the optical article; a removable electrical device disposed on the surface of the optical article; wherein the electrical device is operatively coupled to the optical article; and wherein the electrical device is configured to interact with an activation signal when brought in direct contact with a communication device that applies the activation signal to the electrical device. A removable electrical device is also provided. A system and a method for activation are also provided. | 2009-11-19 |
20090285084 | OPTICAL DISK WITH PLURAL SUBSTRATES - An optical disk of the present invention includes a first substrate having a signal area on a principal plane and a central hole, and a second substrate that is transparent and attached to the first substrate. The second substrate is thinner than the first substrate, and has a central hole whose diameter is larger than that of the first substrate. The first substrate and the second substrate are attached to each other with radiation curable resin (adhesive member) disposed therebetween so as to extend at least from an inner peripheral edge of the second substrate to an outer peripheral edge thereof. | 2009-11-19 |
20090285085 | OPTICAL DISC RECORDING DEVICE, DATA RECORDING METHOD, AND DATA RECORDING PROGRAM - An optical disc recording device includes: an optical disc device to record optical recording data onto an optical disc; a recording data assigning unit to divide a recording region on the optical disc into multiple divisions, part as a data region, assign optical recording data thereto; a redundancy data calculating unit to calculate redundancy data for restoring recorded data; a redundancy data assigning unit to take divided regions other than the data region as a redundancy region, and assign the corresponding redundancy data thereto; a recording/playing device having a recording capacity greater than the data region; and a recording control unit configured to record optical recording data in the data region and also at least a part thereof in the recording/playing device, cause the recording/playing device to play the optical recording data recorded therein at the time of calculating redundancy data, and record calculated redundancy data in the redundancy region. | 2009-11-19 |
20090285086 | OFDM Receiver and OFDM Receiving Method - An FFT unit generates a frequency domain signal by converting an OFDM signal using Fourier transform. A delay amount calculation unit generates a delay profile of the OFDM signal. The control determination unit detects a main wave and an interference wave using the delay profile. When the time difference between the main wave and a preceding wave is larger than a guard interval of the OFDM signal, an FFT window control unit sets the start position of the FFT window at a position shifted forward from the symbol start position of the main wave by an amount corresponding to the guard interval. | 2009-11-19 |
20090285087 | COMMUNICATION APPARATUS AND ABNORMALITY RESTORATION METHOD - According to one embodiment, a communication apparatus includes an acquisition module selectively acquires equipment information showing communication equipment including the same program as the program recorded on the first recording medium to record the equipment information in a second recording medium differing from the first recording medium, and a failure restoration module obtains a program from communication equipment based on the equipment information recorded on the second recording medium, and start the communication apparatus based on the obtained program, when the communication apparatus cannot start by the program recorded on the first recording medium. | 2009-11-19 |
20090285088 | METHOD, SYSTEM AND APPARATUS OF IMPLEMENTING INTER-SYSTEM COMMUNICATIONS - Methods for implementing inter-system communications includes as follows: a serving base station selects a relay terminal, transmits a neighboring base station access request to the selected relay terminal; the relay terminal receives the neighboring base station access request, and accesses a neighboring base station; the relay terminal receives relay information, and communicates with the serving base station or the neighboring base station based on the relay information. Systems and apparatuses for implementing inter-system communications are also disclosed. With the methods, systems and apparatuses of the embodiments of the present disclosure, the probability of correct receipt of relay information at the neighboring base station may be improved. | 2009-11-19 |
20090285089 | Method and Apparatus for Validating Control and Data Plane Association - A method and apparatus for validating control and data plane association is described. In one embodiment of the invention, a first provider edge (PE) network element negotiates a pseudowire with a second PE network element. The pseudowire is uniquely identifiable between the first and second PE network element with a unique pseudowire identifier. The first PE network element receives OAM (operations, administration, and management) packets each including a pseudowire identifier from the second PE network element over the negotiated pseudowire. If an OAM packet is received with a pseudowire identifier that does not match the negotiated pseudowire, the first PE network element determines a data plane fault is associated with the pseudowire on the second PE network element. However, if the OAM packets include the pseudowire identifier that matches the negotiated pseudowire, the control and data plane association of the second PE network element is validated. Other methods and apparatuses are also described. | 2009-11-19 |
20090285090 | Method and System for Providing User Access to Communication Services, and Related Computer Program Product - A system for providing to users of data communication services access to a communication network providing these services, includes an edge node of the communication network providing these services as well as a packet network, such as, an ethernet connecting the users to the edge node. The packet network is equipped with operation and maintenance procedures for preserving edge connectivity over the packet network. The edge node has associated therewith a backup edge node providing access to the communication network. Preferably, the backup edge node is reachable by the users via the packet network by using an address common to the edge node and the backup edge node associated therewith. In the presence of failure of the edge node, connection is established between the users and the backup edge node by applying the operation and maintenance procedures. Preferably, this, occurs by using the address common to the edge node and the associated backup edge node. | 2009-11-19 |
20090285091 | Open Network Connections - One or more logical network connection points are provided within an electronic communications network. The logical network connections are provided via an interface between one or more connectivity plane devices and a network connected application, service, or control plane function in the electronic communication network. The network connected application, service, or control plane function registers itself as a logical network resident (NR) with a function in the connectivity plane that provides a logical network connection between the network resident and another logical network connection point. | 2009-11-19 |
20090285092 | Video stream admission - A video stream admission method including receiving one or more parameters of a video stream, indicative of a required bandwidth for the video stream, in a plurality of different quality levels and determining based on the received one or more parameters, whether a channel can meet a predetermined condition for each of the plurality of quality levels, according to an available bandwidth of the channel. | 2009-11-19 |
20090285093 | INTERACTIVE MPLS TRAFFIC ENGINEERING - An interactive system and method automates the control and management of routing changes that are focused on specific routes or particular network hot spots. Based on the premise that the user is aware of a particular problem that needs to be solved, the system leads the user through an end-to-end process from the identification of the problem to the generation of configuration instructions for effecting a selected solution. A graphic user interface provides a visualization of the current routing and alternative routings, to facilitate the analysis and selection of an improved routing, if any. Throughout the process, the effect of each proposed routing change on the overall network performance is determined, so that the selection of a preferred solution can be made in the appropriate context, and globally sub-optimal solutions can be avoided. | 2009-11-19 |
20090285094 | Apparatus and method for estimating the fill factor of client input buffers of a real time content distribution - The invention concerns a solution for detecting conditions of dearth and overflow of a client input buffer to a real time content distribution. Said detection is performed upstream of clients through a dynamic estimation of the fill factor of the input buffers of said clients. Thus, it is possible to predict the occurrence of dearth or overflow situations and to take actions such as inserting stored video sequences or storing queueing packets. | 2009-11-19 |
20090285095 | TOKEN BUCKET WITH VARIABLE TOKEN VALUE - Various example embodiments are disclosed. According to an example embodiment, a method may include receiving a token count units instruction, periodically increasing or decreasing a token count based at least in part on a refresh rate, and in response to receiving a packet, decreasing or increasing the token count based at least in part on a size of the packet and the instruction. | 2009-11-19 |
20090285096 | HARDWARE ACCELERATED PROTOCOL STACK FOR MEDIAFLO - Protocol stack layer processing for a MediaFLO™ mobile multimedia multicast system comprising a transmitter comprising a host processor and a host memory component. The processing includes a receiver that receives a wireless data stream comprising a MediaFLO™ mobile multimedia multicast system superframe comprising any of audio, video, and text media frames arranged in multiplexed Multicast Logical Channels (MLCs) and received from the transmitter, wherein each MLC is divided into 16 byte data packets, and wherein each MLC carries up to three logical sub-channels comprising stream | 2009-11-19 |
20090285097 | METHOD AND SYSTEM FOR PROVIDING TRAFFIC ENGINEERING INTERWORKING - An approach is provided for interworking traffic onto a composite transport group (CTG). An attribute associated with a composite transport group is determined based on a characteristic of a traffic flow associated with a label-switched network. The traffic flow is mapped to one or more component connections of the composite transport group based on the attribute. | 2009-11-19 |