47th week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090283797 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 μm. | 2009-11-19 |
20090283798 | Semiconductor device and manufacturing method thereof - A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained. | 2009-11-19 |
20090283799 | Reduced Free-Charge Carrier Lifetime Device - According to one embodiment, a semiconductor device comprises a body of a first conductivity type having a source region and a channel, the body being in contact with a top contact layer. The device also comprises a gate arranged adjacent the channel and a drift zone of a second conductivity type arranged between the body and a bottom contact layer. An integrated diode is formed partially by a first zone of the first conductivity type within the body and being in contact with the top contact layer and a second zone of the second conductivity type being in contact with the bottom contact layer. A reduced charge carrier concentration region is formed in the drift zone having a continuously increasing charge carrier lifetime in the vertical direction so that the charge carrier lifetime is lowest near the body and highest near the bottom contact layer. | 2009-11-19 |
20090283800 | PHOTOELECTROCHEMICAL ETCHING OF P-TYPE SEMICONDUCTOR HETEROSTRUCTURES - A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer. | 2009-11-19 |
20090283801 | BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME - Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap. | 2009-11-19 |
20090283802 | HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE WITH ELECTROSTATIC DISCHARGE RUGGEDNESS - A heterojunction bipolar transistor (HBT) device and system having electrostatic discharge ruggedness, and methods for making the same, are disclosed. An HBT device having electrostatic discharge ruggedness may include one or more emitter fingers including an emitter layer, a transition layer formed over the emitter layer, and an emitter cap layer formed over the transition layer. | 2009-11-19 |
20090283803 | ELECTROMECHANICAL MEMORY ARRAY USING NANOTUBE RIBBONS AND METHOD FOR MAKING SAME - Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes. | 2009-11-19 |
20090283804 | SOLID-STATE IMAGE SENSOR, SOLID-STATE IMAGE SENSING DEVICE, AND METHOD OF PRODUCING THE SAME - It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including: a first conductive type semiconductor layer; a first conductive type pillar-shaped semiconductor layer formed on the first conductive type semiconductor layer; a second conductive type photoelectric conversion region formed on the top of the first conductive type pillar-shaped semiconductor layer, an electric charge amount of the photoelectric conversion region being changed by light; and a high-concentrated impurity region of the first conductive type formed on a surface of the second conductive type photoelectric conversion region, the impurity region being spaced apart from a top end of the first conductive type pillar-shaped semiconductor layer by a predetermined distance, wherein a transfer electrode is formed on the side of the first conductive type pillar-shaped semiconductor layer via a gate insulating film, a second conductive type CCD channel region is formed below the transfer electrode, and a read channel is formed in a region between the second conductive type photoelectric conversion region and the second conductive type CCD channel region. | 2009-11-19 |
20090283805 | BIOSENSOR CONTAINING RUTHENIUM, MEASUREMENT USING THE SAME AND THE APPLICATION THEREOF - A biosensor containing ruthenium, measurement using the same, and the application thereof. The biosensor comprises an extended gate field effect transistor (EGFET) structure, including a metal oxide semiconductor field effect transistor (MOSFET), a sensing unit comprising a substrate, a layer comprising ruthenium on the substrate, and a metal wire connecting the MOSFET and the sensing unit. | 2009-11-19 |
20090283806 | MOSFET WITH ASYMMETRICAL EXTENSION IMPLANT - A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure. | 2009-11-19 |
20090283807 | Anti-Reflection Structures For CMOS Image Sensors - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 2009-11-19 |
20090283808 | Photo Sensor - A photo sensor has an insulator layer for covering a diode stack, and the insulator layer is made of photoresist to reduce a side leakage current. | 2009-11-19 |
20090283809 | Image sensor structure and integrated lens module thereof - An image sensor structure and an integrated lens module thereof are provided. In the image sensor structure with the integrated lens module, the image sensor structure comprises a chip and a lens module. The chip has light-sensing elements, first conducting pads, and a conducting channel. The light-sensing elements are electrically connected to the first conducting pads and the first conducting pads are electrically connected to one end of the conducting channel passing through the chip. The lens module comprises a holder and at least one lens. The holder has a through hole and the lens is embedded in the through hole and integrated with the holder. By using the integrated lens and holder, a manufacturing process of the image sensor structure is simplified and a manufacturing cost of the image sensor structure is reduced. | 2009-11-19 |
20090283810 | Integrated Circuit Arrangements With ESD-Resistant Capacitor and Corresponding Method of Production - A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength. | 2009-11-19 |
20090283811 | Flash memory device and methods of forming the same - A flash memory device and/or methods of forming the flash memory device are provided, the flash memory device including a charge storage gate, a gate pattern over the charge storage gate, and a charge storage metal layer disposed between a side surface of the charge storage gate and the gate pattern. The methods include forming a preliminary charge storage gate pattern and forming a metal layer over a side surface of the preliminary charge storage gate pattern. | 2009-11-19 |
20090283812 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer. | 2009-11-19 |
20090283813 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a method for fabricating a nonvolatile semiconductor memory device including a memory cell being formed in a first region of a semiconductor substrate and a periphery circuit being formed in a second region of the semiconductor substrate, including forming a first gate electrode material film over the semiconductor substrate via a first gate insulator in the first region, etching the first gate electrode material film and the first gate insulator using a mask having a first opening in a first element isolation of the first region, etching the semiconductor substrate to a first depth to form a first isolation groove, forming a first insulation isolation layer in the first isolation groove, forming a second insulator on the first insulation isolation layer and on the first gate electrode, removing the second insulator by anisotropic etching, etching an upper portion of the first gate electrode to a second depth to form a first concave portion on the upper portion of the first gate electrode, etching the first side-wall film and the first insulation isolation layer to a depth at a bottom surface of the first concave portion, forming a second gate insulator on the upper portion of the first gate electrode, and forming a second gate electrode material film on the second gate insulator. | 2009-11-19 |
20090283814 | SINGLE-POLY NON-VOLATILE MEMORY CELL - A non-volatile memory cell includes an ion well of a semiconductor substrate; a first half-transistor having a firs select gate, a first diffusion region in the ion well, and a first gate dielectric layer between the first select gate and the ion well; a second half-transistor disposed adjacent to the first half-transistor, wherein the second half-transistor has a second select gate spaced apart from the first select gate, a second diffusion region in the ion well, and a second gate dielectric layer between the second select gate and the ion well. The first and second half-transistors are mirror-symmetrical to each other. | 2009-11-19 |
20090283815 | SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit. | 2009-11-19 |
20090283816 | BAND ENGINEERED HIGH-K TUNNEL OXIDES FOR NON-VOLATILE MEMORY - A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials. | 2009-11-19 |
20090283817 | FLOATING GATE STRUCTURES - Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon. | 2009-11-19 |
20090283818 | Flash Memory Device and Method of Fabricating the Same - A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench. | 2009-11-19 |
20090283819 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a substrate; a plurality of dielectric films and electrode films which are alternately stacked on the substrate and have a through hole penetrating in the stacking direction; a semiconductor pillar formed inside the through hole; and a charge storage layer provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction. | 2009-11-19 |
20090283820 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell array having a cell transistor and a selective transistor provided on a semiconductor substrate. The cell transistor includes a tunnel insulation film, a charge accumulation layer, a block insulation film, and a gate electrode on the substrate. The charge accumulation layer is disconnected between adjacent cell transistors. The selective transistor includes a gate insulation film and a gate electrode formed of the same material as the material of the block insulation film on the substrate. A step is provided on a surface of the substrate between the cell transistor and the selective transistor, such that the step is positioned higher on a side of the cell transistor and lower on a side of the selective transistor. | 2009-11-19 |
20090283821 | NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - Isolation trenches are formed in the main surface of a semiconductor substrate, and isolation regions. are embedded in these trenches. First insulating films, charge storage layers, a second insulating film, and a control gate are formed on the main surface of the semiconductor substrate sectioned by the isolation regions. Shielding layers are arranged in the isolation regions in such a manner that their bottom portions are lower than the channel regions and their upper portions are higher than at least the main surface of the semiconductor substrate to provide an electric and magnetic shield between their storage layers and channel regions of adjacent memory cells. | 2009-11-19 |
20090283822 | NON-VOLATILE MEMORY STRUCTURE AND METHOD FOR PREPARING THE SAME - A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure formed by performing a first thermal oxidation process to form a high-k dielectric layer on a substrate, forming a metal-containing semiconductor layer including silicon or germanium on the high-k dielectric layer, forming a silicon layer on the metal-containing semiconductor layer, and performing a second thermal oxidation process to convert the metal-containing semiconductor layer to a silicon-oxy-nitride layer with embedded metallic nano-dots, wherein at least one of the first thermal oxidation process and the second thermal oxidation process is performed in a nitrogen-containing atmosphere. | 2009-11-19 |
20090283823 | Semiconductor device and method of manufacturing semiconductor device - A semiconductor device includes: a semiconductor layer; a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer; a body region of a second conductivity type formed in the semiconductor layer to be in contact with the first conductivity type region; a trench formed by digging the semiconductor layer from the surface thereof to pass through the body region so that the deepest portion thereof reaches the first conductivity type region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode buried in the trench through the gate insulating film; a source region of the first conductivity type formed in a surface layer portion of the semiconductor layer on a side in a direction orthogonal to the gate width with respect to the trench to be in contact with the body region; and a high-concentration region of the second conductivity type, formed in the body region on a position opposed to the trench in the direction orthogonal to the gate width, having a higher second conductivity type impurity concentration than that of the periphery thereof. | 2009-11-19 |
20090283824 | COOL IMPACT-IONIZATION TRANSISTOR AND METHOD FOR MAKING SAME - In one embodiment, the disclosure relates to a low-power semiconductor switching device, having a substrate supporting thereon a semiconductor body; a source electrode coupled to the semiconductor body at a source interface region; a drain electrode coupled to the semiconductor body at a drain interface region; a gate oxide film formed over a region of the semiconductor body, the gate oxide film interfacing between a gate electrode and the semiconductor body; wherein at least one of the source interface region or the drain interface region defines a sharp junction into the semiconductor body. | 2009-11-19 |
20090283825 | HIGH SPEED ORTHOGONAL GATE EDMOS DEVICE AND FABRICATION - An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (C | 2009-11-19 |
20090283826 | Semiconductor Device and Method of Forming High Voltage SOI Lateral Double Diffused MOSFET with Shallow Trench Insulator - A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator. | 2009-11-19 |
20090283827 | Formation Of A MOSFET Using An Angled Implant - A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n | 2009-11-19 |
20090283828 | Reduced Floating Body Effect Without Impact on Performance-Enhancing Stress - A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region. | 2009-11-19 |
20090283829 | FINFET WITH A V-SHAPED CHANNEL - A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the height of the fin are greater that the width of the fin) and an elongated gate conductor on the planar upper surface of the substrate. The length and the height of the gate conductor are greater than the width of the gate conductor. The fin comprises a center section comprising a semiconducting channel region and end sections distal to the channel region. The end sections of the fin comprise conductive source and drain regions. The gate conductor covers the channel region of the fin. The sidewalls of the channel region comprise a different crystal orientation than the sidewalls of the source and drain regions. | 2009-11-19 |
20090283830 | DUAL METAL GATE SELF-ALIGNED INTEGRATION - A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure. | 2009-11-19 |
20090283831 | Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies - An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration. | 2009-11-19 |
20090283832 | SEMICONDUCTOR DEVICE - A semiconductor device, which is connected to a protected device and protects a protected device, includes a semiconductor layer provided on an insulating film; a plurality of source layers which is formed in the semiconductor layer and extends in a first direction; a plurality of drain layers which is formed in the semiconductor layer and extends along with the source layers; a plurality of body regions which is provided between the source layers and the drain layers in the semiconductor layer and extends in the first direction; and at least one body connecting part connecting the plurality of body regions, wherein a first width between the source layer and the drain layer at a first position is larger than a second width between the source layer and the drain layer at a second position, the second position is closer to the body connecting part than the first position. | 2009-11-19 |
20090283833 | Integrated circuits having a contact structure having an elongate structure and methods for manufacturing the same - In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore, the contact structure may be arranged such that the length direction of the contact structure forms a non-zero angle with the first direction of the active area. | 2009-11-19 |
20090283834 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A MOS semiconductor device including MOSFETs each of which has a gate portion formed on a semiconductor substrate and source/drain regions includes sidewall insulating films formed on the side portions of the gate portions in the gate length direction, alloy layers formed on the source/drain regions, taper adjusting insulating films that are formed on the side portions of the sidewall insulating films and in which a taper angle made between a cross section thereof in the gate length direction and the substrate surface is set smaller than a taper angle made between the sidewall insulating film and the substrate surface, a stress-causing insulating film that applies strains to channels and is formed to cover the gate portions, sidewall insulating films and taper adjusting insulating films, and an interlayer insulating film formed on the stress-causing insulating film. | 2009-11-19 |
20090283835 | METHOD FOR FABRICATING A DUAL WORKFUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions. | 2009-11-19 |
20090283836 | CMOS STRUCTURE INCLUDING PROTECTIVE SPACERS AND METHOD OF FORMING THEREOF - The present invention provides a semiconductor device includes a substrate including a semiconducting region and isolation regions, a gate structure including a high-k gate dielectric layer atop the semiconducting region of the substrate and a metal gate conductor layer atop the high-k gate dielectric; protective nitride spacers enclosing the high-k gate dielectric layer between the metal gate conductor layer and the semiconducting region of the substrate, the protective nitride spacers separating the isolation regions from the high-k dielectric; and a polysilicon gate conductor overlying the metal gate conductor layer and enclosing the protective nitride spacers between at least the high-k dielectric layer, the semiconducting region, and a portion of the polysilicon gate conductor. | 2009-11-19 |
20090283837 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor. | 2009-11-19 |
20090283838 | Fabrication of self-aligned CMOS structure - A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate. | 2009-11-19 |
20090283839 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE - In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained. | 2009-11-19 |
20090283840 | METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR - A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode. | 2009-11-19 |
20090283841 | SCHOTTKY DEVICE - An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer. | 2009-11-19 |
20090283842 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate comprising first and second transistor regions that are isolated by an element isolation region; a first impurity diffusion suppression layer formed on the semiconductor substrate in the first transistor region; a second impurity diffusion suppression layer formed on the semiconductor substrate in the second transistor region, and having a thickness larger than that of the first impurity diffusion suppression layer; a first crystal layer formed on the first impurity diffusion suppression layer; a second crystal layer formed on the second impurity diffusion suppression layer; a first gate electrode formed on the first crystal layer via a first gate insulating film; a second gate electrode formed on the second crystal layer via a second gate insulating film; a first channel region formed in a region in the semiconductor substrate, the first impurity diffusion suppression layer and the first crystal layer below the first gate electrode in the first transistor region, and containing a first p-type impurity; a second channel region formed in a region in the semiconductor substrate, the second impurity diffusion suppression layer and the second crystal layer below the second gate electrode in the second transistor region, and containing a second p-type impurity; first source/drain regions formed on both sides of the first channel region; and second source/drain regions formed on both sides of the second channel region; wherein a concentration of the first p-type impurity in a region of the first channel region in the first crystal layer is lower than that in a region of the first channel region in the semiconductor substrate; and a concentration of the second p-type impurity in a region of the second channel region in the second crystal layer is lower than that in a region of the second channel region in the semiconductor substrate. | 2009-11-19 |
20090283843 | NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and drain metallization formed above the drain region. The lightly-doped source region remains under the first spacer while the lightly-doped drain region remains under the second spacer and extends over the first distance to the drain region. The distance between the first edge of the conductive gate to the source contact opening is the same as the distance between the second edge of the conductive gate to the drain contact opening. | 2009-11-19 |
20090283844 | PROCESS OF FABRICATING MICROFLUIDIC DEVICE CHIPS AND CHIPS FORMED THEREBY - A process for fabricating multiple microfluidic device chips. The process includes fabricating multiple micromachined tubes in a semiconductor device wafer. The tubes are fabricated so that each tube has an internal fluidic passage and an inlet and outlet thereto defined in a surface of the device wafer. The device wafer is then bonded to a glass wafer to form a device wafer stack, and so that through-holes in the glass wafer are individually fluidically coupled with the inlets and outlets of the tubes. The glass wafer is then bonded to a metallic wafer to form a package wafer stack, so that through-holes in the metallic wafer are individually fluidically coupled with the through-holes of the glass wafer. Multiple microfluidic device chips are then singulated from the package wafer stack. Each device chip has a continuous flow path for a fluid therethrough that is preferably free of organic materials. | 2009-11-19 |
20090283845 | SENSING APPARATUS WITH PACKAGING MATERIAL AS SENSING PROTECTION LAYER AND METHOD OF MANUFACTURING THE SAME - A sensing apparatus includes a holding substrate, a sensing chip and a protection layer. The sensing chip is mounted on the holding substrate and electrically connected to the holding substrate. The sensing chip has a sensing region and a non-sensing region other than the sensing region. The sensing region senses image data of an object and thus generates a sensed signal outputted to the holding substrate. The protection layer is formed by a packaging material and is simultaneously processed and integrally formed to cover the sensing region and the non-sensing region of the sensing chip and the holding substrate. The protection layer has an exposed upper surface, which has one portion serving as a sensing surface in contact with the object. The entire protection layer is composed of the same material. | 2009-11-19 |
20090283846 | BACKSIDE CONTROLLED MEMS CAPACITIVE SENSOR AND INTERFACE AND METHOD - Described herein is the sense element assembly for a capacitive pressure sensor and method for creating same that has increased sensitivity despite the parasitic capacitance that is created. The capacitive sensor element assembly, comprises a first semiconductive layer, and a first conductive layer, a first dielectric layer into which a cavity has been formed, the dielectric layer lying between the first semiconductive layer and the first conductive layer, wherein an electrical connection is made to the second conductive layer. A preferred method for fabricating a capacitive sensor assembly of the present invention comprises the steps of forming a dielectric layer on top of a conductive handle wafer; creating at least one cavity in the dielectric layer, bonding a thin semiconductive layer to the dielectric layer and connecting an operational amplifier to the input of the capacitive sensor assembly to overcome the parasitic capacitance formed during fabrication. | 2009-11-19 |
20090283847 | SEMICONDUCTOR PACKAGE INCLUDING THROUGH-HOLE ELECTRODE AND LIGHT-TRANSMITTING SUBSTRATE - An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate. | 2009-11-19 |
20090283848 | Photodiode Assembly With Improved Electrostatic Discharge Damage Threshold - A photodiode with an improved electrostatic damage threshold is disclosed. A Zener or an avalanche diode is connected in parallel to a photodiode. Both diodes are integrated into the same photodiode housing. The diodes can be mounted on a common header or onto each other. An avalanche photodiode and an avalanche diode can be fabricated on a common semiconductor substrate. A regular p-n diode connected in series, cathode-to-cathode or anode-to-anode, to a Zener diode, forms a protection circuit which, when connected in parallel to a photodiode, provides a smaller electrical capacity increase as compared to a simpler circuit consisting just of a Zener or an avalanche diode. | 2009-11-19 |
20090283849 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure. | 2009-11-19 |
20090283850 | OPTICAL SENSOR AND METHOD OF MAKING THE SAME - An optical sensor includes a silicon-rich dielectric photosensitive device and a read-out device. The silicon-rich dielectric photosensitive device includes a first electrode, a second electrode, and a photosensitive silicon-rich dielectric layer disposed therebetween. The photosensitive silicon-rich dielectric layer includes a plurality of nanocrystalline silicon crystals therein. The read-out device is electrically connected to the first electrode of the silicon-rich dielectric photosensitive device for reading out opto-electronic signals transmitted from the photo-sensitive silicon-rich dielectric layer. | 2009-11-19 |
20090283851 | NOVEL SCHOTTKY DIODE FOR HIGH SPEED AND RADIO FREQUENCY APPLICATION - A semiconductor diode that eliminates leakage current and reduces parasitic resistance is disclosed. The semiconductor diode comprises a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate, wherein the semiconductor layer includes a first dopant and a first well with a Schottky region; and a polysilicon device positioned above the semiconductor layer and adjacent to the first well with the Schottky region. | 2009-11-19 |
20090283852 | Stress-Inducing Structures, Methods, and Materials - Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material. | 2009-11-19 |
20090283853 | Programmable Devices and Methods of Manufacture Thereof - Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link. | 2009-11-19 |
20090283854 | Design Structure and Method for Buried Inductors for Ultra-High Resistivity Wafers for SOI/RF SIGE Applications - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween. | 2009-11-19 |
20090283855 | SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME - An inductor having a helicoidal shape is provided on an insulation film formed on a semiconductor substrate. A conductive thin layer (a plating layer) is provided on a surface of the inductor. A conductivity of the conductive thin layer is higher than that of the inductor. According to the constitution, a Q value can be improved, and a large volume of current can be flowed. | 2009-11-19 |
20090283856 | METHOD FOR FABRICATING A SEMICONDUCTOR CAPACITPR DEVICE - A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer. | 2009-11-19 |
20090283857 | METHOD OF MANUFACTURING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a reflowed photoresist pattern surrounding the metal line pattern, forming a metal-insulator-metal (MIM) layer over the semiconductor substrate provided with the reflowed photoresist pattern, and removing the MIM layer arranged over the photoresist pattern and the photoresist pattern. | 2009-11-19 |
20090283858 | Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 2009-11-19 |
20090283859 | Integrated Circuit Arrangements With ESD-Resistant Capacitor and Corresponding Method of Production - A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength. | 2009-11-19 |
20090283860 | HIGH PRECISION SEMICONDUCTOR CHIP AND A METHOD TO CONSTRUCT THE SEMICONDUCTOR CHIP - An embodiment for manufacturing an electronic circuit forms at least one first structure on a semiconductor substrate, determines at least one electrically defined characteristic of the at least one first structure, selects a reticle corresponding to the measured characteristic, and forms at least one additional structure on the semiconductor substrate with the selected reticle. | 2009-11-19 |
20090283861 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND POWER AMPLIFIER ELEMENT - A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the low concentration impurity. And the semiconductor device further includes a high concentration impurity region of the first type conductivity having the same type conductivity as the type of the semiconductor substrate formed in at least the epitaxial layer with the low concentration impurity along an inner wall of the trench and coupled to the semiconductor substrate with the high concentration impurity of a first type conductivity, and contacts formed on the high concentration impurity region of the first type conductivity. | 2009-11-19 |
20090283862 | SEMICONDUCTOR DEVICE HAVING INSULATED GATE BIPOLAR TRANSISTOR - One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region of the first conductive type formed in the base region. Also, the semiconductor device includes a buffer layer of the first conductive type formed on the second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity therein of approximately 5×10 | 2009-11-19 |
20090283863 | SEMICONDUCTOR DEVICE HAVING INSULATED GATE BIPOLAR TRANSISTOR - One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region of the first conductive type formed in the base region. Also, the semiconductor device includes a buffer layer of the first conductive type formed on the second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity therein of approximately 5×10 | 2009-11-19 |
20090283864 | Semiconductor device - In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region for a collector electrode are brought into direct contact with each other to prevent formation of an unnecessary isolation region. Further, an emitter region is disposed to self-align with a device isolation insulating film or a polycrystalline silicon arranged on a surface of a semiconductor substrate. | 2009-11-19 |
20090283865 | ELECTROCHEMICAL METHOD TO MAKE HIGH QUALITY DOPED CRYSTALLINE COMPOUND SEMICONDUCTORS - A process for fabricating doped crystalline semiconductors is provided using layer by layer deposition of semiconductors and the corresponding dopants. | 2009-11-19 |
20090283866 | Semiconductor Substrate and a Method of Manufacturing the Same - The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×10 | 2009-11-19 |
20090283867 | Integration structure of semiconductor circuit and microprobe sensing elements and method for fabricating the same - The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is etched to form a microprobe structure for detect physiological signals. Next, a deposition method is used to sequentially form an electrical isolated layer and an electrical conductive layer on the microprobes. Then, an electrical conductive material is used to electrically connect the electrical conductive layer with the electrical pads of the semiconductor circuit. Thus is achieved the integration of a semiconductor circuit and microprobe sensing elements in an identical semiconductor substrate with the problem of electric electrical isolated being solved simultaneously. Thereby, the voltage level detected by the microprobes will not interfere with the operation of the semiconductor circuit. | 2009-11-19 |
20090283868 | Structure Replication Through Ultra Thin Layer Transfer - Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like the ingot, and to transfer this structure into a respective silicon process step. Some embodiments provide a process that allows one to structure any complex structured layer stacks, where the layers can be applied on top of each other using, e.g., bonding technology. | 2009-11-19 |
20090283869 | Scribe line structure for wafer dicing and method of making the same - The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer. | 2009-11-19 |
20090283870 | Semiconductor Device and Method of Conforming Conductive Vias Between Insulating Layers in Saw Streets - A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias. | 2009-11-19 |
20090283871 | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack - A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside. | 2009-11-19 |
20090283872 | PACKAGE STRUCTURE OF THREE-DIMENSIONAL STACKING DICE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a package structure of three-dimensional stacking dice and its manufacturing method. This invention employs the Through-Silicon-Vias (TSVs) technology to establish vertical electrical connection of the three-dimensional stacking dice and a redistribution layer between a blind hole-on-pad and a vertical through hole formed by the TSVs technology to direct the electrical connection from a first surface to an opposite second surface of this structure. In addition, this invention employs a conductive bump completely covering the pads jointed together between the stacking dice to avoid breakage of the pads. The reliability of the three-dimensional stacking dice of the present invention is increased. | 2009-11-19 |
20090283873 | METHOD FOR FORMING SELF-ALIGNMENT INSULATION STRUCTURE - A method for forming a self-align insulation of a passing gate is disclosed. First, a substrate is provided. A deep trench filled with silicon material and a shallow trench isolation adjacent to the deep trench are formed in the substrate. A patterned pad oxide and a patterned hard mask are sequentially formed on the substrate. The patterned pad oxide and the patterned hard mask together define the opening of the deep trench. Then, an oxidation step is carried out to form a first oxide layer serving as the insulation of a passing gate on the top surface of the silicon material of the deep trench. Later, a first Si layer is formed to cover the first oxide layer. Afterwards, the hard mask is removed. | 2009-11-19 |
20090283874 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps. | 2009-11-19 |
20090283875 | Self-supported film and silicon wafer obtained by sintering - Self-supported film and silicon wafer obtained by sintering. A silicon wafer for a photovoltaic cell is produced by a debinding step of a self-supported film formed of at least one main thin layer comprising at least 50% volume of silicon particles, devoid of silicon oxide and encapsulated in a polymer matrix protecting them against oxidation, followed by a sintering step to form the silicon wafer. | 2009-11-19 |
20090283876 | ELECTROMAGNETIC INTERFERENCE SHIELD FOR SEMICONDUCTORS USING A CONTINUOUS OR NEAR-CONTINUOUS PERIPHERAL CONDUCTING SEAL AND A CONDUCTING LID - A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure. | 2009-11-19 |
20090283877 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL. | 2009-11-19 |
20090283878 | LEAD-ON-CHIP SEMICONDUCTOR PACKAGE AND LEADFRAME FOR THE PACKAGE - A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads. | 2009-11-19 |
20090283879 | SEMICONDUCTOR DEVICE AND METHOD - A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes. | 2009-11-19 |
20090283880 | Semiconductor Chip Package Assembly with Deflection- Resistant Leadfingers - The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebond, and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion at its proximal end for increasing the clearance between the leadfinger and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface. Preferred embodiments of the invention further include a semiconductor chip affixed to the mounting surface and a plurality of bondwires operably coupling bond pads of the chip to the offset portions of the proximal ends of individual leadfingers. | 2009-11-19 |
20090283881 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-DOWN ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-down electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers, and one side of each first conductive layer is electrically connected with the corresponding conductive pad. The second conductive unit has a plurality of second conductive layers respectively formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers. | 2009-11-19 |
20090283882 | QFN SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads. | 2009-11-19 |
20090283883 | Semiconductor device using lead frame - A semiconductor device includes: a semiconductor chip configured to process a signal in a radio frequency band; two conductive antenna connection pins connected with two external antenna conductors, respectively; an island for the semiconductor chip to be mounted thereon; a suspending pin connected with the island; and an antenna connection conductor configured to connect the two antenna connection pins without connection with the island and the suspending pin. A series connection of one of the two external antenna conductors, one of the two antenna connection pins, the antenna connection conductor section, the other of the two antenna connection pins and the other of the two external antenna conductors in this order, functions as an antenna by connecting the series connection with the semiconductor chip. | 2009-11-19 |
20090283884 | LEAD FRAME, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LEAD FRAME AND THE SEMICONDUCTOR PACKAGE - Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns. | 2009-11-19 |
20090283885 | Semiconductor Device and a Method of Manufacturing the Same - On an adapter mounting portion | 2009-11-19 |
20090283886 | IC CARD - The present invention includes an IC card that can realize high function without increasing the size of an IC chip, and that can realize cost reduction. The IC card has a first single crystal integrated circuit, a second integrated circuit, and a display device. The second integrated circuit and the display device are each formed from a thin film semiconductor film, over a plastic substrate, and the first single crystal integrated circuit is mounted on the plastic substrate so as to be electrically connected to the second integrated circuit. | 2009-11-19 |
20090283887 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device of the present invention includes a semiconductor chip ( | 2009-11-19 |
20090283888 | PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY - A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle. | 2009-11-19 |
20090283889 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a heat spreader; attaching an upper substrate to the heat spreader, the upper substrate having an upper through-opening provided therein; attaching a top semiconductor die to the heat spreader through the upper through-opening, the top semiconductor die having a top die interconnect to the upper substrate; attaching a base substrate to the upper substrate, the base substrate having a base through-opening provided therein larger than the upper through-opening; and attaching an external interconnect connected to the base substrate. | 2009-11-19 |
20090283890 | SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE - A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer. | 2009-11-19 |
20090283891 | ELASTICALLY DEFORMABLE INTEGRATED-CIRCUIT DEVICE - The present invention relates to an integrated-circuit device comprising a multitude of separate rigid substrate islands ( | 2009-11-19 |
20090283892 | Design method of semiconductor package substrate - When the impedance of a first circuit is deviated from a standard value, a second circuit is designed for generating a second reflected wave to cancel a first reflected wave generated by the first circuit. Individual structural parts in a transmission line are intentionally designed to be deviated from a standard impedance reversely under a fine control. By this method, the impedance matching between the input and output impedance of the semiconductor element and the transmission line is achieved. As a result, the terminal impedance of the component of the semiconductor circuit and the semiconductor package substrate is adjusted to 50 Ohm, so that a good signal property can be obtained. | 2009-11-19 |
20090283893 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SLOTTED DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system including: providing a selective slot die paddle having selective slots and edge pieces around the perimeter; providing extended leads protruding into the selective slots; mounting an integrated circuit die on the selective slot die paddle; and coupling bond wires between the integrated circuit die, the edge pieces, the extended leads, or a combination thereof. | 2009-11-19 |
20090283894 | SEMICONDUCTOR CHIP PACKAGE AND PRINTED CIRCUIT BOARD HAVING THROUGH INTERCONNECTIONS - A semiconductor chip package includes a signal interconnection penetrating a semiconductor chip and transmitting a signal to the semiconductor chip and a power interconnection and a ground interconnection penetrating the semiconductor and supplying power and ground to the semiconductor chip. The power interconnection and the ground interconnection are arranged to neighbor each other adjacent to the signal interconnection. | 2009-11-19 |
20090283895 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame. | 2009-11-19 |
20090283896 | Package structure and method - A semiconductor die has a surface and an active region on the surface. A thick-film coating is applied to the surface of the semiconductor die to cover only a portion or entire of the active region before the semiconductor die is cut from a wafer. The thick-film coating reduces the stress to the semiconductor die. The thick-film coating does not cover the bonding pads of the semiconductor die to avoid influencing the bonding wires bonding to the boding pads. | 2009-11-19 |