46th week of 2021 patent applcation highlights part 63 |
Patent application number | Title | Published |
20210359045 | ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present disclosure provides an OLED display panel and a manufacturing method thereof. The display panel includes a base substrate; a pixel defining layer disposed on the base substrate; the pixel defining layer comprising at least one blocking unit; an anti-peeling layer covering the blocking unit; a first inorganic layer disposed on the anti-peeling layer. An adhering strength between the anti-peeling layer and the first inorganic layer is greater than an adhering strength between the blocking unit and the first inorganic layer. | 2021-11-18 |
20210359046 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate is provided. The array substrate includes a substrate, a first planarization layer disposed on the substrate, a second planarization layer disposed on the substrate, a partition groove formed between the first planarization layer and the second planarization layer to expose the substrate, a first electrode layer disposed on the first planarization layer, a reflective layer disposed on the second planarization layer and covering a side of the second planarization layer, and a pixel defining layer disposed on the partition groove and covering a portion of the first planarization layer and a portion of the second planarization layer. The reflective layer is configured to improve the light output and prevent light leakage from an edge of the array substrate. A manufacturing method of the array substrate is also provided. | 2021-11-18 |
20210359047 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display device includes: a substrate including a display area and a component area; a first pixel group on the display area; a second pixel group and a transmission area on the component area; an organic insulating layer on the substrate and including an opening corresponding to the transmission area; a display element on the organic insulating layer and including a pixel electrode and an opposite electrode; and a pixel-defining layer covering edges of the pixel electrode and defining an emission area of the display element, wherein the organic insulating layer includes a planarization area and a reduction area on the component area, the reduction area having a thickness that decreases in a direction from the planarization area to the opening, and a portion of the pixel-defining layer is on the reduction area. | 2021-11-18 |
20210359048 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a substrate, a pixel circuit layer having at least one thin-film transistor on the substrate, a first layer disposed on the pixel circuit layer and having a first opening, and a display element disposed in the first opening and including a first electrode, an emission layer, and a second electrode, which are sequentially stacked. The first electrode extends from an inner surface of the first layer defining the first opening along an upper surface of the first layer, and the emission layer extends on the first electrode along the inner surface of the first layer. | 2021-11-18 |
20210359049 | DISPLAY DEVICE - A display device includes a thin film transistor layer including at least one transistor on a substrate; a first electrode on the thin film transistor layer and connected to the at least one transistor; a second electrode spaced from the first electrode on the thin film transistor layer; a plurality of light emitting elements connected to the first electrode and the second electrode; and an electrode pattern on a same layer as the first electrode and the second electrode and overlapping the plurality of light emitting elements in a thickness direction. | 2021-11-18 |
20210359050 | DISPLAY PANEL - A display panel is provided, including a substrate and an organic light-emitting component disposed on the substrate. The display panel further includes a planarization layer and an insulation layer disposed on the planarization layer. An anode of the organic light-emitting component is disposed on the planarization layer. The insulation layer is disposed on the planarization layer and configured to cover the planarization layer, and the anode of the organic light-emitting component is exposed through the insulation layer. | 2021-11-18 |
20210359051 | ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY PANEL AND OLED DISPLAY DEVICE - The present invention provides an organic light-emitting diode (OLED) display panel and an OLED display device. The OLED display panel comprises a light transmission area and a display area surrounding a periphery of the light transmission area; a concave groove is disposed in the OLED display panel corresponding to the light transmission area, and the concave groove penetrates through at least an encapsulation layer, a light emitting function layer and a part of a thin film transistor (TFT) structure layer; and at least a part of a touch function layer extends from the display area toward the concave groove and covers the concave groove. | 2021-11-18 |
20210359052 | DISPLAY PANEL AND DISPLAY APPARATUS - The present application discloses a display panel and a display apparatus. The display panel includes a plurality of pixels. Each of the pixels at least includes a first sub pixel, a second sub pixel and a third sub pixel corresponding to blue. The first sub pixel includes a first active switch. The second sub pixel includes a second active switch. The third sub pixel includes a third active switch. The opening rates of the first sub pixel and the second sub pixel are less than the opening rate of the third sub pixel. The channel ratios of the first active switch and the second active switch are greater than the channel ratio of the third active switch. | 2021-11-18 |
20210359053 | TERMINAL AND DISPLAY SCREEN - The present disclosure relates to terminals and display screens. In an embodiment, a terminal includes a display area, the display area includes at least two display regions, the at least two display regions include a first display region and a second display region, a pixel density of the first display region is less than a pixel density of the second display region, and the pixel density of the first display region is less than or equal to a maximum pixel density of the first display region in a transparent state when the first display region is unlit. | 2021-11-18 |
20210359054 | DISPLAY PANEL AND DISPLAY DEVICE - The present invention provides a display panel. The display panel includes at least three sub-pixel regions. The sub-pixel regions are arranged along a direction of a scan line. A channel region of each driving TFT in the same sub-pixel region has a same width-to-length ratio. Along a direction from a signal input end to a signal output end of the scan line, the width-to-length ratio of the channel region of each driving TFT of any of the sub-pixel regions is smaller than that of a previous one of the sub-pixel regions. | 2021-11-18 |
20210359055 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin-film transistor array substrate includes a substrate, a thin-film transistor disposed on the substrate, where the thin-film transistor includes a semiconductor layer including a channel area and a gate electrode overlapping the channel area, and a storage capacitor including a lower electrode disposed on the channel area and an upper electrode disposed to overlap the lower electrode, where an opening having a single closed curve-shape is defined through the upper electrode. On a plane, the upper electrode includes a first recessed portion and a second recessed portion, each exposing an edge of the lower electrode. | 2021-11-18 |
20210359056 | EMISSIVE DISPLAY DEVICE - An emissive display device includes a polycrystalline semiconductor including a channel, source region, and drain region of a driving transistor disposed on a substrate. The device includes a gate electrode of the driving transistor overlapping the channel of the driving transistor, an oxide semiconductor including a channel, a source region, and a drain region of a second transistor disposed on the substrate, and a first connection electrode. The first connection electrode includes a first connector electrically connected to the gate electrode of the driving transistor, a second connector electrically connected to a second electrode of the second transistor, and a main body disposed between the first connector and the second connector. The device includes an initialization voltage line disposed on the substrate and applying an initialization voltage. The initialization voltage line surrounds at least a part of the second connector of the first connection electrode. | 2021-11-18 |
20210359057 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern. | 2021-11-18 |
20210359058 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes: a substrate having a sub-pixel circuit region including a driving transistor region; an active pattern in the sub-pixel circuit region on the substrate, and including a bent portion having a first length in the driving transistor region, and a straight portion adjacent to the bent portion in the driving transistor region and having a second length shorter than the first length in the driving transistor region; and a sub-pixel structure on the active pattern. Accordingly, when the organic light emitting display device is driven at a low gray level, the organic light emitting display device can improve the low gray-level spot and the crosstalk while relatively reducing the power consumption. | 2021-11-18 |
20210359059 | OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present disclosure provides an OLED display panel which includes a substrate, a drive circuit layer, a light-emitting functional layer, and a pixel definition layer. The light-emitting functional layer includes a light-emitting area and a non-light-emitting area. The drive circuit layer includes a buffer layer, a first electrode plate, and a second electrode plate, and the first electrode plate and the second electrode plate form a storage capacitor. It solves the technical problem of current OLED display panels having dark stripes by not depositing the first electrode plate when silicon nitride is deposited to form a first buffer layer which prevents ionic gases produced when silicon nitride is deposited from having a reduction reaction with the first electrode plate. | 2021-11-18 |
20210359060 | DISPLAY SUBSTRATE AND MANUFATURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - A display substrate includes: a base substrate having a first side and a second side opposite to each other; a transmitter arranged on the first side of the base substrate, and configured to convert a first display electrical signal into a conduction signal; a first light-emitting element arranged on a side of the transmitter away from the base substrate, wherein the first light-emitting element emits light under a driving action of the first display electrical signal; a receiver arranged on the second side of the base substrate, and configured to receive the conduction signal and convert the conduction signal into a second display electrical signal; and a second light-emitting element arranged on a side of the receiver away from the base substrate, wherein the second light-emitting element emits light under a driving action of the second display electrical signal. | 2021-11-18 |
20210359061 | OLED DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, DISPLAY PANEL CONTAINING DISPLAY SUBSTRATE, AND DISPLAY DEVICE CONTAINING DISPLAY PANEL - A display substrate includes a substrate ( | 2021-11-18 |
20210359062 | DISPLAY APPARATUS, COUNTER SUBSTRATE OF DISPLAY APPARATUS, METHOD OF FABRICATING DISPLAY APPARATUS - A display apparatus having a plurality of subpixels is provided. The display apparatus includes an array substrate and a counter substrate facing the array substrate. The counter substrate includes a base substrate; an optical compensation device on the base substrate configured to adjust light emitting brightness values of the plurality of subpixels to target brightness values respectively; and a plurality of light shielding walls on the base substrate. The optical compensation device include a plurality of photosensors configured to respectively detect light emitting brightness values of the plurality of subpixels. A respective one of the plurality of light shielding walls is configured to at least partially shield a lateral side of a respective one of the plurality of photosensors from light emitted from adjacent subpixels. | 2021-11-18 |
20210359063 | ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE - An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate. | 2021-11-18 |
20210359064 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display panel including a base, a metal wire layer, an organic light-emitting diode (OLED) luminous layer, and a blocking layer. The blocking layer is disposed between the metal wire layer and the OLED luminous layer. The blocking layer covers the metal wire layer. Through disposing the blocking layer that can absorb UV light on metal wires, UV light of an exposure machine is prevented from irradiating onto the metal wires of a bottom layer, thereby preventing underlying light from being reflected onto a planarization layer, which reduces a risk of short circuiting or performance abnormality of OLED components due to unevenness of film layers in pixels. | 2021-11-18 |
20210359065 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a thin-film transistor located in a display area and including a semiconductor layer and a gate electrode; a storage capacitor located in the display area and including a first capacitor plate, a second capacitor plate, and a dummy capacitor plate overlapping each other; a light-emitting diode electrically connected to the thin-film transistor and the storage capacitor and including a pixel electrode, an interlayer, and a counter electrode; a pad located in a surrounding area adjacent to the display area; a lower electrode pattern layer disposed below the semiconductor layer, at least a portion of the lower electrode pattern layer overlapping the semiconductor layer; and a bridge electrode electrically connecting the semiconductor layer to the lower electrode pattern layer. | 2021-11-18 |
20210359066 | DISPLAY APPARATUS - A display apparatus includes a substrate including a display area including a display element, a first thin film transistor disposed in the display area, the first thin film transistor including a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a second thin film transistor disposed in the display area, the second thin film transistor including a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer, a first signal line extending at a side of the first thin film transistor in a first direction, a second signal line extending at an opposite side of the first thin film transistor in the first direction, and a shielding pattern extending in the first direction, the shielding pattern at least partially overlapping the first signal line. | 2021-11-18 |
20210359067 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME - A display panel includes a first organic film layer, a first barrier layer disposed on first organic film layer, a shielding pattern disposed on the first barrier layer, a second barrier layer covering the shielding pattern and disposed on first barrier layer, a first active pattern disposed on the second barrier layer and overlapping the shielding pattern in a plan view, a gate electrode disposed on the first active pattern, an emission control line disposed on the first active pattern and adjacent to a first side of the gate electrode in the plan view, an upper compensation control line disposed on the emission control line and adjacent to a second side of gate electrode in the plan view, and a second active pattern disposed on the emission control line. | 2021-11-18 |
20210359068 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL - Provided is an organic light emitting diode display panel, including: a substrate, a plurality of signal lines and at least one spare line disposed on the substrate, wherein the signal lines are at a different layer from the spare line; a plurality of preset connection points are disposed on the spare line, and a projection of any of the signal lines on the substrate overlaps a projection of the two preset connection points on the substrate, and when any of the signal lines is disconnected, the disconnected signal line is electrically connected to the spare line via the preset connection points, so that the disconnected signal line works normally through the spare line. | 2021-11-18 |
20210359069 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device are disclosed. The display substrate includes a base substrate, an insulating layer, a first crack stopper, and a first crack detection line. The base substrate includes a display region and a non-display region. The insulating layer is located on the base substrate. The first crack stopper is located in the non-display region and is configured to block the first crack in the insulating layer from extending towards the display region. The first crack detection line is located in the non-display region, an edge of the orthographic projection of the first crack stopper on the base substrate close to the display region is a blocking edge, and the orthographic projection of the first crack detection line on the base substrate is located at a side of the orthographic projection of the first crack stopper on the base substrate away from the blocking edge. | 2021-11-18 |
20210359070 | DISPLAY DEVICE - A display panel is provided and advantages thereof are that a metal wiring of a bending area is provided with protrusions that extend in a second direction. The design of the protruded metal wiring can effectively reduce a risk of cracking and prevent a longitudinal extension of a crack. | 2021-11-18 |
20210359071 | DISPLAY PANEL, MANUFACTURING METHOD AND DETECTING METHOD THEREOF, AND DISPLAY DEVICE - A display panel, methods for manufacturing and detecting the display panel and a display device are provided. The display panel includes: a substrate, including a display region and a circuit region; multiple signal line terminals in the circuit region, coupled with signal lines respectively; multiple switch elements in the circuit region, first terminals of the switch elements are coupled with the signal line terminals respectively; multiple leads located in the circuit region and on a side of the signal line terminals distal to the display region, spaced apart from each other along a first direction, extending along a second direction, first ends of the leads are coupled with the second terminals of the switch elements respectively, second ends of the leads in the second direction extend to an edge of the substrate, each switch element is configured to connect or disconnect the first terminal and the second terminal thereof. | 2021-11-18 |
20210359072 | DISPLAY DEVICE - A display device includes a display module including a first base substrate and a pad on a top surface of the first base substrate; a circuit film coupled to a lateral surface of the first base substrate and including a contact pad spaced apart from the pad; and a conductive member on the top surface of the first base substrate and in contact with the pad and the contact pad. | 2021-11-18 |
20210359073 | DISPLAY DEVICE - A display device includes: a plurality of main display elements in the main display area; a plurality of auxiliary display elements and a transmission area in the component area; a first pixel circuit in the component area and connected to a first auxiliary display element among the auxiliary display elements; a second pixel circuit in the component area and connected to a second auxiliary display element among the auxiliary display elements, the second pixel circuit neighboring the first pixel circuit in a column direction; and a first initialization voltage line in the component area, extending in a row direction, arranged between the first pixel circuit and the second pixel circuit, and connected to the first pixel circuit and the second pixel circuit, wherein the first pixel circuit and the second pixel circuit are symmetric with respect to the first initialization voltage line. | 2021-11-18 |
20210359074 | DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A display device includes: pixel circuits in a display area, the pixel circuits each comprising a thin film transistor and a capacitor, the thin film transistor including a semiconductor layer and a gate electrode on the substrate and the capacitor including a first capacitor plate and a second capacitor plate; signal lines electrically connected to the pixel circuits, the signal lines passing through the display area; a lower metal layer between the substrate and at least one of the pixel circuits; a pad portion in the peripheral area; and a plurality of wirings in the peripheral area, the plurality of wirings electrically connecting the pad portion to the signal lines, wherein the plurality of wirings further comprise: a first wiring at a same layer as the lower metal layer; and a second wiring above the first wiring with a first insulating layer between the first wiring and the second wiring. | 2021-11-18 |
20210359075 | DISPLAY PANEL, METHOD FOR MANUFACTURING DISPLAY PANEL, AND DISPLAY DEVICE - A display panel, a method for manufacturing the display panel and a display device are provided. The display panel includes a base, a functional film layer, and a plurality of first light-emitting elements. The functional film layer includes a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer includes a power source signal line pattern arranged at each subpixel region, the data line layer includes a data line pattern arranged at each subpixel region, and the compensation functional layer includes a compensation functional pattern arranged at at least one subpixel region. The first light-emitting element includes a first anode, a first light-emitting pattern and a first cathode sequentially laminated. | 2021-11-18 |
20210359076 | ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD FOR PRODUCING SAME - An organic EL device ( | 2021-11-18 |
20210359077 | SUBSTRATE AND MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE - A substrate, a manufacturing method of a substrate and an electronic device are provided. The substrate ( | 2021-11-18 |
20210359078 | DISPLAY APPARATUS - A display apparatus includes: an emission panel comprising a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, and a first power line, wherein the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode have a stacked structure, and the first power line is in a laser drilling area around the pixel area and electrically connected to the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode; and a color panel on the emission panel and comprising a first color area, a second color area, a third color area, which are each capable of transmitting light of different colors, and a light-blocking area, wherein a column spacer is between the emission panel and the color panel and has at least a portion overlapping the laser drilling area in a vertical direction. | 2021-11-18 |
20210359079 | DISPLAY DEVICE - A display device includes: a substrate; first, second, and third data lines extending in a first direction on the substrate and disposed to be adjacent along a second direction crossing the first direction; a semiconductor layer disposed on the first, second, and third data lines; a first insulating layer disposed on the semiconductor layer; first, second, and third lower storage electrodes disposed on the first insulating layer and arranged to be adjacent along the first direction; a second insulating layer disposed on the first, second, and third lower storage electrodes; a first scan line extending in the second direction on the second insulating layer; a first pixel connected to the first scan line and the first data line; a second pixel connected to the first scan line and the second data line; and a third pixel connected to the first scan line and the third data line. | 2021-11-18 |
20210359080 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display apparatus, the display panel including a first display area, a second display area, and a transition display area between the first display area and the second display area, the light transmittance of the second display area being greater than that of the first display area and the transition display area, the display panel including: first pixels in the first display area; seconds pixels in the second display area; third pixels in the transition display area; second pixel circuits in the transition display area and used for driving the second pixels to display; and third pixel circuits in the transition display area and used for driving the third pixels to display, a third pixel unit of the display panel including a third pixel circuit and two or more third pixels of the same colour electrically connected thereto. | 2021-11-18 |
20210359081 | TILED DISPLAY DEVICE - A tiled display device includes: a first display device including: a first display substrate having a plurality of light emitting areas; and a second color conversion substrate comprising a plurality of light transmitting areas respectively corresponding to the light emitting areas and comprising a light scattering material and a plurality of light blocking areas between the light transmitting areas; a second display device comprising a second display substrate and a second color conversion substrate, the second display device being at a side of the first display device; and a light scattering member between the first display device and the second display device and comprising a light scattering material, wherein an external light reflectance of the light scattering member is higher than an average value of an external light reflectance of the light transmitting areas and an external light reflectance of the light blocking areas. | 2021-11-18 |
20210359082 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode, and a multi-layer stack positioned between the first electrode and the second electrode, the multi-layer stack including at least one anti-ferroelectric layer and at least one high-k dielectric layer. | 2021-11-18 |
20210359083 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present application relates to a semiconductor device and a method for forming the same, which can reduce the size of the memory chip and improve the production yield thereof. The semiconductor device includes a substrate; a capacitive post, formed on the surface of the substrate, a length direction of the capacitive post being perpendicular to the surface of the substrate, the capacitive post including: at least three electrode layers which are disposed vertically, forming a side wall of the capacitive post, and a dielectric layer being sandwiched between two adjacent electrode layers; at least two support layers are formed inside the capacitive post, and are in contact with the side wall of the capacitive post for supporting the side wall, and two adjacent support layers being separated by a slot. | 2021-11-18 |
20210359084 | MEMORY AND FORMATION METHOD THEREOF - A memory formation method includes: providing a substrate; forming a first mask layer on the substrate, in the first mask layer there being formed a plurality of parallel-arranged strip-shaped patterns positioned above the array area, and an end of each of the strip-shaped patterns being connected to the first mask layer on the peripheral area of the substrate; forming a second mask layer on the first mask layer, in the second mask layer there being formed a plurality of first patterns; and etching layer by layer by using the second mask layer and the first mask layer as masks to transfer the strip-shaped patterns and the first patterns into the substrate to form the discrete active areas arranged in an array. | 2021-11-18 |
20210359085 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs. | 2021-11-18 |
20210359086 | SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS - Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for iFETs, and a host of other applications. | 2021-11-18 |
20210359087 | Method for Forming a Semiconductor Device and a Semiconductor Device - A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 5*10 | 2021-11-18 |
20210359088 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, including: a drift region of a first conductivity type which is provided in a semiconductor substrate, and a buffer region of the first conductivity type which is provided between the drift region and a lower surface of the semiconductor substrate, and has three or more concentration peaks higher than a doping concentration of the drift region of the semiconductor substrate in a depth direction. Three or more of the concentration peaks includes a shallowest peak closest to the lower surface of the semiconductor substrate, a high concentration peak arranged at an upper side than the lower surface of the semiconductor substrate than the shallowest peak, and one or more low concentration peaks arranged at an upper side than the lower surface of the semiconductor substrate than the high concentration peak and of which the doping concentration is ⅕ or less of the high concentration peak. | 2021-11-18 |
20210359089 | Methods of Forming Conductive Pipes Between Neighboring Features, and Integrated Assemblies Having Conductive Pipes Between Neighboring Features - Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region. | 2021-11-18 |
20210359090 | TRANSISTOR STRUCTURE, GOA CIRCUIT, AND DISPLAY PANEL - A transistor structure, a gate on array (GOA) circuit, and a display panel are provided. The transistor structure includes a substrate, and a source/drain electrode layer and a passivation layer which are disposed on the substrate sequentially. Furthermore, the source/drain electrode layer includes a source electrode and a drain electrode, and the source electrode is arranged around the drain electrode and is in an annular shape. The passivation layer includes a via hole. A projection of the drain electrode on the passivation layer covers the via hole. | 2021-11-18 |
20210359091 | GATE-ALL-AROUND DEVICES HAVING SELF-ALIGNED CAPPING BETWEEN CHANNEL AND BACKSIDE POWER RAIL - A semiconductor device includes a first interconnect structure; multiple channel layers stacked over the first interconnect structure; a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature between the bottommost one of the channel layers and the first conductive via. | 2021-11-18 |
20210359092 | LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS - Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor. | 2021-11-18 |
20210359093 | POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR CHIP - A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer. | 2021-11-18 |
20210359094 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A semiconductor structure and a method for forming the same are provided. The method includes: forming an active region on a substrate; forming at least one trench in the active region, the trench at least dividing the active region into a source region on one side of the trench and a drain region on the other side of the trench; and forming an elevated source region and an elevated drain region on the source region and the drain region respectively. | 2021-11-18 |
20210359095 | Semiconductor Device Structure with Uneven Gate Profile - A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D | 2021-11-18 |
20210359096 | TRANSISTOR GATES AND METHOD OF FORMING - A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal. | 2021-11-18 |
20210359097 | OHMIC CONTACT FOR MULTIPLE CHANNEL FET - An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure. | 2021-11-18 |
20210359098 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR - According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms. | 2021-11-18 |
20210359099 | DEVICES AND METHODS FOR CREATING OHMIC CONTACTS USING BISMUTH - Devices, such as transistors, that use bismuth to create ohmic contacts are provided, as are methods of manufacturing the same. The transistors, such as field-effect transistors, can include one or more two-dimensional materials, and electrical contact areas can be created on the two-dimensional material(s) using bismuth. The bismuth can help to provide energy-barrier free, ohmic contacts, and the resulting devices can have performance levels that rival or exceed state-of-the-art devices that utilize three-dimensional materials, like silicon. The two-dimensional materials can include transition metal dichalcogenides, such as molybdenum disulfide. | 2021-11-18 |
20210359100 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric. | 2021-11-18 |
20210359101 | THIN FILM STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A thin film structure including ferroelectrics and anti-ferroelectrics and a semiconductor device including the same are provided. The thin film structure includes a first anti-ferroelectric layer comprising anti-ferroelectrics, a second anti-ferroelectric layer disposed apart from the first anti-ferroelectric layer and including anti-ferroelectrics, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric layer and including ferroelectrics. | 2021-11-18 |
20210359102 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR - Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure. | 2021-11-18 |
20210359103 | NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK - Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical. | 2021-11-18 |
20210359104 | FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer. | 2021-11-18 |
20210359105 | DIELECTRIC CONSTANT REDUCTION OF GATE SPACER - A semiconductor device includes a substrate, a gate stack over the substrate and a gate spacer on a sidewall of the gate stack. The gate spacer includes an outer spacer and an inner spacer between the gate stack and the outer spacer. The outer spacer and the inner spacer have same k-value reduction impurities, and a concentration of the k-value reduction impurities in the inner spacer is greater than a concentration of the k-value reduction impurities in the outer spacer. | 2021-11-18 |
20210359106 | DESIGN AND MANUFACTURE OF SELF-ALIGNED POWER DEVICES - An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N− drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET. | 2021-11-18 |
20210359107 | 3D Capacitor and Method of Manufacturing Same - A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin. | 2021-11-18 |
20210359108 | DOUBLE DIFFUSION BREAK GATES FULLY OVERLAPPING FIN EDGES WITH INSULATOR REGIONS - Certain aspects of the present disclosure generally relate to a semiconductor device having an insulator region disposed on at least one edge of a semiconductor fin structure. An example semiconductor device generally includes a first semiconductor region, an insulator region, a double diffusion break, and a first gate region. The first semiconductor region comprises a first fin structure and a second fin structure separated by a cavity. The insulator region is disposed along an edge of the first fin structure. The double diffusion break is disposed adjacent to the insulator region in the cavity. The first gate region is disposed around a portion of the first fin structure. | 2021-11-18 |
20210359109 | Semiconductor Device and Method - A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer. | 2021-11-18 |
20210359110 | CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING CONFINED EPITAXIAL REGIONS - Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins. | 2021-11-18 |
20210359111 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum. | 2021-11-18 |
20210359112 | DISPLAY PANEL PREPARATION METHOD AND DISPLAY PANEL - The present application discloses a display panel preparation method and a display panel. The display panel preparation method includes: forming a first metal layer, a buffer layer, an oxide film layer, and a gate insulating layer on a substrate; and etching on a second layer of metal by using a same mask process, to obtain a gate layer, a source layer, and a drain layer. | 2021-11-18 |
20210359113 | TRANSISTOR AND MANUFACTURING METHOD THEREOF - Provided are a transistor and a manufacturing method thereof. The transistor includes a substrate, a collector, a base, an emitter and a diffusion barrier layer. The collector is disposed on the substrate. The base is disposed on the collector. The emitter is disposed on the base. The diffusion barrier layer is disposed between the base and the emitter. An upper portion of the base includes a doped layer, and the diffusion barrier layer is disposed on the doped layer. The emitter, the doped layer, and the collector are of a first conductive type, and the rest of the base is of a second conductive type. | 2021-11-18 |
20210359114 | SEMICONDUCTOR DEVICE - A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface. | 2021-11-18 |
20210359115 | TRANSISTOR WITH IMPROVED SWITCHING - In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer having a first n-type dopant, depositing a first portion of a second epitaxial layer having a second n-type dopant on the first epitaxial layer, implanting ions into the first portion of the second epitaxial layer to form a recombination region, depositing a second portion of the second epitaxial layer having the second n-type dopant on the recombination region, and forming trenches in the second portion of the second epitaxial layer, wherein the trenches comprise a trench gate of the transistor and a termination trench. The second portion of the second epitaxial layer is thicker than the first portion of the second epitaxial layer. | 2021-11-18 |
20210359116 | SEMICONDUCTOR APPARATUS - Provided is a semiconductor apparatus comprising: an emitter region having a first conductivity type provided on a front surface of a semiconductor substrate; a first gate trench part and a second gate trench part in contact with the emitter region; a first emitter non-contact trench part and a second emitter non-contact trench part out of contact with the emitter region; a gate pad for setting the first gate trench part, the second gate trench part, the first emitter non-contact trench part, and the second emitter non-contact trench part to gate potential; and a diode having an anode connected to the gate pad and a cathode connected to the first emitter non-contact trench part and the second emitter non-contact trench part, wherein the first gate trench part, the first emitter non-contact trench part, the second gate trench part, and the second emitter non-contact trench part are adjacently arranged in order. | 2021-11-18 |
20210359117 | VERTICAL POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A vertical power semiconductor device includes a semiconductor body having opposing first and second main surfaces. At least part of a gate trench structure formed at the first main surface extends along a first lateral direction. Body and source regions directly adjoin the gate trench structure. A drift region is arranged between the body region and second main surface. A body contact structure includes first and second body contact sub-regions spaced at a first lateral distance along the first lateral direction. Each body contact sub-region directly adjoins the gate trench structure and has a larger doping concentration than the body region. In a channel region between the body contact sub-regions, the body contact structure has a second lateral distance to the gate trench structure along a second lateral direction perpendicular to the first lateral direction. The first lateral distance is equal to or less than twice the second lateral distance. | 2021-11-18 |
20210359118 | Group III-Nitride High-Electron Mobility Transistors Configured with Recessed Source and/or Drain Contacts for Reduced On State Resistance and Process for Implementing the Same - A high-electron mobility transistor (HEMT) that includes a substrate, a group III-Nitride channel layer on the substrate, a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer that includes a higher bandgap than a bandgap of the group III-Nitride channel layer, a source electrically coupled to the group III-Nitride barrier layer, a gate electrically coupled to the group III-Nitride barrier layer, and a drain electrically coupled to the group III-Nitride barrier layer. The source and/or the drain are structured and arranged to extend through the group III-Nitride barrier layer into the group III-Nitride channel layer. | 2021-11-18 |
20210359119 | Field-Effect Transistor and Manufacturing Method Therefor - A gate opening portion, which is disposed within a recess formation region in a state where the distance from a drain electrode is greater than the distance from a source electrode, is formed in an insulating layer. The gate opening portion is a stripe-shaped opening that extends in a gate width direction. Also, a plurality of asymmetric recess-forming opening portions are formed, arranged in a row in the gate width direction between the gate opening portion and the drain electrode within the recess formation region in the insulating layer. In this step, asymmetric recess-forming opening portions are formed whose opening size in the gate length direction is greater than the opening size in the gate width direction. | 2021-11-18 |
20210359120 | SEMICONDUCTOR DEVICE, COMMUNICATION MODULE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes: a semiconductor substrate; a channel layer on the semiconductor substrate; a barrier layer on the channel layer; a gate electrode on the barrier layer via a gate insulating film; a source electrode and a drain electrode on the channel layer with the gate electrode interposed therebetween; a substrate opening that penetrates the channel layer and exposes the semiconductor substrate; an insulating film provided from upper parts of the gate electrode, the source electrode, and the drain electrode to an inner side of the substrate opening; and a wiring line layer on the insulating film, and electrically coupled to one of the gate electrode, the source electrode, and the drain electrode via an opening on the insulating film, in which at least a portion of the substrate opening is in an activation region in which the gate electrode, the source electrode, and the drain electrode are provided. | 2021-11-18 |
20210359121 | HIGH LINEARITY HEMT DEVICE AND PREPARATION METHOD THEREOF - A high electron mobility transistor (HEMT) device is provided. The HEMT device includes a substrate layer, a buffer layer, a barrier layer, and a metallic electrode layer sequentially arranged in that order from bottom to top. The metallic electrode layer includes a source electrode, a gate electrode and a drain electrode sequentially arranged in that order from left to right. The barrier layer may include m number of fluorine-doped regions arranged in sequence, where m is a positive integer and m≥2. The HEMT device can realize a relative stability of transconductance in a large range of a gate-source-bias through mutual compensation of transconductances in the fluorine-doped regions with different fluorine-ion concentrations of the barrier layer under the gate electrode, and the HEMT device has a good linearity without the need of excessive adjustments of material structure and device. | 2021-11-18 |
20210359122 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY - A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors. | 2021-11-18 |
20210359123 | SEMICONDUCTOR POWER DEVICE - A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 02021-11-18 | |
20210359124 | SCHOTTKY CONTACT REGION FOR HOLE INJECTION SUPPRESSION - A power transistor having: a p-body region, coupled to a first voltage; a first p-type buried layer under the p-body region; a n-implant region surrounding the p-body region and the p-type buried layer; a p-implant region surrounding the n-implant region; and a p-implant guard ring region inserted into the n-implant region to split the n-implant region to a first part and a second part, wherein the first part of the n-implant region is between the p-body region and the p-implant guard ring region, and the second part of the n-implant region is between the p-implant guard ring region and the p-implant region; wherein the second part of the n-implant region has a Schottky contact region coupled to a second voltage via a metal contact. | 2021-11-18 |
20210359125 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH HIGH CONTACT AREA - A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple channel structures suspended over a semiconductor substrate. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the channel structures. The semiconductor device structure further includes a gate stack wrapping around the channel structures. In addition, the semiconductor device structure includes a conductive contact wrapping around terminals of the epitaxial structures. | 2021-11-18 |
20210359126 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate; forming an isolation structure on the substrate; forming a gate structure on the isolation structure; forming a first opening in the gate structure; and forming a first conductive structure in the first opening. Sidewall surfaces of the first conductive structure are in contact with a gate electrode layer of the gate structure. | 2021-11-18 |
20210359127 | VIA STRUCTURE WITH LOW RESISTIVITY AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer. | 2021-11-18 |
20210359128 | SEMICONDUCTOR DEVICE - A main semiconductor device element is a vertical MOSFET with a trench gate structure, containing silicon carbide as a semiconductor material, and having first and second p | 2021-11-18 |
20210359129 | POWER MOSFETS STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate. | 2021-11-18 |
20210359130 | HIGH-VOLTAGE DEVICES INTEGRATED ON SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer. | 2021-11-18 |
20210359131 | SEMICONDUCTOR DEVICE - A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions. | 2021-11-18 |
20210359132 | TRANSISTOR DEVICES AND METHODS OF FORMING TRANSISTOR DEVICES - An LDMOS transistor device may be provided, including a substrate having a conductivity region arranged therein, a first isolation structure arranged within the substrate, a source region and a drain region arranged within the conductivity region, a second isolation (local isolation) structure arranged between the source region and the drain region, and a gate structure arranged at least partially within the second isolation structure. The first isolation structure may extend along at least a portion of a border of the conductivity region, and a depth of the second isolation structure may be less than a depth of the first isolation structure. In use, a channel for electron flow may be formed along at least a part of a side of the gate structure arranged within the second isolation (local isolation) structure. | 2021-11-18 |
20210359133 | OXIDE THIN-FILM TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides an oxide thin-film transistor device and manufacturing method thereof, the method of manufacturing the oxide thin-film transistor device including: depositing a buffer layer on a substrate; depositing a first channel layer composed of a wide bandgap oxide semiconductor on the buffer layer; depositing a second channel layer composed of a high-mobility oxide semiconductor on the first channel layer, which can improve electron mobility and reliability of device. | 2021-11-18 |
20210359134 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed. | 2021-11-18 |
20210359135 | FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITS - Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors. | 2021-11-18 |
20210359136 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a buffer layer disposed on a substrate and comprising a first buffer film, and a second buffer film, wherein the first buffer film and the second buffer film are sequentially stacked in a thickness direction of the display device; a semiconductor pattern disposed on the buffer layer; a gate insulating layer disposed on the semiconductor pattern; and a gate electrode disposed on the gate insulating layer, wherein the first buffer film and the second buffer film comprise a same material, and a density of the first buffer film is greater than a density of the second buffer film. | 2021-11-18 |
20210359137 | TFT DEVICE AND MANUFACTURING METHOD OF SAME, TFT ARRAY SUBSTRATE, AND DISPLAY DEVICE - A TFT device and a manufacturing method of the same, a TFT array substrate and a display device is provided by this disclosure. A light-shielding layer is configured under the active layer, and one of the source doping member and the drain doping member is attached to the buffer layer and the light-shielding layer to generate a stable voltage on the light-shielding layer. At the same time, forming holes in the light-shielding layer and the buffer layer is avoided and connecting a source electrode, the active layer and the light-shielding layer with conductive lines is no more needed, which decreases one mask, and corresponding exposure and etching process, thus decreases manufacturing cost of the TFT. | 2021-11-18 |
20210359138 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND ELECTRONIC DEVICE - A thin film transistor, a manufacturing method thereof, an array substrate and an electronic device are disclosed. The manufacturing method of the thin film transistor includes: forming an active layer pattern on a base substrate; forming a gate insulating layer on the active layer pattern; the gate insulating layer includes a first portion, a second portion and a third portion, the third portion is on both sides of the first portion, the second portion is between the first portion and the third portion on at least one side, and the thickness of the second portion is larger than that of the third portion. | 2021-11-18 |
20210359139 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, AND DISPLAY APPARATUS - An array substrate includes a substrate, an active layer, and an amorphous silicon shielding layer. The substrate has a first surface and a second surface, which are opposing to each other. The active layer is over the first surface of the substrate. The amorphous silicon shielding layer includes amorphous silicon, and is between the active layer and the substrate, or alternatively is disposed over a side of the substrate proximal to the second surface of the substrate. An orthographic projection of the amorphous silicon shielding layer on the first surface at least partially and preferably completely covers an orthographic projection of the active layer on the first surface such that the amorphous silicon shielding layer shields a light from shedding onto the active layer. | 2021-11-18 |
20210359140 | Thin Film Transistor and Manufacturing Method Thereof and Electronic Device - A thin film transistor includes an active layer, a source electrode and a drain electrode. The active layer includes a conductive region and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode. | 2021-11-18 |
20210359141 | ARRAY SUBSTRATE, METHOD FOR FORMING ARRAY SUBSTRATE, AND DISPLAY DEVICE - An array substrate, a method for forming an array substrate, and a display device are provided. The array substrate includes a substrate, and a gate layer, an active layer, and a source/drain layer formed over the substrate. An insulating layer is formed between the gate layer and the active layer, and the source/drain layer, and the active layer comprises at least one graphene layer and at least one molybdenum disulfide layer disposed in a stack, and the at least one graphene layer is located at a side away from the substrate of the active layer and contacts the source/drain layer. | 2021-11-18 |
20210359142 | SILICON CHANNEL TEMPERING - A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer. | 2021-11-18 |
20210359143 | Method of Manufacturing A Semiconductor Transducer Device With Multilayer Diaphragm And Semiconductor Transducer Device With Multilayer Diaphragm - In an embodiment a method includes providing a semiconductor body, forming a sacrificial layer above a surface of the semiconductor body, applying a diaphragm on the sacrificial layer and removing the sacrificial layer by introducing an etchant into openings of the diaphragm, wherein applying the diaphragm comprises applying a first layer, reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and patterning and structuring the first layer to form the openings. | 2021-11-18 |
20210359144 | POWER ELEMENT - A power element includes a substrate structure, an insulation layer, a dielectric layer, a transistor, and a plurality of zener diodes. The transistor is located in a transistor formation region of the substrate structure. The plurality of zener diodes are located in a circuit element formation region of the substrate structure and connected in series with each other. Each of the zener diodes includes a zener diode doping structure and a zener diode metal structure. The zener diode doping structure is formed on the insulation layer and is covered by the dielectric layer. The zener diode doping structure includes a P-type doped region and an N-type doped region that are in contact with each other. The zener diode metal structure is formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. | 2021-11-18 |