46th week of 2016 patent applcation highlights part 56 |
Patent application number | Title | Published |
20160336406 | SEMICONDUCTOR DEVICES WITH SUPERLATTICE AND PUNCH-THROUGH STOP (PTS) LAYERS AT DIFFERENT DEPTHS AND RELATED METHODS - A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice. | 2016-11-17 |
20160336407 | SEMICONDUCTOR DEVICES WITH SUPERLATTICE LAYERS PROVIDING HALO IMPLANT PEAK CONFINEMENT AND RELATED METHODS - A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices. | 2016-11-17 |
20160336408 | REDUCTION OF DEFECT INDUCED LEAKAGE IN III-V SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 | 2016-11-17 |
20160336409 | Semiconductor Device Having an Impurity Concentration and Method of Manufacturing Thereof - A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body. | 2016-11-17 |
20160336410 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region. | 2016-11-17 |
20160336411 | RECESSED CONTACT TO SEMICONDUCTOR NANOWIRES - A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire. | 2016-11-17 |
20160336412 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate. | 2016-11-17 |
20160336413 | RECESS ARRAY DEVICE WITH REDUCED CONTACT RESISTANCE - A recess array device includes a semiconductor substrate having a main surface; a recessed trench in the main surface of the semiconductor substrate; a gate electrode disposed at a lower portion of the recessed trench; a liner layer disposed on directly on the gate electrode and being in direct contact with the gate electrode; a gate dielectric layer disposed only between the gate electrode and the semiconductor substrate and between the liner layer and the semiconductor substrate; and an epitaxial silicon layer disposed at an upper portion of the recessed trench. | 2016-11-17 |
20160336414 | DUAL WORK FUNCTION BURIED GATE-TYPE TRANSISTOR, METHOD FOR FORMING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate between the source region and the drain region; and a buried gate electrode inside the trench, wherein the buried gate electrode includes: a lower buried portion which includes a high work-function barrier layer including an aluminum-containing titanium nitride, and a first low-resistivity layer disposed over the high work-function barrier layer; and an upper buried portion which includes a low work-function barrier layer disposed over the lower buried portion and overlapping with the source region and the drain region, and a second low-resistivity layer disposed over the low work-function barrier layer. | 2016-11-17 |
20160336415 | MEMORY CELL STRUCTURE FOR IMPROVING ERASE SPEED - A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided. | 2016-11-17 |
20160336416 | Semiconductor Device Structure and Method - A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer. | 2016-11-17 |
20160336417 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; using a first patterned mask to form a gate dielectric layer on the substrate; removing the first patterned mask; removing part of the gate dielectric layer; and forming a shallow trench isolation (STI) adjacent to two sides of the gate dielectric layer. | 2016-11-17 |
20160336418 | SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES - A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses. | 2016-11-17 |
20160336419 | THIN FILM TRANSISTOR AND BACKPLANE SUBSTRATE OF A DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor includes a gate electrode on a substrate. The gate electrode includes a flat portion and an inclined portion at a side of the flat portion. A ratio of a height to a width (height/width) of the inclined portion is 1.192 or less. The thin film transistor also includes a gate insulating layer disposed on the substrate to cover the gate electrode and a polysilicon active layer on the gate insulating layer and over the gate electrode. The thin film transistor further includes a source electrode and a drain electrode respectively connected to two opposite end portions of the polysilicon active layer. | 2016-11-17 |
20160336420 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers. | 2016-11-17 |
20160336421 | DUAL WORK FUNCTION INTEGRATION FOR STACKED FINFET - A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type. | 2016-11-17 |
20160336422 | HIGH-K METAL GATE - An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier. | 2016-11-17 |
20160336423 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A semiconductor structure is formed in a SiC substrate. A thermal oxide film is formed on a front surface of the SiC substrate. An opening reaching the front surface of the SiC substrate is formed by etching a part of the thermal oxide film. The opening is filled with a material that becomes a Schottky electrode. Forming a sacrificial thermal oxide film on the front surface of the SiC substrate is not executed after the forming of the semiconductor structure and before the forming of the thermal oxide film. | 2016-11-17 |
20160336424 | SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES - A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses. | 2016-11-17 |
20160336425 | MULTICHANNEL DEVICES WITH IMPROVED PERFORMANCE AND METHODS OF MAKING THE SAME - A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. | 2016-11-17 |
20160336426 | SEMICONDUCTOR STRUCTURE WITH UNLEVELED GATE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over the gate dielectric layer. The gate structure further includes a gate electrode layer formed over the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer. | 2016-11-17 |
20160336427 | DILUTED DRIFT LAYER WITH VARIABLE STRIPE WIDTHS FOR POWER TRANSISTORS - A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions. | 2016-11-17 |
20160336428 | LOCAL SOI FINS WITH MULTIPLE HEIGHTS - A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height and located on a pedestal portion of a first oxide structure. The structure further includes a second silicon fin of a second height and located on a pedestal portion of a second oxide structure. The first oxide structure and the second oxide structure are interconnected and the second oxide structure has a bottommost surface that is located beneath a bottommost surface of the first oxide structure. Further, the second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar with a topmost surface of the second silicon fin. | 2016-11-17 |
20160336429 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer. | 2016-11-17 |
20160336430 | METHOD OF MANUFACTURING A HORIZONTAL GATE-ALL-AROUND TRANSISTOR HAVING A FIN - A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a confronting pair of wall parts. One of the wall parts is more arcuate than the other of the wall parts. A method for fabricating the semiconductor structure is also disclosed. | 2016-11-17 |
20160336431 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly dielectric, a control gate and a metal layer on a substrate, forming a conformal liner on the gate stack structure, covering a mask layer on the liner, where the mask layer is lower than the metal layer so that a portion of the liner is exposed, and performing a nitridation treatment to transform the exposed liner into a nitrided liner, so that at least the portion of the metal layer in the gate stack structure is covered by the nitrided liner. | 2016-11-17 |
20160336432 | TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL - Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions. | 2016-11-17 |
20160336433 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - To improve the electrical characteristics of a semiconductor device including an oxide semiconductor, and to provide a highly reliable semiconductor device with a small variation in electrical characteristics. The semiconductor device includes a first insulating film, a first barrier film over the first insulating film, a second insulating film over the first barrier film, and a first transistor including a first oxide semiconductor film over the second insulating film. The amount of hydrogen molecules released from the first insulating film at a given temperature higher than or equal to 400° C., which is measured by thermal desorption spectroscopy, is less than or equal to 130% of the amount of released hydrogen molecules at 300° C. The second insulating film includes a region containing oxygen at a higher proportion than oxygen in the stoichiometric composition. | 2016-11-17 |
20160336434 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer. | 2016-11-17 |
20160336435 | SEMICONDUCTOR DEVICE - When formed to have a lattice pattern, trenches are deeper at the portions thereof corresponding to the vertices of the lattice pattern than at the portions thereof corresponding to the sides. Such variations in the depths of trenches may disadvantageously result in variations in the gate threshold voltages (V | 2016-11-17 |
20160336436 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In one aspect of the present disclosure, a semiconductor device includes a channel layer, an Al | 2016-11-17 |
20160336437 | FIELD EFFECT TRANSISTOR - A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer. | 2016-11-17 |
20160336438 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer. | 2016-11-17 |
20160336439 | NONVOLATILE MEMORY DEVICE USING TWO-DIMENSIONAL MATERIAL AND METHOD OF MANUFACTURING THE SAME - Example embodiments relate to nonvolatile memory devices using a 2D material, and methods of manufacturing the nonvolatile memory device. The nonvolatile memory device includes a channel layer formed on a substrate, a gate stack that includes a gate electrode, source and drain electrodes. The channel layer has a threshold voltage greater than that of a graphene layer, and the gate stack includes a 2D material floating gate that is not in contact with the channel layer. The channel layer includes first and second material layers and a first barrier layer disposed between the first and second material layers, and the first and second material layers may contact the first barrier layer. | 2016-11-17 |
20160336440 | SUPER JUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing super junction device includes forming a first epitaxial layer on a semiconductor substrate. The first epitaxial layer is patterned to form a trench. The trench has a first sidewall region, a second sidewall region and a bottom region. The bottom region is positioned in between the first and second sidewall regions. A second epitaxial layer is formed on the first sidewall region, the second sidewall region and the bottom region. A portion of the second epitaxial layer on the first sidewall region and the second sidewall region is removed. An oxide layer in contact with the second epitaxial layer is formed. A gate layer in contact with the oxide layer is formed. | 2016-11-17 |
20160336441 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer. | 2016-11-17 |
20160336442 | INTEGRATED HIGH SIDE GATE DRIVER STRUCTURE AND CIRCUIT FOR DRIVING HIGH SIDE POWER TRANSISTORS - The present invention relates to an integrated high side gate driver structure for driving a power transistor. The high side gate driver structure comprises a semiconductor substrate comprising a first polarity semiconductor material in which a first well diffusion comprising a second polarity semiconductor material is formed. A peripheral outer wall of the first well diffusion is abutted to the semiconductor substrate. A second well diffusion, comprising first polarity semiconductor material, is arranged inside the first well diffusion such that an outer peripheral wall of the second well diffusion is abutted to an inner peripheral wall of the first well diffusion. The integrated high side gate driver structure further comprises a gate driver comprising a high side positive supply voltage port, a high side negative supply voltage port, a driver input and a driver output, wherein the gate driver comprises a transistor driver arranged in the second well diffusion such that a control terminal of the transistor driver and an output terminal of the transistor driver is coupled to the driver input and the driver output, respectively; the integrated high side gate driver structure also comprises a first electrical connection between the first well diffusion and the high side negative supply voltage port and a second electrical connection between the second well diffusion and the high side negative supply voltage port. | 2016-11-17 |
20160336443 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction. | 2016-11-17 |
20160336444 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a first direction parallel to the surface and a first insulating film is around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, and a pillar diameter of the bottom of the pillar-shaped silicon layer is equal to a fin width of the top of the fin-shaped silicon layer. The pillar diameter and the fin width are parallel to the surface. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer. | 2016-11-17 |
20160336445 | Tuning Strain in Semiconductor Devices - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. | 2016-11-17 |
20160336446 | METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE - An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption. | 2016-11-17 |
20160336447 | METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE - An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption. | 2016-11-17 |
20160336448 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate stack over the substrate, forming a first recess cavity and a second recess cavity in the substrate, growing a first epitaxial (epi) material in the first recess cavity and a second epi material in the second recess cavity, and etching the first epi material and the second epi material. The first recess cavity is between the isolation feature and the first gate stack and the second recess cavity is between the first gate stack and the second gate stack. A topmost surface of the first epi material has a first crystal plane and a topmost surface of the second epi material has a second crystal plane. The topmost surface of the etched first epi material has a third crystal plane different from both the first crystal plane and the second crystal plane. | 2016-11-17 |
20160336449 | SEMICONDUCTOR TRANSISTOR HAVING BUFFER LAYER BETWEEN CHANNEL AND SUBSTRATE - FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions. | 2016-11-17 |
20160336450 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS - A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions. | 2016-11-17 |
20160336451 | NON-PLANAR TRANSISTOR AND METHOD OF FORMING THE SAME - A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same. | 2016-11-17 |
20160336452 | Thin Film Transistor and Method of Fabricating the Same, Array Substrate, and Display Device - The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a display device. The thin film transistor comprises a gate, an active layer, a source and a drain formed on a substrate, the active layer comprises an oxide having doped ions, the doped ions have a p-orbital electron arrangement structure, and an energy level of p-orbital of the doped ions is higher than that of 2p-orbital of oxygen ions in the oxide, so that top of valence band of the active layer is higher than the energy level of oxygen vacancies formed in the oxide. The active layer of the thin film transistor is made of the oxide having the doped ions, which may improve a stability of the thin film transistor, and there is no need to add a light blocking structure in the display device. | 2016-11-17 |
20160336453 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode. A length of a shortest distance on the semiconductor layer from the first connection point to the second connection point may be no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode. | 2016-11-17 |
20160336454 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening. | 2016-11-17 |
20160336455 | MODULATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A modulation circuit includes a load and a transistor serving as a switch. The transistor has an oxide semiconductor layer in which hydrogen concentration is 5×10 | 2016-11-17 |
20160336456 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE - In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced. | 2016-11-17 |
20160336457 | SEMICONDUCTOR DEVICE - To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer. | 2016-11-17 |
20160336458 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin film transistor, a method of fabricating the same, an array substrate and a display device are disclosed. The method of fabricating the thin film transistor comprises: forming a semiconductor layer; forming a conductive film that does not react with acid solution on the semiconductor layer to be employed as a protective layer; forming a source electrode and a drain electrode on the protective layer; and removing a portion of the protective layer between the source electrode and the drain electrode to expose a portion of the semiconductor layer between the source electrode and the drain electrode. | 2016-11-17 |
20160336459 | THIN FILM ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film. | 2016-11-17 |
20160336460 | THIN-FILM TRANSISTOR WITH CARRIER INJECTION STRUCTURE - A thin-film transistor includes a substrate, a semiconductor channel region, a gate insulating layer, a source region, a drain region, a source electrode, a drain electrode and a gate electrode. The thin-film transistor also includes a carrier injection terminal, and the carrier injection terminal can provide the semiconductor channel region with a carrier of which the polarity is opposite to that of a channel carrier when the thin-film transistor is conducting. The thin-film transistor can significantly reduce device degradation and threshold voltage shift caused by a dynamic hot carrier effect, thereby improving the reliability of a thin-film transistor device and a circuit and simplifying the complexity of the design of a threshold voltage compensation circuit. In addition, the thin-film transistor has low processing difficulty and has no influence on the normal operation of a device. | 2016-11-17 |
20160336461 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME, DISPLAY DEVICE - The present disclosure provides a TFT, an array substrate and a fabricating method thereof and a display device. The TFT includes a gate, an active layer, a first electrode and a second electrode, the first electrode is arranged at one side of the active layer, the second electrode is arranged at the other side of the active layer, the first electrode, the active layer and the second electrode forms a stacked structure, the gate is arranged to surround the stacked structure, and the gate and the stacked structure are insulated and separated from each other. Under fixed occupation area, the conductive channel of the TFT of the present disclosure has increased width, so drain current in saturation region is increased without impacting aperture ratio of a display panel, which further optimizes performance of the TFT and the array substrate, and improves display effect of the display device. | 2016-11-17 |
20160336462 | PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device including a photoelectric converter, a transparent cover, an insulating material layer and a photonic crystal layer is provided. The photoelectric converter is adapted to receive a light. The transparent cover is disposed on a side of the photoelectric converter. The insulating material layer is disposed between the photoelectric converter and the transparent cover. The photonic crystal layer is disposed between the insulating material layer and the transparent cover, wherein the material of the photonic crystal layer is different from the material of the insulating material layer. | 2016-11-17 |
20160336463 | SOLAR CELL AND MANUFACTURING METHOD OF THE SAME - A solar cell includes: a semiconductor substrate having a light receiving surface and a back surface; a first semiconductor layer of the first conductivity type on the back surface; a second semiconductor layer of the second conductivity type on the back surface; a first electrode electrically connected to the first semiconductor layer; and an insulating layer for electrically insulating the first semiconductor layer and the second semiconductor layer from each other in a region in which an edge of the first semiconductor layer and an edge of second semiconductor layer overlap. The first electrode includes a first transparent electrode layer and a first collection electrode layer on the first transparent electrode layer. The first transparent electrode layer is separated into a primary electrode layer that is on the first semiconductor layer and a separated electrode layer that is on the second semiconductor layer in the region. | 2016-11-17 |
20160336464 | SOLAR CELL - A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region. The width of the inclined surface in a direction perpendicular to the thickness direction of the insulating layer and toward the second-conductivity-type region is 10 to 300 times the thickness of the insulating layer in a region excluding the inclined surface. | 2016-11-17 |
20160336465 | HIGH-EFFICIENCY PHOTOVOLTAIC BACK-CONTACT SOLAR CELL STRUCTURES AND MANUFACTURING METHODS - Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell. | 2016-11-17 |
20160336466 | HIGH-PERFORMING BULK PHOTOVOLTAICS - The present invention provides materials with high bulk photovoltaic effect response. The present invention also provides for products comprising the high bulk photovoltaic effect materials of the present invention. | 2016-11-17 |
20160336467 | HIGH-EFFICIENCY FLEXIBLE PHOTOVOLTAIC FILM, MANUFACTURING PROCESS AND USE - A new-generation photovoltaic flexible film offering high efficiency results from the combination of an ultra-thin and very flexible photovoltaic film with a very thin, antireflection, prismatic film absorbing energy from solar radiation and righting the angle of the solar rays is provided. The process of the invention allows encasement of the photovoltaic modules and the prismatic film by an assembly of flexible polymer thermoplastic thin films and resinless thermofusion in vacuo. | 2016-11-17 |
20160336468 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - Disclosed is a solar cell including a semiconductor substrate, a conductive area including a first conductive area and a second conductive area formed on one surface of the semiconductor substrate, a passivation film formed on the conductive area, the passivation film having a contact hole, a protective film formed on the conductive area inside the contact hole, the protective film being formed on at least one of at least a portion of an inner side surface of the contact hole and the passivation film, and an electrode electrically connected to the conductive area through the contact hole with the protective film interposed therebetween. | 2016-11-17 |
20160336469 | ENCAPSULANT FOR PV MODULE, METHOD OF MANUFACTURING THE SAME AND PV MODULE COMPRISING THE SAME (As Amended) - The present application relates to an encapsulant for a PV module, a method of manufacturing the same and a PV module. The encapsulant according to an embodiment of the present application has excellent heat resistance or the like and improved creep physical properties, and thus even when the encapsulant is used under conditions of a high temperature and/or high humidity for a long time, deformation is small and the encapsulant can exhibit excellent adhesive strength. Accordingly, when the encapsulant is applied to a PV module, durability or the like may be improved. | 2016-11-17 |
20160336470 | SOLAR CELL MODULE - This solar cell module is provided with: solar cells; a first protective member winch is provided over a light-receiving-surface side of the solar ceils; a second protective member which is provided over a rear-surface side of the solar cells; and a sealing layer which is provided between the protective members, and which seals the solar cells. A light receiving surface-side area of the sealing layer, said area being positioned further towards the first protective member side than the solar cells, includes: a wavelength conversion material which absorbs light of a specific wavelength, and converts said wavelength: and an ultraviolet-ray absorption material which selectively absorbs ultraviolet rays. | 2016-11-17 |
20160336471 | PHOTOVOLTAIC INTERCONNECT WIRE - A photovoltaic interconnect wire includes a conductive base strip with grooves provided thereon, and the grooves are linear and/or curved strip-shaped grooves ( | 2016-11-17 |
20160336472 | SOLAR CELL AND SOLAR CELL MODULE - To provide a solar cell having improved photoelectric conversion efficiency and a solar cell module. A solar cell ( | 2016-11-17 |
20160336473 | ANNEALING FOR DAMAGE FREE LASER PROCESSING FOR HIGH EFFICIENCY SOLAR CELLS - Annealing solutions providing damage-free laser patterning utilizing auxiliary heating to anneal laser damaged ablation regions are provided herein. Ablation spots on an underlying semiconductor substrate are annealed during or after pulsed laser ablation patterning of overlying transparent passivation layers. | 2016-11-17 |
20160336474 | METHODS OF FORMING COLLOIDAL NANOCRYSTAL-BASED THIN FILM DEVICES - Methods of forming colloidal nanocrystal (NC)-based thin film devicesare disclosed. The methods include the steps of depositing a dispersion of NCs on a substrate to form a NC thin-film, wherein at least a portion of the NCs is capped with chalcogenocyanate (xCN)-based ligands; and doping the NC thin-film with a metal. | 2016-11-17 |
20160336475 | HEXAGONAL PHASE EPITAXIAL CADMIUM SULFIDE ON COPPER INDIUM GALLIUM SELENIDE FOR A PHOTOVOLTAIC JUNCTION - A method of manufacturing a photovoltaic structure includes forming a p-type semiconductor absorber layer containing a copper indium gallium selenide based material over a first electrode, forming a n-type cadmium sulfide layer over the p-type semiconductor absorber layer by sputtering in an ambient including hydrogen gas and oxygen gas, and forming a second electrode over the cadmium sulfide layer. | 2016-11-17 |
20160336476 | P-COMPENSATED AND P-DOPED SUPERLATTICE INFRARED DETECTORS - Barrier infrared detectors configured to operate in the long-wave (LW) infrared regime are provided. The barrier infrared detector systems may be configured as pin, pbp, barrier and double heterostructrure infrared detectors incorporating optimized p-doped absorbers capable of taking advantage of high mobility (electron) minority carriers. The absorber may be a p-doped Ga-free InAs/InAsSb material. The p-doping may be accomplished by optimizing the Be doping levels used in the absorber material. The barrier infrared detectors may incorporate individual superlattice layers having narrower periodicity and optimization of Sb composition to achieve cutoff wavelengths of ˜10 μm. | 2016-11-17 |
20160336477 | ELIMINATING EMISSIVE SUB-BANDGAP STATES IN NANOCRYSTALS - The size-dependent band-gap tunability and solution processability of nanocrystals (NCs) make them attractive candidates for optoelectronic applications. One factor that presently limits the device performance of NC thin films is sub-bandgap states, also referred to as trap states. Trap states can be controlled by surface treatment of the nanocrystals. | 2016-11-17 |
20160336478 | TANDEM SOLAR CELL - This application is related to a method of manufacturing a solar cell device comprising providing a substrate comprising Ge or GaAs; forming a first tunnel junction on the substrate, wherein the first tunnel junction comprises a first n-type layer comprising InGaP:Te, and a first alloy layer comprising AlxGa( | 2016-11-17 |
20160336479 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND SEMICONDUCTOR LIGHT-EMITTING DEVICE ARRAY - A semiconductor light-emitting device comprises an optical semiconductor multilayer disposed above a support substrate, which has a structure in which a first semiconductor layer having a first conductivity type, an active layer having light emitting properties, and a second semiconductor layer having a second conductivity type different from the first conductivity type are sequentially stacked from the support substrate side, in which a groove, which has a height exceeding at least the active layer from the support substrate side, is formed along an outer edge of the optical semiconductor multilayer, and which includes an external region being a region further outside than the groove, an inner region being a region further inside than the groove, and a connection region corresponding to a region where the groove is provided, in plan view. | 2016-11-17 |
20160336480 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element includes: a lower clad layer | 2016-11-17 |
20160336481 | P-SIDE LAYERS FOR SHORT WAVELENGTH LIGHT EMITTERS - A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of Al | 2016-11-17 |
20160336482 | LIGHT-EMITTING DEVICE - An object of the present invention is to provide a light-emitting device comprising: a substrate, a first light-emitting semiconductor stack having a first transverse width, the first light-emitting semiconductor stack comprising a first active layer emitting a first radiation of a first dominant wavelength during operation; a second light-emitting semiconductor stack having a second transverse width less than the first transverse width and comprising a second active layer emitting a second radiation of a second dominant wavelength shorter than the first dominant wavelength during operation; and a first conductive connecting structure between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack, wherein the first conductive connecting structure is lattice-mismatched to the first active layer and to the second active layer, the first light-emitting semiconductor stack is between the substrate and the second light-emitting semiconductor stack. | 2016-11-17 |
20160336483 | Semiconductor Structure with Inhomogeneous Regions - A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device. | 2016-11-17 |
20160336484 | LED WITH INTERNALLY CONFINED CURRENT INJECTION AREA - Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation. | 2016-11-17 |
20160336485 | LIGHT EMITTING DIODE WITH STRUCTURED SUBSTRATE - Embodiments of the invention include a semiconductor light emitting device. The device includes a substrate having first surface and a second surface opposite the first surface. The device further includes a semiconductor structure disposed on the first surface of the substrate. A cavity is disposed within the substrate. The cavity extends from the second surface of the substrate. The cavity has a sloped side wall. | 2016-11-17 |
20160336486 | MICRO-LIGHT-EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A micro-light-emitting diode (micro-LED) device includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer includes a first bottom surface. The active layer is disposed on the first semiconductor layer. The second semiconductor layer disposed on the active layer includes a second bottom surface. A surface of the second semiconductor layer opposite to the active layer is a light-exiting surface of the micro-LED device. The second semiconductor layer has different thicknesses, in which a minimum thickness of the second semiconductor layer is located at an edge or at least one side of the second semiconductor layer. Vertical-projection zones of the first semiconductor layer, the active layer, and the second semiconductor layer on the first bottom surface are substantially the same. | 2016-11-17 |
20160336487 | MANUFACTURING METHODS OF SEMICONDUCTOR LIGHT-EMITTING DEVICES - A method of making a semiconductor device comprising: providing a semiconductor wafer having a semiconductor layer ( | 2016-11-17 |
20160336488 | Printable Inorganic Semiconductor Structures - The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate. | 2016-11-17 |
20160336489 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a substrate, an LED chip, a control element, a conductive layer and an insulating layer. The substrate, made of a semiconductor material, has an obverse surface and a reverse surface spaced apart from each other in the thickness direction of the substrate. The control element controls light emission of the LED chip. The conductive layer is electrically connected to the LED chip and the control element. The insulating layer is arranged between at least apart of the conductive layer and the substrate. The substrate has a recess formed in the obverse surface, and the LED chip is housed in the recess. The control element is arranged between the LED chip and the reverse surface in the thickness direction of the substrate. | 2016-11-17 |
20160336490 | METHODS FOR PREPARING QUANTUM DOTS WITH INSULATOR COATINGS - A method of fabricating a semiconductor structure comprises forming a quantum dot. An insulator layer of silica is then formed encapsulating the quantum dot to create a coated quantum dot, using a reverse micelle sol-gel reaction. In one embodiment, the reverse micelle sol-gel reaction includes dissolving the quantum dot in a first non-polar solvent to form a first solution, adding the first solution to a second solution having a surfactant dissolved in a second non-polar solvent; and adding sodium silicate, potassium silicate, or lithium silicate to the second solution. | 2016-11-17 |
20160336491 | Method for Producing a Ceramic Conversion Element and Light-Emitting Device - A method for producing a ceramic conversion element and a light-emitting device are disclosed. In an embodiment the method includes providing at least four functional layers, each being a green body or a ceramic, wherein first functional layer is formed as a first luminous layer comprising an oxide and configured to at least partially convert light of a first wavelength range into light of a second wavelength range, wherein a second functional layer is formed as a second luminous layer comprising a nitride and configured to at least partially convert light of the first wavelength range into light of a third wavelength range, wherein a third functional layer is formed as a first intermediate layer, wherein the first intermediate layer comprises an oxide, wherein a fourth functional layer is formed as a second intermediate layer, and wherein the second intermediate layer comprises a nitride or an oxynitride. | 2016-11-17 |
20160336492 | QUANTUM PLATELET CONVERTER - In one aspect a light emitting device includes a light emitting diode (LED) chip, and an encapsulant covering the LED chip. The encapsulant is embedded with a downconverter. The downconverter includes a quasi-two dimensional quantum nanoplatelet structure. | 2016-11-17 |
20160336493 | METHOD FOR PRODUCING SEMICONDUCTOR LIGHT-EMITTING DEVICE - A method for producing a semiconductor light-emitting device having a substrate, an element and an encapsulating material as constituent members, includes: a first step of providing the substrate with the element; a second step of potting un uncured encapsulating material onto the substrate to cover the element; and a third step of curing the potted encapsulating material in such a manner that all of the following formulae (1), (2) and (3) are satisfied when the absorbances which a cured encapsulating material having a thickness of t [nm] has at wavelengths of 380 nm, 316 nm and 260 nm are represented by Abs | 2016-11-17 |
20160336494 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate having a first main surface that serves as the light extraction surface, a second main surface that is opposite the first main surface, and a mounting surface that is adjacent to at least the second main surface, and that is provided an insulating base material, a pair of connection terminals disposed on the second main surface, and a heat dissipation terminal disposed on the second main surface and between the pair of connection terminals; a light emitting element that is mounted on the first main surface of the substrate and; a sealing member that seals the light emitting element and is formed substantially in the same plane as the substrate on the mounting surface. | 2016-11-17 |
20160336495 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT - The invention relates to an optoelectronic semiconductor component comprising an optoelectronic semiconductor chip. In particular, the optoelectronic semiconductor component is a radiation-emitting semiconductor component which is designed as a side emitter. The invention also relates to a method for producing an optoelectronic semiconductor component of said type. | 2016-11-17 |
20160336496 | LIGHT-EMITTING ELEMENT - A light-emitting element includes: a light transmissive substrate having a first main surface, a second main surfaces, a first lateral surface, a second lateral surface, a third lateral surface, and a fourth lateral surface; a semiconductor layered body; a first light reflection member; and a second light reflection member. A cross-sectional plane of the light transmissive substrate perpendicular to the first main surface and intersecting with the third lateral surface and the fourth lateral surface has a first concave figure having a first recess. The deepest portion of the first recess is arranged on an inner side of an outer periphery of the semiconductor layered body. The third lateral surface includes one or more surfaces defining the first recess. | 2016-11-17 |
20160336497 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device having an enhanced surface property and an electrical property is provided. The light emitting device includes a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode disposed on one side of the light emitting structure and electrically connected to the first semiconductor layer, a second electrode disposed on one side of the light emitting structure and electrically connected to the second semiconductor layer, and an ohmic contact including a first layer disposed between the second electrode and the second semiconductor layer and having aluminum (Al), a second layer including at least one M | 2016-11-17 |
20160336498 | LED PACKAGE STRUCTURE - An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet. | 2016-11-17 |
20160336499 | ELECTRONIC DEVICE AND METHOD OF MAKING THE SAME - A method of making an electronic device includes: providing a base unit including a metal substrate, an insulating layer disposed on the metal substrate, and a first circuit unit disposed on the insulating layer; and laser ablating the first circuit unit, the insulating layer and the metal substrate in such a manner that a hole defined by a hole-defining wall is formed to expose the metal substrate, and that an interconnecting layer is formed on the hole-defining wall during laser ablation of the metal substrate. | 2016-11-17 |
20160336500 | WAFER-LEVEL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a wafer-level semiconductor device and a manufacturing method thereof. The wafer-level semiconductor device comprises a wafer-level substrate; a plurality of serial groups formed on a surface of the substrate and are disposed in parallel, each serial group comprising a plurality of parallel groups disposed in series, each parallel groups comprising a plurality of unit cells disposed in parallel, wherein each unit cell is an independent functional unit which is formed by processing a semiconductor layer directly grown on a surface of the substrate; and a lead, which is at least electrically connected between two selected parallel groups in each serial group to make ON-voltages of all the serial groups substantially consistent. The device of the present invention, with a simple structure, a simple and convenient manufacturing process, and a high efficiency to produce qualified products, can be put into large-scale production and application. | 2016-11-17 |
20160336501 | ENERGY HARVESTING FOR WEARABLE TECHNOLOGY THROUGH A THIN FLEXIBLE THERMOELECTRIC DEVICE - A method and/or apparatus of energy harvesting for wearable technology through a thin flexible thermoelectric device is disclosed. A lower conduction layer is deposited onto a lower dielectric layer. An active layer, comprising at least one thin film thermoelectric conduit and a thermal insulator, is above the lower conduction layer. An internal dielectric layer is deposited above the active layer, and conduit holes are drilled above each thermoelectric conduit. An upper conduction layer and upper dielectric layer are deposited, connecting the thermoelectric conduits in series. The resulting flexible thermoelectric device generates a voltage when exposed to a temperature gradient. | 2016-11-17 |
20160336502 | THERMAL RADIATION MICROSENSOR COMPRISING THERMOELECTRIC MICRO PILLARS - A thermal radiation microsensor can comprise thermoelectric micro pillars, in which multiple vertically standing thermoelectric micro pillars can act as thermoelectric pairs and mechanical support of an absorption layer. Radiation absorbed by the absorption layer can produce a temperature difference, which drives the thermocouple comprising p-type and n-type micro pillars to output a voltage. Multiple thermocouples can be connected in series to improve the signal output. | 2016-11-17 |
20160336503 | METHOD OF PRODUCING A FLEXIBLE THERMOELECTRIC DEVICE TO HARVEST ENERGY FOR WEARABLE APPLICATIONS - A method and/or apparatus of energy harvesting for wearable technology through a thin flexible thermoelectric device is disclosed. A lower conduction layer is formed on top of a lower dielectric layer. An active layer, comprising at least one thin film thermoelectric conduit and a thermal insulator, is formed above the lower conduction layer. An internal dielectric layer is formed above the active layer, and contact holes are drilled above each thermoelectric conduit. An upper conduction layer and upper dielectric layer are formed, connecting the thermoelectric conduits in series. The resulting flexible thermoelectric device generates a voltage when exposed to a temperature gradient. | 2016-11-17 |
20160336504 | Positioning Device - A piezo-device for positioning a load is described. The piezo-device comprises a stator module comprising one or more piezo-electric actuator(s) oriented in a single direction. The stator module furthermore comprises at least one hinge for allowing deformation of the stator module upon actuation of the piezo-electric actuator. The piezo-device also comprises a slider or rotor module, the slider or rotor module being in contact with the stator module in at least three points of contact. The at least one hinge and the one or more piezo-electric actuator(s) are arranged in position with respect to each other for providing a tangential motion of the slider or rotor module upon actuation of the at least one piezo-actuator. The slider or the rotor are driven and supported through the points of contact. | 2016-11-17 |
20160336505 | ELEMENT AND ELECTRIC GENERATOR - An element including: electrodes; and intermediate layers, each being sandwiched between any pair of the electrodes, wherein the intermediate layers comprise at least two selected from the group consisting of: intermediate layer that can be elongated and deformed in direction that is not parallel to direction in which external force is applied, when the external force is applied to the intermediate layer; intermediate layer that can be compressed and deformed in direction that is parallel to direction in which external force is applied, when the external force is applied to the intermediate layer; and intermediate layer that can be elongated and deformed in direction that is not parallel to direction in which external force is applied, and can be compressed and deformed in direction that is parallel to the direction in which the external force is applied, when the external force is applied to the intermediate layer. | 2016-11-17 |