46th week of 2018 patent applcation highlights part 61 |
Patent application number | Title | Published |
20180331019 | SEMICONDUCTOR DEVICE - A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead. | 2018-11-15 |
20180331020 | PACKAGE WITH BACKSIDE PROTECTIVE LAYER DURING MOLDING TO PREVENT MOLD FLASHING FAILURE - A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process. | 2018-11-15 |
20180331021 | DIE PACKAGE COMPONENT WITH JUMPER STRUCTURE AND MANUFACTURING METHOD THEREOF - A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove. | 2018-11-15 |
20180331022 | DIE PACKAGE COMPONENT WITH JUMPER STRUCTURE AND MANUFACTURING METHOD THEREOF - A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove. | 2018-11-15 |
20180331023 | LEAD FRAME - A lead frame includes a frame part, a lead extending inward from the frame part and having a front surface and a back surface, and an external connection terminal formed at a part of the lead in an extension direction and protruding from the back surface of the lead. The lead includes a pentagonal shape in a cross-section where the front surface of the lead faces upward, the pentagonal shape having a quadrangular main body part and a triangular protrusion protruding from a lower surface of the main body part. A width of a lower end of the main body part is smaller than a width of an upper end of the main body part. | 2018-11-15 |
20180331024 | Electronic component - Electronic component having a first lead frame consisting of an electrically conductive material. The first lead frame carries a first semiconductor component. In the plane of the lead frame a shunt element is arranged, wherein the shunt element comprises a resistor body arranged between a first terminal contact and a second terminal contact. An electrically conducting connection extends from a terminal of the first semiconductor component through the first lead frame to the first terminal contact of the shunt element. A current measurement with good accuracy is facilitated. | 2018-11-15 |
20180331025 | SUPPORT TERMINAL INTEGRAL WITH DIE PAD IN SEMICONDUCTOR PACKAGE - A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces. | 2018-11-15 |
20180331026 | WIRING SUBSTRATE - A wiring substrate includes an insulation layer, a first wiring layer, and a second wiring layer. The first wiring layer is embedded in the insulation layer with an upper surface of the first wiring layer exposed from the insulation layer. The second wiring layer includes a terminal portion located at a lower position than a lower surface of the insulation layer and an embedded portion embedded in the insulation layer. The wiring substrate further includes a connection via connecting the first wiring layer and the embedded portion. The insulation layer includes an extension between the embedded portion and a lower surface of the first wiring layer. The extension includes a through hole. The connection via is located in the through hole of the extension. | 2018-11-15 |
20180331027 | ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic package and a method for fabricating the same are provide. An antenna substrate is stacked on a carrier structure stacking assembly. Since no additional layout area is required to be added to the carrier structure stacking assembly, the length of an antenna can be designed as required, and the antenna can thus meet its operational requirement. | 2018-11-15 |
20180331028 | WAFER-SCALE POWER DELIVERY - A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required. | 2018-11-15 |
20180331029 | Assemblies Which Include Wordlines Over Gate Electrodes - Some embodiments include an assembly having bitlines extending along a first direction. Semiconductor pillars are over the bitlines and are arranged in an array. The array includes columns along the first direction and rows along a second direction which crosses the first direction. Each of the semiconductor pillars extends vertically. The semiconductor pillars are over the bitlines. The semiconductor pillars are spaced from one another along the first direction by first gaps, and are spaced from one another along the second direction by second gaps. Wordlines extend along the second direction, and are elevationally above the semiconductor pillars. The wordlines are directly over the first gaps and are not directly over the semiconductor pillars. Gate electrodes are beneath the wordlines and are coupled with the wordlines. Each of the gate electrodes is within one of the second gaps. Shield lines may be within the first gaps. | 2018-11-15 |
20180331030 | Ultra High Performance Interposer - An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via. | 2018-11-15 |
20180331031 | Semiconductor Device with Slotted Backside Metal for Improving Q Factor - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot. | 2018-11-15 |
20180331032 | InFO Coil Structure and Methods of Manufacturing Same - A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material until the coil is exposed, forming at least one dielectric layer over the encapsulating material and the coil, and forming a plurality of redistribution lines extending into the at least one dielectric layer. The plurality of redistribution lines is electrically coupled to the coil. | 2018-11-15 |
20180331033 | Method for contacting a metallic contact pad in a printed circuit board and printed circuit board - A method for contacting a metallic contact pad embedded in a printed circuit board layer sequence, comprising the steps of producing a first hole matrix having a plurality of holes in a surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, of applying a metal layer in order to at least partly fill the holes of the first hole matrix, of producing a second hole matrix having a plurality of holes in the surface of the printed circuit board layer sequence in order to partly expose the metallic contact pad, wherein the holes of the second hole matrix are arranged in a manner offset relative to the holes of the first hole matrix, and of applying a metal layer in order to at least partly fill the holes of the second hole matrix, and a correspondingly produced printed circuit board. | 2018-11-15 |
20180331034 | THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH - An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure. | 2018-11-15 |
20180331035 | MICROPROCESSOR PACKAGE WITH FIRST LEVEL DIE BUMP GROUND WEBBING STRUCTURE - A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package. | 2018-11-15 |
20180331036 | GROUND PLANE VERTICAL ISOLATION OF, GROUND LINE COAXIAL ISOLATION OF, AND IMPEDANCE TUNING OF HORIZONTAL DATA SIGNAL TRANSMISSION LINES ROUTED THROUGH PACKAGE DEVICES - A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device. | 2018-11-15 |
20180331037 | Stacked IC Structure with System Level Wiring on Multiple Sides of the IC Die - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180331038 | 3D Chip Sharing Data Bus - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180331039 | SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE - Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity. | 2018-11-15 |
20180331040 | DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD - A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer. | 2018-11-15 |
20180331041 | SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor package device, which includes a semiconductor die and a redistribution layer disposed over and electrically coupled to the semiconductor die. The redistribution layer includes a first conductive plate, a second conductive plate disposed over the first conductive plate, an insulating film between the first conductive plate and the second conductive plate, and a first dielectric material encapsulating the first conductive plate, the second conductive plate and the insulating film. The first conductive plate and the second conductive plate are configured as an antenna plane and a ground plane, respectively. | 2018-11-15 |
20180331042 | SIZE AND EFFICIENCY OF DIES - An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate. | 2018-11-15 |
20180331043 | RLINK-GROUND SHIELDING ATTACHMENT STRUCTURES AND SHADOW VOIDING FOR DATA SIGNAL CONTACTS OF PACKAGE DEVICES; VERTICAL GROUND SHIELDING STRUCTURES AND SHIELD FENCING OF VERTICAL DATA SIGNAL INTERCONNECTS OF PACKAGE DEVICES; AND GROUND SHIELDING FOR ELECTRO OPTICAL MODULE CONNECTOR DATA SIGNAL CONTACTS AND CONTACT PINS OF PACKAGE DEVICES - A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts. | 2018-11-15 |
20180331044 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure. | 2018-11-15 |
20180331045 | VARIABLE RESISTANCE VIAS AND RELATED METHODS - Implementations of a via for a semiconductor devices may include a first tungsten layer deposited conformally within the via, and may be recessed within the via, and a second tungsten layer deposited into the recess over the first tungsten layer. A plane formed by the second tungsten layer may be substantially parallel with a plane aligned substantially perpendicularly with a longest dimension of the via viewed in cross section. | 2018-11-15 |
20180331046 | SEMICONDUCTOR DEVICES WITH ALIGNMENT KEYS - A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench. | 2018-11-15 |
20180331047 | REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS - Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask. | 2018-11-15 |
20180331048 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes disposing a plurality of devices on a carrier; immersing the plurality of devices into a molding compound to dispose the molding compound between the plurality of devices; and removing the carrier from the plurality of devices and the molding compound, wherein a first surface of the molding compound adjacent to a plurality of active components over the plurality of devices includes a recessed portion recessed from one of first surfaces of the plurality of devices. | 2018-11-15 |
20180331049 | CHIP ON FILM PACKAGE - A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a first conductive film. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed in the mounting region and electrically connected to the patterned circuit layer. The first conductive film covers at least a part of the first solder resist layer and an opening exposing at least a part of the patterned circuit layer, wherein the first conductive film is configured to shield electromagnetic interference (EMI) emanating by the chip and is electrically connected to the patterned circuit layer. | 2018-11-15 |
20180331050 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - The disclosure relates to a semiconductor package device. The semiconductor package device includes a substrate having a first surface and a second surface opposite to the first surface and including a first conductive contact. The semiconductor package device further includes an electronic component disposed on the first surface of the substrate. The semiconductor package device further includes a metal frame disposed on the first surface of the substrate. The semiconductor package device further includes an antenna disposed on the metal frame, wherein the antenna is electrically isolated from the metal frame and electrically connected to the first conductive contact of the substrate. | 2018-11-15 |
20180331051 | MICROELECTRONIC DEVICES DESIGNED WITH HIGH FREQUENCY COMMUNICATION DEVICES INCLUDING COMPOUND SEMICONDUCTOR DEVICES INTEGRATED ON A DIE FABRIC ON PACKAGE - Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. | 2018-11-15 |
20180331052 | TERAHERTZ DETECTOR COMPRISED OF P-N JUNCTION DIODE - A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode. | 2018-11-15 |
20180331053 | Electrical device and a method for forming an electrical device - An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions. | 2018-11-15 |
20180331054 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other. | 2018-11-15 |
20180331055 | Semiconductor Package System and Method - A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. | 2018-11-15 |
20180331056 | MIXED UBM AND MIXED PITCH ON A SINGLE DIE - Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region. | 2018-11-15 |
20180331057 | THROUGH-SUBSTRATE-VIAS WITH SELF-ALIGNED SOLDER BUMPS - A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material. | 2018-11-15 |
20180331058 | THROUGH-SUBSTRATE-VIAS WITH SELF-ALIGNED SOLDER BUMPS - A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material. | 2018-11-15 |
20180331059 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer. | 2018-11-15 |
20180331060 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DETECTOR, METHODS FOR MANUFACTURING SAME, AND SEMICONDUCTOR CHIP OR SUBSTRATE - In a method for manufacturing a radiation detector, counter pixel electrodes | 2018-11-15 |
20180331061 | INTEGRATED DEVICE COMPRISING BUMP ON EXPOSED REDISTRIBUTION INTERCONNECT - A device comprising a semiconductor die and a redistribution portion coupled to the semiconductor die. The redistribution portion includes a passivation layer and a redistribution interconnect comprising a first surface and a second surface opposite to the first surface. The redistribution interconnect is formed over the passivation layer such that the first surface is over the passivation layer and the second surface is free of contact with any passivation layer. The device includes a bump interconnect coupled to the second surface of the redistribution interconnect. In some implementations, the bump interconnect comprises a surface that faces the redistribution interconnect, and wherein an entire surface of the bump interconnect that faces the redistribution interconnect is free of contact with the passivation layer. | 2018-11-15 |
20180331062 | ELECTRICAL COMPONENT WITH THIN SOLDER RESIST LAYER AND METHOD FOR THE PRODUCTION THEREOF - An electrical device and a method for the manufacture of an electrical device are specified. The device has a carrier with an upper side and a metallized contact surface arranged on it as well as a solder mask layer which covers a part of the upper side but not the contact surface. The solder mask layer has a thickness of 200 nm or less, thereby facilitating subsequent process steps for encapsulating the device. | 2018-11-15 |
20180331063 | METHOD FOR JOINING ELECTRONIC PART USING A JOINING SILVER SHEET - A method for joining an electronic part, comprising: inserting a joining silver sheet between an electronic part and a substrate, to which the electronic part is to be joined; and heating them to the temperature range of T | 2018-11-15 |
20180331064 | ELECTRICAL INTERCONNECTIONS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME - An electrical interconnection includes a wire loop having a first end bonded to a first bonding site using a first bonding portion, and a second end bonded to a second bonding site using a second bonding portion. The second bonding portion includes a folded portion having a wire that extends from the second end of the wire loop and is folded on the second bonding site. The folded portion includes a first folded portion connected to the second end of the wire loop and extending toward the first bonding site, a second folded portion provided on the first folded portion, and a tail protruding from a portion of the second folded portion. An interface is formed between the first and second folded portions. A top surface of the second folded portion includes an inclined surface recessed toward the first folded portion. | 2018-11-15 |
20180331065 | ELECTRONIC SANDWICH STRUCTURE WITH TWO PARTS JOINED TOGETHER BY MEANS OF A SINTERING LAYER - A description is given of an electronic sandwich structure which has at least a first and a second part to be joined, which are sintered together by means of a sintering layer. The sintering layer is formed as a substantially uninterrupted connecting layer, the density of which varies in such a way that at least one region of higher density and at least one region of lower density alternate with one another. A description is also given of a method for forming a sintering layer of an electronic sandwich structure, in which firstly a sintering material layer is applied substantially continuously to a first part to be joined as a connecting layer, this sintering material layer is subsequently dried and, finally, alternating regions of higher density and of lower density of the connecting layer are produced by sintering the first part to be joined with the sintering layer on a second part to be joined. | 2018-11-15 |
20180331066 | Processed stacked dies - Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface. | 2018-11-15 |
20180331067 | Universal Surface-Mount Semiconductor Package - A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques. | 2018-11-15 |
20180331068 | ELECTRONIC COMPONENT PACKAGE - An electronic component package according to an embodiment of the present disclosure includes a first substrate, a sealing member, a second substrate, and connectors. The first substrate has a first top surface on which a first electronic component is mounted. The sealing member is positioned on the first top surface and configured to seal the first electronic component and a second electronic component. The second substrate has a second top surface on which the second electronic component is mounted, and is positioned within the sealing member. The connectors electrically couple the first substrate and the second substrate. | 2018-11-15 |
20180331069 | Package Structure and Method of Forming the Same - An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector. | 2018-11-15 |
20180331070 | PACKAGE STACKING USING CHIP TO WAFER BONDING - Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer. | 2018-11-15 |
20180331071 | STACKED SEMICONDUCTOR PACKAGES, METHODS OF FABRICATING THE SAME, AND/OR SYSTEMS EMPLOYING THE SAME - An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. | 2018-11-15 |
20180331072 | Face-to-Face Mounted IC Dies with Orthogonal Top Interconnect Layers - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180331073 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV). | 2018-11-15 |
20180331074 | Microelectronic Package Having Stub Minimization Using Symmetrically-Positioned Duplicate Sets of Terminals for Wirebond Assemblies Without Windows - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 2018-11-15 |
20180331075 | SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. | 2018-11-15 |
20180331076 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips. | 2018-11-15 |
20180331077 | POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR CORE MODULE - It is an object to provide a pressure-contact power semiconductor device and a power semiconductor core module which are capable of properly reducing their sizes. Each power semiconductor core module includes the following: a plurality of power semiconductor chips including a plurality of self-turn-off semiconductor elements and a plurality of diodes adjacent to each other in plan view; and a plurality of first springs disposed between an upper metal plate and a conductive cover plate. The plurality of self-turn-off semiconductor elements of each power semiconductor core module are arranged along any one of an L-shaped line, a cross-shaped line, and a T-shaped line in plan view. | 2018-11-15 |
20180331078 | TUNABLE INTEGRATED OPTICS LED COMPONENTS AND METHODS - Light emitting diode (LED) devices and methods. An example apparatus can include a substrate, one or more LEDs, light-transmissive encapsulation material, and a reflective material covering a portion of the encapsulation material to form a defined opening. The opening allows light emitted from an LED to pass through in a prescribed manner. In some embodiments, the apparatus can be subsequently treated to modify the surface having the opening. In other embodiments, the reflective material can be disposed on a lateral surface of the encapsulation material to reflect light in a desired direction. | 2018-11-15 |
20180331079 | WATERPROOF SEALED CIRCUIT APPARATUS AND METHOD OF MAKING THE SAME - A waterproof sealed circuit apparatus includes a circuit substrate having a first side opposite a second side. The first side includes a circuit trace. A semiconductor device die is electrically coupled to the circuit trace on the first side of the circuit substrate. A polymer sealing layer is adhered to the first side of the circuit substrate and covers the semiconductor device die. Polymer chains of the sealing layer are crosslinked. | 2018-11-15 |
20180331080 | System-in-Package Devices and Methods for Forming System-in-Package Devices - A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component. | 2018-11-15 |
20180331081 | INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FOR PLATFORM MINIATURIZATION - Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed. | 2018-11-15 |
20180331082 | CO-INTEGRATED III-N VOLTAGE REGULATOR AND RF POWER AMPLIFIER FOR ENVELOPE TRACKING SYSTEMS - Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate. | 2018-11-15 |
20180331083 | Power Converter Monolithically Integrating Transistors, Carrier, and Components - A power converter ( | 2018-11-15 |
20180331084 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - A light emitting device includes: a base comprising a first lead, a second lead, and a supporting member; a light emitting element mounted on the first lead; a protection element mounted on the second lead; a wire including a first end and a second end, wherein the first end is connected to an upper surface of the first lead, and the second end is connected to a first terminal electrode of the protection element; a resin frame located on an upper surface of the base, wherein the resin frame covers at least part of the protection element and surrounds the light emitting element and the first end of the wire; a first resin member surrounded by the resin frame and covering the light emitting element and the first end of the wire; and a second resin member covering the resin frame and the first resin member. | 2018-11-15 |
20180331085 | MICRO-LED ARRAY DISPLAY DEVICES - Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled. | 2018-11-15 |
20180331086 | MICRO-LED ARRAY DISPLAY DEVICES - Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled. | 2018-11-15 |
20180331087 | STACKED SEMICONDUCTOR PACKAGE HAVING MOLD VIAS AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads. | 2018-11-15 |
20180331088 | METHODS AND SYSTEMS FOR PACKAGING SEMICONDUCTOR DEVICES TO IMPROVE YIELD - A method for packaging semiconductor devices in a chamber includes arranging a carrier substrate including a first semiconductor device and a second semiconductor device within the chamber, flowing a molding compound into the chamber to cover surfaces of the first semiconductor device, the second semiconductor device, and the carrier substrate, and flowing a forming gas into the chamber while curing the molding compound. The forming gas includes a reactive gas configured to react with the first semiconductor device and the second semiconductor device during curing. | 2018-11-15 |
20180331089 | PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS - Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad. | 2018-11-15 |
20180331090 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE - Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described. | 2018-11-15 |
20180331091 | DETECTION DEVICE AND METHOD FOR GATE DRIVE CIRCUIT - A detection device for a gate drive circuit and a detection method for the gate drive circuit are disclosed. In a connecting element of the detection device, a first end of the first connecting part is electrically connected with an output end of the gate drive circuit, and a second end thereof is electrically connected with the third connecting part. A first end of the second connecting part is electrically connected with the test pad, and a second end thereof is electrically insulated from the third connecting part. According to the present disclosure, the gate drive circuit can be prevented from being destroyed by electrostatic discharge (ESD), and a qualified rate of a liquid crystal display panel can be improved. | 2018-11-15 |
20180331092 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion. | 2018-11-15 |
20180331093 | PROTECTION CIRCUIT AND OPERATIONAL METHOD OF THE PROTECTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS - A protection circuit includes: a high-side switch connected to a power terminal to which a predetermined power supply voltage VBB is supplied from an onboard battery; and an NMOS transistor MT | 2018-11-15 |
20180331094 | 3D Chip Sharing Data Bus Circuit - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180331095 | 3D Chip with Shielded Clock Lines - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180331096 | FABRICATION OF FIELD EFFECT TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES THROUGH MODIFIED CHANNEL INTERFACES - A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset. | 2018-11-15 |
20180331097 | METHODS, APPARATUS AND SYSTEM FOR VERTICAL FINFET DEVICE WITH REDUCED PARASITIC CAPACITANCE - A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region. | 2018-11-15 |
20180331098 | GATE ISOLATION IN NON-PLANAR TRANSISTORS - An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein. | 2018-11-15 |
20180331099 | SELF-HEATING TEST STRUCTURE - A semiconductor device includes a substrate, a semiconductor fin on the substrate, first and second MOS devices on the substrate, and a dummy gate structure on the semiconductor fin and between the first and second MOS devices. The first dummy gate structure is operative to electrically isolate the first MOS device from the second MOS device when a first potential is applied to the dummy gate structure and a second potential is applied to the substrate. The first MOS device includes a first gate structure on the semiconductor fin, a first source and a first drain on opposite sides of the first gate structure and partially in the semiconductor fin. The second MOS device includes a second gate structure on the semiconductor fin, a second source and a second drain on opposite sides of the second gate structure and partially in the semiconductor fin. | 2018-11-15 |
20180331100 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING MOS TRANSISTORS WITH NONUNIFORM GATE ELECTRODE STRUCTURES - A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width. | 2018-11-15 |
20180331101 | SELF-ALIGNED METAL GATE WITH POLY SILICIDE FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS - A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET). | 2018-11-15 |
20180331102 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body. | 2018-11-15 |
20180331103 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion. | 2018-11-15 |
20180331104 | FABRICATION OF FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICES WITH UNIFORM HYBRID CHANNELS - A method of forming complementary vertical fins and vertical fins with uniform heights, including, forming a trench in a region of a substrate, wherein the trench extends through an upper portion of the substrate and a buried punch-through stop layer, and extends into a lower portion of the substrate, forming a reformed punch-through stop layer in a bottom portion of the trench, forming a fin formation region on the reformed punch-through stop layer, and forming a complementary vertical fin from the fin formation region and a vertical fin from the upper portion of the substrate on a first region of the substrate adjacent to the second region. | 2018-11-15 |
20180331105 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer. | 2018-11-15 |
20180331106 | METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION - Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures. | 2018-11-15 |
20180331107 | Memory Cells and Memory Arrays - Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor. | 2018-11-15 |
20180331108 | QUANTUM DEVICE WITH SPIN QUBITS - A quantum device with spin qubits, comprising:
| 2018-11-15 |
20180331109 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 2018-11-15 |
20180331110 | METHODS OF OPERATING A MEMORY DEVICE - A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween. | 2018-11-15 |
20180331111 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices are provided. A semiconductor device includes a substrate, and a source/drain region in the substrate. Moreover, the semiconductor device includes a gate structure in a recess in the substrate. The gate structure includes a liner that includes a first portion and a second portion on the first portion. The second portion is closer, than the first portion, to the source/drain region. The second portion includes a metal alloy. Methods of forming a semiconductor device are also provided. | 2018-11-15 |
20180331112 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region. | 2018-11-15 |
20180331113 | SEMICONDUCTOR STRUCTURES, MEMORY CELLS AND DEVICES COMPRISING FERROELECTRIC MATERIALS, SYSTEMS INCLUDING SAME, AND RELATED METHODS - A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed. | 2018-11-15 |
20180331114 | PLATE NODE CONFIGURATIONS AND OPERATIONS FOR A MEMORY ARRAY - Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells. | 2018-11-15 |
20180331115 | NON-VOLATILE MEMORY ALLOWING A HIGH INTEGRATION DENSITY - The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer. | 2018-11-15 |
20180331116 | SEMICONDUCTOR MEMORY - According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate. | 2018-11-15 |
20180331117 | MULTILEVEL MEMORY STACK STRUCTURE WITH TAPERED INTER-TIER JOINT REGION AND METHODS OF MAKING THEREOF - A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer. | 2018-11-15 |
20180331118 | MULTI-LAYER BARRIER FOR CMOS UNDER ARRAY TYPE MEMORY DEVICE AND METHOD OF MAKING THEREOF - A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron. | 2018-11-15 |