46th week of 2018 patent applcation highlights part 60 |
Patent application number | Title | Published |
20180330919 | METHOD OF OPERATING A CHARGED PARTICLE BEAM SPECIMEN INSPECTION SYSTEM - A charged particle beam specimen inspection system is described. The system includes an emitter for emitting at least one charged particle beam, a specimen support table configured for supporting the specimen, an objective lens for focusing the at least one charged particle beam, a charge control electrode provided between the objective lens and the specimen support table, wherein the charge control electrode has at least one aperture opening for the at least one charged particle beam, and a flood gun configured to emit further charged particles for charging of the specimen, wherein the charge control electrode has a flood gun aperture opening. | 2018-11-15 |
20180330920 | ION IMPLANTATION APPARATUS - An ion implantation apparatus includes an ion source that is capable of generating a calibration ion beam including a multiply charged ion which has a known energy corresponding to an extraction voltage, an upstream beamline that includes amass analyzing magnet and a high energy multistage linear acceleration unit, an energy analyzing magnet, a beam energy measuring device that measures an energy of the calibration ion beam downstream of the energy analyzing magnet, and a calibration sequence unit that produces an energy calibration table representing a correspondence relation between the known energy and the energy of the calibration ion beam measured by the beam energy measuring device. An upstream beamline pressure is adjusted to a first pressure during an ion implantation process, and is adjusted to a second pressure higher than the first pressure while the energy calibration table is produced. | 2018-11-15 |
20180330921 | Pulsed, Bidirectional Radio Frequency Source/Load - A radio frequency power system includes a master RF generator and an auxiliary RF generator, wherein each generator outputs a respective RF signal. The master RF generator also outputs a RF control signal to the auxiliary RF generator, and the RF signal output by the auxiliary RF generator varies in accordance with the RF control signal. The auxiliary RF generator receives sense signals indicative of an electrical characteristic of the respective RF signals output by the master RF generator and the auxiliary RF generator. The auxiliary RF generator determines a phase difference between the RF signals. The sensed electrical characteristics and the phase are used independently or cooperatively to control the phase and amplitude of the RF signal output by the auxiliary RF generator. The auxiliary generator includes an inductive clamp circuit that returns energy reflected energy back from a coupling network to a variable resistive load. | 2018-11-15 |
20180330922 | APPARATUS AND METHOD FOR SURFACE COATING BY MEANS OF GRID CONTROL AND PLASMA-INITIATED GAS-PHASE POLYMERIZATION - An apparatus and a method for surface coating by means of grid control and plasma-initiated gas-phase polymerization. The method comprises: dividing a vacuum chamber into a discharging cavity and a processing chamber by using a metal grid mesh, the metal grid mesh being insulated from the vacuum chamber; separately feeding carrier gas and monomer steam into the discharging cavity and the processing chamber through different pipes, putting a substrate to be processed in the processing chamber, and generating in the discharging cavity plasma that continuously discharges; and applying pulse positive bias to the metal grid mesh, to release the plasma into the processing chamber to initiate monomer polymerization. | 2018-11-15 |
20180330923 | MULTI-LAYER PLASMA EROSION PROTECTION FOR CHAMBER COMPONENTS - A method of applying a multi-layer plasma resistant coating on an article comprises performing plating or ALD to form a conformal first plasma resistant layer on an article, wherein the conformal first plasma resistant layer is formed on a surface of the article and on walls of high aspect ratio features in the article. The conformal first plasma resistant coating has a porosity of approximately 0% and a thickness of approximately 200 nm to approximately 1 micron. One of electron beam ion assisted deposition (EB-IAD), plasma enhanced chemical vapor deposition (PECVD), aerosol deposition or plasma spraying is then performed to form a second plasma resistant layer that covers the conformal first plasma resistant layer at a region of the surface but not at the walls of the high aspect ratio features. | 2018-11-15 |
20180330924 | INSULATOR STRUCTURE FOR AVOIDING ABNORMAL ELECTRICAL DISCHARGE AND PLASMA CONCENTRATION - An insulator for a processing apparatus including an upper electrode, a lower electrode and a reaction chamber, the insulator being adapted to be arranged around the upper electrode and the insulator including: a bottom end adapted to face the reaction chamber; and a side wall facing a side wall of the upper electrode, wherein an edge portion of the bottom end of the insulator extends radially inwardly to form a projecting portion such that the projecting portion covers an edge of a bottom surface of the upper electrode and a clearance between the side wall of the upper electrode and the side wall of the insulator. | 2018-11-15 |
20180330925 | SUPPORTING UNIT AND SUBSTRATE TREATING APPARATUS INCLUDING THE SAME - An apparatus for treating a substrate comprises a chamber having a treatment space for treating the substrate; a supporting unit which supports the substrate, inside the treatment space; a gas supplying unit which supplies process gas into the treatment space; and a plasma source which generates plasma based on the process gas inside the treatment space. The supporting unit comprises a supporting plate on which the substrate is placed; a focus ring which is disposed to surround the substrate supported by the supporting plate; a temperature control unit which adjusts a temperature of the focus ring. The temperature control unit may include a first heater which is disposed to heat the focus ring under the focus ring and to be opposite to the focus ring; and a cooling member which is provided under the first heater. | 2018-11-15 |
20180330926 | REAL TIME MONITORING WITH CLOSED LOOP CHUCKING FORCE CONTROL - Embodiments disclosed herein include a method for minimizing chucking forces on a workpiece disposed on a electrostatic chuck within a plasma processing chamber. The method begins by placing a workpiece on an electrostatic chuck in a processing chamber. A plasma is struck within the processing chamber. A deflection force is monitored on the workpiece. A chucking voltage is applied at a minimum value. A backside gas pressure is applied at a minimum pressure. The chucking voltage and or backside gas pressure is adjusted such that the deflection force is less than a threshold value. And the chucking voltage and the backside gas pressure are simultaneously ramped up. | 2018-11-15 |
20180330927 | Plasma Source For Rotating Susceptor - Plasma source assemblies comprising an RF hot electrode having a body and at least one return electrode spaced from the RF hot electrode to provide a gap in which a plasma can be formed. An RF feed is connected to the RF hot electrode at a distance from the inner peripheral end of the RF hot electrode that is less than or equal to about 25% of the length of the RF hot electrode. | 2018-11-15 |
20180330928 | TEMPERATURE-TUNED SUBSTRATE SUPPORT FOR SUBSTRATE PROCESSING SYSTEMS - A system for controlling a temperature of a substrate during treatment in a substrate processing system includes a substrate support defining a center zone and a radially-outer zone. The substrate is arranged over both the center zone and the radially-outer zone during treatment. A first heater is configured to heat the center zone. A second heater is configured to heat the radially-outer zone. A first heat sink has one end in thermal communication with the center zone. A second heat sink has one end in thermal communication with the radially-outer zone. A temperature difference between the center zone and the radially-outer zone is greater than 10° C. during the treatment. | 2018-11-15 |
20180330929 | IN-SITU REMOVAL OF ACCUMULATED PROCESS BYPRODUCTS FROM COMPONENTS OF A SEMICONDUCTOR PROCESSING CHAMBER - Embodiments of the disclosure generally relate to methods for removal of accumulated process byproducts from components of a semiconductor processing chamber. In one embodiment of the disclosure, a method for cleaning components within a processing chamber is disclosed. The method includes heating the components within the processing chamber to a temperature between about 150-300 degrees Celsius, exposing the components of the chamber to one or more precursor gases and removing a product of a reaction between a fluorine-based compound disposed on the components and the one or more precursor gases. The one or more precursor gases include trimethyl aluminum or tin acetylacetonate. | 2018-11-15 |
20180330930 | METHOD OF CLEANING PLASMA PROCESSING APPARATUS - There is provision of a cleaning method of a plasma processing apparatus including a plasma treatment chamber for applying plasma treatment to a substrate. The method includes: insulating a part of the plasma treatment chamber, generating plasma of fluorocarbon gas in the plasma treatment chamber, and removing deposits on a non-plasma surface of a space outside of the plasma treatment chamber, by the plasma of the fluorocarbon gas introduced from the plasma treatment chamber to the outside space. | 2018-11-15 |
20180330931 | Sputtering Arrangement and Sputtering Method for Optimized Distribution of the Energy Flow - The present disclosure relates to a sputtering arrangement, a vacuum coating system, and a method for carrying out HiPIMS coating methods; the sputtering arrangement has at least two different interconnection possibilities and the switch to the second interconnection possibility, in which two sputtering sub-assemblies are operated simultaneously with high power pulses, achieves a productivity gain. | 2018-11-15 |
20180330932 | Rapid Evaporative Ionisation Mass Spectrometry ("REIMS") and Desorption Electrospray Ionisation Mass Spectrometry ("DESI-MS") Analysis of Swabs and Biopsy Samples - A method is disclosed comprising providing a biological sample on a swab, directing a spray of charged droplets onto a surface of the swab in order to generate a plurality of analyte ions, and analysing the analyte ions. | 2018-11-15 |
20180330933 | COOLING DEVICES AND INSTRUMENTS INCLUDING THEM - Certain configurations are described herein of an instrument comprising a passive cooling device which includes, in part, a loop thermosyphon configured to thermally couple to a component of the instrument to be cooled. In some instances, the cooling device can cool a transistor, transistor pair, an interface or other components of the instrument. | 2018-11-15 |
20180330934 | ION FOCUSING - The invention generally relates to apparatuses for focusing ions at or above ambient pressure and methods of use thereof. In certain embodiments, the invention provides an apparatus for focusing ions that includes an electrode having a cavity, at least one inlet within the electrode configured to operatively couple with an ionization source, such that discharge generated by the ionization source is injected into the cavity of the electrode, and an outlet. The cavity in the electrode is shaped such that upon application of voltage to the electrode, ions within the cavity are focused and directed to the outlet, which is positioned such that a proximal end of the outlet receives the focused ions and a distal end of the outlet is open to ambient pressure. | 2018-11-15 |
20180330935 | SYSTEMS AND APPROACHES FOR SEMICONDUCTOR METROLOGY AND SURFACE ANALYSIS USING SECONDARY ION MASS SPECTROMETRY - Systems and approaches for semiconductor metrology and surface analysis using Secondary Ion Mass Spectrometry (SIMS) are disclosed. In an example, a secondary ion mass, spectrometry (SIMS) system includes a sample stage. A primary ion beam is directed to the sample stage. An extraction lens is directed at the sample stage. The extraction lens is configured to provide a low extraction field for secondary ions emitted from a sample on the sample stage. A magnetic sector spectrograph is coupled to the extraction lens along an optical path of the SIMS system. The magnetic sector spectrograph includes an electrostatic analyzer (ESA) coupled to a magnetic sector analyzer (MSA). | 2018-11-15 |
20180330936 | IMAGING MASS SPECTROMETER - A time-of-flight mass spectrometer is disclosed comprising ion optics that map an array of ions at an ion source array ( | 2018-11-15 |
20180330937 | Broadband Light Source Including Transparent Portion with High Hydroxide Content - A laser-sustained plasma light source includes a plasma lamp configured to contain a volume of gas and receive illumination from a pump laser in order to generate a plasma. The plasma lamp includes one or more transparent portions transparent to illumination from the pump laser and at least a portion of the broadband radiation emitted by the plasma. The one or more transparent portions are formed from a transparent material having elevated hydroxide content above 700 ppm. | 2018-11-15 |
20180330938 | WAFER PROCESSING METHOD - A wafer processing method includes a close contact making step of pressing a protective film against the front side of a wafer in a radially outward direction starting from the center of the wafer to thereby bring the protective film into close contact with the front side of the wafer, a protective member fixing step of covering the protective film with a protective member formed by curing a liquid resin to thereby fix the protective member through the protective film to the front side of the wafer, a grinding step of grinding the back side of the wafer to reduce the thickness of the wafer, and a peeling step of peeling the protective film and the protective member from the wafer thinned by the grinding step. | 2018-11-15 |
20180330939 | DEPOSITION OF BORON AND CARBON CONTAINING MATERIALS - Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film. | 2018-11-15 |
20180330940 | SEMICONDUCTOR CLEANER SYSTEMS AND METHODS - In an embodiment, the present invention discloses a EUV cleaner system and process for cleaning a EUV carrier. The euv cleaner system comprises separate dirty and cleaned environments, separate cleaning chambers for different components of the double container carrier, gripper arms for picking and placing different components using a same robot handler, gripper arms for picking and placing different components using a same robot handler, gripper arms for holding different components at different locations, horizontal spin cleaning and drying for outer container, hot water and hot air (70 C) cleaning process, vertical nozzles and rasterizing megasonic nozzles for cleaning inner container with hot air nozzles for drying, separate vacuum decontamination chambers for outgassing different components, for example, one for inner and one for outer container with high vacuum (e.g., <10 | 2018-11-15 |
20180330941 | METHOD FOR OBTAINING A SEMI-POLAR NITRIDE LAYER ON A CRYSTALLINE SUBSTRATE - A process allowing at least one semipolar layer of nitride to be obtained, which layer is obtained from a least one among gallium, indium and aluminum on a top surface of a single-crystal layer based on silicon, wherein the process comprises the following steps: etching, from the top surface of the single-crystal layer, a plurality of parallel grooves comprising at least two opposite inclined facets, at least one of two opposite facets having a crystal orientation; masking the top surface of the single-crystal layer such that the facets having a crystal orientation are not masked; and epitaxial growth of the semipolar layer of nitride from the not masked facets; wherein the etching is carried out on a stack comprising the single-crystal layer and at least one stop layer that is surmounted by the single-crystal layer and wherein the etching etches the single-crystal layer selectively with respect to the stop layer so that the etching stops on contact with the stop layer. | 2018-11-15 |
20180330942 | Halogen Removal Module and Associated Systems and Methods - A chamber is formed to enclose a processing region. A passageway is configured to provide for entry of a substrate into the processing region and removal of the substrate from the processing region. A substrate support structure is disposed within the processing region and configured to support the substrate within the processing region. At least one gas input is configured to supply one or more gases to the processing region. At least one gas output is configured to exhaust gases from the processing region. A humidity control device is configured to control a relative humidity within the processing region. At least one heating device is disposed to provide temperature control of the substrate within the processing region. The processing region of the chamber is directly accessible from a substrate handling module configured to operate at atmospheric pressure. | 2018-11-15 |
20180330943 | HALOGEN ABATEMENT FOR HIGH ASPECT RATIO CHANNEL DEVICE DAMAGE LAYER REMOVAL FOR EPI GROWTH - In an embodiment, a method of processing a substrate includes introducing a first process gas or a mixture of the first process gas and a second process gas into an etch chamber; exposing the substrate to the first process gas or to the mixture of the first and second process gases, the substrate having halogen residue formed on an exposed surface, the substrate having high aspect ratio features; forming and maintaining a plasma of the first process gas or a plasma of the mixture of the first and second process gases in the etch chamber to remove the residue from the surface by applying a first source power; exposing the substrate to the second process gas; and forming and maintaining a plasma of the second process gas in the etch chamber to remove the residue from the surface by applying a second source power and a bias power | 2018-11-15 |
20180330944 | TECHNIQUES TO ENGINEER NANOSCALE PATTERNED FEATURES USING IONS - A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension. | 2018-11-15 |
20180330945 | REMOTE PLASMA BASED DEPOSITION OF SILICON CARBIDE FILMS USING SILICON-CONTAINING AND CARBON-CONTAINING PRECURSORS - A doped or undoped silicon carbide film can be deposited using a remote plasma chemical vapor deposition (CVD) technique. One or more silicon-containing precursors are provided to a reaction chamber. Radical species, such as hydrogen radical species, are provided in a substantially low energy state or ground state and interact with the one or more silicon-containing precursors to deposit the silicon carbide film. A co-reactant may be flowed with the one or more silicon-containing precursors, where the co-reactant is a carbon-containing precursor and each silicon-containing precursor is a silane-based precursor with at least a silicon atom having two or more hydrogen atoms bonded to the silicon atom. | 2018-11-15 |
20180330946 | DEVICES, SYSTEMS, AND METHODS FOR LIGHT EMISSION AND DETECTION USING AMORPHOUS SILICON - Amorphous silicon devices, systems, and related methods are described herein. An example method for fabricating a thin film with light-emitting or light-detecting capability can include depositing a thin film of amorphous silicon on a wafer such that crystalline defects are distributed throughout the thin film. Additionally, an example photonic device can include a p-doped region and an n-doped region formed on a wafer, and a resonator structure formed on the wafer. The resonator structure can be formed from amorphous silicon and can be arranged between the p-doped and n-doped regions to form a PIN junction. Optionally, the photonic device can be incorporated into a monolithic integrated optical system. | 2018-11-15 |
20180330947 | DISPLAY PANEL AND MANUFACTURING METHOD OF DISPLAY PANEL - A display panel and a manufacturing method of a display panel are provided. The manufacturing method of a display panel includes: forming the nanoporous silicon oxide material on a substrate to form a nanoporous silicon oxide layer; forming the amorphous silicon material on the nanoporous silicon oxide layer to form an amorphous silicon layer; irradiating the amorphous silicon layer by a laser to crystallize the amorphous silicon layer to form a polycrystalline silicon layer; forming the gate oxide material on the polycrystalline silicon layer to form a gate oxide layer. | 2018-11-15 |
20180330948 | METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A method of fabricating a three-dimensional semiconductor device comprises stacking first hardmask layers and second hardmask layers on a lower layer including a pattern region and a buffer region adjacent to the pattern region, the second hardmask layers and the first hardmask layers for forming a first hardmask pattern and a second hardmask pattern, patterning the second hardmask layer to form the second hardmask pattern including a plurality of first mask holes on the pattern region and at least one recess on the buffer region, the plurality of first mask holes exposing the first hardmask layer, and etching the first hardmask layer using the second hardmask pattern as an etch mask to form the first hardmask pattern including a plurality of etch mask holes on the pattern region and at least one buffer mask hole on the buffer region, the plurality of etch mask holes exposing a top surface of the lower layer, the at least one buffer mask hole having a bottom surface spaced apart from the top surface of the lower layer. | 2018-11-15 |
20180330949 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen. | 2018-11-15 |
20180330950 | METHOD FOR ASSEMBLING SUBSTRATES BY BONDING INDIUM PHOSPHATE SURFACES - The invention concerns an assembly method comprising the following steps: a) providing a first substrate comprising a first face made from crystalline indium phosphide, b) providing a second substrate comprising a second crystalline face different from the indium phosphide, c) forming an intermediate layer of crystalline indium phosphide on the second face of the second substrate, d) forming an assembly, via a direct bonding step, by bringing the first face of the first substrate into contact with the intermediate layer, the direct bonding step being carried out in an atmosphere having a pressure greater than 10−4 Pa, and preferably higher than 10−3 Pa, e) subjecting the assembly formed in step d) to heat treatment. | 2018-11-15 |
20180330951 | DEPOSITION OF METAL SILICIDE LAYERS ON SUBSTRATES AND CHAMBER COMPONENTS - Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support. | 2018-11-15 |
20180330952 | METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus comprises forming a first photoresist on each of a first portion and a second portion of a member, exposing the first photoresist on the first portion using a first photomask, exposing the first photoresist on the second portion using a second photomask, forming a first resist pattern by developing the first photoresist on the first portion and the second portion, etching the first portion and the second portion using the first resist pattern as a mask, forming a second photoresist on a third portion of the member, exposing the second photoresist on the third portion using a third photomask, forming a second resist pattern by developing the second photoresist on the third portion, and etching the third portion using the second resist pattern as a mask. | 2018-11-15 |
20180330953 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and fabrication method are provided. The method includes providing a first dielectric layer with a first groove on a base substrate. A first gate electrode is formed in the first groove, with a top surface lower than the first dielectric layer. A first protective layer is formed on a portion of the top surface of the first gate electrode, with a first oxygen ionic concentration. A compensating protective layer is formed on a remaining portion of the top surface of the first gate electrode exposed by the first protective layer, with a second oxygen ionic concentration. A second dielectric layer is formed on the first protective layer, on the compensating protective layer, and on the first dielectric layer, with a third oxygen ionic concentration. The first oxygen ionic concentration and second oxygen ionic concentration are smaller than the third oxygen ionic concentration. | 2018-11-15 |
20180330954 | TRANSISTOR AND FABRICATION METHOD THEREOF - A junction-less transistor structure and fabrication method thereof are provided. The method includes providing a semiconductor substrate; and forming an epitaxial layer having a first surface and a second surface on the semiconductor substrate. The method also includes forming a plurality of trenches in the epitaxial layer from the first surface thereof; and forming a gate dielectric layer on side and bottom surfaces of the plurality of trenches. Further, the method includes forming a gate electrode layer on the gate dielectric layer and in the plurality of trenches; and forming an insulation layer on the gate electrode layer. Further, the method also includes forming a drain electrode layer on the first surface of the epitaxial layer; removing the semiconductor substrate; and forming a source electrode layer on the second surface of the epitaxial layer. | 2018-11-15 |
20180330955 | POROUS TIN OXIDE FILMS - Initial film layers prepared from tin(II) chloride spontaneously generate open cavities when the initial film layers are thermally cured to about 400° C. using a temperature ramp of 1° C./minute to 10° C./minute while exposed to air. The openings of the bowl-shaped cavities have characteristic dimensions whose lengths are in a range of 30 nm to 300 nm in the plane of the top surfaces of the cured film layers. The cured film layers comprise tin oxide and have utility in gas sensors, electrodes, photocells, and solar cells. | 2018-11-15 |
20180330956 | CHEMICAL MECHANICAL POLISHING APPARATUS AND CONTROL METHOD THEREOF - Provided are a chemical mechanical polishing apparatus and a control method thereof. The chemical mechanical polishing apparatus includes a plurality of polishing platens provided with a polishing pad on an upper surface thereof, and a polishing platen transferring unit for transferring the plurality of polishing platens to different process positions according to a predetermined process sequence. Here, different processes are performed at different process positions. | 2018-11-15 |
20180330957 | WORKPIECE PROCESSING METHOD - Disclosed herein is a workpiece processing method including a mask preparing step of preparing a mask that covers devices on a front surface of a workpiece and exposes streets, a plasma etching step of repeating an operation of supplying plasmatized SF | 2018-11-15 |
20180330958 | ETCHING METHOD - A selectivity can be improved in a desirable manner when etching a processing target object containing silicon carbide. An etching method of processing the processing target object, having a first region containing silicon carbide and a second region containing silicon nitride and in contact with the first region, includes etching the first region to remove the first region atomic layer by atomic layer by repeating a sequence comprising: generating plasma from a first gas containing nitrogen to form a mixed layer containing ions contained in the plasma generated from the first gas in an atomic layer of an exposed surface of the first region; and generating plasma from a second gas containing fluorine to remove the mixed layer by radicals contained in the plasma generated from the second gas. | 2018-11-15 |
20180330959 | METHOD FOR SELECTIVELY ETCHING WITH REDUCED ASPECT RATIO DEPENDENCE - A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase. | 2018-11-15 |
20180330960 | Methods for Improved Critical Dimension Uniformity in a Semiconductor Device Fabrication Process - Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening. | 2018-11-15 |
20180330961 | METHOD FOR FORMING A PLANARIZATION STRUCTURE - A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material. | 2018-11-15 |
20180330962 | SUBSTRATE TREATMENT METHOD AND SUBSTRATE TREATMENT APPARATUS - A substrate treatment method capable of obtaining a flat processing target film. Molecules of an HF gas are adsorbed onto a corner SiO | 2018-11-15 |
20180330963 | IN-SITU SELECTIVE DEPOSITION AND ETCHING FOR ADVANCED PATTERNING APPLICATIONS - Embodiments of the invention provide a method for in-situ selective deposition and etching for advanced patterning applications. According to one embodiment the method includes providing in a process chamber a substrate having a metal-containing layer thereon, and exposing the substrate to a gas pulse sequence to etch the metal-containing layer in the absence of a plasma, where the gas pulse sequence includes, in any order, exposing the substrate to a first reactant gas containing a halogen-containing gas, and exposing the substrate to a second reactant gas containing an aluminum alkyl. According to another embodiment, the substrate has an exposed first material layer and an exposed second material layer, and the exposing to the gas pulse sequence selectively deposits an additional material layer on the exposed first material layer but not on the exposed second material layer. | 2018-11-15 |
20180330964 | ANNEALING METHOD FOR IMPROVING BONDING STRENGTH - The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment. | 2018-11-15 |
20180330965 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication process includes providing a base substrate; forming a carbon-containing dielectric layer over the base substrate; and performing a chemical mechanical polishing (CMP) process on the carbon-containing dielectric layer. The chemical mechanical polishing process includes performing a plurality of polishing processes on the carbon-containing dielectric layer and a weak acid solution is used to clean a polishing pad before and after each of the polishing processes. | 2018-11-15 |
20180330966 | FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE - A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer. | 2018-11-15 |
20180330967 | Power Semiconductor Module Arrangement and Method for Producing the Same - A power semiconductor module arrangement includes a base plate configured to be arranged in a housing, a contact element configured to, when the base plate is arranged in the housing, provide an electrical connection between the inside and the outside of the housing, and a connecting element configured to connect the contact element to the base plate. The connecting element includes a first electrically insulating layer, a second electrically insulating layer configured to attach the contact element to the first electrically insulating layer, and a third electrically insulating layer configured to attach the first electrically insulating layer to the base plate. | 2018-11-15 |
20180330968 | Method Of Fabricating Low-Profile Footed Power Package - A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. | 2018-11-15 |
20180330969 | Package Structures and Method of Forming the Same - Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer. | 2018-11-15 |
20180330970 | Semiconductor Bonding Structures and Methods - A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill. | 2018-11-15 |
20180330971 | SUBSTRATE CLEANING APPARATUS AND SUBSTRATE CLEANING METHOD - A substrate cleaning apparatus includes a first processing unit configured to supply a first processing liquid for removing a residue adhering to a substrate onto the substrate on which a metal film is exposed at a recess of a pattern; a second processing unit configured to supply, onto the substrate, a second processing liquid for forming a protective film insoluble to the first processing liquid; a third processing unit configured to supply, onto the substrate, a third processing liquid for dissolving the protective film; and a control unit. The control unit performs forming the protective film on the metal film in a state that an upper portion of the pattern is exposed from the protective film; removing the residue adhering to the upper portion of the pattern after the forming of the protective film; and removing the protective film from the substrate after the removing of the residue. | 2018-11-15 |
20180330972 | LASER PROCESSING METHOD - A laser processing method includes a step of holding a film side of a workpiece which has been divided into chips and whose reverse side carries an adhesive film stuck thereto, a step of detecting widths of grooves in the workpiece at predetermined chip intervals and central coordinates of the widths of the grooves, a step of calculating laser beam irradiation lines based on the detected widths of the grooves and the detected central coordinates, a step of determining misalignment levels of the calculated laser beam irradiation lines according to misalignments of the grooves in widthwise directions thereof, and a step of processing the adhesive film with a laser beam by applying the laser beam to the adhesive film at bottoms of the grooves along the laser beam irradiation lines, thereby separating the adhesive film. | 2018-11-15 |
20180330973 | WAFER CHARGES MONITORING - Apparatus and method for monitoring wafer charges are proposed. A conductive pin, a conductive spring and a conductive line are configured in series to connect the backside surface of the wafer and the sample conductor so that the backside surface of the wafer and the surface of the sample conductor have identical charge density. Hence, by using a static electricity sensor positioned close to the surface of the sample conductor, the charges on the wafer may be monitored. Note that the charges appeared on the frontside surface of the wafer induces charges on the backside surface of the wafer. As usual, the sample conductor is a sheet conductor and properly insulated from the surrounding environment. As usual, the sample conductor and the static electricity sensor are positioned outside the chamber where the wafer is placed and processed, so as to simplify the apparatus inside the chamber and reduce the contamination risk. | 2018-11-15 |
20180330974 | LIQUID PROCESSING APPARATUS - A liquid processing apparatus includes a processing unit, a first supply route, a first device, a second supply route, a second device, a housing, and an external housing. The processing unit processes a substrate by using processing liquid including first and second processing liquids. The first supply route is for supplying the first processing liquid to the processing unit. The first device is for supplying the first processing liquid to the first supply route. The second supply route is for supplying the second processing liquid to the processing unit. The second processing liquid has higher temperature than the first processing liquid. The second device is for supplying the second processing liquid to the second supply route. The housing accommodates the processing unit. The external housing accommodates the first and second devices, and is adjacent to the housing. The external housing includes a partition wall between the first and second devices. | 2018-11-15 |
20180330975 | IN-LINE WET BENCH DEVICE AND METHOD FOR THE WET-CHEMICAL TREATMENT OF SEMICONDUCTOR WAFERS - An in-line wet bench device for the wet-chemical treatment of semiconductor wafers, comprising a plurality of conveying rollers, each of which is rotatable about an axis of rotation, for the in-line transport of semiconductor wafers along a conveying direction, wherein the axes of rotation are arranged parallel to one another and perpendicular to the conveying direction, the conveying rollers having a cylindrical conveying section which extends axially along the respective axis of rotation and forms a conveying surface in the shape of a cylindrical sleeve. The conveying surface has at least one smooth region with surface roughnesses of less than 10 μm when viewed in the axial direction and rough regions with surface roughnesses of more than 100 μm axially adjacent to the smooth region. | 2018-11-15 |
20180330976 | SYSTEMS AND METHODS FOR WAFER ALIGNMENT - Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison. | 2018-11-15 |
20180330977 | METHOD AND SYSTEM FOR BALANCING THE ELECTROSTATIC CHUCKING FORCE ON A SUBSTRATE - Embodiments of the disclosure relate to methods and a system for adjusting the chucking voltage of an electrostatic chuck. In one embodiment, a system for plasma processing a substrate includes a plasma processing chamber, a radio-frequency (RF) matching circuit coupled to the chamber, a sensor and a controller. The chamber includes a chamber body having an inner volume, a bipolar electrostatic chuck disposed in the inner volume and a power supply configured to provide chucking voltage to a pair of electrodes embedded within the electrostatic chuck. When plasma is energized within the chamber by the application of RF power through an RF matching circuit, the sensor is configured to detect a change in an electrical characteristic at the RF matching circuit. The controller is coupled to the power supply and configured to adjust the chucking voltage in response to the change in the electrical characteristic detected by the sensor. | 2018-11-15 |
20180330978 | WAFER PROCESSING METHOD - A wafer processing method includes a liquid supplying step of supplying a liquid to the front side of a wafer, a close contact making step of pressing a protective film against the front side of the wafer with the liquid interposed therebetween, thereby bringing the protective film into close contact with the front side of the wafer, a protective member fixing step of covering the protective film, with a protective member formed from a liquid resin curable by external stimulus, thereby fixing the protective member through the protective film to the front side of the wafer, a grinding step of grinding the back side of the wafer to reduce the thickness of the wafer, and a peeling step of peeling the protective film and the protective member from the wafer thinned by the grinding step. | 2018-11-15 |
20180330979 | SHEET STICKING METHOD - There is provided a sheet sticking method including a sheet sticking step of sticking a sheet to a plate-shaped object and mounting the sheet to which the plate-shaped object is stuck to a ring-shaped frame having an opening to form a plate-shaped object unit including the ring-shaped frame, the plate-shaped object housed in the opening of the ring-shaped frame, and the sheet stuck to the plate-shaped object, and a tension alleviation step of alleviating tension generated in the sheet in the sheet sticking step after the sheet sticking step is carried out. | 2018-11-15 |
20180330980 | CYCLIC FLOWABLE DEPOSITION AND HIGH-DENSITY PLASMA TREATMENT PROCESSES FOR HIGH QUALITY GAP FILL SOLUTIONS - Implementations disclosed herein relate to methods for forming and filling trenches in a substrate with a flowable dielectric material. In one implementation, the method includes subjecting a substrate having at least one trench to a deposition process to form a flowable layer over a bottom surface and sidewall surfaces of the trench in a bottom-up fashion until the flowable layer reaches a predetermined deposition thickness, subjecting the flowable layer to a first curing process, the first curing process being a UV curing process, subjecting the UV cured flowable layer to a second curing process, the second curing process being a plasma or plasma-assisted process, and performing sequentially and repeatedly the deposition process, the first curing process, and the second curing process until the plasma cured flowable layer fills the trench and reaches a predetermined height over a top surface of the trench. | 2018-11-15 |
20180330981 | Method for Thinning Substrates - According to various embodiments, a method includes: providing a substrate having a first side and a second side opposite the first side; forming a buried layer in and/or over the substrate by implanting a chemical element having a greater electronegativity than the substrate into the first side of the substrate by ion implantation; and thinning the substrate from the second side of the substrate, wherein the buried layer comprises a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer. | 2018-11-15 |
20180330982 | METHOD OF MANUFACTURING A HYBRID SUBSTRATE - A method of manufacturing a hybrid substrate is disclosed, which comprises: bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the layer of dielectric material and second semiconductor substrate; removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and annealing the third combined substrate at a temperature about 250° C. to 1000° C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate. | 2018-11-15 |
20180330983 | MANUFACTURING METHOD OF SMOOTHING A SEMICONDUCTOR SURFACE - A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication. | 2018-11-15 |
20180330984 | Packages with Through-Vias Having Tapered Ends - A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via. | 2018-11-15 |
20180330985 | STAIRCASE ENCAPSULATION IN 3D NAND FABRICATION - Methods and apparatuses for depositing an encapsulation layer over a staircase structure during fabrication of a 3D NAND structure to prevent degradation of an oxide-oxide interface and to prevent punchthrough of a wordline are provided. The encapsulation layer is a carbon-containing conformal film deposited over a staircase structure of alternating oxide and nitride layers prior to depositing oxide over the staircase structure. | 2018-11-15 |
20180330986 | METHOD OF PATTERNING TARGET LAYER - The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines. In one aspect, a method for patterning a target layer comprises: forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines, filling the gaps with a sacrificial material, forming a hole by removing the sacrificial material along a portion of one of the gaps, the hole extending across the gap and exposing a surface portion of the target layer and sidewall surface portions of material lines on opposite sides of the one gap, performing a selective deposition process adapted to grow a fill material selectively on the one or more surface portions inside the hole, thereby forming a block mask extending across the gap, removing, selectively to the material lines and the block mask, the sacrificial material from the target layer to expose the gaps, the one gap being interrupted in the longitudinal direction by the block mask, and transferring a pattern including the material lines and the block mask into the target layer. | 2018-11-15 |
20180330987 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer. | 2018-11-15 |
20180330988 | METHOD OF FORMING VERTICAL CHANNEL DEVICES - The disclosed technology generally relates semiconductor devices and more particularly to vertical channel devices and methods of forming the vertical channel devices. According to one aspect, a method of forming a vertical channel device includes forming on a semiconductor substrate a plurality of vertical channel structures. The method additionally includes forming gates, where each of the gates wraps around one of the vertical channel structures. The method additionally includes embedding the gates in a first dielectric layer and exposing top portions of the vertical channel structures. The method additionally includes forming top electrodes on corresponding top portions of the vertical channel structures. The method additionally includes forming sidewall etch barriers on sidewalls of each of the top electrodes. The method additionally includes forming a second dielectric layer covering the first dielectric layer and the top electrodes. The method additionally includes etching a set of vertically extending gate contact holes through the first and second dielectric layers and selectively against the sidewall etch barriers, where each of the gate contact holes exposes one of the gates adjacent to one of the top electrodes. The method further includes filling the set of gate contact holes with a conductive material. A vertical channel device fabricated using the method is also disclosed according another aspect. | 2018-11-15 |
20180330989 | Techniques for Creating a Local Interconnect Using a SOI Wafer - In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer. | 2018-11-15 |
20180330990 | METHOD OF PROCESSING WORKPIECE - A method of processing a workpiece with a cutting blade, the workpiece having a body of metal disposed in superposed relation to projected dicing lines, including: a first metal burr removing step of moving the cutting blade through first cut grooves while the cutting blade is positioned at such a height that a lowermost end of the cutting blade is lower than an upper end of the body of metal; and a second metal burr removing step of moving the cutting blade through the second cut grooves while the cutting blade is positioned at such a height that the lowermost end of the cutting blade is lower than the upper end of the body of metal. A liquid containing an organic acid and an oxidizing agent is supplied to the workpiece in the first metal burr removing step and the second metal burr removing step. | 2018-11-15 |
20180330991 | Semiconductor Die Singulation and Structures Formed Thereby - An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate. | 2018-11-15 |
20180330992 | 3D Chip Sharing Power Interconnect Layer - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180330993 | 3D Chip Sharing Power Circuit - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2018-11-15 |
20180330994 | PROCESS FOR VARIABLE FIN PITCH AND CRITICAL DIMENSION - A multi-masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch and fin critical dimension within different arrays. A layer of curable silicon nitride is incorporated into a patterning architecture, patterned to form an etch mask, and locally cured to further modify the etch mask geometry. The use of cured and uncured structures facilitate the tuning of the resultant fin geometry. | 2018-11-15 |
20180330995 | METHOD TO REDUCE FINFET SHORT CHANNEL GATE HEIGHT - Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer. | 2018-11-15 |
20180330996 | FIELD EFFECT TRANSISTOR GATE STACK - A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer. | 2018-11-15 |
20180330997 | METHOD OF FORMING VERTICAL TRANSISTOR DEVICE - The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer. | 2018-11-15 |
20180330998 | PROCESS FOR FABRICATING SILICON-GERMANIUM STRIPS - A strip or portions of a strip of silicon-germanium is made by first producing a strip of silicon suspended above a substrate. At least a portion of the strip of silicon is with a layer of silicon-germanium. Germanium enrichment of the portion of the strip of silicon is accomplished through a thermal oxidation. The resulting silicon oxide formed during the thermal oxidation is then removed. | 2018-11-15 |
20180330999 | OVERLAY-CORRECTION METHOD AND A CONTROL SYSTEM USING THE SAME - A method of correcting an overlay includes: forming a first pattern on a first substrate; forming a second pattern on the first pattern; obtaining a first overlay error profile of the second pattern and obtaining a first overlay correction profile from the first overlay error profile; forming a third pattern on the second pattern; obtaining a second overlay error profile of the third pattern and obtaining a second overlay correction profile from the second overlay error profile; and forming the second pattern on a second substrate, wherein the forming of the second pattern on the second substrate includes: determining whether the second overlay correction profile has a non-correctable model parameter; and when the second overlay correction profile has the non-correctable model, obtaining a preliminary correction profile to correct a position of the second pattern to be formed on the second substrate. | 2018-11-15 |
20180331000 | Probe methodology for ultrafine pitch Interconnects - Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component. | 2018-11-15 |
20180331001 | CIRCUIT AND METHOD FOR TESTING GATE LINES OF ARRAY SUBSTRATE - Related to is a gate on array. A circuit for testing a gate line of an array substrate includes: a test pad and a first switch unit which connects the test pad and the gate line and has an end connected to a control terminal. A voltage is applied to the control terminal to control activation and deactivation of the first switch unit. The gate line is in normal operation when the first switch unit is deactivated, and the test pad tests a signal of the gate line when the first switch unit is activated. In normal display, the first switch unit is deactivated, and the gate line is in normal operation. This can avoid influences of an additional load, which would otherwise cause abnormal display of a picture. In a manufacturing procedure, explosive wound caused by electrostatic discharge of the test pad can be prevented. When a display device cannot be lit, an external voltage can be introduced to activate the first switch unit, so as to detect a signal of the gate line. | 2018-11-15 |
20180331002 | ELECTRONIC DEVICE - Each of first and second semiconductor devices mounted on a substrate includes an emitter terminal electrically connected with a front surface electrode of a semiconductor chip and exposed from a main surface of a sealing body located on a front surface side of the semiconductor chip. Each of the first and second semiconductor devices includes a collector terminal electrically connected with a back surface electrode of the semiconductor chip and exposed from the main surface of the sealing body located on a back surface side of the semiconductor chip. The collector terminal of the first semiconductor device is electrically connected with the emitter terminal of the second semiconductor device via a conductor pattern formed on an upper surface of the substrate. | 2018-11-15 |
20180331003 | IMPROVED PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS - Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer. | 2018-11-15 |
20180331004 | PRE-MOLDED ACTIVE IC OF PASSIVE COMPONENTS TO MINIATURIZE SYSTEM IN PACKAGE - A system in package and method of making as system in package are disclosed. The system in package has a substrate ( | 2018-11-15 |
20180331005 | SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - In order to improve reliability of a semiconductor device, in a semiconductor chip according to one embodiment, an uneven shape is formed on an exposed surface of a back surface electrode formed on a back surface of the semiconductor chip. | 2018-11-15 |
20180331006 | Method for Producing an Electrical Device Comprising a Covering Material - A method for producing an electrical device including an electrical component at least partially covered by a covering material having a cement material includes supplying the cement material, mixing an additive into the cement material, applying the covering material having the cement material with the additive onto the electrical component, and treating the covering material. The treatment allows the additive from the cement material to reach a surface of the cement material and to form a protective layer on the surface. | 2018-11-15 |
20180331007 | A SENSOR SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A SENSOR SEMICONDUCTOR DEVICE - The sensor semiconductor device comprises a substrate ( | 2018-11-15 |
20180331008 | SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device for high efficiently releasing heat generated from a semiconductor element to the outside. The semiconductor device of the present disclosure includes a substrate, made of an intrinsic semiconductor material, having a substrate main surface facing toward a thickness direction z, and configured to have a recess recessed from the substrate main surface; an internal wiring layer, disposed on the substrate main surface and the recess; a columnar conductor, protruding from the internal wiring layer disposed on the substrate main surface toward a direction in which the substrate main surface faces; a semiconductor element, having an element main surface facing the same direction as the substrate main surface, and electrically connected to the internal wiring layer; and a sealing resin, filled into the recess and covering a portion of each of the columnar conductor and the semiconductor element; wherein the semiconductor element has a portion overlapping the recess when viewed in the thickness direction of the substrate, and the semiconductor device is configured to have a heat dissipating layer being in contact with the element main surface and exposed to the outside. | 2018-11-15 |
20180331009 | RFIC DEVICE AND METHOD OF FABRICATING SAME - A radio frequency integrated circuit (RFIC) device and methods for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface parallel to the first surface and a thickness of smaller than 3 μm; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 μm; and a sheet-like heat sink formed on a surface of the first dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device. | 2018-11-15 |
20180331010 | RFIC DEVICE AND METHOD OF FABRICATING SAME - A radio frequency integrated circuit (RFIC) device and a method for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface and a thickness of smaller than 3 μm; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 μm; and a sheet-like heat sink that is formed on the surface of the second dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device. | 2018-11-15 |
20180331011 | FLEXIBLE HEAT SPREADER LID - Heat spreader lids and package assemblies including a heat spreader lid. The heat spreader lid has a central region configured to be coupled with an electronic component, a peripheral region configured to be coupled with a substrate, and a connecting region arranged between the central region and the peripheral region. The connecting region is configured to impart stress relief to the central region. | 2018-11-15 |
20180331012 | CONTROL UNIT AND ELECTRIC POWER STEERING DEVICE - Provided are a heat dissipation substrate capable of improving heat dissipation properties of an electronic component, and an electric power steering device. In the heat dissipation substrate, a plurality of thermal vias are disposed at least in an electronic component projection region in which a region of a bottom surface portion of the electronic component is projected to a mounting surface in a direction perpendicular to the mounting surface, and a surface density of the thermal vias which occupy the mounting surface per unit area is at least partially different. The plurality of thermal vias are disposed so that the surface density of the thermal vias becomes the greatest in a dense region on an inner side of an edge portion of the electronic component projection region. | 2018-11-15 |
20180331013 | MOUNT STRUCTURE - A mount structure having a joining capable of withstanding development of cracks generated by thermal stress due to repeated temperature changes in a mount structure having the joining of a large area is formed by joining a ceramic substrate electrode of a ceramic substrate and a metal substrate electrode of a metal substrate by a laminate, in which the laminate is formed by stacking a first interface layer, a first solder joining portion, a second interface layer, a first buffer material electrode, a buffer material, a second buffer material electrode, a third interface layer, a second solder joining portion and a fourth interface layer in this order from the ceramic substrate electrode toward the metal substrate electrode, a thickness of the laminate is 30 μm or more and 100 μm or less, a difference between a thickness of the first solder joining portion and a thickness of the second solder joining portion is within 25%, and differences in elastic moduli and in linear expansion coefficients between the first solder joining portion and the buffer material are respectively within 62%. | 2018-11-15 |
20180331014 | HEAT DISSIPATION ASSEMBLY - A heat dissipating assembly including a layered stack of materials with a highly thermally conductive path for cooling a circuit, the stack including a structurally isolated material having a high coefficient of thermal expansion connected between materials having low coefficients of thermal expansion. | 2018-11-15 |
20180331015 | HEAT SPREADERS WITH STAGGERED FINS - An apparatus is provided which comprises: a first heat spreader surface, a second heat spreader surface, and a plurality of heat spreading fins on, and extending substantially perpendicularly from, the first and second heat spreader surfaces, wherein the plurality of heat spreading fins are arranged substantially parallel to one another in a plurality of substantially linear columns, wherein the columns of heat spreading fins are separated by gap regions wider than the heat spreading fins, and wherein the columns of heat spreading fins on the first heat spreader surface are sited to line up with gap regions between columns of heat spreading fins on the second heat spreader surface when the first and second heat spreader surfaces are aligned. Other embodiments are also disclosed and claimed. | 2018-11-15 |
20180331016 | THREE-DIMENSIONAL HEAT-ABSORBING DEVICE - A three-dimensional heat absorbing device including: an airtight member defining an outer appearance of the three-dimensional heat absorbing device; a first space connected to each other inside the airtight member in a three-dimensional lattice structure; and a second space constituting a space not occupied by the first space among an internal space of the airtight member. In the device, at least one of the first space and the second space forms a channel for working fluid steam, and a wick to which liquefied working fluid is absorbed are provided along inner surfaces of the channel. | 2018-11-15 |
20180331017 | POWER SEMICONDUCTOR MODULE FOR A MOTOR VEHICLE AND MOTOR VEHICLE - A power semiconductor module for a motor vehicle. a plurality of unhoused power semiconductor chips are provided, which are arranged so that a liquid coolant that is introduced into the power semiconductor module through a liquid coolant feed line can circulate directly around them. | 2018-11-15 |
20180331018 | Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters. | 2018-11-15 |