46th week of 2008 patent applcation highlights part 27 |
Patent application number | Title | Published |
20080278943 | Luminaire Comprising Leds - This invention relates to a luminaire ( | 2008-11-13 |
20080278944 | OPTICAL LENS, OPTICAL MODULE HAVING THE SAME, AND BACKLIGHT ASSEMBLY HAVING THE SAME - An optical module includes a point light source device and an optical lens. The point light source device generates light. The optical lens includes an inner curved surface and an outer curved surface. The inner curved surface has a first roughly ellipsoidal shape having a first major axis and a first minor axis that is substantially perpendicular to the first major axis. The outer curved surface has a second roughly ellipsoidal shape having a second major axis that is substantially perpendicular to the first axis and the second minor axis that is substantially perpendicular to the second major axis. The light generated by the point light source device enters the optical lens through the inner curved surface and exits from the optical lens through the outer curved surface. Therefore, the number of optical modules used in a display device may be reduced to lower manufacturing cost thereof. | 2008-11-13 |
20080278945 | SOLID STATE OPTICAL SYSTEM - The invention provides a light fixture including a solid state light emitter coupled to a housing and configured to emit light in a path, and a reflector. The reflector includes a reflective surface positioned in the path of the light emitted by the solid state light emitter, the reflective surface comprising a first substantially parabolic section configured to reflect a first portion of the light, the first substantially parabolic section having a first focal length. The reflective surface further includes a second substantially parabolic section adjacent the first substantially parabolic section and configured to reflect a second portion of the light, the second substantially parabolic section having a second focal length greater than the first focal length. | 2008-11-13 |
20080278946 | LED SPOTLIGHT - A spotlight ( | 2008-11-13 |
20080278947 | Luminous Element For Backlight Unit - The present invention relates to a luminous element, and more particularly, to a luminous element for a backlight unit with a plurality of luminous chips mounted on a substrate. The present invention provides a luminous element for a backlight unit, in which luminous chips are arranged on a substrate so that the manufacturing process and cost can be reduced and the size of a substrate is minimized when manufacturing the luminous element, thereby minimizing the size of a backlight unit. Further, the present invention provides a luminous element for a backlight unit, in which luminance uniformity can be increased by optimizing the viewing angle of the luminous element. | 2008-11-13 |
20080278948 | Dancing Decorative Lamp - The present invention relates to a decorative lamp, and more particularly to a decorative lamp that can generate dancing effect. The dancing decorative lamp comprises string-lights, a pedestal, and a support in a certain shape, the string-lights are mounted on the support; said support comprises at least one main support which asway connects to the pedestal by the elastic component; said support at least comprises one auxiliary support which asway connects to the main support with the elastic component. The present invention provides a dancing decorative lamp that can generate dancing effect. | 2008-11-13 |
20080278949 | OPTICAL SHEET, METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME - An optical sheet includes a base film, a plurality of prism patterns and a plurality of first embossing patterns. The prism patterns are formed on an upper surface of the base film. Each of the prism patterns has the shape of a trigonal prism and includes a first inclined surface and a second inclined surface. The first and second inclined surfaces are inclined with respect to the upper surface of the base film and meet each other at a peak portion. First embossing patterns are formed at the peak portion. | 2008-11-13 |
20080278950 | LIGHT FIXTURES AND LIGHTING DEVICES - A lighting device comprises a heat sink, a housing mounted to and/or thermally coupled to the heat sink, a basket assembly attached to the housing, a solid state light emitter thermally coupled to the heat sink, and a baffle assembly attached to the housing. Also, a lighting device comprising a basket assembly and a baffle assembly. In some embodiments, the basket assembly comprises a first member defining a first opening, a second member, a space between the first and second members, and lenses in the opening and in the space. In some embodiments, the heat sink extends farther in a first direction in a first plane than a largest dimension of the housing in any plane which is parallel to the first plane. In some embodiments, at least one additional component (e.g., a power supply module or a junction box) is in contact with the heat sink element. | 2008-11-13 |
20080278951 | Floor lamp having overload breaker that is operated easily and conveniently - A floor lamp includes a lamp body, an electric cord, a control switch, and a breaker. The breaker is connected to the electric cord and the control switch and hidden in the lamp body. Thus, a user only needs to operate the control switch to restart the floor lamp after a power failure or an overload, so that the floor lamp is restarted easily and conveniently. In addition, the breaker is hidden in the upright tube of the lamp body so that the breaker will not be wet or dirtied and will not be worn out due to hit by a foreign object during transportation, thereby enhancing the lifetime of the breaker and the floor lamp. | 2008-11-13 |
20080278952 | Light fixtures and lighting devices - There is provided a light fixture comprising a baffle system and a side reflector, the baffle system comprising at least an outer baffle structure and an inner baffle structure. Also, there is provided a light fixture which comprises at least two recessed concentric square elements, triangular connecting elements and lenses which are recessed from the faces of each of the square elements. In some embodiments, the lighting device comprises at least one solid state light emitter. In some embodiments, the light fixture further comprises at least one lens positioned between at least two respective baffle elements. | 2008-11-13 |
20080278953 | Toggle Mount Assembly - In an embodiment of an assembly for recessed mounting of a body, the body includes proximal and distal end and further includes as least one mounting point. The assembly includes a threaded shaft connected to body through the mounting point and capable of rotatable movement relative to the mounting point. A toggle having a first end including a threaded interior and a second end that is a free end is screwed onto the threaded shaft and rotatable around it. A spring is mounted around the threaded shaft between the mounting point of the body and the first end of the toggle, whereby the spring biases the toggle toward the distal end of the body. | 2008-11-13 |
20080278954 | Mounting Assembly for Optoelectronic Devices - The present invention provides a mounting assembly for one or more light-emitting elements, wherein the mounting assembly is configured such that the one or more light-emitting elements are inferiorly connected to a carrier. The carrier comprises one or more light transmission regions, wherein each of the one or more light-emitting elements is aligned with a light transmission region enabling light to pass through the carrier. The inferior mounting of the light-emitting elements can provide ease of thermal access to a cooling interface associated with the one or more light-emitting elements by a thermal management system. | 2008-11-13 |
20080278955 | LED LAMP DEVICE AND METHOD TO RETROFIT A LIGHTING FIXTURE - A device and method for retrofitting a light fixture from use with a lamp socket that employs a conventional incandescent or metal halide lamp, to use with a light emitting diode (LED)-based lamp assembly. The lamp fixture has a collar with a base and an annular outer wall extending out from the base. The LED lamp device includes a neck base having an annular outer wall having a shaped outside surface that is placed into direct surface contact with the inner surface of the annular outer wall of the collar, to establish an effective heat-transferring interface. The shaped outer surface of the neck base provides proper fitting of the LED lamp device into the lighting fixture, and provides a heat-transferring interface over substantially all of the outer surface of the neck base, to dissipate heat away from the LED module. Aluminum material provides high thermal conductivity, light weight, availability, and low cost. | 2008-11-13 |
20080278956 | Lamp Device and Method to Retrofit a Lighting Fixture - A device and method for retrofitting a light fixture from use with a lamp socket that employs an incandescent or metal halide lamp, to use with another lamp assembly. The lamp fixture has a collar with a base and an annular outer wall extending out from the base. The LED lamp device includes a neck base having an annular outer wall having a shaped outside surface that is placed into direct surface contact with the inner surface of the annular outer wall of the collar, to establish an effective heat-transferring interface. The shaped outer surface of the neck base provides proper fitting of the LED lamp device into the lighting fixture, and provides a heat-transferring interface over substantially all of the outer surface of the neck base, to dissipate heat away from the LED module. Aluminum material provides high thermal conductivity, light weight, availability, and low cost. | 2008-11-13 |
20080278957 | LIGHT FIXTURES AND LIGHTING DEVICES - There is provided a light fixture, comprising a heat sink element and an upper housing mounted to the heat sink element, the heat sink element extending farther in a first direction in a first plane than a largest dimension of the upper housing in any plane parallel to the first plane. In addition, a light fixture, comprising a heat sink element, an upper housing mounted to the heat sink element and an additional component (e.g., a power supply module or a junction box) in contact with the heat sink element. Also, a light fixture, comprising a heat sink element, an upper housing thermally coupled to the heat sink element and at least one solid state light emitter thermally coupled to the heat sink element. | 2008-11-13 |
20080278958 | PUCK LIGHT WITH MAGNETIC COVER - According to one embodiment of the present invention, at least one puck light with a cover and a base magnetically held together is provided. Other embodiments include a cover and a base magnetically held together while the puck light is mounted to the underside of a horizontal surface, and where the magnetic attraction between the cover and base provides for the removal of the cover from the base by hand without a tool. Other embodiments include two differently shaped covers that are interchangeably attachable to the base. Other embodiments include at least one puck light with a cover and a base magnetically held together, and where the puck light projects a shape onto a support surface and perpendicular to the support surface when the puck light is attached to the surface, where the largest dimension of the projected shape is at most four and one-quarter (4¼) inches. | 2008-11-13 |
20080278959 | MOUNTING APPARATUS FOR LIGHT GUIDE PIPE - An exemplary mounting apparatus is for adjustably fixing a light guide pipe in a chassis of an electronic device. The chassis includes a mounting plate. The mounting apparatus includes a first sleeve engaging with the light guide pipe, a second sleeve attached to the mounting plate, and a resilient member disposed between the first sleeve and the second sleeve. | 2008-11-13 |
20080278960 | ILLUMINATING STRUCTURE - The present invention relates generally to illuminated ornamental and/or decorative sculptures and/or structures. More particularly, the present invention relates to an illuminated structure having a plurality of individual optical elements disposed thereon. | 2008-11-13 |
20080278961 | Hybrid Optics for L.E.D. Lamp - A lighting assembly is adapted to be fixedly secured to a motor vehicle for emitting light out therefrom. The lighting assembly includes a frame for supporting and mounting the lighting assembly to the motor vehicle and a lens fixedly secured to the frame. The lighting assembly also includes a light emitting diode spaced from the lens for emitting light out through the lens. The lighting assembly further includes a reflector extending between the lens and the light emitting diode. The reflector includes a parabolic reflective surface, and a hyperbolic component for directing light emitted from the light emitting diode out toward the parabolic reflective surface at an angle such that the light passes through the lens as collimated light. | 2008-11-13 |
20080278962 | Light System For a Vehicle Headlight Unit - Light system for a vehicle headlight unit, the system comprising a light source ( | 2008-11-13 |
20080278963 | LIGHT SOURCE DEVICE AND ENDOSCOPE DEVICE - A light source device includes a light source, a diaphragm blade for adjusting light quantity of illumination light supplied from the light source, a diaphragm driving part for driving the diaphragm blade to perform opening/closing operation, and a diaphragm control circuit part for setting diaphragm drive instruction voltage to be supplied to the diaphragm driving part and control an opening/closing amount of the diaphragm blade. In the diaphragm control circuit part, a fully-opened voltage and a fully-closed voltage at the time the diaphragm blade is fixed at a fully-opened position and a fully-closed position are read, based on the voltages, adjustment data for adjusting the diaphragm drive instruction voltage and the opening/closing positions of the diaphragm blade is set, and based on the adjustment data, a control range of the diaphragm drive instruction voltage is regulated. | 2008-11-13 |
20080278964 | OPTICAL FIBER ILLUMINATION - A portable device or a cover for a portable device includes a light source to emit light and an optical fiber to illuminate based on light received from the light source. | 2008-11-13 |
20080278965 | Light emitting diode with light emitting chips at inner side surfaces thereof and backlight module using same - An exemplary light emitting diode includes a main body, a red light emitting chip, a green light emitting chip, and a blue light emitting chip. The main body includes two inner side surfaces opposite to each other and a inner bottom surface connected with the side surfaces. The side surfaces and the bottom surface cooperatively define an accommodating space. The red light emitting chip, the green light emitting chip and the blue light emitting chip are positioned at the bottom surface and the side surfaces of the accommodating space, respectively. | 2008-11-13 |
20080278966 | LED Light String - The present invention relates to decorative lights, and more particularly to an LED light string with a safety device. The LED light string includes an electrical plug, lead wires, and LED bulbs, and further includes a safety device connected with the LED bulbs in series. The safety device has a temperature fuse tube and a heating resistance which are connected in series and form two lead pins after connected. The temperature fuse tube and the heating resistance are jointed together so as to transfer heat therebetween. The temperature fuse tube and the heating resistance are encapsulated in a shell. The shell provides two terminals therein. The two lead pins are connected with the two terminals respectively, and the two terminals are connected with the respective lead wires to form a circuit loop. The shell is an assembled shell. | 2008-11-13 |
20080278967 | AC TO DC POWER CONVERTER FOR AEROSPACE APPLICATIONS - Three coils, each having several serial windings, have selected windings connected in a delta. Input AC power is applied through outrigger windings at the delta apices. At least two strategically located, direct tap, natural output points are provided at each side of the delta. For 6-phase output, only the six natural output points are required. For 9-phase output, an additional central output terminal connects to each side of the delta through a stub winding. The 6-phase or 9-phase output is passed to a rectifier circuit. | 2008-11-13 |
20080278968 | Integral stack columns - Systems and methods for power conversion are illustrated. Power conversion architecture for fuel cell systems in particular are described that use dual bus architectures having stack segment pairs and a center-tapped neutral line, and/or an architecture employing integer multiple of three DC/DC converter branches. | 2008-11-13 |
20080278969 | Device and Method for Equalizing Charges of Series-Connected Energy Stores - A device and method for equalizing the charges of series-connected individual cells of an energy storage device with a DC/DC converter, which draws energy from the energy storage device or from another energy source, charges an intermediate circuit capacitor whose voltage is inverted in a DC/AC converter, converts the alternating voltage via AC bus lines and coupling transformers by way of a rectifier into a pulsating direct current, and charges the cell having the lowest cell voltage with the pulsating direct current. | 2008-11-13 |
20080278970 | IN-BODY INFORMATION ACQUIRING APPARATUS AND POWER-SUPPLY CIRCUIT - An in-body information acquiring apparatus includes a function executing unit that realizes a predetermined function inside a body of a patient. A power-supply circuit includes a power unit that includes a cell and that outputs a first current and a first voltage; and a converter that converts the first current to a second current, which is a current required to operate the function executing unit for a predetermined time, and converts the first voltage to a second voltage, which is a voltage required to operate the function executing unit. | 2008-11-13 |
20080278971 | Forward-forward converter - A forward-forward converter (FFC) and method of operation thereof. The FFC has a first transformer, including a primary winding coupled to power and clamp switches and a secondary winding coupled to the primary winding, configured to provide an output energy transfer of the forward-forward converter during conduction of the power switch. The FFC also has a second transformer, including an input winding coupled to the secondary winding, configured to form an intermediate circuit mesh and extend zero-voltage switching opportunity and the output energy transfer, through the outputs windings coupled to the input winding, during conduction of the power and clamp switches. | 2008-11-13 |
20080278972 | Power conversion circuit, driving method and drive unit therefor - A power conversion circuit capable of varying an output voltage within a range from a negative voltage lower than a ground voltage to a positive voltage higher than a supply voltage, and a driving method and a drive unit are provided. A power conversion circuit includes a transformer with a 1:1 ratio between the primary winding and secondary winding, a voltage outputting capacitor, and four switches. The power conversion circuit can be operated as a DC-DC converter of a step-up type, a step-up-and-down type, a step-down type, an inverted-output step-up-and-down type, or an inverted-output step-up type by selecting two switches used for control from among the four switches and alternately turning the two switches on. By switching the operating modes of the power conversion circuit, the output voltage can be varied within a range from a negative voltage to a positive voltage higher than a supply voltage. | 2008-11-13 |
20080278973 | Apparatus and method for providing multiple functions and protections for a power converter - A power converter has a transformer including a primary winding connected between a power input and a power switch, the power switch is switched to deliver power from the power input to a power output, an auxiliary winding provides an induced voltage in such a manner that when the power switch is at a first switch state, the induced voltage reflects an input information of the power converter, and when the power switch is at a second switch state, the induced voltage reflects an output information of the power converter. Two detection signals are generated from the input and output information, respectively, to implement multiple functions and protections. | 2008-11-13 |
20080278974 | QUASI-RESONANT FLY-BACK CONVERTER WITHOUT AUXILIARY WINDING - Disclosed is a switching converter without an auxiliary winding. The switching converter has a transformer, a switching transistor, a coupling circuit and a regulating circuit. The transformer has a primary winding and a secondary winding, and is for transforming an input voltage into an output voltage; a first end of the switching transistor is coupled to the primary winding of the transformer, and the switching transistor is for controlling an operation of the transformer according to a control signal; the coupling circuit is for coupling a signal at the first end of the switching transistor to generate a coupled signal; and the regulating circuit is for detecting the coupled signal to generate the control signal according to the detecting result. | 2008-11-13 |
20080278975 | Switched Mode Power Converter and Method of Operation Thereof - The invention relates to a switched mode power converter and a method of operating such a converter A switched mode power converter according to the invention includes a transformer ( | 2008-11-13 |
20080278976 | DYNAMIC VOLTAGE SAG CORRECTION - A voltage sag correction device includes an input terminal adapted to receive a first operating signal having a line-to-neutral voltage. The first operating signal is provided to a load through an output terminal. A regulator module includes a rectifying device adapted to rectify a line-to-line input signal, a storage unit adapted to store energy corresponding to the rectified line-to-line input signal, and an inverter switching device adapted to use the stored energy to generate a correction signal during at least a portion of a voltage sag. An injection transformer in electrical communication with the regulator module is adapted to reduce a voltage of the correction signal. A bypass switch is in a closed position during a normal operating condition such that the injection transformer is bypassed. The bypass switch is in an open position during at least a portion of the voltage sag such that the injection transformer is energized. | 2008-11-13 |
20080278977 | Method for operating a converter circuit, and device for carrying out the method - A method for operating a converter circuit is specified with the converter circuit having a converter unit with a multiplicity of controllable power semiconductor switches and having an energy storage circuit formed by two series-connected capacitors, in which the controllable power semiconductor switches are controlled by means of a control signal formed from a hysteresis signal vector (x), and the hysteresis signal vector (x) is formed from a difference-phase connection current vector (Δi | 2008-11-13 |
20080278978 | HIGH VOLTAGE INDUCTIVE CHARGE PUMP DC-TO-DC CONVERTER ASSEMBLY - A method and apparatus for a power converter assembly charges a first capacitor and a second capacitor in parallel to a first voltage and at a first polarity, and then discharges the first capacitor and second capacitor in series at an output voltage that is greater than the input voltage and at a second polarity that is opposite the first polarity. This “charge pump” process is repeated and filtered to produce a continuous output. | 2008-11-13 |
20080278979 | n-Buck cascade converter with single active switch - An n-buck cascade converter, where the DC conversion ratio is U | 2008-11-13 |
20080278980 | DC-AC converter with fast response speed - An exemplary direct current to alternating current converter includes a pulse width modulator having a plurality of pulse signal outputs that can provide a plurality of pulse signals, a driving circuit having a plurality of switching units, and a transformation circuit having a plurality of transformers. Each of the switching units includes a P-type transistor and an N-type transistor. Each pulse signal output is electrically connected to the P-type and N-type transistors of one of the switching units. Each of the transformers is connected to two of the switching units, and the P-type transistors and the N-type transistors of the two switching units are not switched on simultaneously. | 2008-11-13 |
20080278981 | SWITCHING CONTROL DEVICE - The present invention reduces switching noise generated in a switching control device having a switching element such as a switching power supply in linear linkage with the state of a load of the output and without increasing the control circuit scale which is a factor of cost increase. The present invention adopts a configuration of a control circuit having an ON/OFF circuit that controls the switching element such that one or both of two specified values (upper limit and lower limit) that specify triangular waves of a triangular wave generation circuit that specifies a drive oscillating frequency of the switching element is/are changed in linear linkage with the output load state. | 2008-11-13 |
20080278982 | Power Factor Correction Boost Circuit - The invention relates to a power factor controller for use in a power factor correction circuit. The power factor controller comprises a first input (VinSense) for receiving an input voltage (Vin) of the power factor correction circuit, a second input (VoSense) for receiving an output voltage (Vout) of the power factor correction circuit, and a controllable current source (VCCI) having a control input coupled to the first input, and a current supply output coupled to the second input, wherein said controllable current source (VCCI) sources a current to the second input (VoSense) that is inversely proportional to the input voltage. | 2008-11-13 |
20080278983 | Controlling Apparatus of a Power Converter of Single-Phase Current For Photovoltaic Generation System - A control apparatus of a single-phase power converter for a photovoltaic power generation system is disclosed, including a POS MPPT controller for calculating a rating current by applying a POS MPPT control method to an output current detected through a current transformer of a single-phase AC filter, a bandpass filter for filtering only signals of a low-frequency band from a load, a single-phase reference current generator for producing a reference current by matching a phase of the current from the POS MPPT controller to a phase from the bandpass filter, a single-phase current subtractor for subtracting an output current of a current transformer from the reference current calculated by the single-phase reference current generator to thereby calculate a difference current between the output current of the current transformer and the reference current, a PI controller for outputting a control signal, corresponding to the difference current from the single-phase current subtractor, to a PWM signal generator, and the PWM signal generator for generating a PWM phase control signal corresponding to the control signal from the PI controller. | 2008-11-13 |
20080278984 | AUTOMATIC ZERO VOLTAGE SWITCHING MODE CONTROLLER - A switching DC to AC power converter includes an automatic zero voltage switching (ZVS) mode controller. The automatic zero voltage switching mode controller may adjust a ZVS dead-time in accordance with a range of load currents being supplied by the power converter that range from quiescent conditions to a predetermined loading level of the power converter. The variable ZVS dead-time may be larger nearer to quiescent conditions, and become progressively smaller as load currents increase. Outside a predetermined range of load currents, the variable ZVS dead-time may be disabled or minimized. | 2008-11-13 |
20080278985 | BI-DIRECTIONAL HEMT/GaN HALF-BRIDGE CIRCUIT - A half-bridge circuit in accordance with an embodiment of the present application includes an input voltage terminal operable to receive an input voltage, a first bi-directional switch, a second bi-directional switch connected in series with the first bi-directional switch, wherein the first and second bi-directional switches are connected to the input voltage terminal such that the input voltage is provided across the first and second bi-directional switches and a controller operable to turn the first and second bi-directional switches ON and OFF such that a desired voltage is provided at an midpoint node positioned between the first bi-directional switch and the second bi-directional switch. The first bi-directional switch and the second bi-directional switch are high electron mobility transistors structured to allow for conduction in two directions when ON and to prevent conduction in any direction when OFF. | 2008-11-13 |
20080278986 | High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array - A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements. | 2008-11-13 |
20080278987 | LAYOUT STRUCTURE OF SUB-WORD LINE DRIVER AND FORMING METHOD THEREOF - A layout structure of a Sub-Word Line Driver (SWD) and a forming method thereof. A layout structure of an SWD may include first through fourth metal-oxide-semiconductor (MOS) transistors. The layout structure may include a first area including an active area of the first MOS transistor, wherein a gate-poly (GP) of the first MOS transistor may be disposed in a predefined direction over a portion of the first area. The layout structure may also include a second area including an active area of the second through fourth MOS transistors. Each GP of the second through fourth MOS transistors may be disposed in parallel to each other. The GP of the first MOS transistor disposed in the predefined direction may be substantially perpendicular to each GP of the second through fourth MOS transistors. The layout structure of an SWD can improve a driving capability without increasing an area of the chip. | 2008-11-13 |
20080278988 | RESISTIVE SWITCHING ELEMENT - According to one aspect, an integrated circuit may comprise a first electrode, a second electrode, and a resistive switching rod extending from the first electrode to the second electrode and being at least partly embedded in a thermal barrier matrix. | 2008-11-13 |
20080278989 | Resistive memory device and method of manufacturing the same - Provided is a resistive memory device and a method of manufacturing the resistive memory device that includes a bottom electrode, an insulating layer that is formed on the bottom electrode and has a hole that exposes the bottom electrode, a resistance layer and an intermediate layer which are formed in the hole, a switch structure formed on a surface of the intermediate layer, and an upper electrode formed on the switch structure. | 2008-11-13 |
20080278990 | RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. | 2008-11-13 |
20080278991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 2008-11-13 |
20080278992 | INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell. | 2008-11-13 |
20080278993 | Static random acess memory device - Additional transistors P | 2008-11-13 |
20080278994 | MRAM Cell with Multiple Storage Elements - An improved MRAM cell may include a first, second, and third contact, a first MTJ between the first and second contact, and a MTJ between the second and third contact. The MRAM cell is nonconductive between the first and second MTJ. The first MTJ may include a first free layer with a first switching field, and the second MTJ may include a second free layer with a second switching field. If the first switching field is substantially higher than the second switching field, the first MTJ may be a reference element for the second MTJ. If the first switching field is adequately higher than the second switching field, the first and second MTJ may each contain a data bit. If the first switching field is substantially similar to the second switching field, the first and second MTJs may contain identical data bits connected in series. | 2008-11-13 |
20080278995 | Magnetic memory and memory cell thereof and method of manufacturing the memory cell - A magnetic memory, a memory cell thereof, and a method of manufacturing the memory cell are provided. The memory cell of the magnetic memory includes a bottom contact layer, a bit line, a magnetic stack structure and a dielectric material. The bit line is disposed over the bottom contact layer. The magnetic stack structure is disposed between the bottom contact layer and the bit line. The dielectric material at least fills between the bottom contact layer and the bit line and surrounds the magnetic stack structure. A gap is formed between the dielectric material and the magnetic stack structure. During programming of the memory cell, the magnetic stack structure generates heat, and the gap delays heat loss. | 2008-11-13 |
20080278996 | PROGRAMMABLE MAGNETIC READ ONLY MEMORY (MROM) - In one embodiment, there is provided a method for programming a memory device having magnetoresistive memory elements as storage elements. The method is performed during fabrication of the memory device and may be used to realize a Magnetic Read Only Memory (MROM) device. In accordance with the method, during fabrication of a memory device comprising a plurality of magnetoresistive memory elements (MRME) e.g. a MTJs, the memory device is programmed by selectively controlling the presence or absence of the magnetoresistive element at each intersection of a word line (WL) and a bit line (BL) in the device. | 2008-11-13 |
20080278997 | SEMICONDUCTOR MEMORY DEVICE AND WRITE CONTROL METHOD THEREOF - A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying a write current to the bit line, a write control circuit controlling operations of the write driver, and a timing signal generation circuit supplying a timing signal to the write control circuit. The timing signal has a waveform including a pulse indicating a time of starting supplying the write current when a first logical level is to be written, a pulse indicating a time of ending supplying the write current if the first logical level is to be written, and a pulse indicating one of a time of starting supplying the write current and a time of ending supplying the write current when a second logical level is to be written. | 2008-11-13 |
20080278998 | Data Storage Device and Method - A serial magnetic mass storage device and associated data storage method is provided based on magnetic nanowires that support single magnetic domains separated by domain walls. Each data-storing nanowire has a plurality of crossing nanowires along its length, forming cross junctions that constitute domain wall pinning sites. Data is fed through each data-storing nanowire by moving the magnetic domains under the action of a field that alternates between alignment and anti-alignment with the crossing nanowires. The data is encoded in the chirality of the domain walls, with up and down chirality transverse domain walls being used to encode 0's and 1's. Data is clocked into each nanowire with suitable nucleation generators capable of nucleating domains with domain walls of pre-defined chirality. Data is clocked out of each nanowire with suitable magnetic field sensors that sense the chirality. | 2008-11-13 |
20080278999 | SOURCE AND DRAIN SIDE EARLY BOOSTING USING LOCAL SELF BOOSTING FOR NON-VOLATILE STORAGE - Program disturb is reduced during programming of non-volatile storage by providing a boosting scheme in which isolation voltage are applied to two word lines to create a source side channel region on a source side of one isolation word line, an intermediate channel region between the isolation word lines and a drain side channel region on a drain side of the other isolation word line. Further, during a programming operation, the source and drain side channel regions are boosted early while the intermediate channel region is boosted later, when a program pulse is applied. This approach prevents charge leakage from the intermediate channel region to the source side, avoiding disturb of already programmed storage elements, while also allowing electrons to flow from the intermediate channel region to the drain side channel region, which makes the boosting of the intermediate channel region easier. | 2008-11-13 |
20080279000 | NONVOLATILE SEMICONDUCTOR MEMORY - There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the memory cells. Further, the dummy cells are disposed for the respective columns of the memory cells. The dummy cells are each made up of a series-circuit including a first switching transistor that is turned into the conducting state in response to a signal potential on a dummy word line (DWL), and a second switching transistor | 2008-11-13 |
20080279001 | OPERATING METHOD OF NON-VOLATILE MEMORY - A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed on the substrate and a first gate dielectric layer disposed between the gate and the substrate. The memory cell includes a pair of floating gate disposed on the substrate, a control gate disposed on the upper surface of the floating gates, an inter-gate dielectric layer disposed between the floating gate and the control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a second gate dielectric layer disposed between the bottom of the control gate and the substrate. | 2008-11-13 |
20080279002 | METHODS OF READING DATA INCLUDING COMPARING CURRENT AND PREVIOUS SECTION ADDRESSES AND RELATED DEVICES - A memory device may include a memory cell array arranged in a plurality of sections of memory cells, with each section of memory cells including a plurality of sub-sections of memory cells. Operation of the memory device may include providing a current memory address for a current read operation from a controller, and the current memory address may include a current section address portion and a current sub-section address portion. The current section address portion and a previous section address portion of a previous read operation may be compared. When the current and previous section address portions are different, a wait signal may be enabled at the controller. While enabling the wait signal at the controller, a section of data may be copied from the memory cell array to a section buffer, with the section of data being copied from a section of memory cells defined by the current section address portion of the current memory address. After copying the section of data to the section buffer, a sub-section of the data from the section of data in the section buffer may be transmitted to the controller. Related systems and devices are also discussed. | 2008-11-13 |
20080279003 | MULTIPLE INDEPENDENT SERIAL LINK MEMORY - An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links. | 2008-11-13 |
20080279004 | Charge-Trapping Memory Device and Methods for its Manufacturing and Operation - A method for leveling bit errors in a charge-trapping memory device is disclosed. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused by accessing memory cells of the second sector. Data stored in the first sector is backed up if the validating indicates a likelihood of a forthcoming failure in the first sector. | 2008-11-13 |
20080279005 | MANAGING FLASH MEMORY PROGRAM AND ERASE CYCLES IN THE TIME DOMAIN - A memory management component can track the amount of time between erase cycles for a particular memory region, and can manage memory region such that the regions are given sufficient time to rest and recover, or are given at least as much rest time as is practical, before being subject to an erase cycle. A reclamation management component can reclaim memory region that have invalid data stored therein, and can reclaim regions on a just-in-time basis when practical, and can determine which regions to reclaim based on various factors, such as the amount of time since a region was last erased, and the number of programming errors associated with a region. The memory management component can thereby optimize the useful life, minimize or reduce loss of margin in memory regions, and minimize or reduce programming errors of memory regions, of non-volatile (e.g., flash) memory. | 2008-11-13 |
20080279006 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRIC POWER SUPPLY METHOD - A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word and bit lines connected to the memory cells; a data program and read control section including a plurality of decoders for, when performing data programming, read or erasure with respect to a corresponding memory cell, selecting, and applying a voltage to corresponding word and bit lines; and a power supply circuit for supplying power to the data program and read control section; wherein when the power supply circuit is to supply power to the second memory cell array, an output terminal of the power supply circuit is electrically connected to at least one of the decoders connected to the first memory cell array. | 2008-11-13 |
20080279007 | BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING - Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed. | 2008-11-13 |
20080279008 | NON-VOLATILE STORAGE WITH BOOSTING USING CHANNEL ISOLATION SWITCHING - Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed. | 2008-11-13 |
20080279009 | Nonvolatile Semiconductor Memory Device and Writing Method of the Same - A nonvolatile semiconductor memory device and a writing method thereof are provided. The nonvolatile semiconductor memory device includes a cell array, a controller configured to receive input data from an outside source, an address latch unit configured to store a Y-address of the input data and X-addresses respectively corresponding to at least two wordlines, over which the input data is written, based on an address of the input data output from the controller, and a page buffer configured to receive the input data from the controller and temporarily store the input data. The controller writes the data stored in the page buffer over the two wordlines in the cell array based on the at least two X-addresses and the Y-address. | 2008-11-13 |
20080279010 | FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method for programming a flash memory device comprising programming memory cells via repetition of program loops, a first of the program loops including a program execution interval and a verify read interval, a second of the program loops including the program execution interval, the verify read interval, and a judging interval. Also disclosed is a flash memory device comprising a memory cell array having memory cells arranged in rows and columns, a read/program circuit configured to perform program and read operations to the memory cell array, and a control logic circuit configured to control the read/program circuit so as to perform a judging operation according to a program loop number. | 2008-11-13 |
20080279011 | DATA PROCESSING APPARATUS - The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened. | 2008-11-13 |
20080279012 | Methods of Operating Memory Devices Including Negative Incremental Step Pulse Programming and Related Devices - A memory device may include a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. Moreover, the string selection transistor may be coupled between the string and a bitline, and the ground selection transistor may be coupled between the string and a common source line. During programming, one of the plurality of memory cell transistors in the string may be selected for a program operation so that other memory cell transistors in the string are unselected, and a plurality of negative voltage pulses may be applied to a channel region of the selected memory cell transistor. While applying the plurality of negative voltage pulses to the channel region, a positive pass voltage may be applied to control gate electrodes of the unselected memory cell transistors, and a positive program voltage may be applied to a control gate electrode of the selected memory cell. Related methods and devices are discussed. | 2008-11-13 |
20080279013 | Multi-level non-volatile memory cell with high-VT enhanced BTBT device - The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage. | 2008-11-13 |
20080279014 | MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY - Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines. | 2008-11-13 |
20080279015 | REGISTER FILE - A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time. | 2008-11-13 |
20080279016 | SIMPLIFIED-DOWN MODE CONTROL CIRCUIT UTILIZING ACTIVE MODE OPERATION CONTROL SIGNALS - A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level. | 2008-11-13 |
20080279017 | Semiconductor memory device - During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner. | 2008-11-13 |
20080279018 | REDUNDANCY CIRCUIT CAPABLE OF REDUCING TIME FOR REDUNDANCY DISCRIMINATION - A redundancy circuit in a semiconductor memory apparatus includes a comparison signal receiving unit to receive a plurality of comparison signals and a fuse enable signal in parallel, wherein the comparison signals are generated by comparing a plurality of row address signals to a plurality of fuse address signals; and a redundancy control signal generating unit for providing a redundancy control signal by controlling an output signal path of the comparison signal receiving unit in response to a signal level of a row address enable signal. The comparison signal receiving unit receives the plurality of the comparison signals and the fuse enable signal while the row address enable signal is activated. | 2008-11-13 |
20080279019 | SEMICONDUCTOR DEVICE - A semiconductor includes a first sensor amplifier, a second sensor amplifier, a first switch and a second switch. The first sensor amplifier is coupled between a local data line and a memory unit to amplify signals of the memory unit. The second sensor amplifier is coupled to a middle data line to amplify signals of the middle data line. The first switch is coupled between the middle data line and the local data line to equalize voltage levels between the middle data line and the local data line by turning on the first switch according to a data control signal. The second switch is coupled between the local data line and a reference voltage to equalize the local data line to the voltage level of the reference voltage by turning on the second switch according to a local data control signal. | 2008-11-13 |
20080279020 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. | 2008-11-13 |
20080279021 | MULTI-WORDLINE TEST CONTROL CIRCUIT AND CONTROLLING METHOD THEREOF - A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal. | 2008-11-13 |
20080279022 | SEMICONDUCTOR DEVICE WITH SELF REFRESH TEST MODE - A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. | 2008-11-13 |
20080279023 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRSM at internally doubled clock testing application - The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. | 2008-11-13 |
20080279024 | PROGRAMMABLE BOOSTING AND CHARGE NEUTRALIZATION - A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node and the output node. Each of the capacitance stages includes a capacitor, and a control transistor having a gate capacitance in series with the capacitor, wherein the gate capacitance is configured to be added to the capacitance of the capacitor between the input node and the output node. | 2008-11-13 |
20080279025 | Electronic Circuit with Memory for Which a Threshold Level is Selected | 2008-11-13 |
20080279026 | Signal sensing circuit and semiconductor memory device using the same - A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level. | 2008-11-13 |
20080279027 | Thermally Stable Reference Voltage Generator for Mram - A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the reference is degraded by thermal instability. This can help reduce a data error rate. Detecting such degradation can prove to be more effective than trying to design in enough margins for the lifetime of the device. The reference cell can be less susceptible to degradation than other cells by using different shape of cells and different write currents. Where each reference cell is used by many memory cells, the reference cell tends to be used more often than any particular memory cell and so can be more susceptible to degradation. Another way of ensuring against longer term degradation of the reference is periodically rewriting the reference cell. | 2008-11-13 |
20080279028 | FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY - A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline. | 2008-11-13 |
20080279029 | LOW VOLTAGE DATA PATH IN MEMORY ARRAY - A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch. | 2008-11-13 |
20080279030 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit includes a control signal generating unit not generating a control signal that is enabled when a supply voltage is unstable and a voltage level maintaining unit for selectively controlling total capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control signal. | 2008-11-13 |
20080279031 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer. | 2008-11-13 |
20080279032 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 2008-11-13 |
20080279033 | Semiconductor integrated circuit device - A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected. | 2008-11-13 |
20080279034 | DATA OUTPUT CIRCUIT OF SYNCHRONOUS MEMORY DEVICE - A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal. | 2008-11-13 |
20080279035 | Expandable Joint - A concrete mixing includes a barrel having an interior surface and an exterior surface. A blade extends from the interior surface for mixing concrete and a ring is positioned about the exterior surface of the barrel for rotation of the barrel. An expandable joint is provided under compression between the ring and the exterior surface of the barrel to accommodate different thermal coefficients of expansion between the barrel and the ring. | 2008-11-13 |
20080279036 | Control for a truck mixer - The present invention relates to a control for truck mixers having a hydraulically driven mixer drum, with the hydraulic pump of the mixer drive being driven by the drive motor of the truck mixer or by a separate motor. In accordance with the invention, the speed of the drive motor is adjustable in dependence on the demanded drum speed, with the desired drum speed being able to be set via an operating lever. | 2008-11-13 |
20080279037 | APPARATUS AND METHOD FOR MIXING A FILM OF FLUID - A method and apparatus is provided for mixing a film of fluid, particularly a film of chemical, biochemical or biological fluids undergoing a reaction. The apparatus comprises a means for nucleating a bubble using a discrete heat source, such as a resistor, and moving the bubble in the fluid by creating a temperature gradient thereby mixing the fluid. | 2008-11-13 |
20080279038 | MULTI-STAGE ACCURATE BLENDING SYSTEM AND METHOD - An accurate blending system for blending a feed liquid and first and second adjusting liquids includes a first feed means adapted to communicate with a supply of feed liquid, a second feed means adapted to communicate with a supply of the first adjusting liquid and a third feed means adapted to communicate with a supply of the second adjusting liquid. The first, second and third feed means may be pumps, valves or combinations thereof. A mixing device is in communication with the first, second and third feed means. First and second sensors are in communication with the mixing device. A controller communicates with the first and second sensors so that first and second characteristics of the solution in the mixing device can be detected. The controller also communicates with the first and second feed means so that delivery of first and second adjusting liquid to the mixing device can be controlled based upon the detected first and second characteristics of the solution in the mixing device. | 2008-11-13 |
20080279039 | Apparatus and Method for Mixing With a Diaphragm Pump - An apparatus for mixing a fluid including a storage vessel including a hollow portion for holding the fluid, the hollow portion including at least one access port, the at least one access port adapted to at least one of receive and expel fluid and a diaphragm pump in fluid communication with and removeably coupled to the vessel, the pump adapted to move fluid into and/or out of the hollow portion. Either the vessel or the pump can be disposable. Also, at least one portion of the vessel can be made of a flexible material that takes shape in relation to the contents of the hollow portion. Also, the fluid can be moved between the vessel and the pump by natural or artificial pressure. | 2008-11-13 |
20080279040 | FROZEN DRINK MIXER HAVING A LID WHICH ENGAGES A CUP FOR DRINK MIXING AND CLEANING OF MIXING COMPONENTS - A drink mixer includes a frame; a support having a drain; a lid having an annular groove and movable relative to a mounted mixing cup from an elevated position to a mating position where the annular groove engages the cup's rim; a mixer shaft passing through the lid; a motor coupled to the mixer shaft; a blade assembly coupled to a lower end of the mixer shaft, the blade assembly alternately assuming either a retracted position within the lid or an extended position within a mounted cup; a mechanism for alternatively bringing said support and said lid towards one another so that the annular groove of said lid can engage the rim of a mounted cup, or moving the cup and lid apart; a mechanism for alternately establishing the retracted and extended positions; and a mechanism for dispensing washing solution into the cleaning cup. | 2008-11-13 |
20080279041 | FLUIDIC MIXER WITH CONTROLLABLE MIXING - In one embodiment of the disclosure, a fluid mixing device comprises a flow duct, with a wall having an inner surface defining a fluid flow path for a primary flow, and at least one deployable and retractable projection. The projection is adapted to controllably generate at least one secondary flow adjacent the inner surface. In other embodiments, methods are provided of controllably mixing at least one fluid within a fluid mixing device. | 2008-11-13 |
20080279042 | ACTIVE STEERING FOR MARINE SOURCES - A seismic survey system includes a winch having a winch cable coupleable to a source array towable between two deflected lead-ins, a positioning system for determining a current position of the source array and a controller for adjusting the winch to modify the current position of the source array to a desired crossline position. The winches may be attached to the deflected lead-ins or mounted on a tow vessel. The winches exert lateral forces on the source array, derived from the deflected lead-ins, to control the inline position of the source array. A method includes positioning a seismic source array in tow behind a vessel comprises determining a current position of the source array and adjusting a lateral force applied to the source array to move the source array to a desired crossline position. Optionally, by adjusting the gun cable winch, the inline position may be controlled. | 2008-11-13 |