46th week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090278131 | Thin film transistor array arrangement, organic light emitting display device having the same, and manufacturing method thereof - A thin film transistor (TFT) array arrangement, an organic light emitting display device that includes the TFT array arrangement and a method of making the TFT array arrangement and the organic light emitting display device. The method seeks to reduce the number of masks used in the making of the TFT array arrangement by employing half-tone masks that are followed by a two step etching process and by forming layers of the capacitor simultaneous with the formation of layers of the source, drain and pixel electrodes. As a result, individual layers of the capacitor are on the same level and are made of the same material as ones of the layers of the source, drain and pixel electrodes. The capacitor has three electrodes spaced apart by two separate dielectric layers to result in an increased capacity capacitor without increasing the size of the capacitor. | 2009-11-12 |
20090278132 | ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE HAVING THIN FILM TRANSISTOR ON COLOR FILTER AND METHOD OF FABRICATING THE SAME - An array substrate of a liquid crystal display device having a color filter on a gate metal layer, and a data metal layer formed on the color filter. First a gate insulating layer is formed on the gate metal layer to protect and a second gate insulating layer is formed on the color filter layer. Gate lines and gate electrodes are formed in direct contact with the substrate, and color filters are formed on the gate electrodes. To protect gate lines in the patterning process of color filters, a first gate insulating layer is formed on the gate lines and electrodes. Therefore, a high aperture ratio may be enhanced, and the manufacturing yield may be increased. | 2009-11-12 |
20090278133 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY - A thin film transistor array panel includes a substrate, a first thin film transistor formed on the substrate, a color filter formed on the first thin film transistor and having a through hole, a capping layer formed on the color filter and having an opening, and a pixel electrode formed on the capping layer and connected to the first thin film transistor through the through hole. The opening exposes the color filter outside the through hole. | 2009-11-12 |
20090278134 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - In a semiconductor device according to the present invention, an insulator layer on a substrate is provided with a trench. A gate electrode is formed in the trench so that an upper surface of the gate electrode is approximately flush with an upper surface of the insulator layer. On the gate electrode, a semiconductor layer is provided via a gate insulating film. At least one of a source electrode and a drain electrode is electrically connected to the semiconductor layer. Particularly, the gate insulating film includes an insulator coating film provided on the gate electrode, and an insulator CVD film formed on the insulator coating film. | 2009-11-12 |
20090278135 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE USING THE SAME - Disclosed herein is a thin film transistor, including: a gate electrode; a crystallized semiconductor layer formed through a gate insulating film on the gate electrode; and a drain electrode and a source electrode provided on both end sides of the crystallized semiconductor layer, respectively, and provided through impurity doped layers each contacting the crystallized semiconductor layer, respectively. | 2009-11-12 |
20090278136 | Process for Growth of Low Dislocation Density Gan - High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 10 | 2009-11-12 |
20090278137 | SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING - Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described. | 2009-11-12 |
20090278138 | LAMINATED STRUCTURE AND IMAGE DISPLAY DEVICE - A laminated structure includes a wettability variable layer formed on a substrate, including a material whose critical surface tension varies by receiving energy so that high and low surface energy regions are formed; a conductive layer formed in one of the high surface energy regions; and an insulating layer formed in such a manner as to cover the conductive layer, wherein another one of the high surface energy regions is formed in such a manner as to surround a periphery of a circuit formation region in which a plurality of the conductive layers are formed; and the insulating layer is formed in such a manner as to also cover the another one of the high surface energy regions so that an adhesive guard ring region is formed between the wettability variable layer and the insulating layer. | 2009-11-12 |
20090278139 | LIGHT-EMITTING DIODE PACKAGE ASSEMBLY - An electrical device containing multiple light emitting diode (LED) dies each having respective first and second connectors suitable to receive current through the LED die. A common base layer of a first electrically conductive material has cavities into which at least one LED die is mounted with its second connector electrically connected by a conductive bonding material to the first conductive material of the base layer. One or more over-layer sections of a second electrically conductive material each are electrically connected by a bond to at least one of the first connector of a LED die. And an insulator electrically separates the first conductive material of the base layer from the second conductive material of over-layer sections. | 2009-11-12 |
20090278140 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises the steps of: providing a substrate; forming a plurality of grooves on the substrate by photolithograph etching or laser engraving, wherein the plurality of grooves divides a surface of the substrate into a plurality of mesas and the substrate is a patterned substrate; and growing a semiconductor device (e.g. photo-electronic device or LED) on the patterned substrate. The semiconductor device comprises at least one layer, wherein the layer directly disposed on the patterned substrate is the first layer. The first layer comprises a plurality of separated regions divided by the grooves. | 2009-11-12 |
20090278141 | Light-emitting devices and displays with improved performance - Light-emitting devices and displays with improved performance are disclosed. A light-emitting device includes an emissive material disposed between a first electrode, and a second electrode. Various embodiments include a device having a peak external quantum efficiency of at least about 2.2%; a device that emits light having a CIE color coordinate of x greater than 0.63; a device having an external quantum efficiency of at least about 2.2 percent when measured at a current density of 5 mA/cm | 2009-11-12 |
20090278142 | LIGHT-EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light-emitting diode display is provided. The method includes pre-fixing first, second, and third light-emitting diodes on a light emitting unit production substrate to produce light-emitting units each including first, second, and third light-emitting diodes, first electrodes of the first, second, and third light-emitting diodes being connected to a sub-common electrode. The method also includes transferring and fixing the light-emitting units from the light-emitting unit production substrate to a display substrate to produce a light-emitting diode display including the light-emitting units which are arranged in a first direction and a second direction perpendicular to the first direction (i.e., arranged in a two-dimensional matrix). | 2009-11-12 |
20090278143 | Semiconductor Light Emitting Device - A plurality of transistors are formed on a substrate in a plurality of columns. Each transistor has a first conductivity type region and second conductivity type regions provided on both sides thereof in a column direction, and has an active layer on the side of each second conductivity type region closer to the substrate. Between two columns adjacent to each other, the second conductivity type region on a first side in the column direction of each transistor arranged on a first column, the second conductivity type region on a second side in the column direction of the transistor adjacent to this transistor on the first side in the column direction and the first conductivity type region of each transistor arranged on a second column are electrically connected by a first wire. Between these two columns, the second conductivity type region on the first side in the column direction of each transistor arranged on the second column, the second conductivity type region on the second side in the column direction of the transistor adjacent to this transistor on the first side in the column direction and the first conductivity type region of each transistor arranged on the first column are electrically connected by a second wire. | 2009-11-12 |
20090278144 | Nitride Semiconductor Light Emitting Device - There is provided a nitride semiconductor light emitting device having a light reflection layer capable of preventing reflectivity from lowering and luminance from lowering due to deterioration of quality of an active layer. A nitride semiconductor laser includes at least a light emitting layer forming portion ( | 2009-11-12 |
20090278145 | Semiconductor Light Emitting Device and Method for Manufacturing the Same - To provide a semiconductor light emitting device with a light extraction efficiency increased and a method for manufacturing the semiconductor light emitting device. | 2009-11-12 |
20090278146 | PHOSPHOR ILLUMINATION OPTICS FOR LED LIGHT SOURCES - Devices and methods for collecting and distributing light from a light emitting diode (LED) emitter onto a phosphor layer to produce substantially white light are provided. The devices may include a reflective cavity with a reflective material, surrounding the reflective cavity, with a reflective side of the reflective material facing towards the inside of the reflective cavity. Further, the devices may incorporate an LED on one end of the reflective cavity and a phosphor layer on another end. Additionally, the devices may use a gradient index (GRIN) rod lens to refract light produced from the LED onto a phosphor surface with an LED on one end of the GRIN rod lens and the phosphor layer on the other end. | 2009-11-12 |
20090278147 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Disclosed is a semiconductor light-emitting device having improved light-extraction efficiency. Specifically disclosed is a semiconductor light-emitting device ( | 2009-11-12 |
20090278148 | LIGHT-EMITTING DIODE AND METHOD FOR FABRICATION THEREOF - A transparent-substrate light-emitting diode ( | 2009-11-12 |
20090278149 | LIGHT EMITTING DIODE | 2009-11-12 |
20090278150 | METHOD FOR FORMING METAL ELECTRODE, METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENTS AND NITRIDE BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENTS - A method for forming a metal electrode and a method for manufacturing semiconductor light emitting elements include providing a substrate having a semiconductor layer formed thereon; forming a bonding metal layer and a reflective metal layer on the semiconductor layer; and forming a metal electrode by layer inversion of the bonding metal layer and the reflective metal layer through a heat treatment process. An interface characteristic between a semiconductor layer and an electrode having a reflective metal layer is enhanced by a layer inversion phenomenon. High reflectivity can be obtained, because a reflection metal layer is uniformly distributed on a semiconductor layer. Further, out-diffusion of a reflective metal layer is prevented through layer inversion to enhance the thermal stability of an electrode. And the number of accepters for generating holes is increased through heat treatment under an oxygen atmosphere, so that contact resistance can be lowered. | 2009-11-12 |
20090278151 | Light emitting diode packages, light emitting diode systems and methods of manufacturing the same - In a method of forming an LED semiconductor device, and in an LED semiconductor device, an LED is provided on a substrate. A first encapsulant material layer is provided on the LED, and the first encapsulant material layer is firstly annealed. A luminescence conversion material layer is provided on the firstly annealed first encapsulant material layer, and the first encapsulant material layer and the luminescence conversion material layer and secondly annealed. | 2009-11-12 |
20090278152 | LIGHT EMITTING DIODE AND PACKAGE METHOD THEREOF - A light emitting diode comprises a sheet-like package body, a barricade, a light emitting diode die, and fluorescent filler. The sheet-like package body has a die-bonding region. The barricade is a transparent wall that is disposed on the die-bonding region, and is integrated with the sheet-like package body or is adhered to sheet-like package body. The light emitting diode die is disposed on the region enclosed by the barricade, and the fluorescent filler is also filled into the region and surrounds the light emitting diode die. The light emitting diode and the method for packaging the light emitting diode can improve the uniformity and efficiency of the outputting light emitted from the light emitting diode, and the loss of the outputted light is reduced. | 2009-11-12 |
20090278153 | LIGHT EMITTING DEVICE - Provided is a light emitting device. The light emitting device comprises a package body, a plurality of electrodes, a light emitting diode, and a lens. The package body comprises a trench. The plurality of electrodes is disposed on and/or in the package body. The light emitting diode is disposed on the package body and is electrically connected to the electrodes. The lens is disposed on an inner side of the trench. | 2009-11-12 |
20090278154 | Led module and method of manufacturing the same - Provided are a light emitting diode (LED) module and a method of manufacturing the same. The LED module may include a package housing including an inner space, a light-emitting chip in the inner space of the package housing, a phosphor layer including a fluorescent material and converting light emitted from the light-emitting chip to light having a longer wavelength than that of the light emitted from the light-emitting chip. The concentration of the fluorescent material of the phosphor layer may be inhomogeneous. The method of manufacturing the LED module may include providing or forming a package housing having an inner space and including a light-emitting chip in the inner space, measuring a radiation pattern of light emitted from the light-emitting chip, and forming a phosphor layer including a fluorescent material on the light-emitting chip and having characteristics that may be determined according to the radiation pattern. | 2009-11-12 |
20090278155 | BACKLIGHT DEVICE FOR LIQUID CRYSTAL DISPLAY INCLUDING A PLURALITY OF LIGHT EMITTING DIODES WITHIN THEIR OWN CONCAVES ALIGNED IN A STRAIGHT LINE WITHIN A LARGER CONCAVE - A semiconductor light emitting device of the present invention includes a plurality of light emitting elements, a package body for storing the light emitting elements, wiring patterns being electrically connected to the light emitting elements, and Au wires for electrically connecting the light emitting elements and the wiring patterns, the package body including mounting concave portions for storing the respective light emitting elements, and storing concave portion for storing the mounting concave portions and the Au wires, the mounting concave portions being aligned on a linear line and spaced from each other with an equal pitch. In the above arrangement, as the semiconductor light emitting device of the present invention, it is possible to provide a semiconductor light emitting device having a high directional characteristic of emitted light, and a backlight device for a liquid crystal display, the backlight device using the semiconductor light emitting device and having an improved brightness of the emitted light. | 2009-11-12 |
20090278156 | MOLDED CHIP FABRICATION METHOD AND APPARATUS - A light emitting diode (LED) is disclosed comprising a plurality of semiconductor layers with a first contact on the bottom surface of the semiconductor layers and a second contact on the top surface of the semiconductor layer. A coating is included that comprises a cured binder and a conversion material that at least partially covers the semiconductor layers, wherein the second contact extends through the coating and is exposed on the same plane as the top surface of the coating. An electrical signal applied to the first and second contacts is conducted through the coating to the semiconductor layers causing the LED to emit light. In other embodiments first and second contacts are accessible from one side of the LED. A coating is included that comprises a cured binder and a conversion material. The coating at least partially covers the semiconductor layers, with the first and second contacts extending through the coating and exposed on the same plane as a surface of the coating. An electrical signal applied to the first and second contacts is conducted through the coating to the semiconductor layers causing the LED to emit light. | 2009-11-12 |
20090278157 | Method for the production of a semiconductor component comprising a planar contact, and semiconductor component - In a method for producing a semiconductor component, in particular a semiconductor structure having a surface structure or topography which is produced by means of electronic components ( | 2009-11-12 |
20090278158 | GALLIUM NITRIDE BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a gallium nitride based compound semiconductor light-emitting device having high light emission efficiency and a low driving voltage Vf. The gallium nitride based compound semiconductor light-emitting device includes a p-type semiconductor layer, and a transparent conductive oxide film that includes dopants and is formed on the p-type semiconductor layer. A dopant concentration at an interface between the p-type semiconductor layer and the transparent conductive oxide film is higher than the bulk dopant concentration of the transparent conductive oxide film. Therefore, the contact resistance between the p-type semiconductor layer and the transparent conductive oxide film is reduced. | 2009-11-12 |
20090278159 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE WITHOUT SUBSTRATES FOR ACHIEVING FACE-UP ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure without substrates for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove for receiving the semiconductor chip. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers. The second conductive unit has a plurality of second conductive layers formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers. | 2009-11-12 |
20090278160 | RADIATION EMITTING SEMICONDUCTOR DEVICE - The present invention provides a radiation emitting semiconductor device, which comprises an active layer for emitting radiation, a p-type conductive layer, a transparent conductive layer, and a non-p-type ohmic contact layer. The p-type conductive layer is formed on the active layer. The transparent conductive layer is formed on the p-type conductive layer. The non-p-type ohmic contact layer is disposed between said p-type conductive layer and said transparent conductive layer. The non-p-type ohmic contact layer is configured to reduce the operating voltage of said radiation emitting semiconductor device. In addition, the present invention provides that the non-p-type ohmic contact layer is made of a quaternary alloy of Al | 2009-11-12 |
20090278161 | Method of fabricating vertical structure LEDs - A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out. | 2009-11-12 |
20090278162 | Low Temperature Co-Fired Ceramic (LTCC) Tape Compositions, Light-Emitting Diode (LED) Modules, Lighting Devices and Methods of Forming Thereof - The present invention provides LTCC (low temperature co-fired ceramic) tape compositions and demonstrates the use of said LTCC tape(s) in the formation of Light-Emitting Diode (LED) chip carriers and modules for various lighting applications. The present invention also provides for the use of (LTCC) tape and LED modules in the formation of lighting devices including, but not limited to, LED devices, High Brightness (HB) LED backlights, display-related light sources, automotive lighting, decorative lighting, signage and advertisement lighting, and information display lighting. | 2009-11-12 |
20090278163 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - A light-emitting device ( | 2009-11-12 |
20090278164 | GaN-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR THE FABRICATION THEREOF - A GaN-based semiconductor light-emitting device | 2009-11-12 |
20090278165 | Light emitting device and fabrication method therefor - A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure formed on the epitaxial layer, and an LED active layer formed on the DBR multi-layer structure. | 2009-11-12 |
20090278166 | SEMICONDUCTOR DEVICE - A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A mean value of the lifetime of holes in the drift layer that includes the low lifetime region is shorter within the IGBT element region than within the diode element region. | 2009-11-12 |
20090278167 | Semiconductor device including a plurality of chips and method of manufacturing semiconductor device - A semiconductor device includes a first chip and a second chip. The first chip includes a first conductivity type channel power MOSFET. The second chip includes a second conductivity type channel power MOSFET. The first chip and the second chip are integrated in such a manner that a second-surface drain electrode of the first chip and a second-surface drain electrode of the second chip face to each other and are electrically coupled with each other through a conductive material. | 2009-11-12 |
20090278168 | STRUCTURE OF SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type. | 2009-11-12 |
20090278169 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers. | 2009-11-12 |
20090278170 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process. | 2009-11-12 |
20090278171 | High linearity doped-channel FET - A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap layer between the source region and the drain region. A source electrode and a drain electrode are respectively formed on the source region and the drain region, and a gate electrode is formed on the gate region, wherein the source region and the drain region of the cap layer are respectively provided with an opening for forming a good ohmic contact between the source region and the drain region with the channel layer respectively. | 2009-11-12 |
20090278172 | GaN based semiconductor element - The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves. | 2009-11-12 |
20090278173 | MEMORY DEVICE INTERCONNECTS AND METHOD OF MANUFACTURING - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes. | 2009-11-12 |
20090278174 | PIXEL STRUCTURE OF SOLID-STATE IMAGE SENSOR - A pixel structure of a solid-state image sensor in which residual electrons in a photodiode is reduced and which has a first-stage gate that is arranged adjacent to the photodiode and controls read-out of electrons generated in the photodiode, a second-stage gate that is adjacent to the first-stage gate on the rear stage of the gate at a predetermined gap and controls movement of electrons read out by the readout control of the first-stage gate to the plurality of the charge-storage sections, and a plurality of third-stage gates that are adjacent to the second-stage gate on the rear stage of the gate at a predetermined gap, severally arranged corresponding to the plurality of the charge-storage sections, and perform control of distributing the electrons moved by the movement control of the second-stage gate severally to the plurality of the charge-storage sections, and gradient on which electrons are moved in the first-stage gate direction is formed on the potential of the photodiode. | 2009-11-12 |
20090278175 | METHOD FOR FORMING EXTENDED GATE FIELD EFFECT TRANSISTOR (EGFET) BASED SENSOR AND THE SENSOR THEREFROM - The invention provides a method for forming an extended gate field effect transistor (EGFET) based sensor, including: (a) providing a substrate; (b) forming a sensing film including titanium dioxide, ruthenium doped titanium dioxide or ruthenium oxide on the substrate; and (c) forming a conductive wire extended from the sensing film for external contact. | 2009-11-12 |
20090278176 | HIGH CURRENT DENSITY POWER FIELD EFFECT TRANSISTOR - An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source. | 2009-11-12 |
20090278177 | SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING - Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described. | 2009-11-12 |
20090278178 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device which includes a MIS FET on a surface of a substrate, an insulating film on the substrate to cover the MIS FET, an opening that gets to an impurity diffusing region formed in the insulating film, another opening that gets to a gate electrode or to an extension part of the gate electrode formed in the insulating film, and an electrically conductive member including mainly copper filled in each of the openings. The insulating film includes a layer including, as main components, silicon, oxygen, carbon and hydrogen (FIG. | 2009-11-12 |
20090278179 | CHIP SCALE SURFACE MOUNT PACKAGE FOR SEMICONDUCTOR DEVICE AND PROCESS OF FABRICATING THE SAME - A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice. | 2009-11-12 |
20090278180 | CMOS IMAGE SENSOR WITH ASYMMETRIC WELL STRUCTURE OF SOURCE FOLLOWER - Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged. | 2009-11-12 |
20090278181 | SOLID-STATE IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - A solid-state image sensor includes: a trench isolation region; a photodiode region for converting incident light to signal charges and accumulating the signal charges therein; a floating diffusion region for accumulating the signal charges of the photodiode region; a gate electrode formed over the element formation region located between the photodiode region and the floating diffusion region, and formed so that both ends of the gate electrode respectively overlap a part of the photodiode region and a part of the floating diffusion region; and an inactive layer formed in a region located in a bottom portion and sidewall portions of the trench isolation region. An impurity concentration in a region located under the gate electrode in the inactive layer is lower than that in a region other than the region located under the gate electrode in the inactive layer. | 2009-11-12 |
20090278182 | SPIN INJECTOR - A spin injector for use in a microelectronic device such as a field effect transistor (FET) is disclosed. The spin injector includes an array of ferromagnetic elements disposed within a semiconductor. The ferromagnetic elements within the array are arranged and spaced with respect to one another in a close arrangement such that electrons or holes are spin-polarized when passing through. The spin injector may be located above or at least partially within a source region of the FET. A spin injector structure may also be located above or at least partially within the drain region of the FET. The spin injector includes a semiconductor material containing an array of ferromagnetic elements disposed in the semiconductor material, wherein adjacent ferromagnetic elements within the array are separated by a distance within the range between about 1 nm and 100 nm. | 2009-11-12 |
20090278183 | Semiconductor Device with Channel of Fin Structure and Method for Manufacturing the Same - Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and a trench with a second width larger than the first width is formed in the device isolation layer. The trench formed in the device isolation layer is filled with a capping layer. A cleaning process is performed on the recess trench to form a bottom protrusion of a FIN structure including a protrusion and a sidewall. Gate stacks filling the recess trench are formed. A landing plug, which is divided by the capping layer filling the trench, is formed between the gate stacks. | 2009-11-12 |
20090278184 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE IN WHICH DECREASE IN COUPLING RATIO OF MEMORY CELLS IS SUPPRESSED - A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer. | 2009-11-12 |
20090278185 | DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY - Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode. | 2009-11-12 |
20090278186 | Double Gate Transistor and Method of Manufacturing Same - A double gate transistor on a semiconductor substrate ( | 2009-11-12 |
20090278187 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device of an aspect of the present invention includes a semiconductor substrate, two diffusion layers provided in the semiconductor substrate, a gate insulating film provided on a channel region between the two diffusion layers, and a gate electrode which is composed of a stack of a plurality of conductive films and a plurality of insulating films provided on the gate insulating film and a silicide layer provided on the stack, wherein of the plurality of films included in the stack, the conductive film different in configuration from the silicide layer is in contact with the gate insulating film. | 2009-11-12 |
20090278188 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - To reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating gate and a control gate. In addition, a second island-shaped semiconductor region is formed under the floating gate with an insulating film interposed therebetween. Since the second island-shaped semiconductor region is electrically connected to the control gate, a capacitance is formed between the second island-shaped semiconductor region and the floating gate. This capacitance contributes to an increase in the coupling ratio of the memory transistor, which makes it possible to increase the coupling ratio without increasing the area of the memory cell. Furthermore, the area of the memory cell can be reduced without reducing the coupling ratio. | 2009-11-12 |
20090278189 | SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD OF FABRICATING SAME - A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral circuit region disposed on the semiconductor substrate and comprising a peripheral gate pattern, and a resistor disposed in the peripheral circuit region at level above the semiconductor substrate similar to that of the cell semiconductor pattern. | 2009-11-12 |
20090278190 | Nonvolatile semiconductor memory - A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines. | 2009-11-12 |
20090278191 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE IN WHICH DECREASE IN COUPLING RATIO OF MEMORY CELLS IS SUPPRESSED - A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer. | 2009-11-12 |
20090278192 | SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern. | 2009-11-12 |
20090278193 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor. | 2009-11-12 |
20090278194 | Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics - A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern. | 2009-11-12 |
20090278195 | SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH STACKED LAYER GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE, AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film formed on the first insulating film. The control gate electrode formed so as to include a first metal film formed on the second insulating film and a first conductive film formed on the first metal film. The first MOS transistor includes a second conductive film, a second metal film, a third conductive film, and a second diffusion layer. The second conductive film formed on a second active region. The second metal film formed on the second conductive film. The third conductive film formed on a second metal film. | 2009-11-12 |
20090278196 | FinFETs having dielectric punch-through stoppers - A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator. | 2009-11-12 |
20090278197 | MIS FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in contact with the drawn portion; and a source electrode electrically connected to the third group III-V nitride semiconductor layer. | 2009-11-12 |
20090278198 | Deep source electrode MOSFET - A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches. | 2009-11-12 |
20090278199 | Method for Preventing Gate Oxide Damage of a Trench MOSFET during Wafer Processing while Adding an ESD Protection Module Atop - A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes:
| 2009-11-12 |
20090278200 | TRANSISTOR, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N | 2009-11-12 |
20090278201 | ENHANCED STRESS-RETENTION SILICON-ON-INSULATOR DEVICES AND METHODS OF FABRICATING ENHANCED STRESS RETENTION SILICON-ON-INSULATOR DEVICES - Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region. | 2009-11-12 |
20090278202 | SOI DEVICE WITH IMPROVED STORAGE CAPACITY AND METHOD FOR MANUFACTURING THE S - An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of each of the grooves. An epi-silicon layer is formed to fill the grooves and cover the barrier layer. Gates are formed on the epi-silicon layer, and junction areas are formed in the silicon layer on both sides of the gates. | 2009-11-12 |
20090278203 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor film with a gate insulating film interposed therebetween, is formed over the semiconductor film. In the semiconductor film, a channel forming region, a first impurity region forming a source or drain region, and a second impurity region are provided. The channel forming region is provided in a region which overlaps with the gate electrode crossing the island-like semiconductor film, the first impurity region is provided so as to be adjacent to the channel forming region, and the second impurity region is provided so as to be adjacent to the channel forming region and the first impurity region. The first impurity region and the second impurity region are provided so as to have different conductivity, and the second impurity region and the channel forming region are made to have different conductivity or to have different concentration of an impurity element contained in the second impurity region and the channel forming region in a case of having the same conductivity. | 2009-11-12 |
20090278204 | SEMICONDUCTOR DEVICE - There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. | 2009-11-12 |
20090278205 | High Voltage BICMOS Device and Method for Manufacturing the Same - A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region. | 2009-11-12 |
20090278206 | High-Frequency Switching Transistor and High-Frequency Circuit - A switching transistor includes a substrate having a substrate dopant concentration and a barrier region bordering on the substrate, having a first conductivity type and having a barrier region dopant concentration that is higher than the substrate dopant concentration. A source region is embedded in the barrier region, and has a second conductivity type and has a dopant concentration that is higher than the barrier region dopant concentration. A drain region is embedded in the barrier region and is offset from the source region. The draining region has the second conductivity type and a dopant concentration that is higher than the barrier region dopant concentration. A channel region extends between the source region and the drain region, wherein the channel region comprises a subregion of the barrier region. An insulation region covers the channel region and is disposed between the channel region and a gate electrode. The barrier region dopant concentration and the substrate dopant concentration are chosen for generating a space-charge region around the source region and the drain region and for depleting the barrier region. | 2009-11-12 |
20090278207 | Electromigration-Complaint High Performance FET Layout - An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor. | 2009-11-12 |
20090278208 | Semiconductor integrated circuit device and method of fabricating the same - A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed on the active region of the semiconductor substrate. Trench insulating layers may be formed in the semiconductor substrate on and around edges of the gate pattern so as to be able to relieve an electrical field from the gate pattern. The depths of each of the trench insulating layers may be defined according to an operating voltage. Source and drain regions enclose the trench insulating layers and may be formed in the semiconductor substrate on both sides of the gate pattern. Therefore, the semiconductor integrated circuit device may have a higher integration density and may relieve an electrical field from the gate pattern. | 2009-11-12 |
20090278209 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon. | 2009-11-12 |
20090278210 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode. | 2009-11-12 |
20090278211 | Composite dielectric thin film, capacitor and field effect transistor using the same, and each fabrication method thereof - a composite dielectric thin film capable of high dielectric constant, low leakage current characteristics, and high dielectric breakdown voltage while being deposited at a room temperature, a capacitor and a field effect transistor (FET) using the same, and their fabrication methods. The composite dielectric thin film is deposited at a room temperature or less than 200° C. and comprises crystalline or amorphous insulating filler uniformly distributed within an amorphous dielectric matrix or within an amorphous and partially nanocrystalline dielectric matrix. | 2009-11-12 |
20090278212 | Integrated Device - An integrated device including a sensor and the like formed on a γ-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a γ-alumina film epitaxially grown on a portion of the silicon substrate; a second function area formed on an area of the silicon substrate other than an area where the γ-alumina film is grown; and wiring means for connecting the first function area with the second function area. | 2009-11-12 |
20090278213 | ELECTRODE ARRAYS AND METHODS OF FABRICATING THE SAME USING PRINTING PLATES TO ARRANGE PARTICLES IN AN ARRAY - Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes. | 2009-11-12 |
20090278214 | Microelectromechanical Systems Encapsulation Process - An encapsulated MEMS process including a high-temperature anti-stiction coating that is stable under processing steps at temperatures over 450 C is described. The coating is applied after device release but before sealing vents in the encapsulation layer. Alternatively, an anti-stiction coating may be applied to released devices directly before encapsulation. | 2009-11-12 |
20090278215 | ELECTRONIC DEVICE, SYSTEM, AND METHOD COMPRISING DIFFERENTIAL SENSOR MEMS DEVICES AND DRILLED SUBSTRATES - Electronic device which comprises a substrate provided with at least one passing opening, a MEMS device with function of differential sensor provided with a first and a second surface and of the type comprising at least one portion sensitive to chemical and/or physical variations of fluids present in correspondence with a first and a second opposed active surface thereof, the first surface of the MEMS device leaving the first active surface exposed and the second surface being provided with a further opening which exposes said second opposed active surface, the electronic device being characterized in that the first surface of the MEMS device faces the substrate and is spaced therefrom by a predetermined distance, the sensitive portion being aligned to the passing opening of the substrate, and in that it also comprises a protective package, which incorporates at least partially the MEMS device and the substrate so as to leave the first and second opposed active surfaces exposed respectively through the passing opening of the substrate and the further opening of the second surface. | 2009-11-12 |
20090278216 | MEMS sensor - An MEMS sensor is described. The MEMS sensor may include a substrate, a lower thin film provided in contact with a surface of the substrate, and an upper thin film opposed to the lower thin film at an interval on the side opposite to the substrate. | 2009-11-12 |
20090278217 | MEMS DEVICE - A micro-electrical-mechanical device comprises: a transducer arrangement having at least a membrane being mounted with respect to a substrate; and electrical interface means for relating electrical signals to movement of the membrane; in which the transducer arrangement comprises stress alleviating formations which at least partially decouple the membrane from expansion or contraction of the substrate. | 2009-11-12 |
20090278218 | Magnetoresistive element - A magnetoresistive element is disclosed, wherein the magnetoresistive element is composed of a synthetic anti-ferromagnetic (SAF) structure that may include a first pinned layer, an intermediate layer, and a second pinned layer; and a Cr layer between the first pinned layer and the intermediate layer and/or the second pinned layer and the intermediate layer. | 2009-11-12 |
20090278219 | MICROELECTRONIC DEVICES HAVING AN EMI SHIELD AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic devices having an EMI shield, systems including such microelectronic devices, and methods for manufacturing such microelectronic devices. One embodiment of a microelectronic device comprises an imaging system comprising a microelectronic die, an optics assembly, and an electromagnetic interference (EMI) shield. The microelectronic die includes an image sensor, processing components electrically coupled to the image sensor, a first interconnect electrically isolated from the processing components, and a second interconnect electrically coupled to the processing components. The optics assembly is aligned with the image sensor, and the electromagnetic interference (EMI) shield is between the optics assembly and the processing components. The EMI shield is electrically coupled to the first interconnect. | 2009-11-12 |
20090278220 | Image sensor and fabricting method thereof - An image sensor includes the steps of forming a sublayer including a photodiode, a transistor and a metal line on a substrate, forming a pattern layer on the sublayer to be overlapped with the photodiode and to having a curved surface, and forming a combined color filter and microlens on the pattern layer to have a curved surface. | 2009-11-12 |
20090278221 | SEMICONDUCTOR DEVICE - A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made of tantalum or a tantalum compound) is formed on the surface of the multilayer wiring area to attenuate incident light on circuit element area. | 2009-11-12 |
20090278222 | INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE - Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit. | 2009-11-12 |
20090278223 | Process for Producing Siliceous Film and Substrate With The Siliceous Film Produced by The Process - An objective of the present invention is to provide a process for producing a siliceous film which has a uniform quality independently of sites and in both the inside and outside of the grooves and is free from voids and cracks in the inside of the grooves. A substrate with the siliceous film can be produced by forming an insulating film having a high hydrogen content on a surface of a silicon substrate having concavoconvexes, then coating a composition containing a polysilazane compound on the substrate, and heating the coated substrate to convert the polysilazane compound to a silicon dioxide film. | 2009-11-12 |
20090278224 | METHODS OF FORMING AN AMORPHOUS SILICON THIN FILM - A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction chamber during a first time period; applying radio frequency power to the reaction chamber at least partly during the first time period; stopping supplying of the silicon precursor and applying of the radio frequency power during a second time period between the first time period and an immediately subsequent deposition cycle; and supplying hydrogen plasma to the reaction chamber during a third time period between the second time period and the immediately subsequent deposition cycle. The method allows formation of an amorphous silicon film having an excellent step-coverage and a low roughness at a relatively low deposition temperature. | 2009-11-12 |
20090278225 | SEMICONDUCTOR DEVICE AND METHOD FOR ISOLATING THE SAME - The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches. | 2009-11-12 |
20090278226 | STRUCTURE FOR CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY AND STRUCTURE THEREOF - The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is formed at an interface of the SIO within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material. | 2009-11-12 |
20090278227 | ISOLATION TRENCH STRUCTURE - Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that are each substantially perpendicular to the surface of the substrate. A second isolation trench portion includes a second pair of sidewalls within the substrate that are each angled obliquely with respect to the surface of the substrate, where the second isolation trench portion has a separation between the second pair of sidewalls that decreases as a distance from the first isolation trench portion increases. A third isolation trench portion includes a third pair of sidewalls within the substrate that are each substantially perpendicular to the surface of the substrate. | 2009-11-12 |
20090278228 | DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure. | 2009-11-12 |
20090278229 | EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS - A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element. | 2009-11-12 |
20090278230 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the surface of the substrate, the interconnect is positioned on the surface of the insulating interlayer, the through-electrode extends through the substrate and the insulating interlayer, from the back surface of the former to the surface of the latter, one end of which is connected to the interconnect, and the bump is provided on the back surface side of the substrate, and connected to the other end of the through-electrode. | 2009-11-12 |