45th week of 2021 patent applcation highlights part 56 |
Patent application number | Title | Published |
20210351048 | HEATER LIFT ASSEMBLY SPRING DAMPER - In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp. | 2021-11-11 |
20210351049 | DUAL-SIDED MOLDING FOR ENCAPSULATING ELECTRONIC DEVICES - A molding system for molding electronic components mounted on first and second sides of a substrate has a molding cavity onto which the substrate is locatable for molding. The molding cavity has a first section covering a molding portion of the first side of the substrate, and a second section covering a molding portion of the second side of the substrate. First and second pots have plungers for compressing molding compound placed therein. First and second runners connect the first and second pots to the first and second sections of the molding cavity for introducing the molding compound onto both sides of the substrate. In particular, the runners extend at least from an edge of the substrate along both sides of the substrate to the molding cavity. | 2021-11-11 |
20210351050 | FRONT SURFACE AND BACK SURFACE ORIENTATION DETECTION OF TRANSPARENT SUBSTRATE - A system includes a substrate support on which to receive a transparent substrate, a non-contact sensor adapted to detect and image a dot pattern etched on a front surface of the transparent substrate, and a processing device attached to the non-contact sensor. The processing device may determine, using imaging data from the non-contact sensor, an orientation of a right-angled edge of the dot pattern. The processing device may determine, based on the orientation of the right-angled edge, whether a front surface of the transparent substrate is facing up or facing down. The processing device may also direct a robot to transfer the transparent substrate to a processing chamber dependent on whether the front surface of the transparent substrate is facing up or facing down. | 2021-11-11 |
20210351051 | METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATE - A method for controlling a temperature of a substrate support assembly is provided. A first direct current (DC) power is supplied to a heating element embedded in a zone of the substrate support assembly included in a processing chamber. A voltage is measured across the heating element. Similarly, a current is measured through the heating element. A temperature of the zone of the substrate support assembly is determined based on the voltage across the heating element and the current through the heating element. A temperature difference between the determined temperature of the zone and a target temperature for the zone is determined. A second DC power to deliver to the heating element is determined to achieve the target temperature based at least in part on the temperature difference. The second DC power is supplied to the heating element to cause the temperature of the zone to be modified to the target temperature. | 2021-11-11 |
20210351052 | LOAD PORT - A load port adapted for wafer cassettes of different sizes detects storage states of wafers stored in the wafer cassettes. The load port includes a body, a positioning mechanism, a sensing mechanism, and a detecting mechanism. The body has a carrier base. The positioning mechanism is disposed on the body and has a positioning unit disposed on the carrier base, a hooking unit, and a limiting unit. The hooking unit is disposed in the body and has a driving assembly and a hooking element. The driving assembly is disposed in the body. The hooking element is mounted to the driving assembly. The sensing mechanism is disposed on the carrier base. The detecting mechanism is disposed on the body, detects the storage states of wafers stored in the wafer cassette, and has a first detecting assembly and a second detecting assembly spaced apart from each other. | 2021-11-11 |
20210351053 | METHOD FOR DIE-LEVEL UNIQUE AUTHENTICATION AND SERIALIZATION OF SEMICONDUCTOR DEVICES USING ELECTRICAL AND OPTICAL MARKING - A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature. | 2021-11-11 |
20210351054 | METHOD FOR CONTAINING A RETICLE IN A POD - A method for containing a reticle in a pod is provided. The method includes opening the pod such that a pressing element retained movably on the pod by a limiting cap moves to a first position, wherein a shoulder part of the pressing element between a pressure receiving part and a pressing part of the pressing element is spaced from the limiting cap. The method further includes placing the reticle in the pod such that the reticle is pressed by the pressing element. | 2021-11-11 |
20210351055 | TRANSPORT MECHANISM FOR WAFERS OF DIFFERENT SIZES AND TYPES - A transport mechanism for wafers of different sizes and types includes a carrier device and a manipulator device. The carrier device has a mounting rack, multiple supporting units, and multiple carrier units. The multiple supporting units are mounted on the mounting rack, and each supporting unit has two supporting bases. Each one of the multiple carrier units has two carrier plates. Each one of the two carrier plates has a connecting rod and two positioning rods. The two positioning rods are respectively located on two sides of the connecting rod. The manipulator device has a driving unit and a manipulator unit. The manipulator unit is mounted on the driving unit and has two arms. Each one of the two arms has a connecting socket and two positioning sockets. The two positioning sockets are respectively located beside the connecting socket. The locking element is movably mounted to the arm. | 2021-11-11 |
20210351056 | MOUNTING DEVICE AND MOUNTING METHOD - A mounting device comprises a recognition mechanism and a control unit. The recognition mechanism recognizes a chip recognition mark and a substrate recognition mark through a mounting head and from above the mounting head and is movable in an in-plane direction of a substrate surface of a substrate. The control unit is connected to the recognition mechanism, calculates an amount of misalignment between a chip component and the substrate from position information about the chip recognition mark and the substrate recognition mark obtained from the recognition mechanism, and performs positioning by driving the mounting head and/or the substrate stage according to the amount of misalignment. The recognition mechanism has a chip recognition sensor for recognizing the chip recognition mark and a substrate recognition sensor for recognizing the substrate recognition mark provided independently so that focal positions thereof are different via a common optical axis path. | 2021-11-11 |
20210351057 | MOUNTING DEVICE AND MOUNTING METHOD - a mounting device and a mounting method is provided with which, after lowering a mounting head holding a chip component in a direction perpendicular to a substrate to bring the chip component into close contact with the substrate subsequent to positioning the chip component and the substrate, a control unit causes a recognition mechanism to start a parallel recognition operation of a chip recognition mark and a substrate recognition mark and recognize the chip recognition mark and the substrate recognition mark through the mounting head in a mounted state in which the chip component is in close contact with the substrate, and calculates mounting position accuracy of the chip component and the substrate. | 2021-11-11 |
20210351058 | MULTI-ZONE PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION APPARATUS AND METHODS FOR OPERATING THE SAME - An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control. | 2021-11-11 |
20210351059 | MULTI-ZONE PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION APPARATUS AND METHODS FOR OPERATING THE SAME - An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control. | 2021-11-11 |
20210351060 | Apparatus and Methods for Real-Time Wafer Chucking Detection - Substrate supports, substrate support assemblies and methods of using the substrate supports are described. The substrate support has a support surface with at least two electrodes and a plurality of purge channels bounded by a seal band. A power supply connected to the electrodes configured as an electrostatic chuck. A capacitance of the substrate is measured while on the substrate support to determine the chucking state of the substrate. | 2021-11-11 |
20210351061 | ELECTROSTATIC CHUCK HAVING A GAS FLOW FEATURE, AND RELATED METHODS - Described are electrostatic chucks designed for use in supporting a workpiece during a workpiece processing step, the electrostatic chuck including a gas flow system. | 2021-11-11 |
20210351062 | VACUUM WAFER CHUCK FOR MANUFACTURING SEMICONDUCTOR DEVICES - Disclosed is a substrate displacing assembly so as to improve its durability during a semiconductor processing. In one embodiment, a semiconductor manufacturing system, includes, a substrate holder, wherein the substrate holder is configured with a plurality of pins; and a substrate displacing assembly for displacing a substrate on the substrate holder in a first direction perpendicular to the top surface of the substrate holder through the plurality of pins, wherein the substrate displacing assembly comprises a pair of load forks, a coupler and a driving shaft, wherein the pair of load forks comprises a fork region and a base region, wherein the coupler is mechanically coupled to the base region through at least one first joining screw extending in the first direction, wherein the coupler is further mechanically coupled to the driving shaft through a second joining screw extending in the first direction. | 2021-11-11 |
20210351063 | IN-SITU APPARATUS FOR SEMICONDUCTOR PROCESS MODULE - Aspects of the present disclosure generally relate to apparatuses and methods for edge ring replacement in processing chambers. In one aspect, a carrier for supporting an edge ring is disclosed. In other aspects, robot blades for supporting a carrier are disclosed. In another aspect, a support structure for supporting a carrier in a degassing chamber is disclosed. In another aspect, a method of transferring an edge ring on a carrier is disclosed. | 2021-11-11 |
20210351064 | PLANARIZATION CONTROLLABILITY FOR INTERCONNECT STRUCTURES - A method for fabricating a semiconductor device includes selectively etching one or more of a plurality of conductive layers within a metallization level to obtain one or more recessed conductive layers each corresponding to a conductive line lacking a via disposed thereon and at least one conductive line having a via disposed thereon. The metallization level is disposed on a base structure including one or more underlying devices. The method further includes forming a pair of planarization stop layers on each of the one or more recessed conductive layers to a height of the via, and forming a plurality of interlevel dielectric (ILD) layers having a uniform height across the metallization level using the one or more pairs of planarization stop layers. | 2021-11-11 |
20210351065 | INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER - An interconnection structure comprises a first metal structure, a first dielectric layer, a second dielectric layer, a second metal structure, a first protective layer, and a second protective layer. The first dielectric layer is over the first metal structure. The second dielectric layer is over the first dielectric layer. The second metal structure has an upper portion extending through the second dielectric layer, and a lower portion extending through the first dielectric layer. The upper portion has a width greater than a width of the lower portion. The first protective layer spaces the first dielectric layer apart from the lower portion of the second metal structure. The second protective layer spaces the second dielectric layer apart from the upper portion of the second metal structure, and has a top width greater than a top width of the first protective layer. | 2021-11-11 |
20210351066 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate as a depth of the first trench is greater than a depth of the second trench; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench. | 2021-11-11 |
20210351067 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING - A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer. | 2021-11-11 |
20210351068 | SINGLE DIFFUSION CUT FOR GATE STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions. | 2021-11-11 |
20210351069 | METHODS FOR VARIABLE ETCH DEPTHS - Methods of producing grating materials with variable height fins are provided. In one example, a method may include providing a mask layer atop a substrate, the mask layer including a first opening over a first processing area and a second opening over a second processing area. The method may further include etching the substrate to recess the first and second processing areas, forming a grating material over the substrate, and etching the grating material in the first and second processing areas to form a plurality of structures oriented at a non-zero angle with respect to a vertical extending from a top surface of the substrate. | 2021-11-11 |
20210351070 | SEMICONDUCTOR DEVICE INCLUDING POLYSILICON STRUCTURES AND METHOD OF MAKING - A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size. | 2021-11-11 |
20210351071 | METHOD OF TUNING FILM PROPERTIES OF METAL NITRIDE USING PLASMA - A method for forming a metal nitride layer on a substrate includes exposing a substrate having features formed therein to a first deposition gas mixture including metal source material in a processing chamber to deposit metal source material in the features, supplying a first purge gas mixture into the processing chamber to remove excess metal source material and reaction byproducts from the processing chamber, exposing the substrate to a second deposition gas mixture including a nitride source compound in the processing chamber to form no more than one monolayer of metal nitride, supplying a second purge gas mixture into the processing chamber to remove excess nitride source compound and reaction byproducts from the processing chamber, and exposing the substrate to plasma using a microwave plasma source. | 2021-11-11 |
20210351072 | DOPING OF METAL BARRIER LAYERS - Described are methods for doping barrier layers such as tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), niobium (Nb), niobium nitride (NbN), manganese (Mn), manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), and molybdenum nitride (MoN), and the like. Dopants may include one or more of one or more of ruthenium (Ru), manganese (Mn), niobium (Nb), cobalt (Co), vanadium (V), copper (Cu), aluminum (Al), carbon (C), oxygen (O), silicon (Si), molybdenum (Mo), and the like. The doped barrier layer provides improved adhesion at a thickness of less than about 15 Å. | 2021-11-11 |
20210351073 | CONTACTS AND LINERS HAVING MULTI-SEGMENTED PROTECTIVE CAPS - Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment. | 2021-11-11 |
20210351074 | SEAMLESS GAP FILL - Methods for filling a substrate feature with a seamless gap fill are described. Methods comprise forming a metal film a substrate surface, the sidewalls and the bottom surface of a feature, the metal film having a void located within the width of the feature; treating the metal film with a plasma; and annealing the metal film to remove the void. | 2021-11-11 |
20210351075 | System and Method for Removing Scalloping and Tapering Effects in High Aspect Ratio Through-Silicon Vias of Wafers - A method for manufacturing vias in a silicon wafer, the silicon wafer having a <110> crystal orientation, and having a <111> plane that is perpendicular to a surface of the wafer, tilted by 35.26°, the method comprising the steps of providing a mask having a rhomboidal-shaped opening onto a surface of the silicon wafer, such that edges of the rhomboidal-shaped opening line up with a <111> plane of a crystalline structure of the silicon wafer, etching a hole in the silicon wafer at the rhomboidal-shaped opening, and polishing the hole after the etching by a anisotropic etching. | 2021-11-11 |
20210351076 | Wafer Level Package Structure and Method of Forming Same - An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure. | 2021-11-11 |
20210351077 | Methods for Processing a Wide Band Gap Semiconductor Wafer Using a Support Layer and Methods for Forming a Plurality of Thin Wide Band Gap Semiconductor Wafers Using Support Layers - A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer. | 2021-11-11 |
20210351078 | VERTICALLY STACKED TRANSISTORS IN A FIN - An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin. | 2021-11-11 |
20210351079 | METHOD FOR FORMING LONG CHANNEL BACK-SIDE POWER RAIL DEVICE - A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench. | 2021-11-11 |
20210351080 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area. | 2021-11-11 |
20210351081 | FinFET Device and Method - A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin. | 2021-11-11 |
20210351082 | VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH DUAL LINER BOTTOM SPACER - Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer. | 2021-11-11 |
20210351083 | Method of Manufacturing a Semiconductor Device - A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH | 2021-11-11 |
20210351084 | SEMICONDUCTOR DEVICE AND METHOD - In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region. | 2021-11-11 |
20210351085 | SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING - The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode. | 2021-11-11 |
20210351086 | INTEGRATED CIRCUIT STRUCTURE - An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure. | 2021-11-11 |
20210351087 | Integrated Assemblies having Conductive Material Along Three of Four Sides Around Active Regions, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies. | 2021-11-11 |
20210351088 | METHOD FOR NON-DESTRUCTIVE INSPECTION OF CELL ETCH REDEPOSITION - Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score. | 2021-11-11 |
20210351089 | Substrate with Cut Semiconductor Pieces Having Measurement Test Structures for Semiconductor Metrology - A device used for semiconductor metrology includes a substrate and a plurality of pieces from one or more semiconductor wafers. Each piece of the plurality of pieces is bonded to the substrate at a respective position on the substrate. Each piece of the plurality of pieces includes a respective instance of a measurement test structure and an alignment mark. Each piece of the plurality of pieces has a known location from the one or more semiconductor wafers. | 2021-11-11 |
20210351090 | PID TEST STRUCTURE AND SEMICONDUCTOR TEST STRUCTURE - Provided is a Plasma Induced Damage (PID) test structure and a semiconductor test structure, including: a gate structure, including a gate layer; a covering dielectric layer, located on a surface of the gate layer; a metal layer structure, located on a surface of the covering dielectric layer, the metal layer structure including at least one metal layer; and an extraction electrode, electrically connected with the gate layer via a conductive structure. | 2021-11-11 |
20210351091 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the boundary region. | 2021-11-11 |
20210351092 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a heatsink plate, a substrate disposed on the heatsink plate, a circuit pattern disposed on the substrate, a semiconductor chip disposed on the circuit pattern, a case fixed to the heatsink plate and surrounding an outer perimeter of the substrate, a terminal attached to the case, and a wire configured to electrically connect the terminal to the circuit pattern or to the semiconductor chip. In a plan view as viewed in the thickness direction of the heatsink plate, a portion of the circuit pattern overlaps the terminal. | 2021-11-11 |
20210351093 | MODULE - A module includes a substrate including a first main surface, a columnar conductor arranged on the first main surface, a first sealing resin that seals at least the columnar conductor and the first main surface while exposing a first end surface of the columnar conductor, a conductive film connected to the columnar conductor and arranged to extend laterally from the first end surface, a resin sheet arranged to cover at least the conductive film, a conductor via provided in the resin sheet and having one end connected to the conductive film, and a conductor pattern arranged on a surface of the resin sheet on a side far from the substrate to be connected to the other end of the conductor via and being larger in area than the first end surface. | 2021-11-11 |
20210351094 | PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A package substrate that prevents breakage of a core substrate is provided. A package substrate includes a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed from an outer peripheral portion of the insulating layer, and the insulating layer being chamfered. | 2021-11-11 |
20210351095 | III-V COMPOUND SEMICONDUCTOR DIES WITH STRESS-TREATED INACTIVE SURFACES TO AVOID PACKAGING-INDUCED FRACTURES, AND RELATED METHODS - Before a semiconductor die of a brittle compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing. | 2021-11-11 |
20210351096 | SELECTIVE MOLD PLACEMENT ON INTEGRATED CIRCUIT (IC) PACKAGES AND METHODS OF FABRICATING - An integrated circuit (IC) package that is to be incorporated into a computing device may include a metallization structure with circuits and/or other elements such as capacitors or inductors thereon. Pads for input/output (I/O) (or other) purposes may also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow mold material to be placed over the circuits and/or other elements in readily-customizable configurations so as to allow placement of the I/O pads in any desired location on the metallization structure. Specifically, before the mold material is applied to the metallization structure, a mask material such as tape may be applied to portions of the metallization structure that contain I/O pads or otherwise have reasons to not have mold material thereon. The mold material is applied, and the mask material is removed, taking unwanted mold material with the mask material. | 2021-11-11 |
20210351097 | METHOD FOR FABRICATING ELECTRONIC STRUCTURE WITH CONDUCTIVE ELEMENTS ARRANGED FOR HEATING PROCESS - An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions. | 2021-11-11 |
20210351098 | Packaged Semiconductor Device With Multilayer Stress Buffer - In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound. | 2021-11-11 |
20210351099 | SEMICONDUCTOR DEVICE PACKAGE WITH CLIP INTERCONNECT AND DUAL SIDE COOLING - In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead. | 2021-11-11 |
20210351100 | ELECTRONIC POWER MODULE - An electronic power module includes at least a semiconductor chip having at least one electronic power component and two metal layers between which the semiconductor chip is directly secured. At least a first of the two metal layers forms a redistribution layer having several distinct metal portions, each electrically connected to at least one electrical contact pad of the semiconductor chip, and/or at least one second of the two metal layers includes at least one first structured face arranged against the semiconductor chip and having at least one pad formed in a part of its thickness. | 2021-11-11 |
20210351101 | HIGH POWER MODULE PACKAGE STRUCTURES - A method includes disposing a semiconductor die between a first high voltage isolation carrier and a second high voltage isolation carrier, disposing a first molding material in a space between the semiconductor die and the first high voltage isolation carrier, and disposing a conductive spacer between the semiconductor die and the second high voltage isolation carrier. The method further includes encapsulating the first molding material and the conductive spacer with a second molding material. | 2021-11-11 |
20210351102 | HEAT RADIATION MATERIAL, METHOD FOR PRODUCING A HEAT RADIATION MATERIAL, COMPOSITION, AND HEAT-GENERATING ELEMENT - This heat radiation material contains metal particles and a resin, and has a structure in which the metal particles are localized in at least one surface side. | 2021-11-11 |
20210351103 | SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING SAME - Provided is a semiconductor package. The semiconductor package comprises a semiconductor chip on a substrate, a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip and a thermoelectric module configured to convert heat released from the semiconductor chip into an auxiliary power, and configured to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in the external voltage. | 2021-11-11 |
20210351104 | MECHANICAL ARCHITECTURE FOR A MULTI-CHIP MODULE - Described is a multi-chip module that may include a Redistribution Layer (RDL) substrate having Integrated Circuit (IC) dies mounted to a first surface of the RDL substrate. A second plurality of IC dies may be mounted to an opposite second surface. A plurality of sockets can be mounted upon the second plurality of IC dies and a cold plate then mounted to the first plurality of IC dies. The mounting structure may include socket frames coupled to the plurality of sockets. | 2021-11-11 |
20210351105 | INTEGRATED CIRCUITS AND METHODS FOR FORMING INTEGRATED CIRCUITS - An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits. | 2021-11-11 |
20210351106 | DIRECTLY IMPINGING PRESSURE MODULATED SPRAY COOLING AND METHODS OF TARGET TEMPERATURE CONTROL - Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate. | 2021-11-11 |
20210351107 | POWER ELECTRONICS FOR AN ELECTRICAL MACHINE, DRIVETRAIN, MOTOR VEHICLE - An inverter ( | 2021-11-11 |
20210351108 | VACUUM MODULATED TWO PHASE COOLING LOOP EFFICIENCY AND PARALLELISM ENHANCEMENT - Embodiments disclosed herein include a temperature control system. In an embodiment, the temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a plurality of fluid lines between the pump and the spray chamber, where individual ones of the plurality of fluid lines are configured to provide the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber. | 2021-11-11 |
20210351109 | THREE-DIMENSIONAL MEMORY DEVICE WITH A DIELECTRIC ISOLATION SPACER AND METHODS OF FORMING THE SAME - An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures extending through the alternating stack are formed. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer and the backside contact via structure are formed within the backside trench. A dielectric isolation trench is formed by removing a peripheral portion of an upper region of the backside contact via structure and an upper portion of the insulating spacer. A dielectric isolation spacer is formed in the dielectric isolation trench to prevent an electrical short between an upper portion of the backside contact via structure and the electrically conductive layers. | 2021-11-11 |
20210351110 | 3D IC POWER GRID - A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV. | 2021-11-11 |
20210351111 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Curable material layer is coated on surface of first die. First die includes first substrate and first contact pad. Second die is bonded to first die. Second die includes second substrate and second contact pad. Second contact pad is located on second substrate, at an active surface of second die. Bonding the second die to the first die includes disposing second die with the active surface closer to the curable material layer and curing the curable material layer. A through die hole is etched in the second substrate from a backside surface of the second substrate opposite to the active surface. The through die hole further extends through the cured material layer, is encircled by the second contact pad, and exposes the first contact pad. A conductive material is disposed in the through die hole. The conductive material electrically connects the first contact pad to the second contact pad. | 2021-11-11 |
20210351112 | SEMICONDUCTOR DEVICE INCLUDING THROUGH SUBSTRATE VIAS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via. | 2021-11-11 |
20210351113 | Integrated Circuit Having Die Attach Materials with Channels and Process of Implementing the Same - A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material. | 2021-11-11 |
20210351114 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor device; a lead frame; a built-in package including an insulated driver having a multi-chip configuration and driving the semiconductor device; a wire connecting the built-in package to the semiconductor device; and a resin sealing the semiconductor device, the lead frame, the built-in package, and the wire, wherein the built-in package is directly joined to the lead frame. | 2021-11-11 |
20210351115 | ELECTRONIC DEVICE - An electronic device includes a mounting substrate; a package arranged facing the mounting substrate; a plurality of first pads arranged on a facing surface facing the mounting substrate along a long side of the facing surface in the package; a plurality of second pads arranged on the facing surface at respective corners of the facing surface; a plurality of first lands provided on the mounting substrate and electrically bonded to the plurality of first pads, respectively facing the plurality of first pads; and a plurality of second lands provided on the mounting substrate and electrically bonded to the plurality of second pads, respectively facing the plurality of second pads. | 2021-11-11 |
20210351116 | INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES - Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed. | 2021-11-11 |
20210351117 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package includes forming an encapsulated semiconductor device and forming a redistribution structure over the encapsulated semiconductor device, where the encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. Forming the redistribution structure includes forming a first dielectric layer on the encapsulated semiconductor device, and forming a first redistribution circuit layer on the first dielectric layer by a plating process carried out at a current density of substantially 4˜6 amperes per square decimeter, where the first dielectric layer comprises a first via opening. An upper surface of the first redistribution circuit layer filling the first via opening is substantially coplanar with an upper surface of the rest of the first redistribution circuit layer. | 2021-11-11 |
20210351118 | Fan-Out Package with Controllable Standoff - A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure. | 2021-11-11 |
20210351119 | FLIP-CHIP FILM - A flip-chip film includes a substrate and a plurality of flip-chip film units. The plurality of flip-chip film units are disposed on the substrate, and each of the flip-chip film units includes a plurality of first metal traces arranged at intervals. A punch cut is defined between the first metal traces of two adjacent flip-chip film units. | 2021-11-11 |
20210351120 | POWER MODULE - A power module comprises a multi-layer base material; a first wiring line pattern provided on a surface on one side of the multi-layer base material; a second wiring line pattern provided on a surface on another side facing the surface of the one side of the multi-layer base material; a first switching element including a first terminal and a second terminal, the first switching element provided on the first wiring line pattern; and a first circuit element provided on any one of the first wiring line pattern and the second wiring line pattern, wherein a direction of a current path passing in a region between the first circuit element and the first switching element intersects with a direction of a current path passing under a region of the first switching element. | 2021-11-11 |
20210351121 | Packaged Transistor with Channeled Die Attach Materials and Process of Implementing the Same - A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material. | 2021-11-11 |
20210351122 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package including a redistribution substrate, a connection substrate on the redistribution substrate, the connection substrate having an opening that penetrates the connection substrate, a semiconductor chip in the opening of the connection substrate, and a molding layer that covers the semiconductor chip and the connection substrate, and fills a space between the semiconductor chip and the connection substrate, the connection substrate includes a base layer, a plurality of vias that vertically penetrate the base layer, a plurality of first patterns on a top surface of the base layer and connected to the plurality of vias, and a plurality of second patterns on a bottom surface of the base layer and connected to the plurality of vias, an extension of the molding layer extends into a plurality of holes that are spaced apart from the plurality of vias and are formed to vertically penetrate the base layer. | 2021-11-11 |
20210351123 | SEMICONDUCTOR DEVICE - A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer. | 2021-11-11 |
20210351124 | VIA ARRAY DESIGN FOR MULTI-LAYER REDISTRIBUTION CIRCUIT STRUCTURE - An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias. | 2021-11-11 |
20210351125 | MICROELECTRONIC DEVICES WITH SELF-ALIGNED INTERCONNECTS, AND RELATED METHODS - Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertically overlapping areas of the lower conductive structure and the upper conductive structure, where such overlapping areas coincide with the opening through the dielectric material. | 2021-11-11 |
20210351126 | INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME - Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line. | 2021-11-11 |
20210351127 | Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed. | 2021-11-11 |
20210351128 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes an insulating film passing through a dummy source structure, a first dummy stack extending to overlap the insulating film and the dummy source structure, and including a depression overlapping the insulating film, a resistive film overlapping the depression of the first dummy stack, and a second dummy stack disposed on the first dummy stack to cover the resistive film. | 2021-11-11 |
20210351129 | SEMICONDUCTOR STRUCTURE AND CONTROLLING METHOD THEREOF - The present disclosure provides a semiconductor structure employing an antifuse structure and a controlling method of the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a transistor and an antifuse structure. The transistor is disposed on the semiconductor substrate. The antifuse structure is disposed on the semiconductor substrate and adjacent to the transistor. The antifuse structure includes a first conductive portion, a fusible portion and a second conductive portion. The first conductive portion is disposed in the semiconductor substrate. The fusible portion is disposed on the first conductive portion. The second conductive portion is disposed on the fusible portion. The antifuse structure encloses the transistor in a top view. | 2021-11-11 |
20210351130 | REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE - A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width. | 2021-11-11 |
20210351131 | MEMORY DEVICE - A memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction. | 2021-11-11 |
20210351132 | POWER DISTRIBUTION NETWORK FOR 3D LOGIC AND MEMORY - A semiconductor device includes a transistor stack. The transistor stack has a plurality of transistors that are stacked over a substrate. Each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors. The semiconductor device also includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack, and are electrically coupled to the transistor stack. | 2021-11-11 |
20210351133 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between. the main circuit region and the scribe region. | 2021-11-11 |
20210351134 | STRUCTURE FOR STANDARD LOGIC PERFORMANCE IMPROVEMENT HAVING A BACK-SIDE THROUGH-SUBSTRATE-VIA - In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnects within a first inter-level dielectric (ILD) structure disposed along a first side of a first substrate. A conductive pad is arranged along a second side of the first substrate. A first through-substrate-via (TSV) physically contacts an interconnect of the first plurality of interconnects and a first surface of the conductive pad. A second plurality of interconnects are within a second ILD structure disposed on a second substrate. A second TSV extends from an interconnect of the second plurality of interconnects to through the second substrate. A conductive bump is arranged on a second surface of the conductive pad opposing the first surface. The second TSV has a greater width than the first TSV. | 2021-11-11 |
20210351135 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the second level includes at least one voltage regulator. | 2021-11-11 |
20210351136 | Binary Metal Liner Layers - Described are microelectronic device comprising a dielectric layer formed on a substrate, a feature | 2021-11-11 |
20210351137 | Semiconductor Package With EMI Shield and Fabricating Method Thereof - A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid. | 2021-11-11 |
20210351138 | DISPLAY PANEL - The invention discloses a display panel, comprising: a first substrate including a display region and a peripheral region adjacent to each other; a plurality of pixel units disposed on the first substrate and located in the display region; a planarization layer disposed on the first substrate and located in the display region and the peripheral region; and an organic passivation layer disposed on the first substrate, covering the planarization layer and located in the display region and the peripheral region; wherein the planarization layer further comprises a first region planarization layer located in the display region, and a second region planarization layer located in the peripheral region, the first region planarization layer is formed with a first sidewall in a boundary region between the display region and the peripheral region, and a height of the first sidewall is greater than a height of the first region planarization layer. The invention can effectively reduce probability of the organic passivation layer on sidewalls of the passivation layers, and can better avoid moisture from penetrating the organic material into the display panel. | 2021-11-11 |
20210351139 | Semiconductor Device and Method of Forming Same - A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure. | 2021-11-11 |
20210351140 | SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP STRUCTURE AND METHOD FOR PREPARING THE SAME - The present disclosure provides a semiconductor device structure with an air gap structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive contact and a second conductive contact disposed over a semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive contact and the second conductive contact, and a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer. The first dielectric layer is separated from the semiconductor substrate by a first air gap structure, the first dielectric layer is separated from the second dielectric layer by a second air gap structure, and the air gap structures reduce capacitive coupling between conductive features. | 2021-11-11 |
20210351141 | RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING ISOLATION STRUCTURES - A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure. | 2021-11-11 |
20210351142 | BOND PAD WITH ENHANCED RELIABILITY - The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a bond pad layer onto a dielectric structure formed over a substrate. The dielectric structure surrounds a plurality of interconnect layers. A protective layer is formed onto the bond pad layer, and the bond pad layer and the protective layer are patterned to define a bond pad covered by the protective layer. One or more upper passivation layers are formed over the protective layer. A dry etching process is performed to form an opening extending through the one or more upper passivation layers to the protective layer. A wet etching process is performed to remove a part of the protective layer and expose an upper surface of the bond pad. | 2021-11-11 |
20210351143 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer. | 2021-11-11 |
20210351144 | SEMICONDUCTOR DEVICE STRUCTURE WITH BONDING PAD AND METHOD FOR FORMING THE SAME - A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad. | 2021-11-11 |
20210351145 | PACKAGE COMPRISING MULTI-LEVEL VERTICALLY STACKED REDISTRIBUTION PORTIONS - A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion. | 2021-11-11 |
20210351146 | MULTILAYER ELECTRICAL CONDUCTORS FOR TRANSFER PRINTING - An electrical conductor structure comprises a substrate and an electrical conductor disposed on or in the substrate. The electrical conductor comprises a first layer and a second layer disposed on a side of the first layer opposite the substrate. The first layer comprises a first electrical conductor that forms a non-conductive layer on a surface of the first electrical conductor when exposed to air and the second layer comprising a second electrical conductor that does not form a non-conductive layer on a surface of the second electrical conductor when exposed to air. A component comprises a connection post that is electrically connected to the second layer and the electrical conductor. The first and second layers can be inorganic. The first layer can comprise a metal such as aluminum and the second layer can comprise an electrically conductive metal oxide such as indium tin oxide. | 2021-11-11 |
20210351147 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film. | 2021-11-11 |