45th week of 2010 patent applcation highlights part 58 |
Patent application number | Title | Published |
20100287299 | CRISSCROSS CANCELLATION PROTOCOL - Technologies, systems, and methods for ordered message delivery that avoid message races or crisscrosses between communicating nodes. For example, if Node A sends message | 2010-11-11 |
20100287300 | CRISSCROSS CANCELLATION PROTOCOL - Technologies, systems, and methods for ordered message delivery that avoid message races or crisscrosses between communicating nodes. For example, if Node A sends message 3 towards Node B and, shortly thereafter, Node B sends message X to Node A, Node A would like to know whether or not message X reflects Node B's state after receiving message 3. If Node B received message 3 prior to sending message X, then proper state may be maintained between the nodes. But if messages 3 and X crisscrossed, or if message 3 was never properly received by Node B, then the state between the nodes may be corrupt. Technologies, systems, and methods are provided to avoid such corruption. | 2010-11-11 |
20100287301 | Communication system and method - A method, system and program for use in a communication system. The method comprises: interacting with a document-browser application executed on a first user terminal, the document-browser being configured to retrieve an electronic document from a first storage unit and display it on a screen, wherein the interaction comprises identifying a sequence of numeric or alphanumeric characters in the displayed document as being for use in initiating communication with a second user terminal over the communication system. The method further comprises: querying a second storage unit; and based on that query, selecting a display configuration for the identified sequence of characters from a plurality of available display configurations. The interaction further comprises modifying the display of a portion of the document so as to display the identified sequence of characters or information associated therewith in dependence on the determined display configuration. | 2010-11-11 |
20100287302 | METHOD FOR MANAGING A DATA CONNECTION AND NETWORK COMPONENT - The invention relates to a method for managing a data connection between a sending network component and a receiving network component via a network, and a network component, the method comprising the following steps: sending an initiating message to the receiving network component by the sending network component, to initiate a data connection between the sending network component and the receiving network component; receiving the initiating message by the receiving network component; sending further messages to the receiving network component by the sending network component; receiving the further messages by the receiving network component calculating a transmission delay for at least one of the further messages received by the receiving network component; estimating optimal transmission parameters for transmitting messages between the sending network component and the receiving network component based on the calculated transmission delay, wherein estimating of the optimal transmission parameters substantially excludes the initiating message; and sending subsequent messages to the receiving network component by the sending network component at the estimated optimal transmission parameters. | 2010-11-11 |
20100287303 | NETWORK TRAFFIC RATE LIMITING SYSTEM AND METHOD - A system and method is provided for rate limiting network traffic flow of an untrusted application. A master module in a server environment manages network traffic flow restrictions. A slave module executes client applications in the server environment. A services module in the server environment executes a trusted application to validate the client application to the master module. A traffic restriction module on the master module sets network traffic restrictions when validation has not been received for the client application on the slave blade, and receives client application validations from the trusted application to unrestrict network traffic flow for the client application on the slave blade. | 2010-11-11 |
20100287304 | Internet Protocol Version 6 Network Connectivity in a Virtual Computer System - A method for sharing a network connection between a host system and a virtual machine is disclosed. The method includes sending an outgoing data frame from the virtual machine to a computer network. The host system is enabled to use the network connection using a first layer 2 address and a first layer 3 address. The first layer 2 and the first layer 3 addresses are associated with the network connection. The virtual machine is enabled to attempt to use the network connection using a second layer 2 address and a second layer 3 address. The first layer 3 and the second layer 3 addresses are compliant with IPv6. An occurrence of the second layer 2 address is replaced within the outgoing data frame with the first layer 2 address. If the outgoing data frame includes a network discover protocol (NDP) message of a selected type, the second layer 2 address in the NDP message is replaced by the first layer 2 address. | 2010-11-11 |
20100287305 | DETERMINING LIVENESS OF PROTOCOLS AND INTERFACES - The liveness of routing protocols can be determined using a mechanism to aggregate liveness information for the protocols. The ability of an interface to send and receive packets and the forwarding capability of an interface can also be determined using this mechanism. Since liveness information for multiple protocols, the liveness of interfaces, the forwarding capability of interfaces, or both, may be aggregated in a message, the message can be sent more often than could individual messages for each of the multiple protocols. This allows fast detection of failures, and sending connectivity messages for the individual protocols, such as neighbor “hellos,” to be sent less often. | 2010-11-11 |
20100287306 | COMPUTER SUPPORTING REMOTE SCAN - A computer acquires first connection information related to a path connecting a host computer and a local storage, and acquires second connection information related to a path connecting storage systems. The computer creates route management information based on the connection information. The route management information is information related to a plurality of routes. A single route is configured from two or more nodes connected in series and an inter-node path. The start node of the two or more nodes is a host computer, and the other node of the two or more nodes is a storage system. Based on the route management information, the computer selects, as the host computer for executing a remote scan, the host computer that is the start node of the optimum route from among the plurality of routes having the scan-targeted remote storage as the end node. | 2010-11-11 |
20100287307 | Data Synchronization - A method for synchronizing a first and a second set of data of a mobile telecommunication device includes: —providing a first processing device, the first processing device including the first set of data, —providing a second processing device, the second processing device including the second set of data, —providing a server, the server being comprised on the first processing device, —providing a client, the client being comprised in the second processing device, —synchronization of the first and the second set of data by way of a communication between the server and the client. | 2010-11-11 |
20100287308 | Intelligent Interaction Between Media Player and Host Computer - Improved techniques for interaction between a host computer (e.g., personal computer) and a media player are disclosed. According to one aspect, interaction between a host computer and a media player, such as automatic synchronization of media contents stored on a media player with media contents stored on a host computer, can be restricted. According to another aspect, management of media items residing on a media player can be performed at and by a host computer for the media player. According to still another aspect, media content can be played by a media player in accordance with quality settings established for the media content at the host computer. | 2010-11-11 |
20100287309 | DATA COMMUNICATION SYSTEMS AND BRIDGES - The present invention may be related to a bridge for communications between a first computing device and a second computing device in a data communication system. The bridge may include a first interface, a second interface and a control module. The first interface may be adapted to couple with the first computing device. The second interface may be adapted to couple with the second computing device. The control module may be configured to process a file input/output (I/O) command from the first computing device so as to allow the first computing device to have access to at least one of data or resource of the second computing device via the first and second interfaces. Moreover, the control module may further include a parser, a decoder and a micro processor. The parser may be configured to identify whether the file I/O command includes an encoded controller command and retrieve the encoded controller command from the file I/O command if the file I/O command includes an encoded controller command. The decoder may be configured to decode the encoded controller command so as to retrieve a controller command if the file I/O command includes the encoded controller command. The micro processor may be configured to respond to a first polling signal from the first computing device and a second polling signal from the second computing device when the controller command is retrieved. | 2010-11-11 |
20100287310 | Method and controller for processing commands in a storage device - A controller for processing a command in a data storage device includes at least one bitmap and a firmware command queue. The at least one bitmap is formed in hardware to indicate that the command is received. The firmware command queue is generated by firmware for storing the command when the at least one bitmap indicates receipt of the command. The firmware generates the firmware command queue that is of variable size for processing a high number of commands. In addition, the bitmaps are generated in the hardware for quickly receiving the high number of commands. | 2010-11-11 |
20100287311 | SYSTEM AND METHOD FOR ORDERING HAPTIC EFFECTS - A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot. | 2010-11-11 |
20100287312 | Apparatus and Method for Intelligent Analysis of Device Compatibility and Adaptive Processing of Multimedia Data - An apparatus and a method for intelligent analysis of device compatibility and adaptive processing of multimedia data are disclosed. By performing a unique intelligent analysis of device compatibility, the present invention provides a full application-level compatibility between the apparatus performing the intelligent analysis and an external device operatively connected to the apparatus even when device driver-level information of the external device is unavailable. Furthermore, a unique intelligent analysis for adaptive processing of multimedia data between the apparatus and the external devices enables an efficient and flexible usage of storage space in the external device for a multimedia data transfer from the apparatus to the external device. | 2010-11-11 |
20100287313 | APPLICATION VIRTUALIZATION - A virtual application packaged for a specific executing environment may be executed on a processing device having an executing environment different from the specific executing environment. A reference, included in extracted installer metadata, to one or more key paths of a hierarchically-structured data store may be modified according to a set of rules related to the executing environment detected in the processing device. The modified extracted installer metadata may be provided to an installer for installing the virtual application. During execution of the virtual application, a request to read, write, or modify the hierarchically-structured data store may be intercepted and changed, such that a first key path included in the request may be mapped to a second key path, based on the detected executing environment. Similarly, a response to the request, which may include the second key path, may be intercepted and modified, to the first key path. | 2010-11-11 |
20100287314 | STORAGE DEVICE ESTIMATING A COMPLETION TIME FOR A STORAGE OPERATION - A storage device or system provides to a host processor an estimation of a completion time of a storage operation. The completion time may be based on the duration of automatic storage operations, which are not administered by the host processor. The storage device includes a non-volatile memory and a controller. The storage system includes: a storage device having a non-volatile memory; and a controller module. The controller or controller module estimates the completion time of a storage operation and provides to the processor the estimated completion time before the storage operation completes. | 2010-11-11 |
20100287315 | Shared Secret Used Between Keyboard And Application - A system comprises a processor which executes an operating system and an application. The system also comprises a keyboard coupled to the processor. The keyboard and application share a shared secret that is used to encode keyboard data provided from the keyboard to the application. The shared secret is not known or accessible to the operating system. | 2010-11-11 |
20100287316 | BUS PROTOCOL FOR CONTROL OF COMMUNICATIONS BETWEEN TWO COMPUTERS - A method for operating a communications bus between a first computer and a second computer is provided. The method comprising monitoring a receiver bus coupled to the first computer for activity and confirming that the communications are determinant. The communications are confirmed by receiving a control label on the receiver bus and acknowledging to the second computer through a transmitter bus coupled to the first computer that communications are determinant. The method also comprises enabling the second computer to access data accessible by the first computer when the reliability of communications is confirmed. | 2010-11-11 |
20100287317 | Source Driver System Having an Integrated Data Bus for Displays - A source driver system includes a scan driver and a data driver. The data driver has a signal controller, a data bus, a connector and a plurality of data driver units. The signal controller is connected with the connector with via the data bus to form a first connection relationship such that the data bus is capable of transmitting control signals from the signal controller to the connector. The connector connects with the data driver units via the data bus to form a second connection relationship such that the data bus is capable of transmitting the control signals from the connector to the corresponding data driver units. In a preferred embodiment, the data bus is further arranged to form a third connection relationship among the data driver units such that the data bus is capable of communicating a serial connection signal among the data driver units. | 2010-11-11 |
20100287318 | I/O AND MEMORY BUS SYSTEM FOR DFPS AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES - A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading). | 2010-11-11 |
20100287319 | ADJUSTING PROCESSOR UTILIZATION DATA IN POLLING ENVIRONMENTS - A method, system, and computer usable program product for adjusting processor utilization data in polling environments are provided in the illustrative embodiments. An amount of a computing resource consumed during polling performed by the polling application over a predetermined period is received at a processor in a data processing system from a polling application executing in the data processing system. The amount forms a polling amount of the computing resource. Using the polling amount of the computing resource, another amount of the computing resource consumed for performing meaningful task is determined. The other amount forms a work amount of the computing resource. Using the work amount of the computing resource, an adjusted utilization of the computing resource is computed over a utilization interval. The data of the adjusted utilization is saved. | 2010-11-11 |
20100287320 | Interprocessor Communication Architecture - Described embodiments provide interprocessor communication between at least two processors of an integrated circuit, each processor running at least one task. For each processor, a proxy task is generated corresponding to each task running on each other processor. A task identifier for each task, and a look-up table having each task identifier associated with each other processor running the task is also generated. When a message is sent from a source task to a destination task that is running on a different processor than the source task, the source task communicates with the proxy task of the destination task. The proxy task appends the task identifier for the destination task to the message and sends the message to an interprocessor communication interface. Based on the task identifier, the processor running the destination task is determined and the destination task retrieves the message. | 2010-11-11 |
20100287321 | COMPUTER DOCK PROVIDING FOR DISCONNECTING MEDIA FROM DOCKING PORT WHEN LOCK IS INSERTED - A computer dock has a lock slot and media on which driver code is encoded. When a lock is inserted into the slot, it causes a switch to open so as to disconnect the media from a docking port of the dock. When the lock is not inserted into the slot, the media is connected to the docking port. | 2010-11-11 |
20100287322 | Computer System With Peripheral Modules Attached To A Display/cpu Assembly - A modular computer includes a display with a docking station on its back side. A CPU module connects to the docking station. Peripheral modules connect with the resulting display/CPU assembly so that the peripheral modules contact the back side of the display screen. | 2010-11-11 |
20100287323 | APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM - A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data. | 2010-11-11 |
20100287324 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described. | 2010-11-11 |
20100287325 | INTEGRATING NON-PERIPHERAL COMPONENT INTERCONNECT (PCI) RESOURCES INTO A PERSONAL COMPUTER SYSTEM - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 2010-11-11 |
20100287326 | Circuit of on-chip network having four-node ring switch structure - A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. The present invention provides multiple data transfer in parallel between multiple processor cores or multiple function units and register banks with dynamic configuration. The present invention thus obtains a low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity and a simplified circuit. | 2010-11-11 |
20100287327 | COMPUTING SYSTEMS AND METHODS FOR MANAGING FLASH MEMORY DEVICE - A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order. | 2010-11-11 |
20100287328 | WEAR LEVELING TECHNIQUE FOR STORAGE DEVICES - A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks. | 2010-11-11 |
20100287329 | Partial Page Operations for Non-Volatile Memory Systems - A read command initiates reads of pages or portions of pages of non-volatile memory using a memory address that specifies a row, column and length. A host controller can use the read command with a read operation or status request. In some implementations, the memory address further specifies a die or plane and a block. | 2010-11-11 |
20100287330 | METHOD FOR WRITING DATA INTO FLASH MEMORY - Method for writing data into flash memory is disclosed. The method includes storing the frequently updated data and the not-aligned data collectively into some of the physical memory blocks of the flash memory. In other words, the method collectively writes those data into the same physical memory blocks of the flash memory as far as possible. By doing this, the invalid physical memory pages in the physical memory blocks can be generated collectively. As a result, the storage releasing efficiency of garbage collection can be greatly improved. | 2010-11-11 |
20100287331 | ELECTRONIC DEVICE AND METHOD FOR RECORDING POWER-ON TIME THEREOF - An electronic device and a method for recording power-on time include a flash memory to store a plurality of bits used to record power-on time. The electronic device sets the plurality of bits stored in the flash memory to a first value, sets a changing interval, and copies the plurality of bits from the flash memory to a random access memory (RAM). The electronic device further searches for a first bit of the first value from the plurality of bits in the RAM, and records an index of the first bit of the first value in a variable. The electronic device further changes the bit corresponding to the variable to a second value and increases the variable by 1 when the changing interval arrives. The electronic device further writes the bit changed to the second value from the RAM to the flash memory. | 2010-11-11 |
20100287332 | DATA STORING SYSTEM, DATA STORING METHOD, EXECUTING DEVICE, CONTROL METHOD THEREOF, CONTROL DEVICE, AND CONTROL METHOD THEREOF - A data storing system including: a non-volatile memory configured to have a plurality of memory blocks each capable of independently operating and allow random access to each of addresses; a controller configured to control writing of data to the non-volatile memory; and an executing unit configured to execute a predetermined application, wherein the executing unit decides the number of interleaves indicating the number of memory blocks operated in parallel among the plurality of memory blocks, and the executing unit notifies the controller of the decided number of interleaves. | 2010-11-11 |
20100287333 | DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A data storage device comprises a plurality of memory devices, a buffer memory, and a controller. The plurality of memory devices are connected to a plurality of channels and a plurality of ways. The buffer memory temporarily stores data to be written in the memory devices. The controller stores the data in the buffer memory based on channel and way information of the memory devices. | 2010-11-11 |
20100287334 | ADDRESSING SCHEME TO ALLOW FLEXIBLE MAPPING OF FUNCTIONS IN A PROGRAMMABLE LOGIC ARRAY - A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB. | 2010-11-11 |
20100287335 | Read Enable Signal Adjusting Flash Memory Device and Read Control Method of Flash Memory Device - Disclosed is a flash memory device for adjusting a read signal timing and read control method of the flash memory device. The flash memory device includes a plurality of flash memory units, a common input/output bus connected with each of the plurality of flash memory units, and a controller to propagate the read control signal to a flash memory unit selected from among the plurality of flash memories and to receive data read from the selected flash memory unit via the common input/output bus, the controller being connected with the common input/output bus, wherein the controller adjusts a propagation timing of the read control signal unit based on a propagation delay corresponding to the selected flash memory unit, and thereby controlling a timing optimized for each flash memory unit. | 2010-11-11 |
20100287336 | EXTERNAL I/O SIGNAL AND DRAM REFRESH SIGNAL SYNCHRONIZATION METHOD AND ITS CIRCUIT - In an LSI that determines timing of DRAM refresh by a refresh timer to synchronize an external I/O signal and DRAM refresh timing with each other, a circuit configuration capable of controlling a value of the refresh timer by a CPU at arbitrary timing is employed. Alternatively, a circuit configuration capable of controlling the value of the refresh timer at arbitrary timing by an external terminal, or a circuit configuration capable of controlling the refresh timing directly from the external terminal without through the refresh timer. | 2010-11-11 |
20100287337 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device has a memory cell array including a memory cell group for storing option information, and a controller configured to wait for a preset period of time after a command for loading the option information has been received before performing an operation of loading the option information. | 2010-11-11 |
20100287338 | SELECTIVE MIRRORING METHOD - A selective mirroring method is disclosed. In the selective mirroring, first mirroring to duplicate an input/output for a first directory or a file at a time point when the input/output occurs and second mirroring to mirror a second directory or file at a necessary time point may be performed cooperatively or selectively. The selective mirroring may be performed in a kernel layer of the OS. The first mirroring may be performed through hooking of a file I/O system call. The second mirroring may be implemented by a daemon. The second mirroring may be performed when the directory is to be entirely mirrored, when an error occurs in the course of mirroring, or when mirroring is to be performed on a medium to which the first mirroring is hardly applied. The second mirroring may wake up from a sleep state at a time point when mirroring is required to perform a given operation. | 2010-11-11 |
20100287339 | DEMAND BASED PARTITIONING OR MICROPROCESSOR CACHES - Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor. | 2010-11-11 |
20100287340 | Concurrent Execution of Critical Sections by Eliding Ownership of Locks - One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section. | 2010-11-11 |
20100287341 | Wake-and-Go Mechanism with System Address Bus Transaction Master - A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus. | 2010-11-11 |
20100287342 | PROCESSING OF COHERENT AND INCOHERENT ACCESSES AT A UNIFORM CACHE - Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit and a return of the cached information regardless of whether the cacheline is marked as coherent or incoherent. However, a subsequent coherent read access to a cacheline marked as incoherent will be returned as a cache miss regardless of whether the cacheline includes information sought by the coherent read access. In response to a cache miss for a coherent read access, a global snoop is initiated so as to query all other target components within the same coherency domain. In contrast, a cache miss resulting from an incoherent read access is processed using a non-global snoop to a limited set of one or a few target components in the coherency domain. | 2010-11-11 |
20100287343 | CONTENTION FREE PARALLEL ACCESS SYSTEM AND A METHOD FOR CONTENTION FREE PARALLEL ACCESS TO A GROUP OF MEMORY BANKS - A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element from an odd memory unit of a pair of memory banks and fetches a second information element from an even memory unit of the pair of memory banks; wherein the first and second information elements are two consecutive interleaved address information elements. | 2010-11-11 |
20100287344 | CAPTURING AND LOADING OPERATING SYSTEM STATES - Operating system states capture and loading technique embodiments are presented that involve the capture and loading of baseline system states. This is accomplished, in one embodiment, by storing the states of a computer's operating system memory that it is desired to restore at a future time. No changes are permitted to the persisted storage associated with the computer. Instead, changes that would have been made to the persisted storage during an ensuing computing session, had they not been prevented, are stored in a separate computing session file. Whenever it is desired to return the operating system to its baseline condition, the stored baseline system memory states are loaded into the operating system memory, in lieu of the operating system memory's current states. | 2010-11-11 |
20100287345 | System and Method for Migration of Data - Systems and methods for data migration are disclosed. A method may include allocating a destination storage resource to receive migration data. The method may also include assigning the destination storage resource a first identifier value equal to an identifier value associated with a source storage resource. The method may additionally include assigning the source storage resource a second identifier value different than the first identifier value. The method may further include migrating data from the source storage resource to the destination storage resource. | 2010-11-11 |
20100287346 | METHOD AND SYSTEM FOR MANAGING LARGE WRITE-ONCE TABLES IN SHADOW PAGE DATABASES - Methods and systems for managing large write-once tables are described. In some embodiments, a relational database management system includes a space allocation module that utilizes both a logical space allocation scheme, as well as a physical space allocation scheme, to allocate space in units (e.g., pages) having two different sizes—small pages and big pages. For instance, small pages are logically allocated with a conventional converter module, which manages a converter table for mapping logical pages to physical pages, while big pages are physically allocated with an object directory manager, which manages big objects comprised of big pages. | 2010-11-11 |
20100287347 | METHOD AND SYSTEM FOR MAPPING DATA TO A PROCESS - The invention relates to mapping data to a process. A method of the invention includes receiving a request to copy a parent process, where the parent process is associated with a first virtual memory address space that includes a first mapping to a page of a file loaded into physical memory. The method includes creating a child process (of the parent process) associated with a second virtual memory address space. The method includes determining that a fork count is greater than a fork count threshold and a COW count to fork count ratio is greater than a threshold ratio. The fork count is associated with the file and the COW count is associated with the page. The method includes creating a copy of the page in physical memory and further includes creating a second mapping from the second virtual memory address space to the copy of the page. | 2010-11-11 |
20100287348 | SYSTEM AND METHOD FOR DIFFERENTIAL BACKUP - A method and system for differential backup of a logical disk of a data storage array is presented. The system comprises: a pool of physical storage space divided into a plurality of addressable memory locations; and a logical disk adapted to store metadata associated with a differential snapshot of the logical disk. The metadata comprises a mapping structure defining a sharing relationship between the differential snapshot of the logical disk and a previous snapshot of the logical disk that is arranged to serve as a baseline snapshot of the logical disk. The mapping structure is adapted to indicate disk regions of the logical disk that have changed in the differential snapshot of the logical disk with reference to the baseline snapshot of the logical disk. | 2010-11-11 |
20100287349 | INFORMATION STORAGE PROTECTOR - The present invention relates to an information storage protector that comprises:
| 2010-11-11 |
20100287350 | Exact Free Space Tracking for Region-Based Garbage Collection - A method for exactly tracking the amount of free space in an independently collectable memory region is described. This enables more accurate decisions about the utility of collecting each individual region. The method uses zombie multiobjects (special multiobject descriptors denoting inaccessible space) to track which inaccessible areas have already been added to a region's free space counters. | 2010-11-11 |
20100287351 | FILE ACCESS MANAGEMENT SYSTEM - A computing device arranged to control access by application threads to a number of data portions stored in memory on the computing device. Each thread includes a handle for each data portion for which it is arranged to access or manipulate. When an application thread includes instructions to manipulate a data portion, it calls a function. The system copies the data portion to a new memory location and applies the function which has been called to the data portion copy. | 2010-11-11 |
20100287352 | VIRTUAL MACHINE TOOL INTERFACE FOR TRACKING OBJECTS - Disclosed is a method and computer program product to track allocation of a plurality of objects in a heap. A data processing system, during an object allocation, prevents an object from being moved to another place in memory or being deleted. The data processing system prevents such activity concurrently with garbage collection on a second object not currently being allocated. The data processing system notifies a profiler of object information based on the object allocation via a callback function, wherein object information is a one-to-one mapping of the object address. The data processing system revives garbage collector processing of the object. | 2010-11-11 |
20100287353 | Multipage Preparation Commands for Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation. | 2010-11-11 |
20100287354 | VSAM SMART REORGANIZATION - Various embodiments for adaptive reorganization of a virtual storage access method (VSAM) data set are provided. In one exemplary embodiment, upon each control interval (CI) split of a plurality of CI splits occurring over a period of time, historical data including a key value for a record causing each CI split is recorded in a data repository. The historical data is analyzed with a predictive algorithm to determine an amount of free space to be allocated to each of a plurality of control intervals generated pursuant to the adaptive reorganization. The predictive algorithm allocates a greater percentage of the free space to a first location of the VVDS having a larger proportion of historically placed key values than a second location of the VVDS having a smaller proportion of the historically placed key values. | 2010-11-11 |
20100287355 | Dynamic Translation in the Presence of Intermixed Code and Data - A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate the software from the first format to the second format. The system also includes a host engine coupled to the emulator and configured to perform instructions in the second format. The emulator is configured to determine whether a store command in the first format stores information to a memory page that includes instructions and to convert the store instruction to a special store instruction in the event that the target of the store instruction does not contain an instruction. | 2010-11-11 |
20100287356 | LARGE MEMORY PAGES FOR SHARED LIBRARIES - A method for loading shared libraries. The method includes receiving an indication of a requirement to load the shared library into the virtual memory and determining that the shared library is a candidate for using shared large pages. Further, the method includes, in response to the determination, storing a text section of the shared library in a shared large page of the virtual memory and storing a data section of the shared library in a page of the virtual memory, where the virtual memory is mapped to a physical memory of the computer, where, within an address space of the virtual memory, a starting address of the text section of the shared library is separated from a starting address of the data section of the shared library by a predefined distance, and where the predefined distance is larger than a size of the large page. | 2010-11-11 |
20100287357 | Computer Memory Architecture for Hybrid Serial and Parallel Computing Systems - In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory. | 2010-11-11 |
20100287358 | Branch Prediction Path Instruction - A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address. | 2010-11-11 |
20100287359 | VARIABLE REGISTER AND IMMEDIATE FIELD ENCODING IN AN INSTRUCTION SET ARCHITECTURE - A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor. | 2010-11-11 |
20100287360 | Task Processing Device - The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register. | 2010-11-11 |
20100287361 | Root Cause Analysis for Complex Event Processing - Root cause analysis for complex event processing is described. In embodiments, root cause analysis at a complex event processor is automatically performed by selecting an output event from an operator and correlating the output event to an input event using event type and lifetime data for the input event and the output event stored in a data store. Embodiments describe how the lifetime data can comprise a start time and an end time for the event, and the correlation can be based on a comparison of the start and end times between the input and output events. Embodiments describe how the correlation algorithm used is selected in dependence on the event type. In embodiments, a complex event processing engine comprises a logging unit arranged to store in the data store an indicator of an event type and lifetime data for each output event from an operator. | 2010-11-11 |
20100287362 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, COMPUTER PROGRAM AND INFORMATION PROCESSING METHOD - It will be provided with an information processing apparatus, an information processing system, a computer program and an information processing method, which can prepare operating environment based on setting information distinctive in respective users without causing interference on operating environments for other users. | 2010-11-11 |
20100287363 | METHOD AND SYSTEM FOR SECURE SOFTWARE PROVISIONING - A method and system for the provisioning of software that enable large scale installation and management of software in computer units in a highly secure manner. The BIOS of the target computer unit is adapted such that upon power up the system attempts to boot from an external media. The BIOS features functions within the code for the implementing a system watchdog for assuring the system remains in a known state, a function for digital signature verification, and loads drivers for a file system. The external media includes the operating system (OS) image and other bootstrap files, each having been digitally signed with an asymmetric private key that corresponds to the public key. A programmable read-only parameter memory on the motherboard is configured to store the public keys and the (failure) state of the system independently of the primary and secondary media enabling reboot from an alternative boot path. | 2010-11-11 |
20100287364 | BOOT SYSTEMS AND METHODS, AND RELATED DEVICES - Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS. | 2010-11-11 |
20100287365 | DEPLOYMENT OF BOOT IMAGES IN DISKLESS SERVERS - In one embodiment, a system, comprises a first computer system comprising at least a first diskless server, at least a first RAID controller coupled to the first diskless server, at least a first storage pool coupled to the RAID controller, and a remote management server coupled to the RAID controller via a an out-of-band communication link. The remote management server comprises a boot management module which, when executed, initiates a command to instruct the RAID controller to create at least a first logical volume in a memory module coupled to the RAID controller, transmits the command to the RAID controller via the out-of-band communication link, and transmits a boot image from the remote management server to the RAID controller via the out-of-band communication link. The RAID controller creates the first logical volume for the boot image in response to the command, and stores the boot image in the first logical volume. | 2010-11-11 |
20100287366 | DISTRIBUTED INFORMATION GENERATION APPARATUS, RECONSTRUCTION APPARATUS, RECONSTRUCTION RESULT VERIFICATION APPARATUS, AND SECRET INFORMATION DISTRIBUTION SYSTEM, METHOD, AND PROGRAM - A shared information creating device capable of detecting false alteration of shared information with high probability even if a traitor has shares the number of which is above a threshold and creating shared information whose data size is smaller than that of secret information. A recovering device, a recovery result verifying device, and a secret information sharing system, program, and method are also provided. The shared information creating device generates a polynomial F in which secret information s is embedded, outputs a shared secret information, generates a polynomial G in which the output of when a fixed value t is substituted in the polynomial F is embedded as secret information, and creates shared secret information. A recovering device receives k sets of shared secret information to generate a polynomial F′, and receives k sets of shared shared secret information to generate a polynomial G′. When the value embedded as secret information in the polynomial G′ is equal to the output of when the fixed value t is substituted in the polynomial F′, the embedded value is outputted. When they are not equal, information indicating falsification detection is outputted. | 2010-11-11 |
20100287367 | SYSTEM AND METHOD FOR DATA TRANSMISSION - A method for transmission data in a system is provided. The system includes a first device, plurality of second devices, and plurality of third devices, the method includes steps of encrypting the data with a first key and encrypting the first key with a second key at the first device, sending the encrypted data from the first device to the second device, decrypting the second key and encrypting the first key with a third key by the second device, sending the encrypted data from the second device to the third device, and decrypting the third key and the first key by the third device. | 2010-11-11 |
20100287368 | METHOD, APPARATUS AND SYSTEM FOR HOSTING INFORMATION EXCHANGE GROUPS ON A WIDE AREA NETWORK - A method and system for hosting information exchange groups on a wide area network is disclosed, using various tools for promoting topical organization and self-evolution of the information exchange groups, and of a system of information exchange groups. These tools include methods for providing user rating of posts within the exchange group, for rating and ranking users of the exchange group, for rating and ranking links to related information pages and especially to related exchange groups operating according to the methods of the invention, and for continuously updating rating and ranking information. Additionally, methods are provided for users to found exchange groups, to filter information in exchange groups according to specified user preferences, and to protect private information from inadvertent disclosure to other users of the exchange group. | 2010-11-11 |
20100287369 | ID SYSTEM AND PROGRAM, AND ID METHOD - [PROBLEMS] To appropriately authenticate a user, a biometric device, and an authentication timing of a client side and prevent leak or tampering of the biometric information. | 2010-11-11 |
20100287370 | REVOCATION OF CRYPTOGRAPHIC DIGITAL CERTIFICATES - Different targets (c | 2010-11-11 |
20100287371 | METHOD AND APPARATUS FOR USE IN A COMMUNICATIONS NETWORK - A method and apparatus for use in a Proxy Mobile IP communications network. An anchor point function serves at least one mobile host. The anchor point function generates an IP address for use by the mobile host, the address being generated using cryptographic materials owned by the anchor point function. The anchor point function can then perform signalling on behalf of the mobile host, using the IP address generated for the mobile host with IP addresses of other mobile hosts S | 2010-11-11 |
20100287372 | MAIL SERVER AND METHOD FOR SENDING E-MAILS TO THEIR RECIPIENTS - The present invention relates to a mail server for a network. The mail server has a sender part arranged to receive outgoing e-mails from users of the network and to send the received e-mails to their recipients. The sending part is arranged to copy at least some of the contents in the received e-mail to a storage. The sending part provides an amended e-mail based on the received e-mail, said amended e-mail comprising at least one pointer substituting the contents copied to the storage, said pointer pointing at said contents in said storage. | 2010-11-11 |
20100287373 | DATA SECURITY SYSTEM WITH ENCRYPTION - A data security system ( | 2010-11-11 |
20100287374 | Protecting Hardware Circuit Design by Secret Sharing - Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable. | 2010-11-11 |
20100287375 | System and Method for Operating End-to-End Security Channel Between Server and IC Card - The present invention relates to a system and method for operating an end-to-end security channel between an IC card and a server on a communication network. A method for connecting an end-to-end security channel between an IC card and a server on a communication network includes the steps of: generating, by the server, a random number Rs for transmission to the IC card, generating an E(Rs) by encrypting the random number Rs by a user public key, and transmitting the E(Rs) to the IC card through the communication network; receiving, by the IC card, the E(Rs) through the communication network and extracting the random number Rs by decrypting the E(Rs) by a user private key; generating, by the IC card, a random number Rc to be transmitted to the server, generating a session key K′ by the random number Rs and the random number Rc, and generating a first card verifier MAC by encrypting the random number Rs by the session key K′; transmitting, by the IC card, the random number Rc and the first card verifier MAC to the server through the communication network; receiving, by the server, the random number Rc and the first card verifier MAC through the communication network, generating a session key K by the random number Rs and the random number Rc, and generating a first server verifier MAC by encrypting the random number Rs by the session key K; and comparing, by the server, the first card verifier MAC and the first server verifier MAC to certify the session key K. | 2010-11-11 |
20100287376 | EXTERNAL SIGNATURE DEVICE FOR A PC WITH WIRELESS COMMUNICATION CAPACITY - External signature device for a PC, with capacity for wireless communication with the computer, which can be used immediately in electronic banking and electronic commerce or in any other system based on electronic signature requiring a high level of security with a relatively small amount of data for signature, said device including a communication interface with wireless connection to the PC, an alphanumeric display ( | 2010-11-11 |
20100287377 | Method and a system for a secure execution of workflow tasks of a workflow in a decentralized workflow system - A computer-implemented method is disclosed for a secure execution of workflow tasks of a workflow to be executed according to a given execution pattern in a decentralized workflow system with a central workflow engine (CWE) initiating the workflow and a plurality of task execution agents (A1, A2, . . . ), wherein task-based public-private key pairs are produced using a workflow signature scheme. The method starts at an i'th execution agent which is selected by at least one preceding execution agent in accord with the execution pattern to perform an i'th task of the workflow. The method includes receiving, from the at least one preceding execution agent via a secure channel, a task-based private key generated by the at least one preceding execution agent; signing workflow information of the workflow for at least one subsequent execution agent with a workflow signature, the workflow signature being computed using the workflow signature scheme by taking as input at least the task-based private key; selecting at least one appropriate subsequent execution agent; computing a task-based private key for the at least one subsequent execution agent wherein the task-based private key is computed using system parameters and a workflow identifier assigned to the subsequent execution agent; forwarding to the at least one subsequent execution agent the workflow information with its associated workflow signature, the system parameters and the task-based private key for the at least one subsequent execution agent through a secure channel. | 2010-11-11 |
20100287378 | SIGNATURES FOR MULTIPLE ENCODINGS - Signatures for multiple encodings is disclosed. In some embodiments, signatures for multiple encodings includes receiving a first signature of digitally signed data, wherein the first signature is a digital signature of data included in a first document having a first document encoding; receiving a second signature of digitally signed data, wherein the second signature is a digital signature of data included in the first document having a second document encoding, and wherein the first document encoding and the second document encoding are different document encodings; receiving a third signature of digitally signed data, wherein the third signature is a digital signature of data included in a canonicalized version of the first document having a canonical encoding, and wherein canonicalizing the first document includes providing a different order of data within the first document based on a canonical ordering; selecting a signature from the received first signature, the received second signature, and the received third signature, wherein the first signature, the second signature, and the third signature are associated with the first document to provide a digitally signed first document; and verifying the digitally signed data using the selected signature. | 2010-11-11 |
20100287379 | METHOD FOR COMPATIBILITY CHECKING OF A MEASURING SYSTEM COMPRISING A MEASUREMENT TRANSMITTER AND A SENSOR - In a method for compatibility checking of a measuring system including a measurement transmitter and a sensor, a first signature is externally created for an identifying data set and is stored in the measurement transmitter. After transmission of the identifying data set from the measurement transmitter to the sensor, a second signature is calculated for the identifying data set in the sensor. If the signatures match, then the measurement transmitter and the sensor are compatible and the measurement transmitter can access data and/or functions of the sensor. | 2010-11-11 |
20100287380 | WRITING AREA SECURITY SYSTEM - A writing area security system ( | 2010-11-11 |
20100287381 | AUTOMATED PASSWORD AUTHENTICATION - A method of automated password authentication by pattern matching regions of screen pixels against a repository of previously captured regions, and submitting a username and a password stored with the regions of the screen pixels for authentication includes triggering an autorunnable application to startup by inserting a memory stick by a user, challenging the user for a master password to access an encrypted database held on the memory stick, running the autorunnable application as a background task following a successful authorization of the user, and checking whether the user has triggered the autorunnable application by a pre-defined key sequence. If the user has triggered the autorunnable application, then the method proceeds with prompting the user to highlight at least one rectangle around a text or an image which uniquely identifies a login panel, capturing a username and a password when entered by the user, and returning the autorunnable application to a background task. If the user has not triggered the autorunnable application, then the method proceeds with monitoring a screen buffer for a matching signature based on the rectangle drawn by the user. | 2010-11-11 |
20100287382 | Two-factor graphical password for text password and encryption key generation - This invention details systems, methods, and devices for providing a two-factor graphical password system to a user so that the user may obtain access to a restricted resource. A first previously selected image (previously selected by the user) is presented to the user to enter his password by sequentially selecting predetermined areas on the first image. The user's input is used to create an encryption/decryption key which is used for communicating between a user application and a device. If the user has entered the correct password, then the device can communicate with the user application. Once the device can communicate with the user application, a second previously selected image (previously selected by the user) is presented to the user from the device. The user enters his second password and the user's input is sent to the device. The device then creates the user's alphanumeric password or another encryption key from the user's input and sends this to the user application. The user application then transmits the password or key to the system which restricts access to the restricted resource. | 2010-11-11 |
20100287383 | TECHNIQUES FOR DETECTING ENCRYPTED DATA - Techniques are described that generally relate to methods for detecting encryption status of a data file or data stream and selectively encrypting the data file or data stream based on the encryption status of the data file or data stream are generally disclosed. Example methods may include one or more of reading the data file or data stream from a data source, calculating a value of a property of the data file or data stream, comparing the calculated value with a threshold value to determine whether the file is encrypted or unencrypted, and encrypting files that are determined to be unencrypted. | 2010-11-11 |
20100287384 | ARRANGEMENT FOR AND METHOD OF PROTECTING A DATA PROCESSING DEVICE AGAINST AN ATTACK OR ANALYSIS - In order to further develop an arrangement for as well as a method of protecting at least one data processing device, in particular at least one embedded system, for example at least one chip card or smart card, against at least one attack, in particular against at least one side-channel attack, for example against at least one current trace analysis, the data processing device, in particular at least one integrated circuit of the data processing device, carrying out calculations, in particular cryptographic operations wherein an attack, for example an E[lectro]M[agnetic] radiation attack, or an analysis, for example a D[ifferential]P[ower]A[nalysis], such attack or such analysis in particular targeted on finding out a private key, is to be securely averted, it is proposed to blind all intermediate results of the calculations by at least one random variable. | 2010-11-11 |
20100287385 | SECURING DATA CACHES THROUGH ENCRYPTION - Encryption techniques for securing data in a data cache are generally disclosed. Example methods may include one or more of reading the cache to identify data, determining whether the data is encrypted to identify previously unencrypted data and/or previously encrypted data, and encrypting selectively at least a portion of the previously unencrypted data. The present disclosure also generally relates to a computer system data processor configured to read a cache to identify data, determine whether the read data is encrypted, and encrypt selectively at least a portion of the previously unencrypted data. The present disclosure also generally relates to computer accessible mediums containing computer-executable instructions for data encryption upon execution of the instructions by a data processor. The instructions may configure the data processor to perform procedures that read the cache to identify data, determine whether the data is encrypted, and selectively encrypt data determined as unencrypted. | 2010-11-11 |
20100287386 | SECURE INTEGRATED CIRCUIT COMPRISING MEANS FOR DISCLOSING COUNTERPART MASK VALUES - An integrated circuit includes a communication interface circuit, a cryptographic algorithm, a countermeasure configured to protect the cryptographic algorithm against side-channel attacks, and a mask generator configured to provide the countermeasure with mask values. The integrated circuit is configured to execute a specific command requiring the disclosure of mask values used by the countermeasures to protect the cryptographic algorithm during a cryptographic session, and, in response to such a command, to send the mask values through the communication interface circuit. | 2010-11-11 |
20100287387 | Docking station - A portable computer has a downstream USB 2.0 port, connected to a docking station of the invention via a USB cable having a Type A plug in the port and a Type B plug plugged into an upstream port in the docking station. This has a housing, in which is mounted hub circuitry, connected to the upstream port, a hard drive and a plurality of downstream ports. Peripheral devices are plugged into the ports. Thus the computer can enumerate and communicate with the hard drive and the peripheral devices. | 2010-11-11 |
20100287388 | Information Processing Apparatus and Method - An information processing apparatus includes: a plurality of electric power generating elements; detection means for determining whether each of the plurality of electric power generating elements has an electromotive force equal to or higher than a predetermined value; determination means determining an input operation performed by a user by identifying an electric power generating element having an electromotive force below the predetermined value when at least one of the plurality of electric power generating elements is determined as having an electromotive force below the predetermined value according to the detection means; processing means carrying out a process associate with the input operation determined by the determination means; and bypass means which is provided in parallel with the electric power generating elements and through which a current flows when the electric power generating elements have an electromotive force below the predetermined value. | 2010-11-11 |
20100287389 | SINGLE CHIP MICROCONTROLLER INCLUDING BATTERY MANAGEMENT AND PROTECTION - A microcontroller is disclosed. The microcontroller comprises a processor system and a high voltage interface coupled to the processor system and adapted to be coupled to a battery. The microcontroller further includes a battery management system for monitoring the battery and managing the battery based upon the monitoring of the battery. The microcontroller is a single chip. This one-chip solution saves design cost and PCB space in addition to broadening the functionality of the smart battery application. With the accuracy of the microcontroller, the charge status of the battery can be predicted more accurately and therefore effectively increases actual battery capacity. | 2010-11-11 |
20100287390 | DEVICE, SYSTEM AND METHOD FOR COMPUTER NETWORK TRAFFIC MONITORING, DISTRIBUTION AND POWER MANAGEMENT - The presently disclosed device, system and method continuously monitors the network traffic within a local area network (LAN) or wide area network (WAN) between a node and multiple servers. With the use of a configurator device, the system can also manage the power in at least one computer network by activating and deactivating these servers as a function of time. Each individual server can be designated as “active” or “standby.” Standby servers can be powered off, from a signal generated from the configurator to a module, if the rate of traffic drops below a predetermined threshold. The same servers can power back on when the network activity level rises above the same or another predetermined threshold. The system comprises a user interface, which allows a user to monitor network activity and define an upper and lower threshold, a configurator adaptable to configure the system based on the network traffic and the pre-defined thresholds, a plurality of modules that activate or deactivate the servers and may comprise a power distribution unit that works in conjunction with the system over the same communication protocol. The disclosed device and system may also control any associated PDU units used to cool the servers. | 2010-11-11 |
20100287391 | MEMORY CONTROL CIRCUIT, CONTROL METHOD, AND STORAGE MEDIUM - A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue. | 2010-11-11 |
20100287392 | POWER SAVING CONTROL SYSTEM AND CONTROL METHOD - A power saving control system includes a memory module, and a main controller. The memory module includes a number of memories. The main controller includes a detecting unit, a determining unit, and a management control unit. The detecting unit is to detect a usage rate of the memory module. The determining unit stores a number of interval parameters denoting a number of usage rate ranges of the memory module, and determine a corresponding interval parameter for the detected usage rate of the memory module. The management control unit stores a number of control instructions corresponding to the number of the interval parameters, and is to invoke a control instruction corresponding to the determined interval parameter, to control corresponding memories of the memory module to work. | 2010-11-11 |
20100287393 | ELECTRONIC DEVICE AND METHOD OF PERFORMING A POWER MANAGEMENT IN AN ELECTRONIC DEVICE - An electronic device is provided which comprises at least one functional unit (HB) for performing a processing. The functional unit (HB) receives a supply current (Isupply). The electronic device furthermore comprises a supply current monitor (SCM) for monitoring the supply current (Isupply) in order to determine an average supply current (Iavg). The electronic device furthermore comprises a characterization unit (CU) for determining a relation between the average supply current (Iavg) and an operating frequency of the functional unit. Furthermore, a slope calculation unit (SCU) is provided to determine the slope of the relation. Moreover, a power management unit (PMU) is provided to control the operation of the functional unit (HB) according to the results of the slope calculation unit (SCU) in order to control the power dissipation of the functional unit (HB). | 2010-11-11 |
20100287394 | NORTH-BRIDGE TO SOUTH-BRIDGE PROTOCOL FOR PLACING PROCESSOR IN LOW POWER STATE - A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations. | 2010-11-11 |
20100287395 | COMPUTER SYSTEM FOR PROCESSING DATA IN NON-OPERATIONAL STATE AND PROCESSING METHOD THEREOF - A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data. | 2010-11-11 |
20100287396 | DATA PROCESSOR PERFORMANCE PREDICTION - A method of processing data using a data processor having an operating system for performing tasks of an application programme, and a power and performance controller controlling parameters and modes of execution of the tasks by the data processor. The power and performance controller includes a performance predictor producing an estimation of required performance of the data processor for the tasks taking account of inactive periods of the tasks and adjusting the performance and power consumption of the data processor in response to the estimation. The performance predictor distinguishes for each of the tasks between: —available inactive periods of the task during which the operating system is available to continue to process the same task, and —unavailable inactive periods of the task during which the operating system is not available to continue to process the same task. A substantial improvement is obtained in quality of service, with fewer missed deadlines in performance of the tasks. | 2010-11-11 |
20100287397 | Method of a Full Coverage Low Power Mode for Storage Systems Storing Replicated Data Items - A novel and useful method of implementing a full coverage low power mode in a storage system comprised of one or more memory storage devices storing replicated data items. A subset of the memory storage devices is chosen whose replicated data items require the least amount of storage. If the chosen subset stores uncovered data items, these data items are copied to an auxiliary memory storage device. The storage system can enter a full coverage low power mode by powering down the chosen subset of memory storage devices. | 2010-11-11 |
20100287398 | VEHICLE CONTROL UNIT HAVING A MICROCONTROLLER THE SUPPLY VOLTAGE OF WHICH IS MONITORED AND ASSOCIATED METHOD - A vehicle control unit has a microcontroller, to which multiple analog supply voltages are applied, and a monitoring unit for the functional monitoring of the microcontroller. The microcontroller includes an A/D converter for the conversion of the plurality of analog supply voltages into digitized supply voltages. A computing area of the microcontroller which is computationally secured is provided for monitoring the digitized supply voltages of the microcontroller. The plurality of digitized supply voltages are monitored in the area as to whether they lie within predetermined tolerance ranges. | 2010-11-11 |